2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "tgsi/tgsi_dump.h"
29 #include "toy_compiler.h"
31 #include "toy_legalize.h"
32 #include "toy_optimize.h"
33 #include "toy_helpers.h"
34 #include "ilo_context.h"
35 #include "ilo_shader.h"
37 struct vs_compile_context {
38 struct ilo_shader *shader;
39 const struct ilo_shader_variant *variant;
41 struct toy_compiler tc;
43 enum brw_message_target const_cache;
45 int output_map[PIPE_MAX_SHADER_OUTPUTS];
58 vs_lower_opcode_tgsi_in(struct vs_compile_context *vcc,
59 struct toy_dst dst, int dim, int idx)
61 struct toy_compiler *tc = &vcc->tc;
66 slot = toy_tgsi_find_input(&vcc->tgsi, idx);
68 const int first_in_grf = vcc->first_vue_grf +
69 (vcc->shader->in.count - vcc->tgsi.num_inputs);
70 const int grf = first_in_grf + vcc->tgsi.inputs[slot].semantic_index;
71 const struct toy_src src = tsrc(TOY_FILE_GRF, grf, 0);
76 /* undeclared input */
77 tc_MOV(tc, dst, tsrc_imm_f(0.0f));
82 vs_lower_opcode_tgsi_const_gen6(struct vs_compile_context *vcc,
83 struct toy_dst dst, int dim,
86 const struct toy_dst header =
87 tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
88 const struct toy_dst block_offsets =
89 tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf + 1, 0));
90 const struct toy_src r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
91 struct toy_compiler *tc = &vcc->tc;
92 unsigned msg_type, msg_ctrl, msg_len;
93 struct toy_inst *inst;
96 /* set message header */
97 inst = tc_MOV(tc, header, r0);
98 inst->mask_ctrl = BRW_MASK_DISABLE;
100 /* set block offsets */
101 tc_MOV(tc, block_offsets, idx);
103 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
104 msg_ctrl = BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD << 8;;
107 desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false,
108 msg_type, msg_ctrl, ILO_VS_CONST_SURFACE(dim));
110 tc_SEND(tc, dst, tsrc_from(header), desc, vcc->const_cache);
114 vs_lower_opcode_tgsi_const_gen7(struct vs_compile_context *vcc,
115 struct toy_dst dst, int dim,
118 struct toy_compiler *tc = &vcc->tc;
119 const struct toy_dst offset =
120 tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
124 * In 259b65e2e7938de4aab323033cfe2b33369ddb07, pull constant load was
125 * changed from OWord Dual Block Read to ld to increase performance in the
126 * classic driver. Since we use the constant cache instead of the data
127 * cache, I wonder if we still want to follow the classic driver.
131 tc_MOV(tc, offset, idx);
133 desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false,
134 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
135 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
137 ILO_VS_CONST_SURFACE(dim));
139 tc_SEND(tc, dst, tsrc_from(offset), desc, BRW_SFID_SAMPLER);
143 vs_lower_opcode_tgsi_imm(struct vs_compile_context *vcc,
144 struct toy_dst dst, int idx)
149 imm = toy_tgsi_get_imm(&vcc->tgsi, idx, NULL);
151 for (ch = 0; ch < 4; ch++) {
154 tdst_writemask(tdst_ud(dst), 1 << ch),
155 tsrc_imm_ud(imm[ch]));
161 vs_lower_opcode_tgsi_sv(struct vs_compile_context *vcc,
162 struct toy_dst dst, int dim, int idx)
164 struct toy_compiler *tc = &vcc->tc;
165 const struct toy_tgsi *tgsi = &vcc->tgsi;
170 slot = toy_tgsi_find_system_value(tgsi, idx);
174 switch (tgsi->system_values[slot].semantic_name) {
175 case TGSI_SEMANTIC_INSTANCEID:
176 case TGSI_SEMANTIC_VERTEXID:
178 * In 3DSTATE_VERTEX_ELEMENTS, we prepend an extra vertex element for
179 * the generated IDs, with VID in the X channel and IID in the Y
183 const int grf = vcc->first_vue_grf;
184 const struct toy_src src = tsrc(TOY_FILE_GRF, grf, 0);
185 const enum toy_swizzle swizzle =
186 (tgsi->system_values[slot].semantic_name ==
187 TGSI_SEMANTIC_INSTANCEID) ? TOY_SWIZZLE_Y : TOY_SWIZZLE_X;
189 tc_MOV(tc, tdst_d(dst), tsrc_d(tsrc_swizzle1(src, swizzle)));
192 case TGSI_SEMANTIC_PRIMID:
194 tc_fail(tc, "unhandled system value");
195 tc_MOV(tc, dst, tsrc_imm_d(0));
201 vs_lower_opcode_tgsi_direct(struct vs_compile_context *vcc,
202 struct toy_inst *inst)
204 struct toy_compiler *tc = &vcc->tc;
207 assert(inst->src[0].file == TOY_FILE_IMM);
208 dim = inst->src[0].val32;
210 assert(inst->src[1].file == TOY_FILE_IMM);
211 idx = inst->src[1].val32;
213 switch (inst->opcode) {
214 case TOY_OPCODE_TGSI_IN:
215 vs_lower_opcode_tgsi_in(vcc, inst->dst, dim, idx);
217 case TOY_OPCODE_TGSI_CONST:
218 if (tc->dev->gen >= ILO_GEN(7))
219 vs_lower_opcode_tgsi_const_gen7(vcc, inst->dst, dim, inst->src[1]);
221 vs_lower_opcode_tgsi_const_gen6(vcc, inst->dst, dim, inst->src[1]);
223 case TOY_OPCODE_TGSI_SV:
224 vs_lower_opcode_tgsi_sv(vcc, inst->dst, dim, idx);
226 case TOY_OPCODE_TGSI_IMM:
228 vs_lower_opcode_tgsi_imm(vcc, inst->dst, idx);
231 tc_fail(tc, "unhandled TGSI fetch");
235 tc_discard_inst(tc, inst);
239 vs_lower_opcode_tgsi_indirect(struct vs_compile_context *vcc,
240 struct toy_inst *inst)
242 struct toy_compiler *tc = &vcc->tc;
243 enum tgsi_file_type file;
245 struct toy_src indirect_dim, indirect_idx;
247 assert(inst->src[0].file == TOY_FILE_IMM);
248 file = inst->src[0].val32;
250 assert(inst->src[1].file == TOY_FILE_IMM);
251 dim = inst->src[1].val32;
252 indirect_dim = inst->src[2];
254 assert(inst->src[3].file == TOY_FILE_IMM);
255 idx = inst->src[3].val32;
256 indirect_idx = inst->src[4];
258 /* no dimension indirection */
259 assert(indirect_dim.file == TOY_FILE_IMM);
260 dim += indirect_dim.val32;
262 switch (inst->opcode) {
263 case TOY_OPCODE_TGSI_INDIRECT_FETCH:
264 if (file == TGSI_FILE_CONSTANT) {
266 struct toy_dst tmp = tc_alloc_tmp(tc);
268 tc_ADD(tc, tmp, indirect_idx, tsrc_imm_d(idx));
269 indirect_idx = tsrc_from(tmp);
272 if (tc->dev->gen >= ILO_GEN(7))
273 vs_lower_opcode_tgsi_const_gen7(vcc, inst->dst, dim, indirect_idx);
275 vs_lower_opcode_tgsi_const_gen6(vcc, inst->dst, dim, indirect_idx);
279 case TOY_OPCODE_TGSI_INDIRECT_STORE:
281 tc_fail(tc, "unhandled TGSI indirection");
285 tc_discard_inst(tc, inst);
289 * Emit instructions to move sampling parameters to the message registers.
292 vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf,
293 struct toy_src coords, int num_coords,
294 struct toy_src bias_or_lod, struct toy_src ref_or_si,
295 struct toy_src ddx, struct toy_src ddy, int num_derivs)
297 const unsigned coords_writemask = (1 << num_coords) - 1;
301 assert(num_coords <= 4);
302 assert(num_derivs <= 3 && num_derivs <= num_coords);
304 for (i = 0; i < Elements(m); i++)
305 m[i] = tdst(TOY_FILE_MRF, base_mrf + i, 0);
308 case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD:
309 tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
310 tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), bias_or_lod);
313 case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS:
314 tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
315 tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_XZ),
316 tsrc_swizzle(ddx, 0, 0, 1, 1));
317 tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_YW),
318 tsrc_swizzle(ddy, 0, 0, 1, 1));
319 if (num_derivs > 2) {
320 tc_MOV(tc, tdst_writemask(m[2], TOY_WRITEMASK_X),
321 tsrc_swizzle1(ddx, 2));
322 tc_MOV(tc, tdst_writemask(m[2], TOY_WRITEMASK_Y),
323 tsrc_swizzle1(ddy, 2));
325 num_params = 4 + num_derivs * 2;
327 case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE:
328 tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
329 tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), ref_or_si);
330 tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_Y), bias_or_lod);
333 case GEN5_SAMPLER_MESSAGE_SAMPLE_LD:
334 assert(num_coords <= 3);
335 tc_MOV(tc, tdst_writemask(tdst_d(m[0]), coords_writemask), coords);
336 tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_W), bias_or_lod);
337 if (tc->dev->gen >= ILO_GEN(7)) {
341 tc_MOV(tc, tdst_writemask(tdst_d(m[1]), TOY_WRITEMASK_X), ref_or_si);
345 case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
346 tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_X), bias_or_lod);
350 tc_fail(tc, "unknown sampler opcode");
355 return (num_params + 3) / 4;
359 * Set up message registers and return the message descriptor for sampling.
361 static struct toy_src
362 vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
363 int base_mrf, unsigned *ret_sampler_index)
365 unsigned simd_mode, msg_type, msg_len, sampler_index, binding_table_index;
366 struct toy_src coords, ddx, ddy, bias_or_lod, ref_or_si;
367 int num_coords, ref_pos, num_derivs;
370 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD4X2;
372 coords = inst->src[0];
375 bias_or_lod = tsrc_null();
376 ref_or_si = tsrc_null();
380 num_coords = toy_tgsi_get_texture_coord_dim(inst->tex.target, &ref_pos);
382 /* extract the parameters */
383 switch (inst->opcode) {
384 case TOY_OPCODE_TGSI_TXD:
386 tc_fail(tc, "TXD with shadow sampler not supported");
388 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
391 num_derivs = num_coords;
394 case TOY_OPCODE_TGSI_TXL:
398 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
399 ref_or_si = tsrc_swizzle1(coords, ref_pos);
402 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
405 bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_W);
407 case TOY_OPCODE_TGSI_TXF:
408 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
410 switch (inst->tex.target) {
411 case TGSI_TEXTURE_2D_MSAA:
412 case TGSI_TEXTURE_2D_ARRAY_MSAA:
413 assert(ref_pos >= 0 && ref_pos < 4);
414 /* lod is always 0 */
415 bias_or_lod = tsrc_imm_d(0);
416 ref_or_si = tsrc_swizzle1(coords, ref_pos);
419 bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_W);
423 /* offset the coordinates */
424 if (!tsrc_is_null(inst->tex.offsets[0])) {
427 tmp = tc_alloc_tmp(tc);
428 tc_ADD(tc, tmp, coords, inst->tex.offsets[0]);
429 coords = tsrc_from(tmp);
434 case TOY_OPCODE_TGSI_TXQ:
435 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
437 bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_X);
439 case TOY_OPCODE_TGSI_TXQ_LZ:
440 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
444 case TOY_OPCODE_TGSI_TXL2:
448 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
449 ref_or_si = tsrc_swizzle1(coords, ref_pos);
452 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
455 bias_or_lod = tsrc_swizzle1(inst->src[1], TOY_SWIZZLE_X);
459 assert(!"unhandled sampling opcode");
464 assert(inst->src[sampler_src].file == TOY_FILE_IMM);
465 sampler_index = inst->src[sampler_src].val32;
466 binding_table_index = ILO_VS_TEXTURE_SURFACE(sampler_index);
469 * From the Sandy Bridge PRM, volume 4 part 1, page 18:
471 * "Note that the (cube map) coordinates delivered to the sampling
472 * engine must already have been divided by the component with the
473 * largest absolute value."
475 switch (inst->tex.target) {
476 case TGSI_TEXTURE_CUBE:
477 case TGSI_TEXTURE_SHADOWCUBE:
478 case TGSI_TEXTURE_CUBE_ARRAY:
479 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
480 /* TXQ does not need coordinates */
481 if (num_coords >= 3) {
482 struct toy_dst tmp, max;
483 struct toy_src abs_coords[3];
486 tmp = tc_alloc_tmp(tc);
487 max = tdst_writemask(tmp, TOY_WRITEMASK_W);
489 for (i = 0; i < 3; i++)
490 abs_coords[i] = tsrc_absolute(tsrc_swizzle1(coords, i));
492 tc_SEL(tc, max, abs_coords[0], abs_coords[0], BRW_CONDITIONAL_GE);
493 tc_SEL(tc, max, tsrc_from(max), abs_coords[0], BRW_CONDITIONAL_GE);
494 tc_INV(tc, max, tsrc_from(max));
496 for (i = 0; i < 3; i++)
497 tc_MUL(tc, tdst_writemask(tmp, 1 << i), coords, tsrc_from(max));
499 coords = tsrc_from(tmp);
504 /* set up sampler parameters */
505 msg_len = vs_add_sampler_params(tc, msg_type, base_mrf,
506 coords, num_coords, bias_or_lod, ref_or_si, ddx, ddy, num_derivs);
509 * From the Sandy Bridge PRM, volume 4 part 1, page 136:
511 * "The maximum message length allowed to the sampler is 11. This would
512 * disallow sample_d, sample_b_c, and sample_l_c with a SIMD Mode of
516 tc_fail(tc, "maximum length for messages to the sampler is 11");
518 if (ret_sampler_index)
519 *ret_sampler_index = sampler_index;
521 return tsrc_imm_mdesc_sampler(tc, msg_len, 1,
522 false, simd_mode, msg_type, sampler_index, binding_table_index);
526 vs_lower_opcode_tgsi_sampling(struct vs_compile_context *vcc,
527 struct toy_inst *inst)
529 struct toy_compiler *tc = &vcc->tc;
531 struct toy_dst dst, tmp;
532 unsigned sampler_index;
534 unsigned swizzle_zero_mask, swizzle_one_mask, swizzle_normal_mask;
537 desc = vs_prepare_tgsi_sampling(tc, inst,
538 vcc->first_free_mrf, &sampler_index);
540 switch (inst->opcode) {
541 case TOY_OPCODE_TGSI_TXF:
542 case TOY_OPCODE_TGSI_TXQ:
543 case TOY_OPCODE_TGSI_TXQ_LZ:
551 toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_SAMPLER);
552 inst->src[0] = tsrc(TOY_FILE_MRF, vcc->first_free_mrf, 0);
555 /* write to a temp first */
556 tmp = tc_alloc_tmp(tc);
560 tc_move_inst(tc, inst);
563 assert(sampler_index < vcc->variant->num_sampler_views);
564 swizzles[0] = vcc->variant->sampler_view_swizzles[sampler_index].r;
565 swizzles[1] = vcc->variant->sampler_view_swizzles[sampler_index].g;
566 swizzles[2] = vcc->variant->sampler_view_swizzles[sampler_index].b;
567 swizzles[3] = vcc->variant->sampler_view_swizzles[sampler_index].a;
570 swizzles[0] = PIPE_SWIZZLE_RED;
571 swizzles[1] = PIPE_SWIZZLE_GREEN;
572 swizzles[2] = PIPE_SWIZZLE_BLUE;
573 swizzles[3] = PIPE_SWIZZLE_ALPHA;
576 swizzle_zero_mask = 0;
577 swizzle_one_mask = 0;
578 swizzle_normal_mask = 0;
579 for (i = 0; i < 4; i++) {
580 switch (swizzles[i]) {
581 case PIPE_SWIZZLE_ZERO:
582 swizzle_zero_mask |= 1 << i;
585 case PIPE_SWIZZLE_ONE:
586 swizzle_one_mask |= 1 << i;
590 swizzle_normal_mask |= 1 << i;
595 /* swizzle the results */
596 if (swizzle_normal_mask) {
597 tc_MOV(tc, tdst_writemask(dst, swizzle_normal_mask),
598 tsrc_swizzle(tsrc_from(tmp), swizzles[0],
599 swizzles[1], swizzles[2], swizzles[3]));
601 if (swizzle_zero_mask)
602 tc_MOV(tc, tdst_writemask(dst, swizzle_zero_mask), tsrc_imm_f(0.0f));
603 if (swizzle_one_mask)
604 tc_MOV(tc, tdst_writemask(dst, swizzle_one_mask), tsrc_imm_f(1.0f));
608 vs_lower_opcode_urb_write(struct toy_compiler *tc, struct toy_inst *inst)
610 /* vs_write_vue() has set up the message registers */
611 toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_URB);
615 vs_lower_virtual_opcodes(struct vs_compile_context *vcc)
617 struct toy_compiler *tc = &vcc->tc;
618 struct toy_inst *inst;
621 while ((inst = tc_next(tc)) != NULL) {
622 switch (inst->opcode) {
623 case TOY_OPCODE_TGSI_IN:
624 case TOY_OPCODE_TGSI_CONST:
625 case TOY_OPCODE_TGSI_SV:
626 case TOY_OPCODE_TGSI_IMM:
627 vs_lower_opcode_tgsi_direct(vcc, inst);
629 case TOY_OPCODE_TGSI_INDIRECT_FETCH:
630 case TOY_OPCODE_TGSI_INDIRECT_STORE:
631 vs_lower_opcode_tgsi_indirect(vcc, inst);
633 case TOY_OPCODE_TGSI_TEX:
634 case TOY_OPCODE_TGSI_TXB:
635 case TOY_OPCODE_TGSI_TXD:
636 case TOY_OPCODE_TGSI_TXL:
637 case TOY_OPCODE_TGSI_TXP:
638 case TOY_OPCODE_TGSI_TXF:
639 case TOY_OPCODE_TGSI_TXQ:
640 case TOY_OPCODE_TGSI_TXQ_LZ:
641 case TOY_OPCODE_TGSI_TEX2:
642 case TOY_OPCODE_TGSI_TXB2:
643 case TOY_OPCODE_TGSI_TXL2:
644 case TOY_OPCODE_TGSI_SAMPLE:
645 case TOY_OPCODE_TGSI_SAMPLE_I:
646 case TOY_OPCODE_TGSI_SAMPLE_I_MS:
647 case TOY_OPCODE_TGSI_SAMPLE_B:
648 case TOY_OPCODE_TGSI_SAMPLE_C:
649 case TOY_OPCODE_TGSI_SAMPLE_C_LZ:
650 case TOY_OPCODE_TGSI_SAMPLE_D:
651 case TOY_OPCODE_TGSI_SAMPLE_L:
652 case TOY_OPCODE_TGSI_GATHER4:
653 case TOY_OPCODE_TGSI_SVIEWINFO:
654 case TOY_OPCODE_TGSI_SAMPLE_POS:
655 case TOY_OPCODE_TGSI_SAMPLE_INFO:
656 vs_lower_opcode_tgsi_sampling(vcc, inst);
661 case TOY_OPCODE_SQRT:
665 case TOY_OPCODE_FDIV:
667 case TOY_OPCODE_INT_DIV_QUOTIENT:
668 case TOY_OPCODE_INT_DIV_REMAINDER:
669 toy_compiler_lower_math(tc, inst);
671 case TOY_OPCODE_URB_WRITE:
672 vs_lower_opcode_urb_write(tc, inst);
675 if (inst->opcode > 127)
676 tc_fail(tc, "unhandled virtual opcode");
683 * Compile the shader.
686 vs_compile(struct vs_compile_context *vcc)
688 struct toy_compiler *tc = &vcc->tc;
689 struct ilo_shader *sh = vcc->shader;
691 vs_lower_virtual_opcodes(vcc);
692 toy_compiler_legalize_for_ra(tc);
693 toy_compiler_optimize(tc);
694 toy_compiler_allocate_registers(tc,
697 vcc->num_grf_per_vrf);
698 toy_compiler_legalize_for_asm(tc);
701 ilo_err("failed to legalize VS instructions: %s\n", tc->reason);
705 if (ilo_debug & ILO_DEBUG_VS) {
706 ilo_printf("legalized instructions:\n");
707 toy_compiler_dump(tc);
712 sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size);
715 static const uint32_t microcode[] = {
716 /* fill in the microcode here */
719 const bool swap = true;
721 sh->kernel_size = sizeof(microcode);
722 sh->kernel = MALLOC(sh->kernel_size);
725 const int num_dwords = sizeof(microcode) / 4;
726 const uint32_t *src = microcode;
727 uint32_t *dst = (uint32_t *) sh->kernel;
730 for (i = 0; i < num_dwords; i += 4) {
732 dst[i + 0] = src[i + 3];
733 dst[i + 1] = src[i + 2];
734 dst[i + 2] = src[i + 1];
735 dst[i + 3] = src[i + 0];
738 memcpy(dst, src, 16);
745 ilo_err("failed to compile VS: %s\n", tc->reason);
749 if (ilo_debug & ILO_DEBUG_VS) {
750 ilo_printf("disassembly:\n");
751 toy_compiler_disassemble(tc, sh->kernel, sh->kernel_size);
759 * Collect the toy registers to be written to the VUE.
762 vs_collect_outputs(struct vs_compile_context *vcc, struct toy_src *outs)
764 const struct toy_tgsi *tgsi = &vcc->tgsi;
767 for (i = 0; i < vcc->shader->out.count; i++) {
768 const int slot = vcc->output_map[i];
769 const int vrf = (slot >= 0) ? toy_tgsi_get_vrf(tgsi,
770 TGSI_FILE_OUTPUT, 0, tgsi->outputs[slot].index) : -1;
776 dst = tdst(TOY_FILE_VRF, vrf, 0);
777 src = tsrc_from(dst);
780 /* PSIZE is at channel W */
781 tc_MOV(&vcc->tc, tdst_writemask(dst, TOY_WRITEMASK_W),
782 tsrc_swizzle1(src, TOY_SWIZZLE_X));
784 /* the other channels are for the header */
786 tc_MOV(&vcc->tc, tdst_writemask(dst, TOY_WRITEMASK_XYZ),
790 /* initialize unused channels to 0.0f */
791 if (tgsi->outputs[slot].undefined_mask) {
792 dst = tdst_writemask(dst, tgsi->outputs[slot].undefined_mask);
793 tc_MOV(&vcc->tc, dst, tsrc_imm_f(0.0f));
798 /* XXX this is too ugly */
799 if (vcc->shader->out.semantic_names[i] == TGSI_SEMANTIC_CLIPDIST &&
801 /* ok, we need to compute clip distance */
802 int clipvert_slot = -1, clipvert_vrf, j;
804 for (j = 0; j < tgsi->num_outputs; j++) {
805 if (tgsi->outputs[j].semantic_name ==
806 TGSI_SEMANTIC_CLIPVERTEX) {
810 else if (tgsi->outputs[j].semantic_name ==
811 TGSI_SEMANTIC_POSITION) {
812 /* remember pos, but keep looking */
817 clipvert_vrf = (clipvert_slot >= 0) ? toy_tgsi_get_vrf(tgsi,
818 TGSI_FILE_OUTPUT, 0, tgsi->outputs[clipvert_slot].index) : -1;
819 if (clipvert_vrf >= 0) {
820 struct toy_dst tmp = tc_alloc_tmp(&vcc->tc);
821 struct toy_src clipvert = tsrc(TOY_FILE_VRF, clipvert_vrf, 0);
822 int first_ucp, last_ucp;
824 if (vcc->shader->out.semantic_indices[i]) {
826 last_ucp = MIN2(7, vcc->variant->u.vs.num_ucps - 1);
830 last_ucp = MIN2(3, vcc->variant->u.vs.num_ucps - 1);
833 for (j = first_ucp; j <= last_ucp; j++) {
834 const int plane_grf = vcc->first_const_grf + j / 2;
835 const int plane_subreg = (j & 1) * 16;
836 const struct toy_src plane = tsrc_rect(tsrc(TOY_FILE_GRF,
837 plane_grf, plane_subreg), TOY_RECT_041);
838 const unsigned writemask = 1 << ((j >= 4) ? j - 4 : j);
840 tc_DP4(&vcc->tc, tdst_writemask(tmp, writemask),
844 src = tsrc_from(tmp);
847 src = tsrc_imm_f(0.0f);
851 src = (i == 0) ? tsrc_imm_d(0) : tsrc_imm_f(0.0f);
862 * Emit instructions to write the VUE.
865 vs_write_vue(struct vs_compile_context *vcc)
867 struct toy_compiler *tc = &vcc->tc;
868 struct toy_src outs[PIPE_MAX_SHADER_OUTPUTS];
869 struct toy_dst header;
871 struct toy_inst *inst;
872 int sent_attrs, total_attrs;
874 header = tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
875 r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
876 inst = tc_MOV(tc, header, r0);
877 inst->mask_ctrl = BRW_MASK_DISABLE;
879 if (tc->dev->gen >= ILO_GEN(7)) {
880 inst = tc_OR(tc, tdst_offset(header, 0, 5),
881 tsrc_rect(tsrc_offset(r0, 0, 5), TOY_RECT_010),
882 tsrc_rect(tsrc_imm_ud(0xff00), TOY_RECT_010));
883 inst->exec_size = BRW_EXECUTE_1;
884 inst->access_mode = BRW_ALIGN_1;
885 inst->mask_ctrl = BRW_MASK_DISABLE;
888 total_attrs = vs_collect_outputs(vcc, outs);
890 while (sent_attrs < total_attrs) {
892 int mrf = vcc->first_free_mrf + 1, avail_mrf_for_attrs;
893 int num_attrs, msg_len, i;
896 num_attrs = total_attrs - sent_attrs;
899 /* see if we need another message */
900 avail_mrf_for_attrs = vcc->last_free_mrf - mrf + 1;
901 if (num_attrs > avail_mrf_for_attrs) {
903 * From the Sandy Bridge PRM, volume 4 part 2, page 22:
905 * "Offset. This field specifies a destination offset (in 256-bit
906 * units) from the start of the URB entry(s), as referenced by
907 * URB Return Handle n, at which the data (if any) will be
910 * As we need to offset the following messages, we must make sure
911 * this one writes an even number of attributes.
913 num_attrs = avail_mrf_for_attrs & ~1;
917 if (tc->dev->gen >= ILO_GEN(7)) {
918 /* do not forget about the header */
919 msg_len = 1 + num_attrs;
923 * From the Sandy Bridge PRM, volume 4 part 2, page 26:
925 * "At least 256 bits per vertex (512 bits total, M1 & M2) must
926 * be written. Writing only 128 bits per vertex (256 bits
927 * total, M1 only) results in UNDEFINED operation."
929 * "[DevSNB] Interleave writes must be in multiples of 256 per
932 * That is, we must write or appear to write an even number of
933 * attributes, starting from two.
935 if (num_attrs % 2 && num_attrs == avail_mrf_for_attrs) {
940 msg_len = 1 + align(num_attrs, 2);
943 for (i = 0; i < num_attrs; i++)
944 tc_MOV(tc, tdst(TOY_FILE_MRF, mrf++, 0), outs[sent_attrs + i]);
946 assert(sent_attrs % 2 == 0);
947 desc = tsrc_imm_mdesc_urb(tc, eot, msg_len, 0,
948 eot, true, false, BRW_URB_SWIZZLE_INTERLEAVE, sent_attrs / 2, 0);
950 tc_add2(tc, TOY_OPCODE_URB_WRITE, tdst_null(), tsrc_from(header), desc);
952 sent_attrs += num_attrs;
957 * Set up shader inputs for fixed-function units.
960 vs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi)
964 /* vertex/instance id is the first VE if exists */
965 for (i = 0; i < tgsi->num_system_values; i++) {
968 switch (tgsi->system_values[i].semantic_name) {
969 case TGSI_SEMANTIC_INSTANCEID:
970 case TGSI_SEMANTIC_VERTEXID:
978 sh->in.semantic_names[sh->in.count] =
979 tgsi->system_values[i].semantic_name;
980 sh->in.semantic_indices[sh->in.count] =
981 tgsi->system_values[i].semantic_index;
982 sh->in.interp[sh->in.count] = TGSI_INTERPOLATE_CONSTANT;
983 sh->in.centroid[sh->in.count] = false;
991 for (i = 0; i < tgsi->num_inputs; i++) {
992 assert(tgsi->inputs[i].semantic_name == TGSI_SEMANTIC_GENERIC);
993 if (tgsi->inputs[i].semantic_index >= num_attrs)
994 num_attrs = tgsi->inputs[i].semantic_index + 1;
996 assert(num_attrs <= PIPE_MAX_ATTRIBS);
998 /* VF cannot remap VEs. VE[i] must be used as GENERIC[i]. */
999 for (i = 0; i < num_attrs; i++) {
1000 sh->in.semantic_names[sh->in.count + i] = TGSI_SEMANTIC_GENERIC;
1001 sh->in.semantic_indices[sh->in.count + i] = i;
1002 sh->in.interp[sh->in.count + i] = TGSI_INTERPOLATE_CONSTANT;
1003 sh->in.centroid[sh->in.count + i] = false;
1006 sh->in.count += num_attrs;
1008 sh->in.has_pos = false;
1009 sh->in.has_linear_interp = false;
1010 sh->in.barycentric_interpolation_mode = 0;
1014 * Set up shader outputs for fixed-function units.
1017 vs_setup_shader_out(struct ilo_shader *sh, const struct toy_tgsi *tgsi,
1018 bool output_clipdist, int *output_map)
1020 int psize_slot = -1, pos_slot = -1;
1021 int clipdist_slot[2] = { -1, -1 };
1022 int color_slot[4] = { -1, -1, -1, -1 };
1025 /* find out the slots of outputs that need special care */
1026 for (i = 0; i < tgsi->num_outputs; i++) {
1027 switch (tgsi->outputs[i].semantic_name) {
1028 case TGSI_SEMANTIC_PSIZE:
1031 case TGSI_SEMANTIC_POSITION:
1034 case TGSI_SEMANTIC_CLIPDIST:
1035 if (tgsi->outputs[i].semantic_index)
1036 clipdist_slot[1] = i;
1038 clipdist_slot[0] = i;
1040 case TGSI_SEMANTIC_COLOR:
1041 if (tgsi->outputs[i].semantic_index)
1046 case TGSI_SEMANTIC_BCOLOR:
1047 if (tgsi->outputs[i].semantic_index)
1057 /* the first two VUEs are always PSIZE and POSITION */
1059 output_map[0] = psize_slot;
1060 output_map[1] = pos_slot;
1062 sh->out.register_indices[0] =
1063 (psize_slot >= 0) ? tgsi->outputs[psize_slot].index : -1;
1064 sh->out.semantic_names[0] = TGSI_SEMANTIC_PSIZE;
1065 sh->out.semantic_indices[0] = 0;
1067 sh->out.register_indices[1] =
1068 (pos_slot >= 0) ? tgsi->outputs[pos_slot].index : -1;
1069 sh->out.semantic_names[1] = TGSI_SEMANTIC_POSITION;
1070 sh->out.semantic_indices[1] = 0;
1072 sh->out.has_pos = true;
1074 /* followed by optional clip distances */
1075 if (output_clipdist) {
1076 sh->out.register_indices[num_outs] =
1077 (clipdist_slot[0] >= 0) ? tgsi->outputs[clipdist_slot[0]].index : -1;
1078 sh->out.semantic_names[num_outs] = TGSI_SEMANTIC_CLIPDIST;
1079 sh->out.semantic_indices[num_outs] = 0;
1080 output_map[num_outs++] = clipdist_slot[0];
1082 sh->out.register_indices[num_outs] =
1083 (clipdist_slot[1] >= 0) ? tgsi->outputs[clipdist_slot[1]].index : -1;
1084 sh->out.semantic_names[num_outs] = TGSI_SEMANTIC_CLIPDIST;
1085 sh->out.semantic_indices[num_outs] = 1;
1086 output_map[num_outs++] = clipdist_slot[1];
1090 * make BCOLOR follow COLOR so that we can make use of
1091 * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING in 3DSTATE_SF
1093 for (i = 0; i < 4; i++) {
1094 const int slot = color_slot[i];
1099 sh->out.register_indices[num_outs] = tgsi->outputs[slot].index;
1100 sh->out.semantic_names[num_outs] = tgsi->outputs[slot].semantic_name;
1101 sh->out.semantic_indices[num_outs] = tgsi->outputs[slot].semantic_index;
1103 output_map[num_outs++] = slot;
1106 /* add the rest of the outputs */
1107 for (i = 0; i < tgsi->num_outputs; i++) {
1108 switch (tgsi->outputs[i].semantic_name) {
1109 case TGSI_SEMANTIC_PSIZE:
1110 case TGSI_SEMANTIC_POSITION:
1111 case TGSI_SEMANTIC_CLIPDIST:
1112 case TGSI_SEMANTIC_COLOR:
1113 case TGSI_SEMANTIC_BCOLOR:
1116 sh->out.register_indices[num_outs] = tgsi->outputs[i].index;
1117 sh->out.semantic_names[num_outs] = tgsi->outputs[i].semantic_name;
1118 sh->out.semantic_indices[num_outs] = tgsi->outputs[i].semantic_index;
1119 output_map[num_outs++] = i;
1124 sh->out.count = num_outs;
1128 * Translate the TGSI tokens.
1131 vs_setup_tgsi(struct toy_compiler *tc, const struct tgsi_token *tokens,
1132 struct toy_tgsi *tgsi)
1134 if (ilo_debug & ILO_DEBUG_VS) {
1135 ilo_printf("dumping vertex shader\n");
1138 tgsi_dump(tokens, 0);
1142 toy_compiler_translate_tgsi(tc, tokens, true, tgsi);
1144 ilo_err("failed to translate VS TGSI tokens: %s\n", tc->reason);
1148 if (ilo_debug & ILO_DEBUG_VS) {
1149 ilo_printf("TGSI translator:\n");
1150 toy_tgsi_dump(tgsi);
1152 toy_compiler_dump(tc);
1160 * Set up VS compile context. This includes translating the TGSI tokens.
1163 vs_setup(struct vs_compile_context *vcc,
1164 const struct ilo_shader_state *state,
1165 const struct ilo_shader_variant *variant)
1169 memset(vcc, 0, sizeof(*vcc));
1171 vcc->shader = CALLOC_STRUCT(ilo_shader);
1175 vcc->variant = variant;
1177 toy_compiler_init(&vcc->tc, state->info.dev);
1178 vcc->tc.templ.access_mode = BRW_ALIGN_16;
1179 vcc->tc.templ.exec_size = BRW_EXECUTE_8;
1180 vcc->tc.rect_linear_width = 4;
1183 * The classic driver uses the sampler cache (gen6) or the data cache
1186 vcc->const_cache = GEN6_SFID_DATAPORT_CONSTANT_CACHE;
1188 if (!vs_setup_tgsi(&vcc->tc, state->info.tokens, &vcc->tgsi)) {
1189 toy_compiler_cleanup(&vcc->tc);
1194 vs_setup_shader_in(vcc->shader, &vcc->tgsi);
1195 vs_setup_shader_out(vcc->shader, &vcc->tgsi,
1196 (vcc->variant->u.vs.num_ucps > 0), vcc->output_map);
1198 /* fit each pair of user clip planes into a register */
1199 num_consts = (vcc->variant->u.vs.num_ucps + 1) / 2;
1201 /* r0 is reserved for payload header */
1202 vcc->first_const_grf = 1;
1203 vcc->first_vue_grf = vcc->first_const_grf + num_consts;
1204 vcc->first_free_grf = vcc->first_vue_grf + vcc->shader->in.count;
1205 vcc->last_free_grf = 127;
1207 /* m0 is reserved for system routines */
1208 vcc->first_free_mrf = 1;
1209 vcc->last_free_mrf = 15;
1211 vcc->num_grf_per_vrf = 1;
1213 if (vcc->tc.dev->gen >= ILO_GEN(7)) {
1214 vcc->last_free_grf -= 15;
1215 vcc->first_free_mrf = vcc->last_free_grf + 1;
1216 vcc->last_free_mrf = vcc->first_free_mrf + 14;
1219 vcc->shader->in.start_grf = vcc->first_const_grf;
1220 vcc->shader->pcb.clip_state_size =
1221 vcc->variant->u.vs.num_ucps * (sizeof(float) * 4);
1227 * Compile the vertex shader.
1230 ilo_shader_compile_vs(const struct ilo_shader_state *state,
1231 const struct ilo_shader_variant *variant)
1233 struct vs_compile_context vcc;
1236 if (!vs_setup(&vcc, state, variant))
1239 if (vcc.tc.dev->gen >= ILO_GEN(7)) {
1243 need_gs = variant->u.vs.rasterizer_discard ||
1244 state->info.stream_output.num_outputs;
1249 if (!vs_compile(&vcc)) {
1254 toy_tgsi_cleanup(&vcc.tgsi);
1255 toy_compiler_cleanup(&vcc.tc);
1258 int so_mapping[PIPE_MAX_SHADER_OUTPUTS];
1261 for (i = 0; i < vcc.tgsi.num_outputs; i++) {
1264 for (j = 0; j < vcc.shader->out.count; j++) {
1265 if (vcc.tgsi.outputs[i].semantic_name ==
1266 vcc.shader->out.semantic_names[j] &&
1267 vcc.tgsi.outputs[i].semantic_index ==
1268 vcc.shader->out.semantic_indices[j]) {
1274 so_mapping[i] = attr;
1277 if (!ilo_shader_compile_gs_passthrough(state, variant,
1278 so_mapping, vcc.shader)) {
1279 ilo_shader_destroy(vcc.shader);