2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 typedef short GLshort;
32 typedef unsigned char GLubyte;
33 typedef unsigned int GLuint;
34 typedef float GLfloat;
36 #include "brw_defines.h"
37 #include "brw_structs.h"
38 static int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
40 #include "toy_compiler.h"
43 toy_compiler_disassemble(struct toy_compiler *tc, const void *kernel, int size)
45 /* set this to true to dump the hex */
46 const bool dump_hex = false;
47 const struct brw_instruction *instructions = kernel;
50 for (i = 0; i < size / sizeof(*instructions); i++) {
52 const uint32_t *dwords = (const uint32_t *) &instructions[i];
53 ilo_printf("0x%08x 0x%08x 0x%08x 0x%08x ",
54 dwords[3], dwords[2], dwords[1], dwords[0]);
57 brw_disasm(stderr, (struct brw_instruction *) &instructions[i],
58 ILO_GEN_GET_MAJOR(tc->gen));
62 static const struct opcode_desc {
66 } opcode_descs[128] = {
67 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
68 [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
69 [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
70 [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
71 [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
72 [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
73 [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
74 [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
75 [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
76 [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
78 [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
79 [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
80 [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
81 [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
82 [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
83 [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
84 [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
85 [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
86 [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
87 [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
88 [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
89 [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
90 [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
91 [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
93 [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
94 [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
95 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
96 [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
97 [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
98 [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
99 [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
100 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
101 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
102 [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
103 [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
105 [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
106 [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
107 [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
108 [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
109 [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
110 [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
111 [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
112 [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
113 [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
114 [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
115 [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
116 [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
117 [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
118 [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
119 [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
120 [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
121 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
122 [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
124 static const struct opcode_desc *opcode = opcode_descs;
126 static const char * const conditional_modifier[16] = {
127 [BRW_CONDITIONAL_NONE] = "",
128 [BRW_CONDITIONAL_Z] = ".e",
129 [BRW_CONDITIONAL_NZ] = ".ne",
130 [BRW_CONDITIONAL_G] = ".g",
131 [BRW_CONDITIONAL_GE] = ".ge",
132 [BRW_CONDITIONAL_L] = ".l",
133 [BRW_CONDITIONAL_LE] = ".le",
134 [BRW_CONDITIONAL_R] = ".r",
135 [BRW_CONDITIONAL_O] = ".o",
136 [BRW_CONDITIONAL_U] = ".u",
139 static const char * const negate[2] = {
144 static const char * const _abs[2] = {
149 static const char * const vert_stride[16] = {
160 static const char * const width[8] = {
168 static const char * const horiz_stride[4] = {
175 static const char * const chan_sel[4] = {
182 static const char * const debug_ctrl[2] = {
187 static const char * const saturate[2] = {
192 static const char * const accwr[2] = {
197 static const char * const wectrl[2] = {
202 static const char * const exec_size[8] = {
211 static const char * const pred_inv[2] = {
216 static const char * const pred_ctrl_align16[16] = {
226 static const char * const pred_ctrl_align1[16] = {
240 static const char * const thread_ctrl[4] = {
245 static const char * const compr_ctrl[4] = {
252 static const char * const dep_ctrl[4] = {
256 [3] = "NoDDClr,NoDDChk",
259 static const char * const mask_ctrl[4] = {
264 static const char * const access_mode[2] = {
269 static const char * const reg_encoding[8] = {
279 const int reg_type_size[8] = {
289 static const char * const reg_file[4] = {
296 static const char * const writemask[16] = {
315 static const char * const end_of_thread[2] = {
320 static const char * const target_function[16] = {
321 [BRW_SFID_NULL] = "null",
322 [BRW_SFID_MATH] = "math",
323 [BRW_SFID_SAMPLER] = "sampler",
324 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
325 [BRW_SFID_DATAPORT_READ] = "read",
326 [BRW_SFID_DATAPORT_WRITE] = "write",
327 [BRW_SFID_URB] = "urb",
328 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner"
331 static const char * const target_function_gen6[16] = {
332 [BRW_SFID_NULL] = "null",
333 [BRW_SFID_MATH] = "math",
334 [BRW_SFID_SAMPLER] = "sampler",
335 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
336 [BRW_SFID_URB] = "urb",
337 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
338 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
339 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
340 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
341 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data"
344 static const char * const dp_rc_msg_type_gen6[16] = {
345 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
346 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
347 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
348 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
349 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read",
350 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
351 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
352 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
353 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write",
354 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
355 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write",
356 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
357 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
358 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write",
361 static const char * const math_function[16] = {
362 [BRW_MATH_FUNCTION_INV] = "inv",
363 [BRW_MATH_FUNCTION_LOG] = "log",
364 [BRW_MATH_FUNCTION_EXP] = "exp",
365 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
366 [BRW_MATH_FUNCTION_RSQ] = "rsq",
367 [BRW_MATH_FUNCTION_SIN] = "sin",
368 [BRW_MATH_FUNCTION_COS] = "cos",
369 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
370 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
371 [BRW_MATH_FUNCTION_POW] = "pow",
372 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
373 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
374 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
377 static const char * const math_saturate[2] = {
382 static const char * const math_signed[2] = {
387 static const char * const math_scalar[2] = {
392 static const char * const math_precision[2] = {
394 [1] = "partial_precision"
397 static const char * const urb_opcode[2] = {
402 static const char * const urb_swizzle[4] = {
403 [BRW_URB_SWIZZLE_NONE] = "",
404 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
405 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
408 static const char * const urb_allocate[2] = {
413 static const char * const urb_used[2] = {
418 static const char * const urb_complete[2] = {
423 static const char * const sampler_target_format[4] = {
432 static int string (FILE *file, const char *string)
434 fputs (string, file);
435 column += strlen (string);
439 static int format (FILE *f, const char *format, ...)
443 va_start (args, format);
445 vsnprintf (buf, sizeof (buf) - 1, format, args);
451 static int newline (FILE *f)
458 static int pad (FILE *f, int c)
466 static int control (FILE *file, const char *name, const char * const ctrl[],
467 GLuint id, int *space)
470 fprintf (file, "*** invalid %s value %d ",
478 string (file, ctrl[id]);
485 static int print_opcode (FILE *file, int id)
487 if (!opcode[id].name) {
488 format (file, "*** invalid opcode value %d ", id);
491 string (file, opcode[id].name);
495 static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
499 /* Clear the Compr4 instruction compression bit. */
500 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
501 _reg_nr &= ~(1 << 7);
503 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
504 switch (_reg_nr & 0xf0) {
506 string (file, "null");
508 case BRW_ARF_ADDRESS:
509 format (file, "a%d", _reg_nr & 0x0f);
511 case BRW_ARF_ACCUMULATOR:
512 format (file, "acc%d", _reg_nr & 0x0f);
515 format (file, "f%d", _reg_nr & 0x0f);
518 format (file, "mask%d", _reg_nr & 0x0f);
520 case BRW_ARF_MASK_STACK:
521 format (file, "msd%d", _reg_nr & 0x0f);
524 format (file, "sr%d", _reg_nr & 0x0f);
526 case BRW_ARF_CONTROL:
527 format (file, "cr%d", _reg_nr & 0x0f);
529 case BRW_ARF_NOTIFICATION_COUNT:
530 format (file, "n%d", _reg_nr & 0x0f);
537 format (file, "ARF%d", _reg_nr);
541 err |= control (file, "src reg file", reg_file, _reg_file, NULL);
542 format (file, "%d", _reg_nr);
547 static int dest (FILE *file, struct brw_instruction *inst)
551 if (inst->header.access_mode == BRW_ALIGN_1)
553 if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
555 err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
558 if (inst->bits1.da1.dest_subreg_nr)
559 format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
560 reg_type_size[inst->bits1.da1.dest_reg_type]);
562 err |= control (file, "horiz stride", horiz_stride, inst->bits1.da1.dest_horiz_stride, NULL);
564 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
568 string (file, "g[a0");
569 if (inst->bits1.ia1.dest_subreg_nr)
570 format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
571 reg_type_size[inst->bits1.ia1.dest_reg_type]);
572 if (inst->bits1.ia1.dest_indirect_offset)
573 format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
575 err |= control (file, "horiz stride", horiz_stride, inst->bits1.ia1.dest_horiz_stride, NULL);
577 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL);
582 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
584 err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr);
587 if (inst->bits1.da16.dest_subreg_nr)
588 format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
589 reg_type_size[inst->bits1.da16.dest_reg_type]);
590 string (file, "<1>");
591 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
592 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
597 string (file, "Indirect align16 address mode not supported");
604 static int dest_3src (FILE *file, struct brw_instruction *inst)
609 if (inst->bits1.da3src.dest_reg_file)
610 reg_file = BRW_MESSAGE_REGISTER_FILE;
612 reg_file = BRW_GENERAL_REGISTER_FILE;
614 err |= reg (file, reg_file, inst->bits1.da3src.dest_reg_nr);
617 if (inst->bits1.da3src.dest_subreg_nr)
618 format (file, ".%d", inst->bits1.da3src.dest_subreg_nr);
619 string (file, "<1>");
620 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
621 err |= control (file, "dest reg encoding", reg_encoding, BRW_REGISTER_TYPE_F, NULL);
626 static int src_align1_region (FILE *file,
627 GLuint _vert_stride, GLuint _width, GLuint _horiz_stride)
631 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
633 err |= control (file, "width", width, _width, NULL);
635 err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
640 static int src_da1 (FILE *file, GLuint type, GLuint _reg_file,
641 GLuint _vert_stride, GLuint _width, GLuint _horiz_stride,
642 GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate)
645 err |= control (file, "negate", negate, _negate, NULL);
646 err |= control (file, "abs", _abs, __abs, NULL);
648 err |= reg (file, _reg_file, reg_num);
652 format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
653 src_align1_region (file, _vert_stride, _width, _horiz_stride);
654 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
658 static int src_ia1 (FILE *file,
662 GLuint _addr_subreg_nr,
666 GLuint _horiz_stride,
671 err |= control (file, "negate", negate, _negate, NULL);
672 err |= control (file, "abs", _abs, __abs, NULL);
674 string (file, "g[a0");
676 format (file, ".%d", _addr_subreg_nr);
678 format (file, " %d", _addr_imm);
680 src_align1_region (file, _vert_stride, _width, _horiz_stride);
681 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
685 static int src_da16 (FILE *file,
699 err |= control (file, "negate", negate, _negate, NULL);
700 err |= control (file, "abs", _abs, __abs, NULL);
702 err |= reg (file, _reg_file, _reg_nr);
706 /* bit4 for subreg number byte addressing. Make this same meaning as
707 in da1 case, so output looks consistent. */
708 format (file, ".%d", 16 / reg_type_size[_reg_type]);
710 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
711 string (file, ",4,1>");
713 * Three kinds of swizzle display:
714 * identity - nothing printed
715 * 1->all - print the single channel
716 * 1->1 - print the mapping
718 if (swz_x == BRW_CHANNEL_X &&
719 swz_y == BRW_CHANNEL_Y &&
720 swz_z == BRW_CHANNEL_Z &&
721 swz_w == BRW_CHANNEL_W)
725 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
728 err |= control (file, "channel select", chan_sel, swz_x, NULL);
733 err |= control (file, "channel select", chan_sel, swz_x, NULL);
734 err |= control (file, "channel select", chan_sel, swz_y, NULL);
735 err |= control (file, "channel select", chan_sel, swz_z, NULL);
736 err |= control (file, "channel select", chan_sel, swz_w, NULL);
738 err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
742 static int src0_3src (FILE *file, struct brw_instruction *inst)
745 GLuint swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
746 GLuint swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
747 GLuint swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
748 GLuint swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
750 err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL);
751 err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL);
753 err |= reg (file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr);
756 if (inst->bits2.da3src.src0_subreg_nr)
757 format (file, ".%d", inst->bits2.da3src.src0_subreg_nr);
758 string (file, "<4,1,1>");
759 err |= control (file, "src da16 reg type", reg_encoding,
760 BRW_REGISTER_TYPE_F, NULL);
762 * Three kinds of swizzle display:
763 * identity - nothing printed
764 * 1->all - print the single channel
765 * 1->1 - print the mapping
767 if (swz_x == BRW_CHANNEL_X &&
768 swz_y == BRW_CHANNEL_Y &&
769 swz_z == BRW_CHANNEL_Z &&
770 swz_w == BRW_CHANNEL_W)
774 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
777 err |= control (file, "channel select", chan_sel, swz_x, NULL);
782 err |= control (file, "channel select", chan_sel, swz_x, NULL);
783 err |= control (file, "channel select", chan_sel, swz_y, NULL);
784 err |= control (file, "channel select", chan_sel, swz_z, NULL);
785 err |= control (file, "channel select", chan_sel, swz_w, NULL);
790 static int src1_3src (FILE *file, struct brw_instruction *inst)
793 GLuint swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
794 GLuint swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
795 GLuint swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
796 GLuint swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
797 GLuint src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
798 (inst->bits3.da3src.src1_subreg_nr_high << 2));
800 err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate,
802 err |= control (file, "abs", _abs, inst->bits1.da3src.src1_abs, NULL);
804 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
805 inst->bits3.da3src.src1_reg_nr);
809 format (file, ".%d", src1_subreg_nr);
810 string (file, "<4,1,1>");
811 err |= control (file, "src da16 reg type", reg_encoding,
812 BRW_REGISTER_TYPE_F, NULL);
814 * Three kinds of swizzle display:
815 * identity - nothing printed
816 * 1->all - print the single channel
817 * 1->1 - print the mapping
819 if (swz_x == BRW_CHANNEL_X &&
820 swz_y == BRW_CHANNEL_Y &&
821 swz_z == BRW_CHANNEL_Z &&
822 swz_w == BRW_CHANNEL_W)
826 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
829 err |= control (file, "channel select", chan_sel, swz_x, NULL);
834 err |= control (file, "channel select", chan_sel, swz_x, NULL);
835 err |= control (file, "channel select", chan_sel, swz_y, NULL);
836 err |= control (file, "channel select", chan_sel, swz_z, NULL);
837 err |= control (file, "channel select", chan_sel, swz_w, NULL);
843 static int src2_3src (FILE *file, struct brw_instruction *inst)
846 GLuint swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
847 GLuint swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
848 GLuint swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
849 GLuint swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
851 err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate,
853 err |= control (file, "abs", _abs, inst->bits1.da3src.src2_abs, NULL);
855 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
856 inst->bits3.da3src.src2_reg_nr);
859 if (inst->bits3.da3src.src2_subreg_nr)
860 format (file, ".%d", inst->bits3.da3src.src2_subreg_nr);
861 string (file, "<4,1,1>");
862 err |= control (file, "src da16 reg type", reg_encoding,
863 BRW_REGISTER_TYPE_F, NULL);
865 * Three kinds of swizzle display:
866 * identity - nothing printed
867 * 1->all - print the single channel
868 * 1->1 - print the mapping
870 if (swz_x == BRW_CHANNEL_X &&
871 swz_y == BRW_CHANNEL_Y &&
872 swz_z == BRW_CHANNEL_Z &&
873 swz_w == BRW_CHANNEL_W)
877 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
880 err |= control (file, "channel select", chan_sel, swz_x, NULL);
885 err |= control (file, "channel select", chan_sel, swz_x, NULL);
886 err |= control (file, "channel select", chan_sel, swz_y, NULL);
887 err |= control (file, "channel select", chan_sel, swz_z, NULL);
888 err |= control (file, "channel select", chan_sel, swz_w, NULL);
893 static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
895 case BRW_REGISTER_TYPE_UD:
896 format (file, "0x%08xUD", inst->bits3.ud);
898 case BRW_REGISTER_TYPE_D:
899 format (file, "%dD", inst->bits3.d);
901 case BRW_REGISTER_TYPE_UW:
902 format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
904 case BRW_REGISTER_TYPE_W:
905 format (file, "%dW", (int16_t) inst->bits3.d);
907 case BRW_REGISTER_TYPE_UB:
908 format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
910 case BRW_REGISTER_TYPE_VF:
911 format (file, "Vector Float");
913 case BRW_REGISTER_TYPE_V:
914 format (file, "0x%08xV", inst->bits3.ud);
916 case BRW_REGISTER_TYPE_F:
917 format (file, "%-gF", inst->bits3.f);
922 static int src0 (FILE *file, struct brw_instruction *inst)
924 if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
925 return imm (file, inst->bits1.da1.src0_reg_type,
927 else if (inst->header.access_mode == BRW_ALIGN_1)
929 if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT)
931 return src_da1 (file,
932 inst->bits1.da1.src0_reg_type,
933 inst->bits1.da1.src0_reg_file,
934 inst->bits2.da1.src0_vert_stride,
935 inst->bits2.da1.src0_width,
936 inst->bits2.da1.src0_horiz_stride,
937 inst->bits2.da1.src0_reg_nr,
938 inst->bits2.da1.src0_subreg_nr,
939 inst->bits2.da1.src0_abs,
940 inst->bits2.da1.src0_negate);
944 return src_ia1 (file,
945 inst->bits1.ia1.src0_reg_type,
946 inst->bits1.ia1.src0_reg_file,
947 inst->bits2.ia1.src0_indirect_offset,
948 inst->bits2.ia1.src0_subreg_nr,
949 inst->bits2.ia1.src0_negate,
950 inst->bits2.ia1.src0_abs,
951 inst->bits2.ia1.src0_address_mode,
952 inst->bits2.ia1.src0_horiz_stride,
953 inst->bits2.ia1.src0_width,
954 inst->bits2.ia1.src0_vert_stride);
959 if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT)
961 return src_da16 (file,
962 inst->bits1.da16.src0_reg_type,
963 inst->bits1.da16.src0_reg_file,
964 inst->bits2.da16.src0_vert_stride,
965 inst->bits2.da16.src0_reg_nr,
966 inst->bits2.da16.src0_subreg_nr,
967 inst->bits2.da16.src0_abs,
968 inst->bits2.da16.src0_negate,
969 inst->bits2.da16.src0_swz_x,
970 inst->bits2.da16.src0_swz_y,
971 inst->bits2.da16.src0_swz_z,
972 inst->bits2.da16.src0_swz_w);
976 string (file, "Indirect align16 address mode not supported");
982 static int src1 (FILE *file, struct brw_instruction *inst)
984 if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
985 return imm (file, inst->bits1.da1.src1_reg_type,
987 else if (inst->header.access_mode == BRW_ALIGN_1)
989 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT)
991 return src_da1 (file,
992 inst->bits1.da1.src1_reg_type,
993 inst->bits1.da1.src1_reg_file,
994 inst->bits3.da1.src1_vert_stride,
995 inst->bits3.da1.src1_width,
996 inst->bits3.da1.src1_horiz_stride,
997 inst->bits3.da1.src1_reg_nr,
998 inst->bits3.da1.src1_subreg_nr,
999 inst->bits3.da1.src1_abs,
1000 inst->bits3.da1.src1_negate);
1004 return src_ia1 (file,
1005 inst->bits1.ia1.src1_reg_type,
1006 inst->bits1.ia1.src1_reg_file,
1007 inst->bits3.ia1.src1_indirect_offset,
1008 inst->bits3.ia1.src1_subreg_nr,
1009 inst->bits3.ia1.src1_negate,
1010 inst->bits3.ia1.src1_abs,
1011 inst->bits3.ia1.src1_address_mode,
1012 inst->bits3.ia1.src1_horiz_stride,
1013 inst->bits3.ia1.src1_width,
1014 inst->bits3.ia1.src1_vert_stride);
1019 if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT)
1021 return src_da16 (file,
1022 inst->bits1.da16.src1_reg_type,
1023 inst->bits1.da16.src1_reg_file,
1024 inst->bits3.da16.src1_vert_stride,
1025 inst->bits3.da16.src1_reg_nr,
1026 inst->bits3.da16.src1_subreg_nr,
1027 inst->bits3.da16.src1_abs,
1028 inst->bits3.da16.src1_negate,
1029 inst->bits3.da16.src1_swz_x,
1030 inst->bits3.da16.src1_swz_y,
1031 inst->bits3.da16.src1_swz_z,
1032 inst->bits3.da16.src1_swz_w);
1036 string (file, "Indirect align16 address mode not supported");
1051 static int qtr_ctrl(FILE *file, struct brw_instruction *inst)
1053 int qtr_ctl = inst->header.compression_control;
1054 int exec_size = esize[inst->header.execution_size];
1056 if (exec_size == 8) {
1059 string (file, " 1Q");
1062 string (file, " 2Q");
1065 string (file, " 3Q");
1068 string (file, " 4Q");
1071 } else if (exec_size == 16){
1073 string (file, " 1H");
1075 string (file, " 2H");
1080 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
1085 if (inst->header.predicate_control) {
1087 err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
1088 format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1089 if (inst->bits2.da1.flag_subreg_nr)
1090 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1091 if (inst->header.access_mode == BRW_ALIGN_1)
1092 err |= control (file, "predicate control align1", pred_ctrl_align1,
1093 inst->header.predicate_control, NULL);
1095 err |= control (file, "predicate control align16", pred_ctrl_align16,
1096 inst->header.predicate_control, NULL);
1097 string (file, ") ");
1100 err |= print_opcode (file, inst->header.opcode);
1101 err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
1102 err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
1104 if (inst->header.opcode == BRW_OPCODE_MATH) {
1106 err |= control (file, "function", math_function,
1107 inst->header.destreg__conditionalmod, NULL);
1108 } else if (inst->header.opcode != BRW_OPCODE_SEND &&
1109 inst->header.opcode != BRW_OPCODE_SENDC) {
1110 err |= control (file, "conditional modifier", conditional_modifier,
1111 inst->header.destreg__conditionalmod, NULL);
1113 /* If we're using the conditional modifier, print which flags reg is
1114 * used for it. Note that on gen6+, the embedded-condition SEL and
1115 * control flow doesn't update flags.
1117 if (inst->header.destreg__conditionalmod &&
1118 (gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL &&
1119 inst->header.opcode != BRW_OPCODE_IF &&
1120 inst->header.opcode != BRW_OPCODE_WHILE))) {
1121 format (file, ".f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1122 if (inst->bits2.da1.flag_subreg_nr)
1123 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1127 if (inst->header.opcode != BRW_OPCODE_NOP) {
1129 err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
1133 if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6)
1134 format (file, " %d", inst->header.destreg__conditionalmod);
1136 if (opcode[inst->header.opcode].nsrc == 3) {
1138 err |= dest_3src (file, inst);
1141 err |= src0_3src (file, inst);
1144 err |= src1_3src (file, inst);
1147 err |= src2_3src (file, inst);
1149 if (opcode[inst->header.opcode].ndst > 0) {
1151 err |= dest (file, inst);
1152 } else if (gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE ||
1153 inst->header.opcode == BRW_OPCODE_ENDIF ||
1154 inst->header.opcode == BRW_OPCODE_WHILE)) {
1155 format (file, " %d", inst->bits3.break_cont.jip);
1156 } else if (gen == 6 && (inst->header.opcode == BRW_OPCODE_IF ||
1157 inst->header.opcode == BRW_OPCODE_ELSE ||
1158 inst->header.opcode == BRW_OPCODE_ENDIF ||
1159 inst->header.opcode == BRW_OPCODE_WHILE)) {
1160 format (file, " %d", inst->bits1.branch_gen6.jump_count);
1161 } else if ((gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
1162 inst->header.opcode == BRW_OPCODE_CONTINUE ||
1163 inst->header.opcode == BRW_OPCODE_HALT)) ||
1164 (gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) {
1165 format (file, " %d %d", inst->bits3.break_cont.uip, inst->bits3.break_cont.jip);
1166 } else if (inst->header.opcode == BRW_OPCODE_JMPI) {
1167 format (file, " %d", inst->bits3.d);
1170 if (opcode[inst->header.opcode].nsrc > 0) {
1172 err |= src0 (file, inst);
1174 if (opcode[inst->header.opcode].nsrc > 1) {
1176 err |= src1 (file, inst);
1180 if (inst->header.opcode == BRW_OPCODE_SEND ||
1181 inst->header.opcode == BRW_OPCODE_SENDC) {
1182 enum brw_message_target target;
1185 target = inst->header.destreg__conditionalmod;
1187 target = inst->bits2.send_gen5.sfid;
1189 target = inst->bits3.generic.msg_target;
1196 err |= control (file, "target function", target_function_gen6,
1199 err |= control (file, "target function", target_function,
1205 err |= control (file, "math function", math_function,
1206 inst->bits3.math.function, &space);
1207 err |= control (file, "math saturate", math_saturate,
1208 inst->bits3.math.saturate, &space);
1209 err |= control (file, "math signed", math_signed,
1210 inst->bits3.math.int_type, &space);
1211 err |= control (file, "math scalar", math_scalar,
1212 inst->bits3.math.data_type, &space);
1213 err |= control (file, "math precision", math_precision,
1214 inst->bits3.math.precision, &space);
1216 case BRW_SFID_SAMPLER:
1218 format (file, " (%d, %d, %d, %d)",
1219 inst->bits3.sampler_gen7.binding_table_index,
1220 inst->bits3.sampler_gen7.sampler,
1221 inst->bits3.sampler_gen7.msg_type,
1222 inst->bits3.sampler_gen7.simd_mode);
1223 } else if (gen >= 5) {
1224 format (file, " (%d, %d, %d, %d)",
1225 inst->bits3.sampler_gen5.binding_table_index,
1226 inst->bits3.sampler_gen5.sampler,
1227 inst->bits3.sampler_gen5.msg_type,
1228 inst->bits3.sampler_gen5.simd_mode);
1229 } else if (0 /* FINISHME: is_g4x */) {
1230 format (file, " (%d, %d)",
1231 inst->bits3.sampler_g4x.binding_table_index,
1232 inst->bits3.sampler_g4x.sampler);
1234 format (file, " (%d, %d, ",
1235 inst->bits3.sampler.binding_table_index,
1236 inst->bits3.sampler.sampler);
1237 err |= control (file, "sampler target format",
1238 sampler_target_format,
1239 inst->bits3.sampler.return_format, NULL);
1243 case BRW_SFID_DATAPORT_READ:
1245 format (file, " (%d, %d, %d, %d)",
1246 inst->bits3.gen6_dp.binding_table_index,
1247 inst->bits3.gen6_dp.msg_control,
1248 inst->bits3.gen6_dp.msg_type,
1249 inst->bits3.gen6_dp.send_commit_msg);
1250 } else if (gen >= 5 /* FINISHME: || is_g4x */) {
1251 format (file, " (%d, %d, %d)",
1252 inst->bits3.dp_read_gen5.binding_table_index,
1253 inst->bits3.dp_read_gen5.msg_control,
1254 inst->bits3.dp_read_gen5.msg_type);
1256 format (file, " (%d, %d, %d)",
1257 inst->bits3.dp_read.binding_table_index,
1258 inst->bits3.dp_read.msg_control,
1259 inst->bits3.dp_read.msg_type);
1263 case BRW_SFID_DATAPORT_WRITE:
1265 format (file, " (");
1267 err |= control (file, "DP rc message type",
1268 dp_rc_msg_type_gen6,
1269 inst->bits3.gen7_dp.msg_type, &space);
1271 format (file, ", %d, %d, %d)",
1272 inst->bits3.gen7_dp.binding_table_index,
1273 inst->bits3.gen7_dp.msg_control,
1274 inst->bits3.gen7_dp.msg_type);
1275 } else if (gen == 6) {
1276 format (file, " (");
1278 err |= control (file, "DP rc message type",
1279 dp_rc_msg_type_gen6,
1280 inst->bits3.gen6_dp.msg_type, &space);
1282 format (file, ", %d, %d, %d, %d)",
1283 inst->bits3.gen6_dp.binding_table_index,
1284 inst->bits3.gen6_dp.msg_control,
1285 inst->bits3.gen6_dp.msg_type,
1286 inst->bits3.gen6_dp.send_commit_msg);
1288 format (file, " (%d, %d, %d, %d)",
1289 inst->bits3.dp_write.binding_table_index,
1290 (inst->bits3.dp_write.last_render_target << 3) |
1291 inst->bits3.dp_write.msg_control,
1292 inst->bits3.dp_write.msg_type,
1293 inst->bits3.dp_write.send_commit_msg);
1299 format (file, " %d", inst->bits3.urb_gen5.offset);
1301 format (file, " %d", inst->bits3.urb.offset);
1306 err |= control (file, "urb opcode", urb_opcode,
1307 inst->bits3.urb_gen5.opcode, &space);
1309 err |= control (file, "urb swizzle", urb_swizzle,
1310 inst->bits3.urb.swizzle_control, &space);
1311 err |= control (file, "urb allocate", urb_allocate,
1312 inst->bits3.urb.allocate, &space);
1313 err |= control (file, "urb used", urb_used,
1314 inst->bits3.urb.used, &space);
1315 err |= control (file, "urb complete", urb_complete,
1316 inst->bits3.urb.complete, &space);
1318 case BRW_SFID_THREAD_SPAWNER:
1320 case GEN7_SFID_DATAPORT_DATA_CACHE:
1321 format (file, " (%d, %d, %d)",
1322 inst->bits3.gen7_dp.binding_table_index,
1323 inst->bits3.gen7_dp.msg_control,
1324 inst->bits3.gen7_dp.msg_type);
1329 format (file, "unsupported target %d", target);
1335 format (file, "mlen %d",
1336 inst->bits3.generic_gen5.msg_length);
1337 format (file, " rlen %d",
1338 inst->bits3.generic_gen5.response_length);
1340 format (file, "mlen %d",
1341 inst->bits3.generic.msg_length);
1342 format (file, " rlen %d",
1343 inst->bits3.generic.response_length);
1347 if (inst->header.opcode != BRW_OPCODE_NOP) {
1350 err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
1352 err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space);
1354 err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
1355 err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
1358 err |= qtr_ctrl (file, inst);
1360 if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED &&
1361 opcode[inst->header.opcode].ndst > 0 &&
1362 inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE &&
1363 inst->bits1.da1.dest_reg_nr & (1 << 7)) {
1364 format (file, " compr4");
1366 err |= control (file, "compression control", compr_ctrl,
1367 inst->header.compression_control, &space);
1371 err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
1373 err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
1374 if (inst->header.opcode == BRW_OPCODE_SEND ||
1375 inst->header.opcode == BRW_OPCODE_SENDC)
1376 err |= control (file, "end of thread", end_of_thread,
1377 inst->bits3.generic.end_of_thread, &space);