src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
  68       return 120;
  69    case PIPE_CAP_ENDIANNESS:
  70       return PIPE_ENDIAN_LITTLE;
  71    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  72       return 16;
  73    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  74       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  75    case PIPE_CAP_MAX_VIEWPORTS:
  76       return 1;
  77    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  78       return 2048;
  79    /* supported capabilities */
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SWIZZLE:
  86    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  87    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  91    case PIPE_CAP_TGSI_TEXCOORD:
  92    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  93    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  94    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  95    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
  98       return 1;
  99    /* nv35 capabilities */
 100    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 101       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 102    /* nv4x capabilities */
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_NPOT_TEXTURES:
 105    case PIPE_CAP_CONDITIONAL_RENDER:
 106    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 107    case PIPE_CAP_PRIMITIVE_RESTART:
 108       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 109    /* unsupported */
 110    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 111    case PIPE_CAP_SM3:
 112    case PIPE_CAP_INDEP_BLEND_ENABLE:
 113    case PIPE_CAP_INDEP_BLEND_FUNC:
 114    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 115    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 116    case PIPE_CAP_TGSI_INSTANCEID:
 117    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 121    case PIPE_CAP_MIN_TEXEL_OFFSET:
 122    case PIPE_CAP_MAX_TEXEL_OFFSET:
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 128    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 129    case PIPE_CAP_MAX_VERTEX_STREAMS:
 130    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 131    case PIPE_CAP_TEXTURE_BARRIER:
 132    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 134    case PIPE_CAP_CUBE_MAP_ARRAY:
 135    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 136    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 137    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 138    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 139    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 140    case PIPE_CAP_START_INSTANCE:
 141    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 142    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 143    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 144    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 145    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 146    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 147    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 148    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 149    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 150    case PIPE_CAP_TEXTURE_GATHER_SM5:
 151    case PIPE_CAP_FAKE_SW_MSAA:
 152    case PIPE_CAP_TEXTURE_QUERY_LOD:
 153    case PIPE_CAP_SAMPLE_SHADING:
 154    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 155    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 156    case PIPE_CAP_USER_VERTEX_BUFFERS:
 157    case PIPE_CAP_COMPUTE:
 158    case PIPE_CAP_DRAW_INDIRECT:
 159    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 161    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 162    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 163    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 164    case PIPE_CAP_CLIP_HALFZ:
 165    case PIPE_CAP_VERTEXID_NOBASE:
 166    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 167    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 168    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 169    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 170    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 171    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 172    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 173    case PIPE_CAP_TGSI_TXQS:
 174    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 175    case PIPE_CAP_SHAREABLE_SHADERS:
 176    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 177    case PIPE_CAP_CLEAR_TEXTURE:
 178    case PIPE_CAP_DRAW_PARAMETERS:
 179    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 180    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 181    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 182    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 183    case PIPE_CAP_INVALIDATE_BUFFER:
 184    case PIPE_CAP_GENERATE_MIPMAP:
 185    case PIPE_CAP_STRING_MARKER:
 186    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 187    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 188    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 189    case PIPE_CAP_QUERY_MEMORY_INFO:
 190    case PIPE_CAP_PCI_GROUP:
 191    case PIPE_CAP_PCI_BUS:
 192    case PIPE_CAP_PCI_DEVICE:
 193    case PIPE_CAP_PCI_FUNCTION:
 194    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 195    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 196    case PIPE_CAP_CULL_DISTANCE:
 197    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 198    case PIPE_CAP_TGSI_VOTE:
 199    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 200    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 201    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 202    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 203    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 204    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 205    case PIPE_CAP_NATIVE_FENCE_FD:
 206    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 207    case PIPE_CAP_TGSI_FS_FBFETCH:
 208    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 209    case PIPE_CAP_DOUBLES:
 210    case PIPE_CAP_INT64:
 211    case PIPE_CAP_INT64_DIVMOD:
 212    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 213    case PIPE_CAP_TGSI_CLOCK:
 214    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 215    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 216    case PIPE_CAP_TGSI_BALLOT:
 217    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 218    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 219    case PIPE_CAP_POST_DEPTH_COVERAGE:
 220    case PIPE_CAP_BINDLESS_TEXTURE:
 221    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 222    case PIPE_CAP_QUERY_SO_OVERFLOW:
 223    case PIPE_CAP_MEMOBJ:
 224    case PIPE_CAP_LOAD_CONSTBUF:
 225    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 226    case PIPE_CAP_TILE_RASTER_ORDER:
 227    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 228    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 229    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 230    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 231    case PIPE_CAP_FENCE_SIGNAL:
 232    case PIPE_CAP_CONSTBUF0_FLAGS:
 233    case PIPE_CAP_PACKED_UNIFORMS:
 234    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 235    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 236    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 237    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 238    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 239    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 240    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 241       return 0;
 242
 243    case PIPE_CAP_VENDOR_ID:
 244       return 0x10de;
 245    case PIPE_CAP_DEVICE_ID: {
 246       uint64_t device_id;
 247       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 248          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 249          return -1;
 250       }
 251       return device_id;
 252    }
 253    case PIPE_CAP_ACCELERATED:
 254       return 1;
 255    case PIPE_CAP_VIDEO_MEMORY:
 256       return dev->vram_size >> 20;
 257    case PIPE_CAP_UMA:
 258       return 0;
 259    }
 260
 261    debug_printf("unknown param %d\n", param);
 262    return 0;
 263 }
 264
 265 static float
 266 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 267 {
 268    struct nv30_screen *screen = nv30_screen(pscreen);
 269    struct nouveau_object *eng3d = screen->eng3d;
 270
 271    switch (param) {
 272    case PIPE_CAPF_MAX_LINE_WIDTH:
 273    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 274       return 10.0;
 275    case PIPE_CAPF_MAX_POINT_WIDTH:
 276    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 277       return 64.0;
 278    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 279       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 280    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 281       return 15.0;
 282    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 283    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 284    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 285       return 0.0;
 286    default:
 287       debug_printf("unknown paramf %d\n", param);
 288       return 0;
 289    }
 290 }
 291
 292 static int
 293 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 294                              enum pipe_shader_type shader,
 295                              enum pipe_shader_cap param)
 296 {
 297    struct nv30_screen *screen = nv30_screen(pscreen);
 298    struct nouveau_object *eng3d = screen->eng3d;
 299
 300    switch (shader) {
 301    case PIPE_SHADER_VERTEX:
 302       switch (param) {
 303       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 304       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 305          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 306       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 307       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 308          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 309       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 310          return 0;
 311       case PIPE_SHADER_CAP_MAX_INPUTS:
 312       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 313          return 16;
 314       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 315          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 316       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 317          return 1;
 318       case PIPE_SHADER_CAP_MAX_TEMPS:
 319          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 320       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 321          return 32;
 322       case PIPE_SHADER_CAP_PREFERRED_IR:
 323          return PIPE_SHADER_IR_TGSI;
 324       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 325       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 326          return 0;
 327       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 328       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 329       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 330       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 331       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 332       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 333       case PIPE_SHADER_CAP_SUBROUTINES:
 334       case PIPE_SHADER_CAP_INTEGERS:
 335       case PIPE_SHADER_CAP_INT64_ATOMICS:
 336       case PIPE_SHADER_CAP_FP16:
 337       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 338       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 339       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 340       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 341       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 342       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 343       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 344       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 345       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 346       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 347       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 348       case PIPE_SHADER_CAP_SCALAR_ISA:
 349          return 0;
 350       default:
 351          debug_printf("unknown vertex shader param %d\n", param);
 352          return 0;
 353       }
 354       break;
 355    case PIPE_SHADER_FRAGMENT:
 356       switch (param) {
 357       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 358       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 359       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 360       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 361          return 4096;
 362       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 363          return 0;
 364       case PIPE_SHADER_CAP_MAX_INPUTS:
 365          return 8; /* should be possible to do 10 with nv4x */
 366       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 367          return 4;
 368       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 369          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 370       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 371          return 1;
 372       case PIPE_SHADER_CAP_MAX_TEMPS:
 373          return 32;
 374       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 375       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 376          return 16;
 377       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 378          return 32;
 379       case PIPE_SHADER_CAP_PREFERRED_IR:
 380          return PIPE_SHADER_IR_TGSI;
 381       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 382       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 383       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 384       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 385       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 386       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 387       case PIPE_SHADER_CAP_SUBROUTINES:
 388       case PIPE_SHADER_CAP_INTEGERS:
 389       case PIPE_SHADER_CAP_FP16:
 390       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 391       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 392       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 393       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 394       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 395       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 396       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 397       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 398       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 399       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 400       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 401       case PIPE_SHADER_CAP_SCALAR_ISA:
 402          return 0;
 403       default:
 404          debug_printf("unknown fragment shader param %d\n", param);
 405          return 0;
 406       }
 407       break;
 408    default:
 409       return 0;
 410    }
 411 }
 412
 413 static boolean
 414 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 415                                 enum pipe_format format,
 416                                 enum pipe_texture_target target,
 417                                 unsigned sample_count,
 418                                 unsigned storage_sample_count,
 419                                 unsigned bindings)
 420 {
 421    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 422       return false;
 423
 424    if (!(0x00000017 & (1 << sample_count)))
 425       return false;
 426
 427    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 428       return false;
 429
 430    /* shared is always supported */
 431    bindings &= ~PIPE_BIND_SHARED;
 432
 433    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 434 }
 435
 436 static void
 437 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 438 {
 439    struct nv30_screen *screen = nv30_screen(pscreen);
 440    struct nouveau_pushbuf *push = screen->base.pushbuf;
 441
 442    *sequence = ++screen->base.fence.sequence;
 443
 444    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 445    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 446               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 447    PUSH_DATA (push, 0);
 448    PUSH_DATA (push, *sequence);
 449 }
 450
 451 static uint32_t
 452 nv30_screen_fence_update(struct pipe_screen *pscreen)
 453 {
 454    struct nv30_screen *screen = nv30_screen(pscreen);
 455    struct nv04_notify *fence = screen->fence->data;
 456    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 457 }
 458
 459 static void
 460 nv30_screen_destroy(struct pipe_screen *pscreen)
 461 {
 462    struct nv30_screen *screen = nv30_screen(pscreen);
 463
 464    if (!nouveau_drm_screen_unref(&screen->base))
 465       return;
 466
 467    if (screen->base.fence.current) {
 468       struct nouveau_fence *current = NULL;
 469
 470       /* nouveau_fence_wait will create a new current fence, so wait on the
 471        * _current_ one, and remove both.
 472        */
 473       nouveau_fence_ref(screen->base.fence.current, &current);
 474       nouveau_fence_wait(current, NULL);
 475       nouveau_fence_ref(NULL, &current);
 476       nouveau_fence_ref(NULL, &screen->base.fence.current);
 477    }
 478
 479    nouveau_bo_ref(NULL, &screen->notify);
 480
 481    nouveau_heap_destroy(&screen->query_heap);
 482    nouveau_heap_destroy(&screen->vp_exec_heap);
 483    nouveau_heap_destroy(&screen->vp_data_heap);
 484
 485    nouveau_object_del(&screen->query);
 486    nouveau_object_del(&screen->fence);
 487    nouveau_object_del(&screen->ntfy);
 488
 489    nouveau_object_del(&screen->sifm);
 490    nouveau_object_del(&screen->swzsurf);
 491    nouveau_object_del(&screen->surf2d);
 492    nouveau_object_del(&screen->m2mf);
 493    nouveau_object_del(&screen->eng3d);
 494    nouveau_object_del(&screen->null);
 495
 496    nouveau_screen_fini(&screen->base);
 497    FREE(screen);
 498 }
 499
 500 #define FAIL_SCREEN_INIT(str, err)                    \
 501    do {                                               \
 502       NOUVEAU_ERR(str, err);                          \
 503       screen->base.base.context_create = NULL;        \
 504       return &screen->base;                           \
 505    } while(0)
 506
 507 struct nouveau_screen *
 508 nv30_screen_create(struct nouveau_device *dev)
 509 {
 510    struct nv30_screen *screen;
 511    struct pipe_screen *pscreen;
 512    struct nouveau_pushbuf *push;
 513    struct nv04_fifo *fifo;
 514    unsigned oclass = 0;
 515    int ret, i;
 516
 517    switch (dev->chipset & 0xf0) {
 518    case 0x30:
 519       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 520          oclass = NV30_3D_CLASS;
 521       else
 522       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 523          oclass = NV34_3D_CLASS;
 524       else
 525       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 526          oclass = NV35_3D_CLASS;
 527       break;
 528    case 0x40:
 529       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 530          oclass = NV40_3D_CLASS;
 531       else
 532       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 533          oclass = NV44_3D_CLASS;
 534       break;
 535    case 0x60:
 536       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 537          oclass = NV44_3D_CLASS;
 538       break;
 539    default:
 540       break;
 541    }
 542
 543    if (!oclass) {
 544       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 545       return NULL;
 546    }
 547
 548    screen = CALLOC_STRUCT(nv30_screen);
 549    if (!screen)
 550       return NULL;
 551
 552    pscreen = &screen->base.base;
 553    pscreen->destroy = nv30_screen_destroy;
 554
 555    /*
 556     * Some modern apps try to use msaa without keeping in mind the
 557     * restrictions on videomem of older cards. Resulting in dmesg saying:
 558     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 559     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 560     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 561     *
 562     * Because we are running out of video memory, after which the program
 563     * using the msaa visual freezes, and eventually the entire system freezes.
 564     *
 565     * To work around this we do not allow msaa visauls by default and allow
 566     * the user to override this via NV30_MAX_MSAA.
 567     */
 568    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 569    if (screen->max_sample_count > 4)
 570       screen->max_sample_count = 4;
 571
 572    pscreen->get_param = nv30_screen_get_param;
 573    pscreen->get_paramf = nv30_screen_get_paramf;
 574    pscreen->get_shader_param = nv30_screen_get_shader_param;
 575    pscreen->context_create = nv30_context_create;
 576    pscreen->is_format_supported = nv30_screen_is_format_supported;
 577    nv30_resource_screen_init(pscreen);
 578    nouveau_screen_init_vdec(&screen->base);
 579
 580    screen->base.fence.emit = nv30_screen_fence_emit;
 581    screen->base.fence.update = nv30_screen_fence_update;
 582
 583    ret = nouveau_screen_init(&screen->base, dev);
 584    if (ret)
 585       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 586
 587    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 588    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 589    if (oclass == NV40_3D_CLASS) {
 590       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 591       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 592    }
 593
 594    fifo = screen->base.channel->data;
 595    push = screen->base.pushbuf;
 596    push->rsvd_kick = 16;
 597
 598    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 599                             NULL, 0, &screen->null);
 600    if (ret)
 601       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 602
 603    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 604     * this means that the address pointed at by the DMA object must
 605     * be 4KiB aligned, which means this object needs to be the first
 606     * one allocated on the channel.
 607     */
 608    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 609                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 610                             .length = 32 }, sizeof(struct nv04_notify),
 611                             &screen->fence);
 612    if (ret)
 613       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 614
 615    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 616    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 617                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 618                             .length = 32 }, sizeof(struct nv04_notify),
 619                             &screen->ntfy);
 620    if (ret)
 621       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 622
 623    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 624     * the remainder of the "notifier block" assigned by the kernel for
 625     * use as query objects
 626     */
 627    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 628                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 629                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 630                             &screen->query);
 631    if (ret)
 632       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 633
 634    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 635    if (ret)
 636       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 637
 638    LIST_INITHEAD(&screen->queries);
 639
 640    /* Vertex program resources (code/data), currently 6 of the constant
 641     * slots are reserved to implement user clipping planes
 642     */
 643    if (oclass < NV40_3D_CLASS) {
 644       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 645       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 646    } else {
 647       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 648       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 649    }
 650
 651    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 652    if (ret == 0)
 653       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 654    if (ret)
 655       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 656
 657    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 658                             NULL, 0, &screen->eng3d);
 659    if (ret)
 660       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 661
 662    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 663    PUSH_DATA (push, screen->eng3d->handle);
 664    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 665    PUSH_DATA (push, screen->ntfy->handle);
 666    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 667    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 668    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 669    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 670    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 671    PUSH_DATA (push, fifo->vram);     /* ZETA */
 672    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 673    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 674    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 675    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 676    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 677    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 678    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 679       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 680       PUSH_DATA (push, 0x00100000);
 681       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 682       PUSH_DATA (push, 3);
 683
 684       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 685       PUSH_DATA (push, 0);
 686       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 687       PUSH_DATA (push, fui(0.0));
 688       PUSH_DATA (push, fui(0.0));
 689       PUSH_DATA (push, fui(1.0));
 690       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 691       for (i = 0; i < 16; i++)
 692          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 693
 694       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 695       PUSH_DATA (push, 0);
 696    } else {
 697       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 698       PUSH_DATA (push, fifo->vram);
 699       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 700
 701       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 702       PUSH_DATA (push, 0x00000004);
 703
 704       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 705       PUSH_DATA (push, 0x00000010);
 706       PUSH_DATA (push, 0x01000100);
 707       PUSH_DATA (push, 0xff800006);
 708
 709       /* vtxprog output routing */
 710       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 711       PUSH_DATA (push, 0x06144321);
 712       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 713       PUSH_DATA (push, 0xedcba987);
 714       PUSH_DATA (push, 0x0000006f);
 715       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 716       PUSH_DATA (push, 0x00171615);
 717       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 718       PUSH_DATA (push, 0x001b1a19);
 719
 720       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 721       PUSH_DATA (push, 0x0020ffff);
 722       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 723       PUSH_DATA (push, 0x01d300d4);
 724
 725       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 726       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 727    }
 728
 729    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 730                             NULL, 0, &screen->m2mf);
 731    if (ret)
 732       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 733
 734    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 735    PUSH_DATA (push, screen->m2mf->handle);
 736    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 737    PUSH_DATA (push, screen->ntfy->handle);
 738
 739    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 740                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 741    if (ret)
 742       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 743
 744    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 745    PUSH_DATA (push, screen->surf2d->handle);
 746    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 747    PUSH_DATA (push, screen->ntfy->handle);
 748
 749    if (dev->chipset < 0x40)
 750       oclass = NV30_SURFACE_SWZ_CLASS;
 751    else
 752       oclass = NV40_SURFACE_SWZ_CLASS;
 753
 754    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 755                             NULL, 0, &screen->swzsurf);
 756    if (ret)
 757       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 758
 759    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 760    PUSH_DATA (push, screen->swzsurf->handle);
 761    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 762    PUSH_DATA (push, screen->ntfy->handle);
 763
 764    if (dev->chipset < 0x40)
 765       oclass = NV30_SIFM_CLASS;
 766    else
 767       oclass = NV40_SIFM_CLASS;
 768
 769    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 770                             NULL, 0, &screen->sifm);
 771    if (ret)
 772       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 773
 774    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 775    PUSH_DATA (push, screen->sifm->handle);
 776    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 777    PUSH_DATA (push, screen->ntfy->handle);
 778    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 779    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 780
 781    nouveau_pushbuf_kick(push, push->channel);
 782
 783    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 784    return &screen->base;
 785 }