2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
52 struct nv30_screen *screen = nv30_screen(pscreen);
53 struct nouveau_object *eng3d = screen->eng3d;
54 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS:
59 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
66 case PIPE_CAP_GLSL_FEATURE_LEVEL:
67 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
69 case PIPE_CAP_ENDIANNESS:
70 return PIPE_ENDIAN_LITTLE;
71 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
73 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
74 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
75 case PIPE_CAP_MAX_VIEWPORTS:
77 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
79 /* supported capabilities */
80 case PIPE_CAP_ANISOTROPIC_FILTER:
81 case PIPE_CAP_POINT_SPRITE:
82 case PIPE_CAP_OCCLUSION_QUERY:
83 case PIPE_CAP_QUERY_TIME_ELAPSED:
84 case PIPE_CAP_QUERY_TIMESTAMP:
85 case PIPE_CAP_TEXTURE_SWIZZLE:
86 case PIPE_CAP_DEPTH_CLIP_DISABLE:
87 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
88 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
89 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
90 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
91 case PIPE_CAP_TGSI_TEXCOORD:
92 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
93 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
94 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
95 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
96 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
97 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
99 /* nv35 capabilities */
100 case PIPE_CAP_DEPTH_BOUNDS_TEST:
101 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
102 /* nv4x capabilities */
103 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
104 case PIPE_CAP_NPOT_TEXTURES:
105 case PIPE_CAP_CONDITIONAL_RENDER:
106 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
107 case PIPE_CAP_PRIMITIVE_RESTART:
108 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
110 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
112 case PIPE_CAP_INDEP_BLEND_ENABLE:
113 case PIPE_CAP_INDEP_BLEND_FUNC:
114 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
115 case PIPE_CAP_SHADER_STENCIL_EXPORT:
116 case PIPE_CAP_TGSI_INSTANCEID:
117 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
118 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
119 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
120 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
121 case PIPE_CAP_MIN_TEXEL_OFFSET:
122 case PIPE_CAP_MAX_TEXEL_OFFSET:
123 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
124 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
125 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
127 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
128 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
129 case PIPE_CAP_MAX_VERTEX_STREAMS:
130 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
131 case PIPE_CAP_TEXTURE_BARRIER:
132 case PIPE_CAP_SEAMLESS_CUBE_MAP:
133 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
134 case PIPE_CAP_CUBE_MAP_ARRAY:
135 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
136 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
137 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
138 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
139 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
140 case PIPE_CAP_START_INSTANCE:
141 case PIPE_CAP_TEXTURE_MULTISAMPLE:
142 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
143 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
144 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
145 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
146 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
147 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
148 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
149 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
150 case PIPE_CAP_TEXTURE_GATHER_SM5:
151 case PIPE_CAP_FAKE_SW_MSAA:
152 case PIPE_CAP_TEXTURE_QUERY_LOD:
153 case PIPE_CAP_SAMPLE_SHADING:
154 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
155 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
156 case PIPE_CAP_USER_VERTEX_BUFFERS:
157 case PIPE_CAP_COMPUTE:
158 case PIPE_CAP_DRAW_INDIRECT:
159 case PIPE_CAP_MULTI_DRAW_INDIRECT:
160 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
161 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
162 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
163 case PIPE_CAP_SAMPLER_VIEW_TARGET:
164 case PIPE_CAP_CLIP_HALFZ:
165 case PIPE_CAP_VERTEXID_NOBASE:
166 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
167 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
168 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
169 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
170 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
171 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
172 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
173 case PIPE_CAP_TGSI_TXQS:
174 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
175 case PIPE_CAP_SHAREABLE_SHADERS:
176 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
177 case PIPE_CAP_CLEAR_TEXTURE:
178 case PIPE_CAP_DRAW_PARAMETERS:
179 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
180 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
181 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
182 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
183 case PIPE_CAP_INVALIDATE_BUFFER:
184 case PIPE_CAP_GENERATE_MIPMAP:
185 case PIPE_CAP_STRING_MARKER:
186 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
187 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
188 case PIPE_CAP_QUERY_BUFFER_OBJECT:
189 case PIPE_CAP_QUERY_MEMORY_INFO:
190 case PIPE_CAP_PCI_GROUP:
191 case PIPE_CAP_PCI_BUS:
192 case PIPE_CAP_PCI_DEVICE:
193 case PIPE_CAP_PCI_FUNCTION:
194 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
195 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
196 case PIPE_CAP_CULL_DISTANCE:
197 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
198 case PIPE_CAP_TGSI_VOTE:
199 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
200 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
201 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
202 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
203 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
204 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
205 case PIPE_CAP_NATIVE_FENCE_FD:
206 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
207 case PIPE_CAP_TGSI_FS_FBFETCH:
208 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
209 case PIPE_CAP_DOUBLES:
211 case PIPE_CAP_INT64_DIVMOD:
212 case PIPE_CAP_TGSI_TEX_TXF_LZ:
213 case PIPE_CAP_TGSI_CLOCK:
214 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
215 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
216 case PIPE_CAP_TGSI_BALLOT:
217 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
218 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
219 case PIPE_CAP_POST_DEPTH_COVERAGE:
220 case PIPE_CAP_BINDLESS_TEXTURE:
221 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
222 case PIPE_CAP_QUERY_SO_OVERFLOW:
223 case PIPE_CAP_MEMOBJ:
224 case PIPE_CAP_LOAD_CONSTBUF:
225 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
226 case PIPE_CAP_TILE_RASTER_ORDER:
227 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
228 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
229 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
230 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
231 case PIPE_CAP_FENCE_SIGNAL:
232 case PIPE_CAP_CONSTBUF0_FLAGS:
233 case PIPE_CAP_PACKED_UNIFORMS:
234 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
235 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
236 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
237 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
238 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
239 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
240 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
243 case PIPE_CAP_MAX_GS_INVOCATIONS:
245 case PIPE_CAP_VENDOR_ID:
247 case PIPE_CAP_DEVICE_ID: {
249 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
250 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
255 case PIPE_CAP_ACCELERATED:
257 case PIPE_CAP_VIDEO_MEMORY:
258 return dev->vram_size >> 20;
263 debug_printf("unknown param %d\n", param);
268 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
270 struct nv30_screen *screen = nv30_screen(pscreen);
271 struct nouveau_object *eng3d = screen->eng3d;
274 case PIPE_CAPF_MAX_LINE_WIDTH:
275 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
277 case PIPE_CAPF_MAX_POINT_WIDTH:
278 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
280 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
281 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
282 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
284 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
285 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
286 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
289 debug_printf("unknown paramf %d\n", param);
295 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
296 enum pipe_shader_type shader,
297 enum pipe_shader_cap param)
299 struct nv30_screen *screen = nv30_screen(pscreen);
300 struct nouveau_object *eng3d = screen->eng3d;
303 case PIPE_SHADER_VERTEX:
305 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
306 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
307 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
308 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
309 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
310 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
311 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
313 case PIPE_SHADER_CAP_MAX_INPUTS:
314 case PIPE_SHADER_CAP_MAX_OUTPUTS:
316 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
317 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
318 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
320 case PIPE_SHADER_CAP_MAX_TEMPS:
321 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
322 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
324 case PIPE_SHADER_CAP_PREFERRED_IR:
325 return PIPE_SHADER_IR_TGSI;
326 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
327 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
329 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
330 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
331 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
332 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
333 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
334 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
335 case PIPE_SHADER_CAP_SUBROUTINES:
336 case PIPE_SHADER_CAP_INTEGERS:
337 case PIPE_SHADER_CAP_INT64_ATOMICS:
338 case PIPE_SHADER_CAP_FP16:
339 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
340 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
341 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
342 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
343 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
344 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
345 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
346 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
347 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
348 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
349 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
350 case PIPE_SHADER_CAP_SCALAR_ISA:
353 debug_printf("unknown vertex shader param %d\n", param);
357 case PIPE_SHADER_FRAGMENT:
359 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
360 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
361 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
362 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
364 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
366 case PIPE_SHADER_CAP_MAX_INPUTS:
367 return 8; /* should be possible to do 10 with nv4x */
368 case PIPE_SHADER_CAP_MAX_OUTPUTS:
370 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
371 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
372 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
374 case PIPE_SHADER_CAP_MAX_TEMPS:
376 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
377 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
379 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
381 case PIPE_SHADER_CAP_PREFERRED_IR:
382 return PIPE_SHADER_IR_TGSI;
383 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
384 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
385 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
386 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
387 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
388 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
389 case PIPE_SHADER_CAP_SUBROUTINES:
390 case PIPE_SHADER_CAP_INTEGERS:
391 case PIPE_SHADER_CAP_FP16:
392 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
393 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
394 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
395 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
396 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
397 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
398 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
399 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
400 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
401 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
402 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
403 case PIPE_SHADER_CAP_SCALAR_ISA:
406 debug_printf("unknown fragment shader param %d\n", param);
416 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
417 enum pipe_format format,
418 enum pipe_texture_target target,
419 unsigned sample_count,
420 unsigned storage_sample_count,
423 if (sample_count > nv30_screen(pscreen)->max_sample_count)
426 if (!(0x00000017 & (1 << sample_count)))
429 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
432 /* shared is always supported */
433 bindings &= ~PIPE_BIND_SHARED;
435 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
439 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
441 struct nv30_screen *screen = nv30_screen(pscreen);
442 struct nouveau_pushbuf *push = screen->base.pushbuf;
444 *sequence = ++screen->base.fence.sequence;
446 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
447 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
448 (2 /* size */ << 18) | (7 /* subchan */ << 13));
450 PUSH_DATA (push, *sequence);
454 nv30_screen_fence_update(struct pipe_screen *pscreen)
456 struct nv30_screen *screen = nv30_screen(pscreen);
457 struct nv04_notify *fence = screen->fence->data;
458 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
462 nv30_screen_destroy(struct pipe_screen *pscreen)
464 struct nv30_screen *screen = nv30_screen(pscreen);
466 if (!nouveau_drm_screen_unref(&screen->base))
469 if (screen->base.fence.current) {
470 struct nouveau_fence *current = NULL;
472 /* nouveau_fence_wait will create a new current fence, so wait on the
473 * _current_ one, and remove both.
475 nouveau_fence_ref(screen->base.fence.current, ¤t);
476 nouveau_fence_wait(current, NULL);
477 nouveau_fence_ref(NULL, ¤t);
478 nouveau_fence_ref(NULL, &screen->base.fence.current);
481 nouveau_bo_ref(NULL, &screen->notify);
483 nouveau_heap_destroy(&screen->query_heap);
484 nouveau_heap_destroy(&screen->vp_exec_heap);
485 nouveau_heap_destroy(&screen->vp_data_heap);
487 nouveau_object_del(&screen->query);
488 nouveau_object_del(&screen->fence);
489 nouveau_object_del(&screen->ntfy);
491 nouveau_object_del(&screen->sifm);
492 nouveau_object_del(&screen->swzsurf);
493 nouveau_object_del(&screen->surf2d);
494 nouveau_object_del(&screen->m2mf);
495 nouveau_object_del(&screen->eng3d);
496 nouveau_object_del(&screen->null);
498 nouveau_screen_fini(&screen->base);
502 #define FAIL_SCREEN_INIT(str, err) \
504 NOUVEAU_ERR(str, err); \
505 screen->base.base.context_create = NULL; \
506 return &screen->base; \
509 struct nouveau_screen *
510 nv30_screen_create(struct nouveau_device *dev)
512 struct nv30_screen *screen;
513 struct pipe_screen *pscreen;
514 struct nouveau_pushbuf *push;
515 struct nv04_fifo *fifo;
519 switch (dev->chipset & 0xf0) {
521 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
522 oclass = NV30_3D_CLASS;
524 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
525 oclass = NV34_3D_CLASS;
527 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
528 oclass = NV35_3D_CLASS;
531 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
532 oclass = NV40_3D_CLASS;
534 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
535 oclass = NV44_3D_CLASS;
538 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
539 oclass = NV44_3D_CLASS;
546 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
550 screen = CALLOC_STRUCT(nv30_screen);
554 pscreen = &screen->base.base;
555 pscreen->destroy = nv30_screen_destroy;
558 * Some modern apps try to use msaa without keeping in mind the
559 * restrictions on videomem of older cards. Resulting in dmesg saying:
560 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
561 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
562 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
564 * Because we are running out of video memory, after which the program
565 * using the msaa visual freezes, and eventually the entire system freezes.
567 * To work around this we do not allow msaa visauls by default and allow
568 * the user to override this via NV30_MAX_MSAA.
570 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
571 if (screen->max_sample_count > 4)
572 screen->max_sample_count = 4;
574 pscreen->get_param = nv30_screen_get_param;
575 pscreen->get_paramf = nv30_screen_get_paramf;
576 pscreen->get_shader_param = nv30_screen_get_shader_param;
577 pscreen->context_create = nv30_context_create;
578 pscreen->is_format_supported = nv30_screen_is_format_supported;
579 nv30_resource_screen_init(pscreen);
580 nouveau_screen_init_vdec(&screen->base);
582 screen->base.fence.emit = nv30_screen_fence_emit;
583 screen->base.fence.update = nv30_screen_fence_update;
585 ret = nouveau_screen_init(&screen->base, dev);
587 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
589 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
590 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
591 if (oclass == NV40_3D_CLASS) {
592 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
593 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
596 fifo = screen->base.channel->data;
597 push = screen->base.pushbuf;
598 push->rsvd_kick = 16;
600 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
601 NULL, 0, &screen->null);
603 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
605 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
606 * this means that the address pointed at by the DMA object must
607 * be 4KiB aligned, which means this object needs to be the first
608 * one allocated on the channel.
610 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
611 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
612 .length = 32 }, sizeof(struct nv04_notify),
615 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
617 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
618 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
619 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
620 .length = 32 }, sizeof(struct nv04_notify),
623 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
625 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
626 * the remainder of the "notifier block" assigned by the kernel for
627 * use as query objects
629 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
630 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
631 .length = 4096 - 128 }, sizeof(struct nv04_notify),
634 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
636 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
638 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
640 LIST_INITHEAD(&screen->queries);
642 /* Vertex program resources (code/data), currently 6 of the constant
643 * slots are reserved to implement user clipping planes
645 if (oclass < NV40_3D_CLASS) {
646 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
647 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
649 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
650 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
653 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
655 ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
657 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
659 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
660 NULL, 0, &screen->eng3d);
662 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
664 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
665 PUSH_DATA (push, screen->eng3d->handle);
666 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
667 PUSH_DATA (push, screen->ntfy->handle);
668 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
669 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
670 PUSH_DATA (push, fifo->vram); /* COLOR1 */
671 PUSH_DATA (push, screen->null->handle); /* UNK190 */
672 PUSH_DATA (push, fifo->vram); /* COLOR0 */
673 PUSH_DATA (push, fifo->vram); /* ZETA */
674 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
675 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
676 PUSH_DATA (push, screen->fence->handle); /* FENCE */
677 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
678 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
679 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
680 if (screen->eng3d->oclass < NV40_3D_CLASS) {
681 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
682 PUSH_DATA (push, 0x00100000);
683 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
686 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
688 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
689 PUSH_DATA (push, fui(0.0));
690 PUSH_DATA (push, fui(0.0));
691 PUSH_DATA (push, fui(1.0));
692 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
693 for (i = 0; i < 16; i++)
694 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
696 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
699 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
700 PUSH_DATA (push, fifo->vram);
701 PUSH_DATA (push, fifo->vram); /* COLOR3 */
703 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
704 PUSH_DATA (push, 0x00000004);
706 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
707 PUSH_DATA (push, 0x00000010);
708 PUSH_DATA (push, 0x01000100);
709 PUSH_DATA (push, 0xff800006);
711 /* vtxprog output routing */
712 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
713 PUSH_DATA (push, 0x06144321);
714 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
715 PUSH_DATA (push, 0xedcba987);
716 PUSH_DATA (push, 0x0000006f);
717 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
718 PUSH_DATA (push, 0x00171615);
719 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
720 PUSH_DATA (push, 0x001b1a19);
722 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
723 PUSH_DATA (push, 0x0020ffff);
724 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
725 PUSH_DATA (push, 0x01d300d4);
727 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
728 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
731 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
732 NULL, 0, &screen->m2mf);
734 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
736 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
737 PUSH_DATA (push, screen->m2mf->handle);
738 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
739 PUSH_DATA (push, screen->ntfy->handle);
741 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
742 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
744 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
746 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
747 PUSH_DATA (push, screen->surf2d->handle);
748 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
749 PUSH_DATA (push, screen->ntfy->handle);
751 if (dev->chipset < 0x40)
752 oclass = NV30_SURFACE_SWZ_CLASS;
754 oclass = NV40_SURFACE_SWZ_CLASS;
756 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
757 NULL, 0, &screen->swzsurf);
759 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
761 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
762 PUSH_DATA (push, screen->swzsurf->handle);
763 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
764 PUSH_DATA (push, screen->ntfy->handle);
766 if (dev->chipset < 0x40)
767 oclass = NV30_SIFM_CLASS;
769 oclass = NV40_SIFM_CLASS;
771 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
772 NULL, 0, &screen->sifm);
774 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
776 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
777 PUSH_DATA (push, screen->sifm->handle);
778 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
779 PUSH_DATA (push, screen->ntfy->handle);
780 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
781 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
783 nouveau_pushbuf_kick(push, push->channel);
785 nouveau_fence_new(&screen->base, &screen->base.fence.current);
786 return &screen->base;