2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
33 #include "nouveau_vp3_video.h"
35 #include "nv_object.xml.h"
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
42 #define THREADS_IN_WARP 32
45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned storage_sample_count,
54 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
56 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
59 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
63 case PIPE_FORMAT_Z16_UNORM:
64 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
71 if (bindings & PIPE_BIND_LINEAR)
72 if (util_format_is_depth_or_stencil(format) ||
73 (target != PIPE_TEXTURE_1D &&
74 target != PIPE_TEXTURE_2D &&
75 target != PIPE_TEXTURE_RECT) ||
79 /* shared is always supported */
80 bindings &= ~(PIPE_BIND_LINEAR |
83 return (( nv50_format_table[format].usage |
84 nv50_vertex_format[format].usage) & bindings) == bindings;
88 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
90 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
91 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
94 /* non-boolean caps */
95 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
97 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
99 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
101 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
103 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
104 case PIPE_CAP_MIN_TEXEL_OFFSET:
106 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
107 case PIPE_CAP_MAX_TEXEL_OFFSET:
109 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
110 return 128 * 1024 * 1024;
111 case PIPE_CAP_GLSL_FEATURE_LEVEL:
113 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
115 case PIPE_CAP_MAX_RENDER_TARGETS:
117 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
119 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
121 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
122 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
124 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
125 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
127 case PIPE_CAP_MAX_VERTEX_STREAMS:
129 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
131 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
133 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
134 return 16; /* 256 for binding as RT, but that's not possible in GL */
135 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
136 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
137 case PIPE_CAP_MAX_VIEWPORTS:
138 return NV50_MAX_VIEWPORTS;
139 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
140 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
141 case PIPE_CAP_ENDIANNESS:
142 return PIPE_ENDIAN_LITTLE;
143 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
144 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
145 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
146 return NV50_MAX_WINDOW_RECTANGLES;
149 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
150 case PIPE_CAP_TEXTURE_SWIZZLE:
151 case PIPE_CAP_NPOT_TEXTURES:
152 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
153 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
154 case PIPE_CAP_ANISOTROPIC_FILTER:
155 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
156 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
157 case PIPE_CAP_DEPTH_CLIP_DISABLE:
158 case PIPE_CAP_POINT_SPRITE:
160 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
161 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
162 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
163 case PIPE_CAP_QUERY_TIMESTAMP:
164 case PIPE_CAP_QUERY_TIME_ELAPSED:
165 case PIPE_CAP_OCCLUSION_QUERY:
166 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
167 case PIPE_CAP_INDEP_BLEND_ENABLE:
168 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
169 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
170 case PIPE_CAP_PRIMITIVE_RESTART:
171 case PIPE_CAP_TGSI_INSTANCEID:
172 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
173 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
174 case PIPE_CAP_CONDITIONAL_RENDER:
175 case PIPE_CAP_TEXTURE_BARRIER:
176 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
177 case PIPE_CAP_START_INSTANCE:
178 case PIPE_CAP_USER_VERTEX_BUFFERS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
181 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
182 case PIPE_CAP_SAMPLER_VIEW_TARGET:
183 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
184 case PIPE_CAP_CLIP_HALFZ:
185 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
186 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_DEPTH_BOUNDS_TEST:
190 case PIPE_CAP_TGSI_TXQS:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_CLEAR_TEXTURE:
194 case PIPE_CAP_COMPUTE:
195 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
196 case PIPE_CAP_INVALIDATE_BUFFER:
197 case PIPE_CAP_STRING_MARKER:
198 case PIPE_CAP_CULL_DISTANCE:
199 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
200 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
201 case PIPE_CAP_TGSI_TEX_TXF_LZ:
202 case PIPE_CAP_TGSI_CLOCK:
203 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
204 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
206 case PIPE_CAP_SEAMLESS_CUBE_MAP:
207 return 1; /* class_3d >= NVA0_3D_CLASS; */
208 /* supported on nva0+ */
209 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
210 return class_3d >= NVA0_3D_CLASS;
211 /* supported on nva3+ */
212 case PIPE_CAP_CUBE_MAP_ARRAY:
213 case PIPE_CAP_INDEP_BLEND_FUNC:
214 case PIPE_CAP_TEXTURE_QUERY_LOD:
215 case PIPE_CAP_SAMPLE_SHADING:
216 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
217 return class_3d >= NVA3_3D_CLASS;
219 /* unsupported caps */
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
221 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
222 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
223 case PIPE_CAP_SHADER_STENCIL_EXPORT:
224 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
225 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
226 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
227 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
228 case PIPE_CAP_TGSI_TEXCOORD:
229 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
230 case PIPE_CAP_TEXTURE_GATHER_SM5:
231 case PIPE_CAP_FAKE_SW_MSAA:
232 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
233 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
234 case PIPE_CAP_DRAW_INDIRECT:
235 case PIPE_CAP_MULTI_DRAW_INDIRECT:
236 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
237 case PIPE_CAP_VERTEXID_NOBASE:
238 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
239 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
240 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
241 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
242 case PIPE_CAP_DRAW_PARAMETERS:
243 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
244 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
245 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
246 case PIPE_CAP_GENERATE_MIPMAP:
247 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
248 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
249 case PIPE_CAP_QUERY_BUFFER_OBJECT:
250 case PIPE_CAP_QUERY_MEMORY_INFO:
251 case PIPE_CAP_PCI_GROUP:
252 case PIPE_CAP_PCI_BUS:
253 case PIPE_CAP_PCI_DEVICE:
254 case PIPE_CAP_PCI_FUNCTION:
255 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
256 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
257 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
258 case PIPE_CAP_TGSI_VOTE:
259 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
260 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
261 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
262 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
263 case PIPE_CAP_NATIVE_FENCE_FD:
264 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 case PIPE_CAP_DOUBLES:
268 case PIPE_CAP_INT64_DIVMOD:
269 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
270 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
271 case PIPE_CAP_TGSI_BALLOT:
272 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
273 case PIPE_CAP_POST_DEPTH_COVERAGE:
274 case PIPE_CAP_BINDLESS_TEXTURE:
275 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
276 case PIPE_CAP_QUERY_SO_OVERFLOW:
277 case PIPE_CAP_MEMOBJ:
278 case PIPE_CAP_LOAD_CONSTBUF:
279 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
280 case PIPE_CAP_TILE_RASTER_ORDER:
281 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
282 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
283 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
284 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
285 case PIPE_CAP_FENCE_SIGNAL:
286 case PIPE_CAP_CONSTBUF0_FLAGS:
287 case PIPE_CAP_PACKED_UNIFORMS:
288 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
289 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
290 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
291 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
292 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
293 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
294 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
297 case PIPE_CAP_MAX_GS_INVOCATIONS:
299 case PIPE_CAP_VENDOR_ID:
301 case PIPE_CAP_DEVICE_ID: {
303 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
304 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
309 case PIPE_CAP_ACCELERATED:
311 case PIPE_CAP_VIDEO_MEMORY:
312 return dev->vram_size >> 20;
317 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
322 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
323 enum pipe_shader_type shader,
324 enum pipe_shader_cap param)
327 case PIPE_SHADER_VERTEX:
328 case PIPE_SHADER_GEOMETRY:
329 case PIPE_SHADER_FRAGMENT:
331 case PIPE_SHADER_COMPUTE:
337 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
338 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
339 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
340 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
342 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
344 case PIPE_SHADER_CAP_MAX_INPUTS:
345 if (shader == PIPE_SHADER_VERTEX)
348 case PIPE_SHADER_CAP_MAX_OUTPUTS:
350 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
352 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
353 return NV50_MAX_PIPE_CONSTBUFS;
354 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
355 return shader != PIPE_SHADER_FRAGMENT;
356 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
357 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
360 case PIPE_SHADER_CAP_MAX_TEMPS:
361 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
362 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
364 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
366 case PIPE_SHADER_CAP_INT64_ATOMICS:
367 case PIPE_SHADER_CAP_FP16:
368 case PIPE_SHADER_CAP_SUBROUTINES:
369 return 0; /* please inline, or provide function declarations */
370 case PIPE_SHADER_CAP_INTEGERS:
372 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
374 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
375 /* The chip could handle more sampler views than samplers */
376 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
377 return MIN2(16, PIPE_MAX_SAMPLERS);
378 case PIPE_SHADER_CAP_PREFERRED_IR:
379 return PIPE_SHADER_IR_TGSI;
380 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
382 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
383 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
384 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
385 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
386 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
387 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
388 case PIPE_SHADER_CAP_SUPPORTED_IRS:
389 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
390 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
391 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
392 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
394 case PIPE_SHADER_CAP_SCALAR_ISA:
397 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
403 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
406 case PIPE_CAPF_MAX_LINE_WIDTH:
407 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
409 case PIPE_CAPF_MAX_POINT_WIDTH:
410 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
412 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
414 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
416 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
417 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
418 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
422 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
427 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
428 enum pipe_shader_ir ir_type,
429 enum pipe_compute_cap param, void *data)
431 struct nv50_screen *screen = nv50_screen(pscreen);
433 #define RET(x) do { \
435 memcpy(data, x, sizeof(x)); \
440 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
441 RET((uint64_t []) { 2 });
442 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
443 RET(((uint64_t []) { 65535, 65535 }));
444 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
445 RET(((uint64_t []) { 512, 512, 64 }));
446 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
447 RET((uint64_t []) { 512 });
448 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
449 RET((uint64_t []) { 1ULL << 32 });
450 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
451 RET((uint64_t []) { 16 << 10 });
452 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
453 RET((uint64_t []) { 16 << 10 });
454 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
455 RET((uint64_t []) { 4096 });
456 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
457 RET((uint32_t []) { 32 });
458 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
459 RET((uint64_t []) { 1ULL << 40 });
460 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
461 RET((uint32_t []) { 0 });
462 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
463 RET((uint32_t []) { screen->mp_count });
464 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
465 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
466 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
467 RET((uint32_t []) { 32 });
468 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
469 RET((uint64_t []) { 0 });
478 nv50_screen_destroy(struct pipe_screen *pscreen)
480 struct nv50_screen *screen = nv50_screen(pscreen);
482 if (!nouveau_drm_screen_unref(&screen->base))
485 if (screen->base.fence.current) {
486 struct nouveau_fence *current = NULL;
488 /* nouveau_fence_wait will create a new current fence, so wait on the
489 * _current_ one, and remove both.
491 nouveau_fence_ref(screen->base.fence.current, ¤t);
492 nouveau_fence_wait(current, NULL);
493 nouveau_fence_ref(NULL, ¤t);
494 nouveau_fence_ref(NULL, &screen->base.fence.current);
496 if (screen->base.pushbuf)
497 screen->base.pushbuf->user_priv = NULL;
500 nv50_blitter_destroy(screen);
501 if (screen->pm.prog) {
502 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
503 nv50_program_destroy(NULL, screen->pm.prog);
504 FREE(screen->pm.prog);
507 nouveau_bo_ref(NULL, &screen->code);
508 nouveau_bo_ref(NULL, &screen->tls_bo);
509 nouveau_bo_ref(NULL, &screen->stack_bo);
510 nouveau_bo_ref(NULL, &screen->txc);
511 nouveau_bo_ref(NULL, &screen->uniforms);
512 nouveau_bo_ref(NULL, &screen->fence.bo);
514 nouveau_heap_destroy(&screen->vp_code_heap);
515 nouveau_heap_destroy(&screen->gp_code_heap);
516 nouveau_heap_destroy(&screen->fp_code_heap);
518 FREE(screen->tic.entries);
520 nouveau_object_del(&screen->tesla);
521 nouveau_object_del(&screen->eng2d);
522 nouveau_object_del(&screen->m2mf);
523 nouveau_object_del(&screen->compute);
524 nouveau_object_del(&screen->sync);
526 nouveau_screen_fini(&screen->base);
532 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
534 struct nv50_screen *screen = nv50_screen(pscreen);
535 struct nouveau_pushbuf *push = screen->base.pushbuf;
537 /* we need to do it after possible flush in MARK_RING */
538 *sequence = ++screen->base.fence.sequence;
540 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
541 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
542 PUSH_DATAh(push, screen->fence.bo->offset);
543 PUSH_DATA (push, screen->fence.bo->offset);
544 PUSH_DATA (push, *sequence);
545 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
546 NV50_3D_QUERY_GET_UNK4 |
547 NV50_3D_QUERY_GET_UNIT_CROP |
548 NV50_3D_QUERY_GET_TYPE_QUERY |
549 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
550 NV50_3D_QUERY_GET_SHORT);
554 nv50_screen_fence_update(struct pipe_screen *pscreen)
556 return nv50_screen(pscreen)->fence.map[0];
560 nv50_screen_init_hwctx(struct nv50_screen *screen)
562 struct nouveau_pushbuf *push = screen->base.pushbuf;
563 struct nv04_fifo *fifo;
566 fifo = (struct nv04_fifo *)screen->base.channel->data;
568 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
569 PUSH_DATA (push, screen->m2mf->handle);
570 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
571 PUSH_DATA (push, screen->sync->handle);
572 PUSH_DATA (push, fifo->vram);
573 PUSH_DATA (push, fifo->vram);
575 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
576 PUSH_DATA (push, screen->eng2d->handle);
577 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
578 PUSH_DATA (push, screen->sync->handle);
579 PUSH_DATA (push, fifo->vram);
580 PUSH_DATA (push, fifo->vram);
581 PUSH_DATA (push, fifo->vram);
582 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
583 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
584 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
586 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
588 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
590 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
591 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
593 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
594 PUSH_DATA (push, screen->tesla->handle);
596 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
597 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
599 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
600 PUSH_DATA (push, screen->sync->handle);
601 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
602 for (i = 0; i < 11; ++i)
603 PUSH_DATA(push, fifo->vram);
604 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
605 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
606 PUSH_DATA(push, fifo->vram);
608 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
609 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
610 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
611 PUSH_DATA (push, 0xf);
613 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
614 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
615 PUSH_DATA (push, 0x18);
618 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
619 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
621 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
622 for (i = 0; i < 8; ++i)
623 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
625 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
628 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
630 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
632 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
633 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
634 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
636 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
638 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
641 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
642 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
646 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
648 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
651 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
652 PUSH_DATA (push, 0x3f);
654 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
655 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
656 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
658 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
659 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
660 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
662 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
663 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
664 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
666 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
667 PUSH_DATAh(push, screen->tls_bo->offset);
668 PUSH_DATA (push, screen->tls_bo->offset);
669 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
671 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
672 PUSH_DATAh(push, screen->stack_bo->offset);
673 PUSH_DATA (push, screen->stack_bo->offset);
676 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
677 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
678 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
679 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
681 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
682 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
683 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
684 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
686 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
687 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
688 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
689 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
691 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
692 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
693 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
694 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
696 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
697 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
698 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
699 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
701 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
702 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
703 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
704 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
705 PUSH_DATAf(push, 0.0f);
706 PUSH_DATAf(push, 0.0f);
707 PUSH_DATAf(push, 0.0f);
708 PUSH_DATAf(push, 0.0f);
709 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
710 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
711 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
713 nv50_upload_ms_info(push);
715 /* max TIC (bits 4:8) & TSC bindings, per program type */
716 for (i = 0; i < 3; ++i) {
717 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
718 PUSH_DATA (push, 0x54);
721 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
722 PUSH_DATAh(push, screen->txc->offset);
723 PUSH_DATA (push, screen->txc->offset);
724 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
726 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
727 PUSH_DATAh(push, screen->txc->offset + 65536);
728 PUSH_DATA (push, screen->txc->offset + 65536);
729 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
731 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
734 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
736 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
737 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
738 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
739 for (i = 0; i < 8 * 2; ++i)
741 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
744 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
746 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
747 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
748 PUSH_DATAf(push, 0.0f);
749 PUSH_DATAf(push, 1.0f);
750 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
751 PUSH_DATA (push, 8192 << 16);
752 PUSH_DATA (push, 8192 << 16);
755 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
756 #ifdef NV50_SCISSORS_CLIPPING
757 PUSH_DATA (push, 0x0000);
759 PUSH_DATA (push, 0x1080);
762 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
763 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
765 /* We use scissors instead of exact view volume clipping,
766 * so they're always enabled.
768 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
769 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
771 PUSH_DATA (push, 8192 << 16);
772 PUSH_DATA (push, 8192 << 16);
775 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
777 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
778 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
779 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
780 PUSH_DATA (push, 0x11111111);
781 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
784 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
786 if (screen->base.class_3d >= NV84_3D_CLASS) {
787 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
791 BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
793 BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
799 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
802 struct nouveau_device *dev = screen->base.device;
805 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
807 if (nouveau_mesa_debug)
808 debug_printf("allocating space for %u temps\n",
809 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
810 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
811 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
813 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
814 *tls_size, NULL, &screen->tls_bo);
816 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
823 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
825 struct nouveau_pushbuf *push = screen->base.pushbuf;
829 if (tls_space < screen->cur_tls_space)
831 if (tls_space > screen->max_tls_space) {
832 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
833 * LOCAL_WARPS_NO_CLAMP) */
834 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
835 (unsigned)(tls_space / ONE_TEMP_SIZE),
836 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
840 nouveau_bo_ref(NULL, &screen->tls_bo);
841 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
845 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
846 PUSH_DATAh(push, screen->tls_bo->offset);
847 PUSH_DATA (push, screen->tls_bo->offset);
848 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
853 struct nouveau_screen *
854 nv50_screen_create(struct nouveau_device *dev)
856 struct nv50_screen *screen;
857 struct pipe_screen *pscreen;
858 struct nouveau_object *chan;
860 uint32_t tesla_class;
864 screen = CALLOC_STRUCT(nv50_screen);
867 pscreen = &screen->base.base;
868 pscreen->destroy = nv50_screen_destroy;
870 ret = nouveau_screen_init(&screen->base, dev);
872 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
876 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
877 * admit them to VRAM.
879 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
880 PIPE_BIND_VERTEX_BUFFER;
881 screen->base.sysmem_bindings |=
882 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
884 screen->base.pushbuf->user_priv = screen;
885 screen->base.pushbuf->rsvd_kick = 5;
887 chan = screen->base.channel;
889 pscreen->context_create = nv50_create;
890 pscreen->is_format_supported = nv50_screen_is_format_supported;
891 pscreen->get_param = nv50_screen_get_param;
892 pscreen->get_shader_param = nv50_screen_get_shader_param;
893 pscreen->get_paramf = nv50_screen_get_paramf;
894 pscreen->get_compute_param = nv50_screen_get_compute_param;
895 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
896 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
898 nv50_screen_init_resource_functions(pscreen);
900 if (screen->base.device->chipset < 0x84 ||
901 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
903 nouveau_screen_init_vdec(&screen->base);
904 } else if (screen->base.device->chipset < 0x98 ||
905 screen->base.device->chipset == 0xa0) {
907 screen->base.base.get_video_param = nv84_screen_get_video_param;
908 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
911 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
912 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
915 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
916 NULL, &screen->fence.bo);
918 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
922 nouveau_bo_map(screen->fence.bo, 0, NULL);
923 screen->fence.map = screen->fence.bo->map;
924 screen->base.fence.emit = nv50_screen_fence_emit;
925 screen->base.fence.update = nv50_screen_fence_update;
927 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
928 &(struct nv04_notify){ .length = 32 },
929 sizeof(struct nv04_notify), &screen->sync);
931 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
935 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
936 NULL, 0, &screen->m2mf);
938 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
942 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
943 NULL, 0, &screen->eng2d);
945 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
949 switch (dev->chipset & 0xf0) {
951 tesla_class = NV50_3D_CLASS;
955 tesla_class = NV84_3D_CLASS;
958 switch (dev->chipset) {
962 tesla_class = NVA0_3D_CLASS;
965 tesla_class = NVAF_3D_CLASS;
968 tesla_class = NVA3_3D_CLASS;
973 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
976 screen->base.class_3d = tesla_class;
978 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
979 NULL, 0, &screen->tesla);
981 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
985 /* This over-allocates by a page. The GP, which would execute at the end of
986 * the last page, would trigger faults. The going theory is that it
987 * prefetches up to a certain amount.
989 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
990 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
991 NULL, &screen->code);
993 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
997 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
998 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
999 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1001 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1003 screen->TPs = util_bitcount(value & 0xffff);
1004 screen->MPsInTP = util_bitcount(value & 0x0f000000);
1006 screen->mp_count = screen->TPs * screen->MPsInTP;
1008 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1009 STACK_WARPS_ALLOC * 64 * 8;
1011 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1014 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1018 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1019 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
1021 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1022 screen->max_tls_space /= 2; /* half of vram */
1024 /* hw can address max 64 KiB */
1025 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1028 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1029 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1033 if (nouveau_mesa_debug)
1034 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1035 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1037 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1040 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1044 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1047 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1051 screen->tic.entries = CALLOC(4096, sizeof(void *));
1052 screen->tsc.entries = screen->tic.entries + 2048;
1054 if (!nv50_blitter_create(screen))
1057 nv50_screen_init_hwctx(screen);
1059 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1061 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1065 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1067 return &screen->base;
1070 screen->base.base.context_create = NULL;
1071 return &screen->base;
1075 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1077 int i = screen->tic.next;
1079 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1080 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1082 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1084 if (screen->tic.entries[i])
1085 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1087 screen->tic.entries[i] = entry;
1092 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1094 int i = screen->tsc.next;
1096 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1097 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1099 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1101 if (screen->tsc.entries[i])
1102 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1104 screen->tsc.entries[i] = entry;