2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_math.h"
31 #include "util/u_surface.h"
33 #include "tgsi/tgsi_ureg.h"
35 #include "os/os_thread.h"
37 #include "nv50/nv50_context.h"
38 #include "nv50/nv50_resource.h"
40 #include "nv50/g80_defs.xml.h"
41 #include "nv50/g80_texture.xml.h"
43 /* these are used in nv50_blit.h */
44 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
45 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
47 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
48 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
50 #define NOUVEAU_DRIVER 0x50
51 #include "nv50/nv50_blit.h"
54 nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
56 uint8_t id = nv50_format_table[format].rt;
58 /* Hardware values for color formats range from 0xc0 to 0xff,
59 * but the 2D engine doesn't support all of them.
61 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
63 assert(dst_src_equal);
65 switch (util_format_get_blocksize(format)) {
67 return G80_SURFACE_FORMAT_R8_UNORM;
69 return G80_SURFACE_FORMAT_R16_UNORM;
71 return G80_SURFACE_FORMAT_BGRA8_UNORM;
73 return G80_SURFACE_FORMAT_RGBA16_FLOAT;
75 return G80_SURFACE_FORMAT_RGBA32_FLOAT;
82 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
83 struct nv50_miptree *mt, unsigned level, unsigned layer,
84 enum pipe_format pformat, bool dst_src_pformat_equal)
86 struct nouveau_bo *bo = mt->base.bo;
87 uint32_t width, height, depth;
89 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
90 uint32_t offset = mt->level[level].offset;
92 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
94 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
95 util_format_name(pformat));
99 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
100 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
101 depth = u_minify(mt->base.base.depth0, level);
103 offset = mt->level[level].offset;
104 if (!mt->layout_3d) {
105 offset += mt->layer_stride * layer;
110 offset += nv50_mt_zslice_offset(mt, level, layer);
114 if (!nouveau_bo_memtype(bo)) {
115 BEGIN_NV04(push, SUBC_2D(mthd), 2);
116 PUSH_DATA (push, format);
118 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
119 PUSH_DATA (push, mt->level[level].pitch);
120 PUSH_DATA (push, width);
121 PUSH_DATA (push, height);
122 PUSH_DATAh(push, mt->base.address + offset);
123 PUSH_DATA (push, mt->base.address + offset);
125 BEGIN_NV04(push, SUBC_2D(mthd), 5);
126 PUSH_DATA (push, format);
128 PUSH_DATA (push, mt->level[level].tile_mode);
129 PUSH_DATA (push, depth);
130 PUSH_DATA (push, layer);
131 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
132 PUSH_DATA (push, width);
133 PUSH_DATA (push, height);
134 PUSH_DATAh(push, mt->base.address + offset);
135 PUSH_DATA (push, mt->base.address + offset);
140 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
143 PUSH_DATA (push, width);
144 PUSH_DATA (push, height);
151 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
152 struct nv50_miptree *dst, unsigned dst_level,
153 unsigned dx, unsigned dy, unsigned dz,
154 struct nv50_miptree *src, unsigned src_level,
155 unsigned sx, unsigned sy, unsigned sz,
156 unsigned w, unsigned h)
158 const enum pipe_format dfmt = dst->base.base.format;
159 const enum pipe_format sfmt = src->base.base.format;
161 bool eqfmt = dfmt == sfmt;
163 if (!PUSH_SPACE(push, 2 * 16 + 32))
166 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
170 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
174 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
175 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
176 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
177 PUSH_DATA (push, dx << dst->ms_x);
178 PUSH_DATA (push, dy << dst->ms_y);
179 PUSH_DATA (push, w << dst->ms_x);
180 PUSH_DATA (push, h << dst->ms_y);
181 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
186 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
188 PUSH_DATA (push, sx << src->ms_x);
190 PUSH_DATA (push, sy << src->ms_y);
196 nv50_resource_copy_region(struct pipe_context *pipe,
197 struct pipe_resource *dst, unsigned dst_level,
198 unsigned dstx, unsigned dsty, unsigned dstz,
199 struct pipe_resource *src, unsigned src_level,
200 const struct pipe_box *src_box)
202 struct nv50_context *nv50 = nv50_context(pipe);
205 unsigned dst_layer = dstz, src_layer = src_box->z;
207 pipe_mutex_lock(nv50->screen->base.push_mutex);
209 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
210 nouveau_copy_buffer(&nv50->base,
211 nv04_resource(dst), dstx,
212 nv04_resource(src), src_box->x, src_box->width);
213 pipe_mutex_unlock(nv50->screen->base.push_mutex);
217 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
218 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
220 m2mf = (src->format == dst->format) ||
221 (util_format_get_blocksizebits(src->format) ==
222 util_format_get_blocksizebits(dst->format));
224 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
227 struct nv50_miptree *src_mt = nv50_miptree(src);
228 struct nv50_miptree *dst_mt = nv50_miptree(dst);
229 struct nv50_m2mf_rect drect, srect;
231 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
233 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
236 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
237 nv50_m2mf_rect_setup(&srect, src, src_level,
238 src_box->x, src_box->y, src_box->z);
240 for (i = 0; i < src_box->depth; ++i) {
241 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
243 if (dst_mt->layout_3d)
246 drect.base += dst_mt->layer_stride;
248 if (src_mt->layout_3d)
251 srect.base += src_mt->layer_stride;
253 pipe_mutex_unlock(nv50->screen->base.push_mutex);
257 assert((src->format == dst->format) ||
258 (nv50_2d_src_format_faithful(src->format) &&
259 nv50_2d_dst_format_faithful(dst->format)));
261 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
262 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
263 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
264 nouveau_pushbuf_validate(nv50->base.pushbuf);
266 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
267 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
268 nv50_miptree(dst), dst_level,
269 dstx, dsty, dst_layer,
270 nv50_miptree(src), src_level,
271 src_box->x, src_box->y, src_layer,
272 src_box->width, src_box->height);
276 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
277 pipe_mutex_unlock(nv50->screen->base.push_mutex);
281 nv50_clear_render_target(struct pipe_context *pipe,
282 struct pipe_surface *dst,
283 const union pipe_color_union *color,
284 unsigned dstx, unsigned dsty,
285 unsigned width, unsigned height,
286 bool render_condition_enabled)
288 struct nv50_context *nv50 = nv50_context(pipe);
289 struct nouveau_pushbuf *push = nv50->base.pushbuf;
290 struct nv50_miptree *mt = nv50_miptree(dst->texture);
291 struct nv50_surface *sf = nv50_surface(dst);
292 struct nouveau_bo *bo = mt->base.bo;
295 assert(dst->texture->target != PIPE_BUFFER);
297 pipe_mutex_lock(nv50->screen->base.push_mutex);
299 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
300 PUSH_DATAf(push, color->f[0]);
301 PUSH_DATAf(push, color->f[1]);
302 PUSH_DATAf(push, color->f[2]);
303 PUSH_DATAf(push, color->f[3]);
305 if (nouveau_pushbuf_space(push, 64 + sf->depth, 1, 0)) {
306 pipe_mutex_unlock(nv50->screen->base.push_mutex);
310 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
312 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
313 PUSH_DATA (push, ( width << 16) | dstx);
314 PUSH_DATA (push, (height << 16) | dsty);
315 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
316 PUSH_DATA (push, 8192 << 16);
317 PUSH_DATA (push, 8192 << 16);
318 nv50->scissors_dirty |= 1;
320 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
322 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
323 PUSH_DATAh(push, mt->base.address + sf->offset);
324 PUSH_DATA (push, mt->base.address + sf->offset);
325 PUSH_DATA (push, nv50_format_table[dst->format].rt);
326 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
327 PUSH_DATA (push, mt->layer_stride >> 2);
328 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
329 if (nouveau_bo_memtype(bo))
330 PUSH_DATA(push, sf->width);
332 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
333 PUSH_DATA (push, sf->height);
334 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
336 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
338 PUSH_DATA(push, 512);
340 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
341 PUSH_DATA (push, mt->ms_mode);
343 if (!nouveau_bo_memtype(bo)) {
344 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
348 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
350 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
351 PUSH_DATA (push, (width << 16) | dstx);
352 PUSH_DATA (push, (height << 16) | dsty);
354 if (!render_condition_enabled) {
355 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
356 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
359 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
360 for (z = 0; z < sf->depth; ++z) {
361 PUSH_DATA (push, 0x3c |
362 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
365 if (!render_condition_enabled) {
366 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
367 PUSH_DATA (push, nv50->cond_condmode);
370 pipe_mutex_unlock(nv50->screen->base.push_mutex);
372 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
376 nv50_clear_depth_stencil(struct pipe_context *pipe,
377 struct pipe_surface *dst,
378 unsigned clear_flags,
381 unsigned dstx, unsigned dsty,
382 unsigned width, unsigned height,
383 bool render_condition_enabled)
385 struct nv50_context *nv50 = nv50_context(pipe);
386 struct nouveau_pushbuf *push = nv50->base.pushbuf;
387 struct nv50_miptree *mt = nv50_miptree(dst->texture);
388 struct nv50_surface *sf = nv50_surface(dst);
389 struct nouveau_bo *bo = mt->base.bo;
393 assert(dst->texture->target != PIPE_BUFFER);
394 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
396 pipe_mutex_lock(nv50->screen->base.push_mutex);
398 if (clear_flags & PIPE_CLEAR_DEPTH) {
399 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
400 PUSH_DATAf(push, depth);
401 mode |= NV50_3D_CLEAR_BUFFERS_Z;
404 if (clear_flags & PIPE_CLEAR_STENCIL) {
405 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
406 PUSH_DATA (push, stencil & 0xff);
407 mode |= NV50_3D_CLEAR_BUFFERS_S;
410 if (nouveau_pushbuf_space(push, 64 + sf->depth, 1, 0)) {
411 pipe_mutex_unlock(nv50->screen->base.push_mutex);
415 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
417 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
418 PUSH_DATA (push, ( width << 16) | dstx);
419 PUSH_DATA (push, (height << 16) | dsty);
420 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
421 PUSH_DATA (push, 8192 << 16);
422 PUSH_DATA (push, 8192 << 16);
423 nv50->scissors_dirty |= 1;
425 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
426 PUSH_DATAh(push, mt->base.address + sf->offset);
427 PUSH_DATA (push, mt->base.address + sf->offset);
428 PUSH_DATA (push, nv50_format_table[dst->format].rt);
429 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
430 PUSH_DATA (push, mt->layer_stride >> 2);
431 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
433 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
434 PUSH_DATA (push, sf->width);
435 PUSH_DATA (push, sf->height);
436 PUSH_DATA (push, (1 << 16) | 1);
438 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
439 PUSH_DATA (push, 512);
441 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
442 PUSH_DATA (push, mt->ms_mode);
444 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
445 PUSH_DATA (push, (width << 16) | dstx);
446 PUSH_DATA (push, (height << 16) | dsty);
448 if (!render_condition_enabled) {
449 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
450 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
453 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
454 for (z = 0; z < sf->depth; ++z) {
455 PUSH_DATA (push, mode |
456 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
459 if (!render_condition_enabled) {
460 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
461 PUSH_DATA (push, nv50->cond_condmode);
464 pipe_mutex_unlock(nv50->screen->base.push_mutex);
466 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
470 nv50_clear_texture(struct pipe_context *pipe,
471 struct pipe_resource *res,
473 const struct pipe_box *box,
476 struct pipe_surface tmpl = {{0}}, *sf;
478 tmpl.format = res->format;
479 tmpl.u.tex.first_layer = box->z;
480 tmpl.u.tex.last_layer = box->z + box->depth - 1;
481 tmpl.u.tex.level = level;
482 sf = pipe->create_surface(pipe, res, &tmpl);
486 if (util_format_is_depth_or_stencil(res->format)) {
490 const struct util_format_description *desc =
491 util_format_description(res->format);
493 if (util_format_has_depth(desc)) {
494 clear |= PIPE_CLEAR_DEPTH;
495 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
497 if (util_format_has_stencil(desc)) {
498 clear |= PIPE_CLEAR_STENCIL;
499 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
501 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
502 box->x, box->y, box->width, box->height, false);
504 union pipe_color_union color;
506 switch (util_format_get_blocksizebits(res->format)) {
508 sf->format = PIPE_FORMAT_R32G32B32A32_UINT;
509 memcpy(&color.ui, data, 128 / 8);
512 sf->format = PIPE_FORMAT_R32G32_UINT;
513 memcpy(&color.ui, data, 64 / 8);
514 memset(&color.ui[2], 0, 64 / 8);
517 sf->format = PIPE_FORMAT_R32_UINT;
518 memcpy(&color.ui, data, 32 / 8);
519 memset(&color.ui[1], 0, 96 / 8);
522 sf->format = PIPE_FORMAT_R16_UINT;
523 color.ui[0] = util_cpu_to_le32(
524 util_le16_to_cpu(*(unsigned short *)data));
525 memset(&color.ui[1], 0, 96 / 8);
528 sf->format = PIPE_FORMAT_R8_UINT;
529 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
530 memset(&color.ui[1], 0, 96 / 8);
533 assert(!"Unknown texel element size");
537 pipe->clear_render_target(pipe, sf, &color,
538 box->x, box->y, box->width, box->height, false);
540 pipe->surface_destroy(pipe, sf);
544 nv50_clear(struct pipe_context *pipe, unsigned buffers,
545 const union pipe_color_union *color,
546 double depth, unsigned stencil)
548 struct nv50_context *nv50 = nv50_context(pipe);
549 struct nouveau_pushbuf *push = nv50->base.pushbuf;
550 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
554 pipe_mutex_lock(nv50->screen->base.push_mutex);
555 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
556 if (!nv50_state_validate_3d(nv50, NV50_NEW_3D_FRAMEBUFFER)) {
557 pipe_mutex_unlock(nv50->screen->base.push_mutex);
561 /* We have to clear ALL of the layers, not up to the min number of layers
562 * of any attachment. */
563 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
564 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
566 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
567 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
568 PUSH_DATAf(push, color->f[0]);
569 PUSH_DATAf(push, color->f[1]);
570 PUSH_DATAf(push, color->f[2]);
571 PUSH_DATAf(push, color->f[3]);
572 if (buffers & PIPE_CLEAR_COLOR0)
574 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
575 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
578 if (buffers & PIPE_CLEAR_DEPTH) {
579 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
580 PUSH_DATA (push, fui(depth));
581 mode |= NV50_3D_CLEAR_BUFFERS_Z;
584 if (buffers & PIPE_CLEAR_STENCIL) {
585 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
586 PUSH_DATA (push, stencil & 0xff);
587 mode |= NV50_3D_CLEAR_BUFFERS_S;
591 int zs_layers = 0, color0_layers = 0;
592 if (fb->cbufs[0] && (mode & 0x3c))
593 color0_layers = nv50_surface(fb->cbufs[0])->depth;
594 if (fb->zsbuf && (mode & ~0x3c))
595 zs_layers = nv50_surface(fb->zsbuf)->depth;
597 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
598 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
599 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
601 for (k = j; k < zs_layers; k++) {
602 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
603 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
605 for (k = j; k < color0_layers; k++) {
606 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
607 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
611 for (i = 1; i < fb->nr_cbufs; i++) {
612 struct pipe_surface *sf = fb->cbufs[i];
613 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
615 for (j = 0; j < nv50_surface(sf)->depth; j++) {
616 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
617 PUSH_DATA (push, (i << 6) | 0x3c |
618 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
622 /* restore the array mode */
623 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
624 PUSH_DATA (push, nv50->rt_array_mode);
625 pipe_mutex_unlock(nv50->screen->base.push_mutex);
629 nv50_clear_buffer_push(struct pipe_context *pipe,
630 struct pipe_resource *res,
631 unsigned offset, unsigned size,
632 const void *data, int data_size)
634 struct nv50_context *nv50 = nv50_context(pipe);
635 struct nouveau_pushbuf *push = nv50->base.pushbuf;
636 struct nv04_resource *buf = nv04_resource(res);
637 unsigned count = (size + 3) / 4;
638 unsigned xcoord = offset & 0xff;
641 if (data_size == 1) {
642 tmp = *(unsigned char *)data;
643 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
646 } else if (data_size == 2) {
647 tmp = *(unsigned short *)data;
648 tmp = (tmp << 16) | tmp;
653 unsigned data_words = data_size / 4;
655 nouveau_bufctx_refn(nv50->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
656 nouveau_pushbuf_bufctx(push, nv50->bufctx);
657 nouveau_pushbuf_validate(push);
661 BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
662 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
664 BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
665 PUSH_DATA (push, 262144);
666 PUSH_DATA (push, 65536);
668 PUSH_DATAh(push, buf->address + offset);
669 PUSH_DATA (push, buf->address + offset);
670 BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
672 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
673 BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
674 PUSH_DATA (push, size);
681 PUSH_DATA (push, xcoord);
686 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
687 unsigned nr = nr_data * data_words;
689 BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);
690 for (i = 0; i < nr_data; i++)
691 PUSH_DATAp(push, data, data_words);
697 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
698 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
701 nouveau_bufctx_reset(nv50->bufctx, 0);
705 nv50_clear_buffer(struct pipe_context *pipe,
706 struct pipe_resource *res,
707 unsigned offset, unsigned size,
708 const void *data, int data_size)
710 struct nv50_context *nv50 = nv50_context(pipe);
711 struct nouveau_pushbuf *push = nv50->base.pushbuf;
712 struct nv04_resource *buf = (struct nv04_resource *)res;
713 union pipe_color_union color;
714 enum pipe_format dst_fmt;
715 unsigned width, height, elements;
717 assert(res->target == PIPE_BUFFER);
718 assert(nouveau_bo_memtype(buf->bo) == 0);
722 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
723 memcpy(&color.ui, data, 16);
726 dst_fmt = PIPE_FORMAT_R32G32_UINT;
727 memcpy(&color.ui, data, 8);
728 memset(&color.ui[2], 0, 8);
731 dst_fmt = PIPE_FORMAT_R32_UINT;
732 memcpy(&color.ui, data, 4);
733 memset(&color.ui[1], 0, 12);
736 dst_fmt = PIPE_FORMAT_R16_UINT;
737 color.ui[0] = util_cpu_to_le32(
738 util_le16_to_cpu(*(unsigned short *)data));
739 memset(&color.ui[1], 0, 12);
742 dst_fmt = PIPE_FORMAT_R8_UINT;
743 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
744 memset(&color.ui[1], 0, 12);
747 assert(!"Unsupported element size");
751 assert(size % data_size == 0);
753 pipe_mutex_lock(nv50->screen->base.push_mutex);
756 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
757 assert(fixup_size % data_size == 0);
758 nv50_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
759 offset += fixup_size;
762 pipe_mutex_unlock(nv50->screen->base.push_mutex);
767 elements = size / data_size;
768 height = (elements + 8191) / 8192;
769 width = elements / height;
774 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
775 PUSH_DATAf(push, color.f[0]);
776 PUSH_DATAf(push, color.f[1]);
777 PUSH_DATAf(push, color.f[2]);
778 PUSH_DATAf(push, color.f[3]);
780 if (nouveau_pushbuf_space(push, 64, 1, 0)) {
781 pipe_mutex_unlock(nv50->screen->base.push_mutex);
785 PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
787 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
788 PUSH_DATA (push, width << 16);
789 PUSH_DATA (push, height << 16);
790 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
791 PUSH_DATA (push, 8192 << 16);
792 PUSH_DATA (push, 8192 << 16);
793 nv50->scissors_dirty |= 1;
795 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
797 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
798 PUSH_DATAh(push, buf->address + offset);
799 PUSH_DATA (push, buf->address + offset);
800 PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
803 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
804 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | align(width * data_size, 0x100));
805 PUSH_DATA (push, height);
806 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
808 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
811 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
813 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
814 PUSH_DATA (push, (width << 16));
815 PUSH_DATA (push, (height << 16));
817 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
818 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
820 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
821 PUSH_DATA (push, 0x3c);
823 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
824 PUSH_DATA (push, nv50->cond_condmode);
827 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
828 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
831 if (width * height != elements) {
832 offset += width * height * data_size;
833 width = elements - width * height;
834 nv50_clear_buffer_push(pipe, res, offset, width * data_size,
838 pipe_mutex_unlock(nv50->screen->base.push_mutex);
840 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
843 /* =============================== BLIT CODE ===================================
848 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
849 struct nv50_program vp;
851 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
858 struct nv50_context *nv50;
859 struct nv50_program *fp;
863 uint8_t render_condition_enable;
864 enum pipe_texture_target target;
866 struct pipe_framebuffer_state fb;
867 struct nv50_window_rect_stateobj window_rect;
868 struct nv50_rasterizer_stateobj *rast;
869 struct nv50_program *vp;
870 struct nv50_program *gp;
871 struct nv50_program *fp;
872 unsigned num_textures[3];
873 unsigned num_samplers[3];
874 struct pipe_sampler_view *texture[2];
875 struct nv50_tsc_entry *sampler[2];
876 unsigned min_samples;
879 struct nv50_rasterizer_stateobj rast;
883 nv50_blitter_make_vp(struct nv50_blitter *blit)
885 static const uint32_t code[] =
887 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
888 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
889 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
890 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
891 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
894 blit->vp.type = PIPE_SHADER_VERTEX;
895 blit->vp.translated = true;
896 blit->vp.code = (uint32_t *)code; /* const_cast */
897 blit->vp.code_size = sizeof(code);
898 blit->vp.max_gpr = 4;
899 blit->vp.max_out = 5;
901 blit->vp.out[0].mask = 0x3;
902 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
903 blit->vp.out[1].hw = 2;
904 blit->vp.out[1].mask = 0x7;
905 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
906 blit->vp.out[1].si = 0;
907 blit->vp.vp.attrs[0] = 0x73;
908 blit->vp.vp.psiz = 0x40;
909 blit->vp.vp.edgeflag = 0x40;
913 nv50_blitter_make_fp(struct pipe_context *pipe,
915 enum pipe_texture_target ptarg)
917 struct ureg_program *ureg;
920 struct ureg_dst data;
922 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
924 bool tex_rgbaz = false;
926 bool cvt_un8 = false;
928 if (mode != NV50_BLIT_MODE_PASS &&
929 mode != NV50_BLIT_MODE_Z24X8 &&
930 mode != NV50_BLIT_MODE_X8Z24)
933 if (mode != NV50_BLIT_MODE_X24S8 &&
934 mode != NV50_BLIT_MODE_S8X24 &&
935 mode != NV50_BLIT_MODE_XS)
938 if (mode != NV50_BLIT_MODE_PASS &&
939 mode != NV50_BLIT_MODE_ZS &&
940 mode != NV50_BLIT_MODE_XS)
943 ureg = ureg_create(PIPE_SHADER_FRAGMENT);
947 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
948 tc = ureg_DECL_fs_input(
949 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
951 if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
952 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
953 tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
954 TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
957 data = ureg_DECL_temporary(ureg);
960 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
961 target, tc, ureg_DECL_sampler(ureg, 1));
962 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
963 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
966 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
967 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
968 ureg_TEX(ureg, ureg_writemask(data, mask),
969 target, tc, ureg_DECL_sampler(ureg, 0));
973 struct ureg_src mask;
974 struct ureg_src scale;
975 struct ureg_dst outz;
976 struct ureg_dst outs;
977 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
978 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
979 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
980 struct ureg_src zsrc3 = ureg_src(data);
981 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
982 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
983 struct ureg_src zshuf;
985 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
986 scale = ureg_imm4f(ureg,
987 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
990 if (mode == NV50_BLIT_MODE_Z24S8 ||
991 mode == NV50_BLIT_MODE_X24S8 ||
992 mode == NV50_BLIT_MODE_Z24X8) {
993 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
994 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
995 zshuf = ureg_src(data);
997 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
998 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
999 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
1000 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
1004 ureg_I2F(ureg, sdst, ssrc);
1005 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
1009 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
1010 ureg_F2I(ureg, zdst, zsrc);
1011 ureg_AND(ureg, zdst3, zsrc, mask);
1012 ureg_I2F(ureg, zdst3, zsrc3);
1013 ureg_MUL(ureg, zdst3, zsrc3, scale);
1014 ureg_MOV(ureg, outz, zshuf);
1017 unsigned mask = TGSI_WRITEMASK_XYZW;
1019 if (mode != NV50_BLIT_MODE_PASS) {
1020 mask &= ~TGSI_WRITEMASK_ZW;
1022 mask = TGSI_WRITEMASK_X;
1024 mask = TGSI_WRITEMASK_Y;
1026 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
1030 return ureg_create_shader_and_destroy(ureg, pipe);
1034 nv50_blitter_make_sampler(struct nv50_blitter *blit)
1036 /* clamp to edge, min/max lod = 0, nearest filtering */
1038 blit->sampler[0].id = -1;
1040 blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
1041 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
1042 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
1043 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
1044 blit->sampler[0].tsc[1] =
1045 G80_TSC_1_MAG_FILTER_NEAREST |
1046 G80_TSC_1_MIN_FILTER_NEAREST |
1047 G80_TSC_1_MIP_FILTER_NONE;
1049 /* clamp to edge, min/max lod = 0, bilinear filtering */
1051 blit->sampler[1].id = -1;
1053 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
1054 blit->sampler[1].tsc[1] =
1055 G80_TSC_1_MAG_FILTER_LINEAR |
1056 G80_TSC_1_MIN_FILTER_LINEAR |
1057 G80_TSC_1_MIP_FILTER_NONE;
1061 nv50_blit_select_mode(const struct pipe_blit_info *info)
1063 const unsigned mask = info->mask;
1065 switch (info->dst.resource->format) {
1066 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1067 case PIPE_FORMAT_Z24X8_UNORM:
1068 case PIPE_FORMAT_X24S8_UINT:
1069 switch (mask & PIPE_MASK_ZS) {
1070 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
1071 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
1073 return NV50_BLIT_MODE_X24S8;
1075 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1076 case PIPE_FORMAT_X8Z24_UNORM:
1077 case PIPE_FORMAT_S8X24_UINT:
1078 switch (mask & PIPE_MASK_ZS) {
1079 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
1080 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
1082 return NV50_BLIT_MODE_S8X24;
1084 case PIPE_FORMAT_Z32_FLOAT:
1085 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1086 case PIPE_FORMAT_X32_S8X24_UINT:
1087 switch (mask & PIPE_MASK_ZS) {
1088 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
1089 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
1091 return NV50_BLIT_MODE_XS;
1094 return NV50_BLIT_MODE_PASS;
1099 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
1101 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
1103 const enum pipe_texture_target ptarg =
1104 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
1106 const unsigned targ = nv50_blit_texture_type(ptarg);
1107 const unsigned mode = ctx->mode;
1109 if (!blitter->fp[targ][mode]) {
1110 pipe_mutex_lock(blitter->mutex);
1111 if (!blitter->fp[targ][mode])
1112 blitter->fp[targ][mode] =
1113 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
1114 pipe_mutex_unlock(blitter->mutex);
1116 ctx->fp = blitter->fp[targ][mode];
1120 nv50_blit_set_dst(struct nv50_blitctx *ctx,
1121 struct pipe_resource *res, unsigned level, unsigned layer,
1122 enum pipe_format format)
1124 struct nv50_context *nv50 = ctx->nv50;
1125 struct pipe_context *pipe = &nv50->base.pipe;
1126 struct pipe_surface templ;
1128 if (util_format_is_depth_or_stencil(format))
1129 templ.format = nv50_blit_zeta_to_colour_format(format);
1131 templ.format = format;
1133 templ.u.tex.level = level;
1134 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1137 templ.u.tex.first_layer = 0;
1138 templ.u.tex.last_layer =
1139 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1142 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
1143 nv50->framebuffer.nr_cbufs = 1;
1144 nv50->framebuffer.zsbuf = NULL;
1145 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
1146 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
1150 nv50_blit_set_src(struct nv50_blitctx *blit,
1151 struct pipe_resource *res, unsigned level, unsigned layer,
1152 enum pipe_format format, const uint8_t filter)
1154 struct nv50_context *nv50 = blit->nv50;
1155 struct pipe_context *pipe = &nv50->base.pipe;
1156 struct pipe_sampler_view templ;
1158 enum pipe_texture_target target;
1160 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
1162 templ.format = format;
1163 templ.u.tex.first_level = templ.u.tex.last_level = level;
1164 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1165 templ.swizzle_r = PIPE_SWIZZLE_X;
1166 templ.swizzle_g = PIPE_SWIZZLE_Y;
1167 templ.swizzle_b = PIPE_SWIZZLE_Z;
1168 templ.swizzle_a = PIPE_SWIZZLE_W;
1171 templ.u.tex.first_layer = 0;
1172 templ.u.tex.last_layer =
1173 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1176 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
1177 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
1178 if (filter && res->nr_samples == 8)
1179 flags |= NV50_TEXVIEW_FILTER_MSAA8;
1181 nv50->textures[2][0] = nv50_create_texture_view(
1182 pipe, res, &templ, flags, target);
1183 nv50->textures[2][1] = NULL;
1185 nv50->num_textures[0] = nv50->num_textures[1] = 0;
1186 nv50->num_textures[2] = 1;
1188 templ.format = nv50_zs_to_s_format(format);
1189 if (templ.format != res->format) {
1190 nv50->textures[2][1] = nv50_create_texture_view(
1191 pipe, res, &templ, flags, target);
1192 nv50->num_textures[2] = 2;
1197 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
1199 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
1201 if (blit->nv50->cond_query && !blit->render_condition_enable) {
1202 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
1203 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
1207 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
1208 PUSH_DATA (push, blit->color_mask);
1209 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
1210 PUSH_DATA (push, 0);
1211 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
1212 PUSH_DATA (push, 0);
1214 /* rasterizer state */
1215 #ifndef NV50_SCISSORS_CLIPPING
1216 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
1217 PUSH_DATA (push, 1);
1219 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
1220 PUSH_DATA (push, 0);
1221 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
1222 PUSH_DATA (push, 0);
1223 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
1224 PUSH_DATA (push, 0);
1225 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
1226 PUSH_DATA (push, 0xffff);
1227 PUSH_DATA (push, 0xffff);
1228 PUSH_DATA (push, 0xffff);
1229 PUSH_DATA (push, 0xffff);
1230 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
1231 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
1232 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
1233 PUSH_DATA (push, 0);
1234 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
1235 PUSH_DATA (push, 0);
1236 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
1237 PUSH_DATA (push, 0);
1238 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
1239 PUSH_DATA (push, 0);
1242 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
1243 PUSH_DATA (push, 0);
1244 BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
1245 PUSH_DATA (push, 0);
1246 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
1247 PUSH_DATA (push, 0);
1248 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
1249 PUSH_DATA (push, 0);
1253 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx,
1254 const struct pipe_blit_info *info)
1256 struct nv50_context *nv50 = ctx->nv50;
1257 struct nv50_blitter *blitter = nv50->screen->blitter;
1260 ctx->saved.fb.width = nv50->framebuffer.width;
1261 ctx->saved.fb.height = nv50->framebuffer.height;
1262 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
1263 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
1264 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
1266 ctx->saved.rast = nv50->rast;
1268 ctx->saved.vp = nv50->vertprog;
1269 ctx->saved.gp = nv50->gmtyprog;
1270 ctx->saved.fp = nv50->fragprog;
1272 ctx->saved.min_samples = nv50->min_samples;
1273 ctx->saved.window_rect = nv50->window_rect;
1275 nv50->rast = &ctx->rast;
1277 nv50->vertprog = &blitter->vp;
1278 nv50->gmtyprog = NULL;
1279 nv50->fragprog = ctx->fp;
1281 nv50->window_rect.rects =
1282 MIN2(info->num_window_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1283 nv50->window_rect.inclusive = info->window_rectangle_include;
1284 if (nv50->window_rect.rects)
1285 memcpy(nv50->window_rect.rect, info->window_rectangles,
1286 sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1288 for (s = 0; s < 3; ++s) {
1289 ctx->saved.num_textures[s] = nv50->num_textures[s];
1290 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1292 ctx->saved.texture[0] = nv50->textures[2][0];
1293 ctx->saved.texture[1] = nv50->textures[2][1];
1294 ctx->saved.sampler[0] = nv50->samplers[2][0];
1295 ctx->saved.sampler[1] = nv50->samplers[2][1];
1297 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
1298 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
1300 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
1301 nv50->num_samplers[2] = 2;
1303 nv50->min_samples = 1;
1305 ctx->saved.dirty_3d = nv50->dirty_3d;
1307 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1308 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
1311 NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_MIN_SAMPLES |
1312 NV50_NEW_3D_VERTPROG | NV50_NEW_3D_FRAGPROG | NV50_NEW_3D_GMTYPROG |
1313 NV50_NEW_3D_TEXTURES | NV50_NEW_3D_SAMPLERS | NV50_NEW_3D_WINDOW_RECTS;
1317 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1319 struct nv50_context *nv50 = blit->nv50;
1322 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1324 nv50->framebuffer.width = blit->saved.fb.width;
1325 nv50->framebuffer.height = blit->saved.fb.height;
1326 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1327 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1328 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1330 nv50->rast = blit->saved.rast;
1332 nv50->vertprog = blit->saved.vp;
1333 nv50->gmtyprog = blit->saved.gp;
1334 nv50->fragprog = blit->saved.fp;
1336 nv50->min_samples = blit->saved.min_samples;
1337 nv50->window_rect = blit->saved.window_rect;
1339 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
1340 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
1342 for (s = 0; s < 3; ++s) {
1343 nv50->num_textures[s] = blit->saved.num_textures[s];
1344 nv50->num_samplers[s] = blit->saved.num_samplers[s];
1346 nv50->textures[2][0] = blit->saved.texture[0];
1347 nv50->textures[2][1] = blit->saved.texture[1];
1348 nv50->samplers[2][0] = blit->saved.sampler[0];
1349 nv50->samplers[2][1] = blit->saved.sampler[1];
1351 if (nv50->cond_query && !blit->render_condition_enable)
1352 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1353 nv50->cond_cond, nv50->cond_mode);
1355 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1356 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
1358 nv50->dirty_3d = blit->saved.dirty_3d |
1359 (NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR | NV50_NEW_3D_SAMPLE_MASK |
1360 NV50_NEW_3D_RASTERIZER | NV50_NEW_3D_ZSA | NV50_NEW_3D_BLEND |
1361 NV50_NEW_3D_TEXTURES | NV50_NEW_3D_SAMPLERS | NV50_NEW_3D_WINDOW_RECTS |
1362 NV50_NEW_3D_VERTPROG | NV50_NEW_3D_GMTYPROG | NV50_NEW_3D_FRAGPROG);
1363 nv50->scissors_dirty |= 1;
1365 nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1370 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1372 struct nv50_blitctx *blit = nv50->blit;
1373 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1374 struct pipe_resource *src = info->src.resource;
1375 struct pipe_resource *dst = info->dst.resource;
1376 int32_t minx, maxx, miny, maxy;
1378 float x0, x1, y0, y1, z;
1380 float x_range, y_range;
1383 blit->mode = nv50_blit_select_mode(info);
1384 blit->color_mask = nv50_blit_derive_color_mask(info);
1385 blit->filter = nv50_blit_get_filter(info);
1386 blit->render_condition_enable = info->render_condition_enable;
1388 nv50_blit_select_fp(blit, info);
1389 nv50_blitctx_pre_blit(blit, info);
1391 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1392 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1395 nv50_blitctx_prepare_state(blit);
1397 nv50_state_validate_3d(nv50, ~0);
1399 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1400 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1402 tri_x = 16384 << nv50_miptree(dst)->ms_x;
1403 tri_y = 16384 << nv50_miptree(dst)->ms_y;
1405 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1406 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1408 x1 = x0 + tri_x * x_range;
1409 y1 = y0 + tri_y * y_range;
1411 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1412 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1413 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1414 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1416 /* XXX: multiply by 6 for cube arrays ? */
1417 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1418 z = (float)info->src.box.z;
1419 if (nv50_miptree(src)->layout_3d)
1422 if (src->last_level > 0) {
1423 /* If there are mip maps, GPU always assumes normalized coordinates. */
1424 const unsigned l = info->src.level;
1425 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1426 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1431 if (nv50_miptree(src)->layout_3d) {
1432 z /= u_minify(src->depth0, l);
1433 dz /= u_minify(src->depth0, l);
1437 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1438 PUSH_DATA (push, 0);
1439 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1440 PUSH_DATA (push, 0x1);
1442 /* Draw a large triangle in screen coordinates covering the whole
1443 * render target, with scissors defining the destination region.
1444 * The vertex is supplied with non-normalized texture coordinates
1445 * arranged in a way to yield the desired offset and scale.
1448 minx = info->dst.box.x;
1449 maxx = info->dst.box.x + info->dst.box.width;
1450 miny = info->dst.box.y;
1451 maxy = info->dst.box.y + info->dst.box.height;
1452 if (info->scissor_enable) {
1453 minx = MAX2(minx, info->scissor.minx);
1454 maxx = MIN2(maxx, info->scissor.maxx);
1455 miny = MAX2(miny, info->scissor.miny);
1456 maxy = MIN2(maxy, info->scissor.maxy);
1458 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1459 PUSH_DATA (push, (maxx << 16) | minx);
1460 PUSH_DATA (push, (maxy << 16) | miny);
1462 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1463 if (info->dst.box.z + i) {
1464 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1465 PUSH_DATA (push, info->dst.box.z + i);
1467 PUSH_SPACE(push, 32);
1468 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1469 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1470 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1471 PUSH_DATAf(push, x0);
1472 PUSH_DATAf(push, y0);
1473 PUSH_DATAf(push, z);
1474 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1475 PUSH_DATAf(push, 0.0f);
1476 PUSH_DATAf(push, 0.0f);
1477 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1478 PUSH_DATAf(push, x1);
1479 PUSH_DATAf(push, y0);
1480 PUSH_DATAf(push, z);
1481 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1482 PUSH_DATAf(push, tri_x);
1483 PUSH_DATAf(push, 0.0f);
1484 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1485 PUSH_DATAf(push, x0);
1486 PUSH_DATAf(push, y1);
1487 PUSH_DATAf(push, z);
1488 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1489 PUSH_DATAf(push, 0.0f);
1490 PUSH_DATAf(push, tri_y);
1491 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1492 PUSH_DATA (push, 0);
1494 if (info->dst.box.z + info->dst.box.depth - 1) {
1495 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1496 PUSH_DATA (push, 0);
1499 /* re-enable normally constant state */
1501 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1502 PUSH_DATA (push, 1);
1504 nv50_blitctx_post_blit(blit);
1508 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1510 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1511 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1512 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1513 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1514 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1515 const int32_t dz = info->dst.box.z;
1516 const int32_t sz = info->src.box.z;
1517 uint32_t dstw, dsth;
1520 int64_t du_dx, dv_dy;
1523 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1526 mode = nv50_blit_get_filter(info) ?
1527 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1528 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1529 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1530 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1532 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1533 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1535 b = info->dst.format == info->src.format;
1536 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1537 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1539 if (info->scissor_enable) {
1540 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1541 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1542 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1543 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1544 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1545 PUSH_DATA (push, 1); /* enable */
1548 if (nv50->cond_query && info->render_condition_enable) {
1549 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1550 PUSH_DATA (push, nv50->cond_condmode);
1553 if (mask != 0xffffffff) {
1554 BEGIN_NV04(push, NV50_2D(ROP), 1);
1555 PUSH_DATA (push, 0xca); /* DPSDxax */
1556 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1557 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1558 BEGIN_NV04(push, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1559 PUSH_DATA (push, 0x00000000);
1560 PUSH_DATA (push, mask);
1561 PUSH_DATA (push, 0xffffffff);
1562 PUSH_DATA (push, 0xffffffff);
1563 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1564 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1566 if (info->src.format != info->dst.format) {
1567 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1568 info->src.format == PIPE_FORMAT_R16_UNORM ||
1569 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1570 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1571 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1572 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1573 PUSH_DATA (push, mask);
1574 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1578 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1579 /* ms_x is always >= ms_y */
1580 du_dx <<= src->ms_x - dst->ms_x;
1581 dv_dy <<= src->ms_y - dst->ms_y;
1583 du_dx >>= dst->ms_x - src->ms_x;
1584 dv_dy >>= dst->ms_y - src->ms_y;
1587 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1588 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1590 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1591 /* center src coorinates for proper MS resolve filtering */
1592 srcx += (int64_t)1 << (src->ms_x + 31);
1593 srcy += (int64_t)1 << (src->ms_y + 31);
1596 dstx = info->dst.box.x << dst->ms_x;
1597 dsty = info->dst.box.y << dst->ms_y;
1599 dstw = info->dst.box.width << dst->ms_x;
1600 dsth = info->dst.box.height << dst->ms_y;
1604 srcx -= du_dx * dstx;
1609 srcy -= dv_dy * dsty;
1613 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1614 PUSH_DATA (push, mode);
1615 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1616 PUSH_DATA (push, dstx);
1617 PUSH_DATA (push, dsty);
1618 PUSH_DATA (push, dstw);
1619 PUSH_DATA (push, dsth);
1620 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1621 PUSH_DATA (push, du_dx);
1622 PUSH_DATA (push, du_dx >> 32);
1623 PUSH_DATA (push, dv_dy);
1624 PUSH_DATA (push, dv_dy >> 32);
1626 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1627 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1628 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1629 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1632 for (i = 0; i < info->dst.box.depth; ++i) {
1634 /* no scaling in z-direction possible for eng2d blits */
1635 if (dst->layout_3d) {
1636 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1637 PUSH_DATA (push, info->dst.box.z + i);
1639 const unsigned z = info->dst.box.z + i;
1640 const uint64_t address = dst->base.address +
1641 dst->level[info->dst.level].offset +
1642 z * dst->layer_stride;
1643 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1644 PUSH_DATAh(push, address);
1645 PUSH_DATA (push, address);
1647 if (src->layout_3d) {
1648 /* not possible because of depth tiling */
1651 const unsigned z = info->src.box.z + i;
1652 const uint64_t address = src->base.address +
1653 src->level[info->src.level].offset +
1654 z * src->layer_stride;
1655 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1656 PUSH_DATAh(push, address);
1657 PUSH_DATA (push, address);
1659 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1660 PUSH_DATA (push, srcy >> 32);
1662 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1663 PUSH_DATA (push, srcx);
1664 PUSH_DATA (push, srcx >> 32);
1665 PUSH_DATA (push, srcy);
1666 PUSH_DATA (push, srcy >> 32);
1669 nv50_bufctx_fence(nv50->bufctx, false);
1671 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1673 if (info->scissor_enable) {
1674 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1675 PUSH_DATA (push, 0);
1677 if (mask != 0xffffffff) {
1678 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1679 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1681 if (nv50->cond_query && info->render_condition_enable) {
1682 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1683 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1688 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1690 struct nv50_context *nv50 = nv50_context(pipe);
1691 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1694 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1695 if (!(info->mask & PIPE_MASK_ZS))
1697 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1698 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1700 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1703 if (!(info->mask & PIPE_MASK_RGBA))
1705 if (info->mask != PIPE_MASK_RGBA)
1709 if (nv50_miptree(info->src.resource)->layout_3d) {
1712 if (info->src.box.depth != info->dst.box.depth) {
1714 debug_printf("blit: cannot filter array or cube textures in z direction");
1717 if (!eng3d && info->dst.format != info->src.format) {
1718 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1719 !nv50_2d_src_format_faithful(info->src.format)) {
1722 if (!nv50_2d_src_format_faithful(info->src.format)) {
1723 if (!util_format_is_luminance(info->src.format)) {
1724 if (util_format_is_intensity(info->src.format))
1727 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1730 eng3d = !nv50_2d_format_supported(info->src.format);
1733 if (util_format_is_luminance_alpha(info->src.format))
1737 if (info->src.resource->nr_samples == 8 &&
1738 info->dst.resource->nr_samples <= 1)
1741 if (info->num_window_rectangles > 0 || info->window_rectangle_include)
1744 /* FIXME: can't make this work with eng2d anymore */
1745 if ((info->src.resource->nr_samples | 1) !=
1746 (info->dst.resource->nr_samples | 1))
1749 /* FIXME: find correct src coordinate adjustments */
1750 if ((info->src.box.width != info->dst.box.width &&
1751 info->src.box.width != -info->dst.box.width) ||
1752 (info->src.box.height != info->dst.box.height &&
1753 info->src.box.height != -info->dst.box.height))
1756 pipe_mutex_lock(nv50->screen->base.push_mutex);
1758 if (nv50->screen->num_occlusion_queries_active) {
1759 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1760 PUSH_DATA (push, 0);
1764 nv50_blit_eng2d(nv50, info);
1766 nv50_blit_3d(nv50, info);
1768 if (nv50->screen->num_occlusion_queries_active) {
1769 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1770 PUSH_DATA (push, 1);
1773 pipe_mutex_unlock(nv50->screen->base.push_mutex);
1777 nv50_flush_resource(struct pipe_context *ctx,
1778 struct pipe_resource *resource)
1783 nv50_blitter_create(struct nv50_screen *screen)
1785 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1786 if (!screen->blitter) {
1787 NOUVEAU_ERR("failed to allocate blitter struct\n");
1791 pipe_mutex_init(screen->blitter->mutex);
1793 nv50_blitter_make_vp(screen->blitter);
1794 nv50_blitter_make_sampler(screen->blitter);
1800 nv50_blitter_destroy(struct nv50_screen *screen)
1802 struct nv50_blitter *blitter = screen->blitter;
1805 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1806 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1807 struct nv50_program *prog = blitter->fp[i][m];
1809 nv50_program_destroy(NULL, prog);
1810 FREE((void *)prog->pipe.tokens);
1816 pipe_mutex_destroy(blitter->mutex);
1821 nv50_blitctx_create(struct nv50_context *nv50)
1823 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1825 NOUVEAU_ERR("failed to allocate blit context\n");
1829 nv50->blit->nv50 = nv50;
1831 nv50->blit->rast.pipe.half_pixel_center = 1;
1837 nv50_init_surface_functions(struct nv50_context *nv50)
1839 struct pipe_context *pipe = &nv50->base.pipe;
1841 pipe->resource_copy_region = nv50_resource_copy_region;
1842 pipe->blit = nv50_blit;
1843 pipe->flush_resource = nv50_flush_resource;
1844 pipe->clear_texture = nv50_clear_texture;
1845 pipe->clear_render_target = nv50_clear_render_target;
1846 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1847 pipe->clear_buffer = nv50_clear_buffer;