src/gallium/drivers/nouveau/nvc0/nvc0_state.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_defines.h"
  24 #include "util/u_framebuffer.h"
  25 #include "util/u_helpers.h"
  26 #include "util/u_inlines.h"
  27 #include "util/u_transfer.h"
  28
  29 #include "tgsi/tgsi_parse.h"
  30
  31 #include "nvc0/nvc0_stateobj.h"
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_query_hw.h"
  34
  35 #include "nvc0/nvc0_3d.xml.h"
  36
  37 #include "nouveau_gldefs.h"
  38
  39 static inline uint32_t
  40 nvc0_colormask(unsigned mask)
  41 {
  42     uint32_t ret = 0;
  43
  44     if (mask & PIPE_MASK_R)
  45         ret |= 0x0001;
  46     if (mask & PIPE_MASK_G)
  47         ret |= 0x0010;
  48     if (mask & PIPE_MASK_B)
  49         ret |= 0x0100;
  50     if (mask & PIPE_MASK_A)
  51         ret |= 0x1000;
  52
  53     return ret;
  54 }
  55
  56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
  57    case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
  58
  59 static inline uint32_t
  60 nvc0_blend_fac(unsigned factor)
  61 {
  62    switch (factor) {
  63    NVC0_BLEND_FACTOR_CASE(ONE, ONE);
  64    NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
  65    NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
  66    NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
  67    NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
  68    NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
  69    NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
  70    NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
  71    NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
  72    NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
  73    NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
  74    NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
  75    NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
  76    NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
  77    NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
  78    NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
  79    NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
  80    NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
  81    NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
  82    default:
  83       return NV50_BLEND_FACTOR_ZERO;
  84    }
  85 }
  86
  87 static void *
  88 nvc0_blend_state_create(struct pipe_context *pipe,
  89                         const struct pipe_blend_state *cso)
  90 {
  91    struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
  92    int i;
  93    int r; /* reference */
  94    uint8_t blend_en = 0;
  95    bool indep_masks = false;
  96    bool indep_funcs = false;
  97
  98    so->pipe = *cso;
  99
 100    /* check which states actually have differing values */
 101    if (cso->independent_blend_enable) {
 102       for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
 103       blend_en |= 1 << r;
 104       for (i = r + 1; i < 8; ++i) {
 105          if (!cso->rt[i].blend_enable)
 106             continue;
 107          blend_en |= 1 << i;
 108          if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
 109              cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
 110              cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
 111              cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
 112              cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
 113              cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
 114             indep_funcs = true;
 115             break;
 116          }
 117       }
 118       for (; i < 8; ++i)
 119          blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
 120
 121       for (i = 1; i < 8; ++i) {
 122          if (cso->rt[i].colormask != cso->rt[0].colormask) {
 123             indep_masks = true;
 124             break;
 125          }
 126       }
 127    } else {
 128       r = 0;
 129       if (cso->rt[0].blend_enable)
 130          blend_en = 0xff;
 131    }
 132
 133    if (cso->logicop_enable) {
 134       SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
 135       SB_DATA    (so, 1);
 136       SB_DATA    (so, nvgl_logicop_func(cso->logicop_func));
 137
 138       SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
 139    } else {
 140       SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
 141
 142       SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
 143       SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
 144       if (indep_funcs) {
 145          for (i = 0; i < 8; ++i) {
 146             if (cso->rt[i].blend_enable) {
 147                SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
 148                SB_DATA    (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
 149                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
 150                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
 151                SB_DATA    (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
 152                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
 153                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
 154             }
 155          }
 156       } else
 157       if (blend_en) {
 158          SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
 159          SB_DATA    (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
 160          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
 161          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
 162          SB_DATA    (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
 163          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
 164          SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
 165          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
 166       }
 167
 168       SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
 169       if (indep_masks) {
 170          SB_BEGIN_3D(so, COLOR_MASK(0), 8);
 171          for (i = 0; i < 8; ++i)
 172             SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
 173       } else {
 174          SB_BEGIN_3D(so, COLOR_MASK(0), 1);
 175          SB_DATA    (so, nvc0_colormask(cso->rt[0].colormask));
 176       }
 177    }
 178
 179    assert(so->size <= ARRAY_SIZE(so->state));
 180    return so;
 181 }
 182
 183 static void
 184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
 185 {
 186     struct nvc0_context *nvc0 = nvc0_context(pipe);
 187
 188     nvc0->blend = hwcso;
 189     nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
 190 }
 191
 192 static void
 193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
 194 {
 195     FREE(hwcso);
 196 }
 197
 198 /* NOTE: ignoring line_last_pixel */
 199 static void *
 200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
 201                              const struct pipe_rasterizer_state *cso)
 202 {
 203     struct nvc0_rasterizer_stateobj *so;
 204     uint32_t reg;
 205
 206     so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
 207     if (!so)
 208         return NULL;
 209     so->pipe = *cso;
 210
 211     /* Scissor enables are handled in scissor state, we will not want to
 212      * always emit 16 commands, one for each scissor rectangle, here.
 213      */
 214
 215     SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
 216     SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
 217
 218     SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
 219     SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
 220     SB_DATA    (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
 221
 222     SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
 223
 224     SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
 225     if (cso->line_smooth || cso->multisample)
 226        SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
 227     else
 228        SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
 229     SB_DATA    (so, fui(cso->line_width));
 230
 231     SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
 232     if (cso->line_stipple_enable) {
 233         SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
 234         SB_DATA    (so, (cso->line_stipple_pattern << 8) |
 235                          cso->line_stipple_factor);
 236
 237     }
 238
 239     SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
 240     if (!cso->point_size_per_vertex) {
 241        SB_BEGIN_3D(so, POINT_SIZE, 1);
 242        SB_DATA    (so, fui(cso->point_size));
 243     }
 244
 245     reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
 246        NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
 247        NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
 248
 249     SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
 250     SB_DATA    (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
 251     SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
 252     SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
 253
 254     SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
 255     SB_DATA    (so, nvgl_polygon_mode(cso->fill_front));
 256     SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
 257     SB_DATA    (so, nvgl_polygon_mode(cso->fill_back));
 258     SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
 259
 260     SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
 261     SB_DATA    (so, cso->cull_face != PIPE_FACE_NONE);
 262     SB_DATA    (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
 263                                      NVC0_3D_FRONT_FACE_CW);
 264     switch (cso->cull_face) {
 265     case PIPE_FACE_FRONT_AND_BACK:
 266        SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
 267        break;
 268     case PIPE_FACE_FRONT:
 269        SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
 270        break;
 271     case PIPE_FACE_BACK:
 272     default:
 273        SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
 274        break;
 275     }
 276
 277     SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
 278     SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
 279     SB_DATA    (so, cso->offset_point);
 280     SB_DATA    (so, cso->offset_line);
 281     SB_DATA    (so, cso->offset_tri);
 282
 283     if (cso->offset_point || cso->offset_line || cso->offset_tri) {
 284         SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
 285         SB_DATA    (so, fui(cso->offset_scale));
 286         SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
 287         SB_DATA    (so, fui(cso->offset_units * 2.0f));
 288         SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
 289         SB_DATA    (so, fui(cso->offset_clamp));
 290     }
 291
 292     if (cso->depth_clip)
 293        reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
 294     else
 295        reg =
 296           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
 297           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
 298           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
 299           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
 300
 301     SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
 302     SB_DATA    (so, reg);
 303
 304     SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
 305
 306     SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
 307
 308     assert(so->size <= ARRAY_SIZE(so->state));
 309     return (void *)so;
 310 }
 311
 312 static void
 313 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 314 {
 315    struct nvc0_context *nvc0 = nvc0_context(pipe);
 316
 317    nvc0->rast = hwcso;
 318    nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
 319 }
 320
 321 static void
 322 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
 323 {
 324    FREE(hwcso);
 325 }
 326
 327 static void *
 328 nvc0_zsa_state_create(struct pipe_context *pipe,
 329                       const struct pipe_depth_stencil_alpha_state *cso)
 330 {
 331    struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
 332
 333    so->pipe = *cso;
 334
 335    SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
 336    if (cso->depth.enabled) {
 337       SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
 338       SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
 339       SB_DATA    (so, nvgl_comparison_op(cso->depth.func));
 340    }
 341
 342    SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
 343    if (cso->depth.bounds_test) {
 344       SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
 345       SB_DATA    (so, fui(cso->depth.bounds_min));
 346       SB_DATA    (so, fui(cso->depth.bounds_max));
 347    }
 348
 349    if (cso->stencil[0].enabled) {
 350       SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
 351       SB_DATA    (so, 1);
 352       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].fail_op));
 353       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
 354       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
 355       SB_DATA    (so, nvgl_comparison_op(cso->stencil[0].func));
 356       SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
 357       SB_DATA    (so, cso->stencil[0].valuemask);
 358       SB_DATA    (so, cso->stencil[0].writemask);
 359    } else {
 360       SB_IMMED_3D(so, STENCIL_ENABLE, 0);
 361    }
 362
 363    if (cso->stencil[1].enabled) {
 364       assert(cso->stencil[0].enabled);
 365       SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
 366       SB_DATA    (so, 1);
 367       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].fail_op));
 368       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
 369       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
 370       SB_DATA    (so, nvgl_comparison_op(cso->stencil[1].func));
 371       SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
 372       SB_DATA    (so, cso->stencil[1].writemask);
 373       SB_DATA    (so, cso->stencil[1].valuemask);
 374    } else
 375    if (cso->stencil[0].enabled) {
 376       SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
 377    }
 378
 379    SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
 380    if (cso->alpha.enabled) {
 381       SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
 382       SB_DATA    (so, fui(cso->alpha.ref_value));
 383       SB_DATA    (so, nvgl_comparison_op(cso->alpha.func));
 384    }
 385
 386    assert(so->size <= ARRAY_SIZE(so->state));
 387    return (void *)so;
 388 }
 389
 390 static void
 391 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
 392 {
 393    struct nvc0_context *nvc0 = nvc0_context(pipe);
 394
 395    nvc0->zsa = hwcso;
 396    nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
 397 }
 398
 399 static void
 400 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
 401 {
 402    FREE(hwcso);
 403 }
 404
 405 /* ====================== SAMPLERS AND TEXTURES ================================
 406  */
 407
 408 #define NV50_TSC_WRAP_CASE(n) \
 409     case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
 410
 411 static void
 412 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
 413 {
 414    unsigned s, i;
 415
 416    for (s = 0; s < 6; ++s)
 417       for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
 418          if (nvc0_context(pipe)->samplers[s][i] == hwcso)
 419             nvc0_context(pipe)->samplers[s][i] = NULL;
 420
 421    nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
 422
 423    FREE(hwcso);
 424 }
 425
 426 static inline void
 427 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
 428                                unsigned nr, void **hwcso)
 429 {
 430    unsigned i;
 431
 432    for (i = 0; i < nr; ++i) {
 433       struct nv50_tsc_entry *old = nvc0->samplers[s][i];
 434
 435       if (hwcso[i] == old)
 436          continue;
 437       nvc0->samplers_dirty[s] |= 1 << i;
 438
 439       nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
 440       if (old)
 441          nvc0_screen_tsc_unlock(nvc0->screen, old);
 442    }
 443    for (; i < nvc0->num_samplers[s]; ++i) {
 444       if (nvc0->samplers[s][i]) {
 445          nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
 446          nvc0->samplers[s][i] = NULL;
 447       }
 448    }
 449
 450    nvc0->num_samplers[s] = nr;
 451
 452    nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
 453 }
 454
 455 static void
 456 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
 457                                      const unsigned s,
 458                                      unsigned start, unsigned nr, void **cso)
 459 {
 460    const unsigned end = start + nr;
 461    int last_valid = -1;
 462    unsigned i;
 463
 464    if (cso) {
 465       for (i = start; i < end; ++i) {
 466          const unsigned p = i - start;
 467          if (cso[p])
 468             last_valid = i;
 469          if (cso[p] == nvc0->samplers[s][i])
 470             continue;
 471          nvc0->samplers_dirty[s] |= 1 << i;
 472
 473          if (nvc0->samplers[s][i])
 474             nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
 475          nvc0->samplers[s][i] = cso[p];
 476       }
 477    } else {
 478       for (i = start; i < end; ++i) {
 479          if (nvc0->samplers[s][i]) {
 480             nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
 481             nvc0->samplers[s][i] = NULL;
 482             nvc0->samplers_dirty[s] |= 1 << i;
 483          }
 484       }
 485    }
 486
 487    if (nvc0->num_samplers[s] <= end) {
 488       if (last_valid < 0) {
 489          for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
 490          nvc0->num_samplers[s] = i;
 491       } else {
 492          nvc0->num_samplers[s] = last_valid + 1;
 493       }
 494    }
 495 }
 496
 497 static void
 498 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
 499                          unsigned start, unsigned nr, void **s)
 500 {
 501    switch (shader) {
 502    case PIPE_SHADER_VERTEX:
 503       assert(start == 0);
 504       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
 505       break;
 506    case PIPE_SHADER_TESS_CTRL:
 507       assert(start == 0);
 508       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
 509       break;
 510    case PIPE_SHADER_TESS_EVAL:
 511       assert(start == 0);
 512       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
 513       break;
 514    case PIPE_SHADER_GEOMETRY:
 515       assert(start == 0);
 516       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
 517       break;
 518    case PIPE_SHADER_FRAGMENT:
 519       assert(start == 0);
 520       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
 521       break;
 522    case PIPE_SHADER_COMPUTE:
 523       nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
 524                                            start, nr, s);
 525       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
 526       break;
 527    }
 528 }
 529
 530
 531 /* NOTE: only called when not referenced anywhere, won't be bound */
 532 static void
 533 nvc0_sampler_view_destroy(struct pipe_context *pipe,
 534                           struct pipe_sampler_view *view)
 535 {
 536    pipe_resource_reference(&view->texture, NULL);
 537
 538    nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
 539
 540    FREE(nv50_tic_entry(view));
 541 }
 542
 543 static inline void
 544 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
 545                              unsigned nr,
 546                              struct pipe_sampler_view **views)
 547 {
 548    unsigned i;
 549
 550    for (i = 0; i < nr; ++i) {
 551       struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
 552
 553       if (views[i] == nvc0->textures[s][i])
 554          continue;
 555       nvc0->textures_dirty[s] |= 1 << i;
 556
 557       if (views[i] && views[i]->texture) {
 558          struct pipe_resource *res = views[i]->texture;
 559          if (res->target == PIPE_BUFFER &&
 560              (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
 561             nvc0->textures_coherent[s] |= 1 << i;
 562          else
 563             nvc0->textures_coherent[s] &= ~(1 << i);
 564       } else {
 565          nvc0->textures_coherent[s] &= ~(1 << i);
 566       }
 567
 568       if (old) {
 569          nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
 570          nvc0_screen_tic_unlock(nvc0->screen, old);
 571       }
 572
 573       pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
 574    }
 575
 576    for (i = nr; i < nvc0->num_textures[s]; ++i) {
 577       struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
 578       if (old) {
 579          nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
 580          nvc0_screen_tic_unlock(nvc0->screen, old);
 581          pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
 582       }
 583    }
 584
 585    nvc0->num_textures[s] = nr;
 586
 587    nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
 588 }
 589
 590 static void
 591 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
 592                                    unsigned start, unsigned nr,
 593                                    struct pipe_sampler_view **views)
 594 {
 595    struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
 596    const unsigned end = start + nr;
 597    const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_3D_TEX(s, 0);
 598    int last_valid = -1;
 599    unsigned i;
 600
 601    if (views) {
 602       for (i = start; i < end; ++i) {
 603          const unsigned p = i - start;
 604          if (views[p])
 605             last_valid = i;
 606          if (views[p] == nvc0->textures[s][i])
 607             continue;
 608          nvc0->textures_dirty[s] |= 1 << i;
 609
 610          if (views[p] && views[p]->texture) {
 611             struct pipe_resource *res = views[p]->texture;
 612             if (res->target == PIPE_BUFFER &&
 613                 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
 614                nvc0->textures_coherent[s] |= 1 << i;
 615             else
 616                nvc0->textures_coherent[s] &= ~(1 << i);
 617          } else {
 618             nvc0->textures_coherent[s] &= ~(1 << i);
 619          }
 620
 621          if (nvc0->textures[s][i]) {
 622             struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
 623             nouveau_bufctx_reset(bctx, bin + i);
 624             nvc0_screen_tic_unlock(nvc0->screen, old);
 625          }
 626          pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
 627       }
 628    } else {
 629       for (i = start; i < end; ++i) {
 630          struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
 631          if (!old)
 632             continue;
 633          nvc0->textures_dirty[s] |= 1 << i;
 634
 635          nvc0_screen_tic_unlock(nvc0->screen, old);
 636          pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
 637          nouveau_bufctx_reset(bctx, bin + i);
 638       }
 639    }
 640
 641    if (nvc0->num_textures[s] <= end) {
 642       if (last_valid < 0) {
 643          for (i = start; i && !nvc0->textures[s][i - 1]; --i);
 644          nvc0->num_textures[s] = i;
 645       } else {
 646          nvc0->num_textures[s] = last_valid + 1;
 647       }
 648    }
 649 }
 650
 651 static void
 652 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 653                        unsigned start, unsigned nr,
 654                        struct pipe_sampler_view **views)
 655 {
 656    assert(start == 0);
 657    switch (shader) {
 658    case PIPE_SHADER_VERTEX:
 659       nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
 660       break;
 661    case PIPE_SHADER_TESS_CTRL:
 662       nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
 663       break;
 664    case PIPE_SHADER_TESS_EVAL:
 665       nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
 666       break;
 667    case PIPE_SHADER_GEOMETRY:
 668       nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
 669       break;
 670    case PIPE_SHADER_FRAGMENT:
 671       nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
 672       break;
 673    case PIPE_SHADER_COMPUTE:
 674       nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
 675                                          start, nr, views);
 676       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
 677       break;
 678    default:
 679       ;
 680    }
 681 }
 682
 683
 684 /* ============================= SHADERS =======================================
 685  */
 686
 687 static void *
 688 nvc0_sp_state_create(struct pipe_context *pipe,
 689                      const struct pipe_shader_state *cso, unsigned type)
 690 {
 691    struct nvc0_program *prog;
 692
 693    prog = CALLOC_STRUCT(nvc0_program);
 694    if (!prog)
 695       return NULL;
 696
 697    prog->type = type;
 698
 699    if (cso->tokens)
 700       prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
 701
 702    if (cso->stream_output.num_outputs)
 703       prog->pipe.stream_output = cso->stream_output;
 704
 705    prog->translated = nvc0_program_translate(
 706       prog, nvc0_context(pipe)->screen->base.device->chipset,
 707       &nouveau_context(pipe)->debug);
 708
 709    return (void *)prog;
 710 }
 711
 712 static void
 713 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
 714 {
 715    struct nvc0_program *prog = (struct nvc0_program *)hwcso;
 716
 717    nvc0_program_destroy(nvc0_context(pipe), prog);
 718
 719    FREE((void *)prog->pipe.tokens);
 720    FREE(prog);
 721 }
 722
 723 static void *
 724 nvc0_vp_state_create(struct pipe_context *pipe,
 725                      const struct pipe_shader_state *cso)
 726 {
 727    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
 728 }
 729
 730 static void
 731 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
 732 {
 733     struct nvc0_context *nvc0 = nvc0_context(pipe);
 734
 735     nvc0->vertprog = hwcso;
 736     nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
 737 }
 738
 739 static void *
 740 nvc0_fp_state_create(struct pipe_context *pipe,
 741                      const struct pipe_shader_state *cso)
 742 {
 743    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
 744 }
 745
 746 static void
 747 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
 748 {
 749     struct nvc0_context *nvc0 = nvc0_context(pipe);
 750
 751     nvc0->fragprog = hwcso;
 752     nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
 753 }
 754
 755 static void *
 756 nvc0_gp_state_create(struct pipe_context *pipe,
 757                      const struct pipe_shader_state *cso)
 758 {
 759    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
 760 }
 761
 762 static void
 763 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
 764 {
 765     struct nvc0_context *nvc0 = nvc0_context(pipe);
 766
 767     nvc0->gmtyprog = hwcso;
 768     nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
 769 }
 770
 771 static void *
 772 nvc0_tcp_state_create(struct pipe_context *pipe,
 773                      const struct pipe_shader_state *cso)
 774 {
 775    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
 776 }
 777
 778 static void
 779 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
 780 {
 781     struct nvc0_context *nvc0 = nvc0_context(pipe);
 782
 783     nvc0->tctlprog = hwcso;
 784     nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
 785 }
 786
 787 static void *
 788 nvc0_tep_state_create(struct pipe_context *pipe,
 789                      const struct pipe_shader_state *cso)
 790 {
 791    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
 792 }
 793
 794 static void
 795 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
 796 {
 797     struct nvc0_context *nvc0 = nvc0_context(pipe);
 798
 799     nvc0->tevlprog = hwcso;
 800     nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
 801 }
 802
 803 static void *
 804 nvc0_cp_state_create(struct pipe_context *pipe,
 805                      const struct pipe_compute_state *cso)
 806 {
 807    struct nvc0_program *prog;
 808
 809    prog = CALLOC_STRUCT(nvc0_program);
 810    if (!prog)
 811       return NULL;
 812    prog->type = PIPE_SHADER_COMPUTE;
 813
 814    prog->cp.smem_size = cso->req_local_mem;
 815    prog->cp.lmem_size = cso->req_private_mem;
 816    prog->parm_size = cso->req_input_mem;
 817
 818    prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
 819
 820    return (void *)prog;
 821 }
 822
 823 static void
 824 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
 825 {
 826     struct nvc0_context *nvc0 = nvc0_context(pipe);
 827
 828     nvc0->compprog = hwcso;
 829     nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
 830 }
 831
 832 static void
 833 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
 834                          struct pipe_constant_buffer *cb)
 835 {
 836    struct nvc0_context *nvc0 = nvc0_context(pipe);
 837    struct pipe_resource *res = cb ? cb->buffer : NULL;
 838    const unsigned s = nvc0_shader_stage(shader);
 839    const unsigned i = index;
 840
 841    if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
 842       if (nvc0->constbuf[s][i].user)
 843          nvc0->constbuf[s][i].u.buf = NULL;
 844       else
 845       if (nvc0->constbuf[s][i].u.buf)
 846          nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
 847
 848       nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
 849    } else {
 850       if (nvc0->constbuf[s][i].user)
 851          nvc0->constbuf[s][i].u.buf = NULL;
 852       else
 853       if (nvc0->constbuf[s][i].u.buf)
 854          nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
 855
 856       nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
 857    }
 858    nvc0->constbuf_dirty[s] |= 1 << i;
 859
 860    if (nvc0->constbuf[s][i].u.buf)
 861       nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
 862    pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
 863
 864    nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
 865    if (nvc0->constbuf[s][i].user) {
 866       nvc0->constbuf[s][i].u.data = cb->user_buffer;
 867       nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
 868       nvc0->constbuf_valid[s] |= 1 << i;
 869       nvc0->constbuf_coherent[s] &= ~(1 << i);
 870    } else
 871    if (cb) {
 872       nvc0->constbuf[s][i].offset = cb->buffer_offset;
 873       nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
 874       nvc0->constbuf_valid[s] |= 1 << i;
 875       if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 876          nvc0->constbuf_coherent[s] |= 1 << i;
 877       else
 878          nvc0->constbuf_coherent[s] &= ~(1 << i);
 879    }
 880    else {
 881       nvc0->constbuf_valid[s] &= ~(1 << i);
 882       nvc0->constbuf_coherent[s] &= ~(1 << i);
 883    }
 884 }
 885
 886 /* =============================================================================
 887  */
 888
 889 static void
 890 nvc0_set_blend_color(struct pipe_context *pipe,
 891                      const struct pipe_blend_color *bcol)
 892 {
 893     struct nvc0_context *nvc0 = nvc0_context(pipe);
 894
 895     nvc0->blend_colour = *bcol;
 896     nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
 897 }
 898
 899 static void
 900 nvc0_set_stencil_ref(struct pipe_context *pipe,
 901                      const struct pipe_stencil_ref *sr)
 902 {
 903     struct nvc0_context *nvc0 = nvc0_context(pipe);
 904
 905     nvc0->stencil_ref = *sr;
 906     nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
 907 }
 908
 909 static void
 910 nvc0_set_clip_state(struct pipe_context *pipe,
 911                     const struct pipe_clip_state *clip)
 912 {
 913     struct nvc0_context *nvc0 = nvc0_context(pipe);
 914
 915     memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
 916
 917     nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
 918 }
 919
 920 static void
 921 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 922 {
 923     struct nvc0_context *nvc0 = nvc0_context(pipe);
 924
 925     nvc0->sample_mask = sample_mask;
 926     nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
 927 }
 928
 929 static void
 930 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
 931 {
 932    struct nvc0_context *nvc0 = nvc0_context(pipe);
 933
 934    if (nvc0->min_samples != min_samples) {
 935       nvc0->min_samples = min_samples;
 936       nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
 937    }
 938 }
 939
 940 static void
 941 nvc0_set_framebuffer_state(struct pipe_context *pipe,
 942                            const struct pipe_framebuffer_state *fb)
 943 {
 944     struct nvc0_context *nvc0 = nvc0_context(pipe);
 945
 946     nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
 947
 948     util_copy_framebuffer_state(&nvc0->framebuffer, fb);
 949
 950     nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
 951 }
 952
 953 static void
 954 nvc0_set_polygon_stipple(struct pipe_context *pipe,
 955                          const struct pipe_poly_stipple *stipple)
 956 {
 957     struct nvc0_context *nvc0 = nvc0_context(pipe);
 958
 959     nvc0->stipple = *stipple;
 960     nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
 961 }
 962
 963 static void
 964 nvc0_set_scissor_states(struct pipe_context *pipe,
 965                         unsigned start_slot,
 966                         unsigned num_scissors,
 967                         const struct pipe_scissor_state *scissor)
 968 {
 969    struct nvc0_context *nvc0 = nvc0_context(pipe);
 970    int i;
 971
 972    assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
 973    for (i = 0; i < num_scissors; i++) {
 974       if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
 975          continue;
 976       nvc0->scissors[start_slot + i] = scissor[i];
 977       nvc0->scissors_dirty |= 1 << (start_slot + i);
 978       nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
 979    }
 980 }
 981
 982 static void
 983 nvc0_set_viewport_states(struct pipe_context *pipe,
 984                          unsigned start_slot,
 985                          unsigned num_viewports,
 986                          const struct pipe_viewport_state *vpt)
 987 {
 988    struct nvc0_context *nvc0 = nvc0_context(pipe);
 989    int i;
 990
 991    assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
 992    for (i = 0; i < num_viewports; i++) {
 993       if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
 994          continue;
 995       nvc0->viewports[start_slot + i] = vpt[i];
 996       nvc0->viewports_dirty |= 1 << (start_slot + i);
 997       nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
 998    }
 999
1000 }
1001
1002 static void
1003 nvc0_set_tess_state(struct pipe_context *pipe,
1004                     const float default_tess_outer[4],
1005                     const float default_tess_inner[2])
1006 {
1007    struct nvc0_context *nvc0 = nvc0_context(pipe);
1008
1009    memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1010    memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1011    nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
1012 }
1013
1014 static void
1015 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1016                         unsigned start_slot, unsigned count,
1017                         const struct pipe_vertex_buffer *vb)
1018 {
1019     struct nvc0_context *nvc0 = nvc0_context(pipe);
1020     unsigned i;
1021
1022     nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
1023     nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1024
1025     util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1026                                   start_slot, count);
1027
1028     if (!vb) {
1029        nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1030        nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1031        nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1032        return;
1033     }
1034
1035     for (i = 0; i < count; ++i) {
1036        unsigned dst_index = start_slot + i;
1037
1038        if (vb[i].user_buffer) {
1039           nvc0->vbo_user |= 1 << dst_index;
1040           if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1041              nvc0->constant_vbos |= 1 << dst_index;
1042           else
1043              nvc0->constant_vbos &= ~(1 << dst_index);
1044           nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1045        } else {
1046           nvc0->vbo_user &= ~(1 << dst_index);
1047           nvc0->constant_vbos &= ~(1 << dst_index);
1048
1049           if (vb[i].buffer &&
1050               vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1051              nvc0->vtxbufs_coherent |= (1 << dst_index);
1052           else
1053              nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1054        }
1055     }
1056 }
1057
1058 static void
1059 nvc0_set_index_buffer(struct pipe_context *pipe,
1060                       const struct pipe_index_buffer *ib)
1061 {
1062     struct nvc0_context *nvc0 = nvc0_context(pipe);
1063
1064     if (nvc0->idxbuf.buffer)
1065        nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
1066
1067     if (ib) {
1068        pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1069        nvc0->idxbuf.index_size = ib->index_size;
1070        if (ib->buffer) {
1071           nvc0->idxbuf.offset = ib->offset;
1072           nvc0->dirty_3d |= NVC0_NEW_3D_IDXBUF;
1073        } else {
1074           nvc0->idxbuf.user_buffer = ib->user_buffer;
1075           nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
1076        }
1077     } else {
1078        nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
1079        pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1080     }
1081 }
1082
1083 static void
1084 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1085 {
1086     struct nvc0_context *nvc0 = nvc0_context(pipe);
1087
1088     nvc0->vertex = hwcso;
1089     nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1090 }
1091
1092 static struct pipe_stream_output_target *
1093 nvc0_so_target_create(struct pipe_context *pipe,
1094                       struct pipe_resource *res,
1095                       unsigned offset, unsigned size)
1096 {
1097    struct nv04_resource *buf = (struct nv04_resource *)res;
1098    struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1099    if (!targ)
1100       return NULL;
1101
1102    targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1103    if (!targ->pq) {
1104       FREE(targ);
1105       return NULL;
1106    }
1107    targ->clean = true;
1108
1109    targ->pipe.buffer_size = size;
1110    targ->pipe.buffer_offset = offset;
1111    targ->pipe.context = pipe;
1112    targ->pipe.buffer = NULL;
1113    pipe_resource_reference(&targ->pipe.buffer, res);
1114    pipe_reference_init(&targ->pipe.reference, 1);
1115
1116    assert(buf->base.target == PIPE_BUFFER);
1117    util_range_add(&buf->valid_buffer_range, offset, offset + size);
1118
1119    return &targ->pipe;
1120 }
1121
1122 static void
1123 nvc0_so_target_save_offset(struct pipe_context *pipe,
1124                            struct pipe_stream_output_target *ptarg,
1125                            unsigned index, bool *serialize)
1126 {
1127    struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1128
1129    if (*serialize) {
1130       *serialize = false;
1131       PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1132       IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1133
1134       NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1135    }
1136
1137    nvc0_query(targ->pq)->index = index;
1138    pipe->end_query(pipe, targ->pq);
1139 }
1140
1141 static void
1142 nvc0_so_target_destroy(struct pipe_context *pipe,
1143                        struct pipe_stream_output_target *ptarg)
1144 {
1145    struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1146    pipe->destroy_query(pipe, targ->pq);
1147    pipe_resource_reference(&targ->pipe.buffer, NULL);
1148    FREE(targ);
1149 }
1150
1151 static void
1152 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1153                                     unsigned num_targets,
1154                                     struct pipe_stream_output_target **targets,
1155                                     const unsigned *offsets)
1156 {
1157    struct nvc0_context *nvc0 = nvc0_context(pipe);
1158    unsigned i;
1159    bool serialize = true;
1160
1161    assert(num_targets <= 4);
1162
1163    for (i = 0; i < num_targets; ++i) {
1164       const bool changed = nvc0->tfbbuf[i] != targets[i];
1165       const bool append = (offsets[i] == ((unsigned)-1));
1166       if (!changed && append)
1167          continue;
1168       nvc0->tfbbuf_dirty |= 1 << i;
1169
1170       if (nvc0->tfbbuf[i] && changed)
1171          nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1172
1173       if (targets[i] && !append)
1174          nvc0_so_target(targets[i])->clean = true;
1175
1176       pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1177    }
1178    for (; i < nvc0->num_tfbbufs; ++i) {
1179       if (nvc0->tfbbuf[i]) {
1180          nvc0->tfbbuf_dirty |= 1 << i;
1181          nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1182          pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1183       }
1184    }
1185    nvc0->num_tfbbufs = num_targets;
1186
1187    if (nvc0->tfbbuf_dirty) {
1188       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1189       nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1190    }
1191 }
1192
1193 static void
1194 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1195                          unsigned start, unsigned nr,
1196                          struct pipe_surface **psurfaces)
1197 {
1198    const unsigned end = start + nr;
1199    const unsigned mask = ((1 << nr) - 1) << start;
1200    unsigned i;
1201
1202    if (psurfaces) {
1203       for (i = start; i < end; ++i) {
1204          const unsigned p = i - start;
1205          if (psurfaces[p])
1206             nvc0->surfaces_valid[t] |= (1 << i);
1207          else
1208             nvc0->surfaces_valid[t] &= ~(1 << i);
1209          pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1210       }
1211    } else {
1212       for (i = start; i < end; ++i)
1213          pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1214       nvc0->surfaces_valid[t] &= ~mask;
1215    }
1216    nvc0->surfaces_dirty[t] |= mask;
1217
1218    if (t == 0)
1219       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1220    else
1221       nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1222 }
1223
1224 static void
1225 nvc0_set_compute_resources(struct pipe_context *pipe,
1226                            unsigned start, unsigned nr,
1227                            struct pipe_surface **resources)
1228 {
1229    nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1230
1231    nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1232 }
1233
1234 static void
1235 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1236                        unsigned start, unsigned nr,
1237                        struct pipe_image_view *pimages)
1238 {
1239    const unsigned end = start + nr;
1240    const unsigned mask = ((1 << nr) - 1) << start;
1241    unsigned i;
1242
1243    assert(s < 6);
1244
1245    if (pimages) {
1246       for (i = start; i < end; ++i) {
1247          const unsigned p = i - start;
1248          if (pimages[p].resource)
1249             nvc0->images_valid[s] |= (1 << i);
1250          else
1251             nvc0->images_valid[s] &= ~(1 << i);
1252
1253          nvc0->images[s][i].format = pimages[p].format;
1254          nvc0->images[s][i].access = pimages[p].access;
1255          if (pimages[p].resource->target == PIPE_BUFFER)
1256             nvc0->images[s][i].u.buf = pimages[p].u.buf;
1257          else
1258             nvc0->images[s][i].u.tex = pimages[p].u.tex;
1259
1260          pipe_resource_reference(
1261                &nvc0->images[s][i].resource, pimages[p].resource);
1262       }
1263    } else {
1264       for (i = start; i < end; ++i)
1265          pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1266       nvc0->images_valid[s] &= ~mask;
1267    }
1268    nvc0->images_dirty[s] |= mask;
1269
1270    if (s == 5)
1271       nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1272    else
1273       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1274 }
1275
1276 static void
1277 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1278                        unsigned start, unsigned nr,
1279                        struct pipe_image_view *images)
1280 {
1281    const unsigned s = nvc0_shader_stage(shader);
1282    nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images);
1283
1284    if (s == 5)
1285       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1286    else
1287       nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1288 }
1289
1290 static bool
1291 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1292                          unsigned start, unsigned nr,
1293                          struct pipe_shader_buffer *pbuffers)
1294 {
1295    const unsigned end = start + nr;
1296    unsigned mask = 0;
1297    unsigned i;
1298
1299    assert(t < 6);
1300
1301    if (pbuffers) {
1302       for (i = start; i < end; ++i) {
1303          struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1304          const unsigned p = i - start;
1305          if (buf->buffer == pbuffers[p].buffer &&
1306              buf->buffer_offset == pbuffers[p].buffer_offset &&
1307              buf->buffer_size == pbuffers[p].buffer_size)
1308             continue;
1309
1310          mask |= (1 << i);
1311          if (pbuffers[p].buffer)
1312             nvc0->buffers_valid[t] |= (1 << i);
1313          else
1314             nvc0->buffers_valid[t] &= ~(1 << i);
1315          buf->buffer_offset = pbuffers[p].buffer_offset;
1316          buf->buffer_size = pbuffers[p].buffer_size;
1317          pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1318       }
1319       if (!mask)
1320          return false;
1321    } else {
1322       mask = ((1 << nr) - 1) << start;
1323       if (!(nvc0->buffers_valid[t] & mask))
1324          return false;
1325       for (i = start; i < end; ++i)
1326          pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1327       nvc0->buffers_valid[t] &= ~mask;
1328    }
1329    nvc0->buffers_dirty[t] |= mask;
1330
1331    if (t == 5)
1332       nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1333    else
1334       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1335
1336    return true;
1337 }
1338
1339 static void
1340 nvc0_set_shader_buffers(struct pipe_context *pipe,
1341                         unsigned shader,
1342                         unsigned start, unsigned nr,
1343                         struct pipe_shader_buffer *buffers)
1344 {
1345    const unsigned s = nvc0_shader_stage(shader);
1346    if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1347       return;
1348
1349    if (s == 5)
1350       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1351    else
1352       nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1353 }
1354
1355 static inline void
1356 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1357 {
1358    struct nv04_resource *buf = nv04_resource(res);
1359    if (buf) {
1360       uint64_t limit = (buf->address + buf->base.width0) - 1;
1361       if (limit < (1ULL << 32)) {
1362          *phandle = (uint32_t)buf->address;
1363       } else {
1364          NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1365                      "resource not contained within 32-bit address space !\n");
1366          *phandle = 0;
1367       }
1368    } else {
1369       *phandle = 0;
1370    }
1371 }
1372
1373 static void
1374 nvc0_set_global_bindings(struct pipe_context *pipe,
1375                          unsigned start, unsigned nr,
1376                          struct pipe_resource **resources,
1377                          uint32_t **handles)
1378 {
1379    struct nvc0_context *nvc0 = nvc0_context(pipe);
1380    struct pipe_resource **ptr;
1381    unsigned i;
1382    const unsigned end = start + nr;
1383
1384    if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1385       const unsigned old_size = nvc0->global_residents.size;
1386       const unsigned req_size = end * sizeof(struct pipe_resource *);
1387       util_dynarray_resize(&nvc0->global_residents, req_size);
1388       memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1389              req_size - old_size);
1390    }
1391
1392    if (resources) {
1393       ptr = util_dynarray_element(
1394          &nvc0->global_residents, struct pipe_resource *, start);
1395       for (i = 0; i < nr; ++i) {
1396          pipe_resource_reference(&ptr[i], resources[i]);
1397          nvc0_set_global_handle(handles[i], resources[i]);
1398       }
1399    } else {
1400       ptr = util_dynarray_element(
1401          &nvc0->global_residents, struct pipe_resource *, start);
1402       for (i = 0; i < nr; ++i)
1403          pipe_resource_reference(&ptr[i], NULL);
1404    }
1405
1406    nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1407
1408    nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1409 }
1410
1411 void
1412 nvc0_init_state_functions(struct nvc0_context *nvc0)
1413 {
1414    struct pipe_context *pipe = &nvc0->base.pipe;
1415
1416    pipe->create_blend_state = nvc0_blend_state_create;
1417    pipe->bind_blend_state = nvc0_blend_state_bind;
1418    pipe->delete_blend_state = nvc0_blend_state_delete;
1419
1420    pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1421    pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1422    pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1423
1424    pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1425    pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1426    pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1427
1428    pipe->create_sampler_state = nv50_sampler_state_create;
1429    pipe->delete_sampler_state = nvc0_sampler_state_delete;
1430    pipe->bind_sampler_states = nvc0_bind_sampler_states;
1431
1432    pipe->create_sampler_view = nvc0_create_sampler_view;
1433    pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1434    pipe->set_sampler_views = nvc0_set_sampler_views;
1435
1436    pipe->create_vs_state = nvc0_vp_state_create;
1437    pipe->create_fs_state = nvc0_fp_state_create;
1438    pipe->create_gs_state = nvc0_gp_state_create;
1439    pipe->create_tcs_state = nvc0_tcp_state_create;
1440    pipe->create_tes_state = nvc0_tep_state_create;
1441    pipe->bind_vs_state = nvc0_vp_state_bind;
1442    pipe->bind_fs_state = nvc0_fp_state_bind;
1443    pipe->bind_gs_state = nvc0_gp_state_bind;
1444    pipe->bind_tcs_state = nvc0_tcp_state_bind;
1445    pipe->bind_tes_state = nvc0_tep_state_bind;
1446    pipe->delete_vs_state = nvc0_sp_state_delete;
1447    pipe->delete_fs_state = nvc0_sp_state_delete;
1448    pipe->delete_gs_state = nvc0_sp_state_delete;
1449    pipe->delete_tcs_state = nvc0_sp_state_delete;
1450    pipe->delete_tes_state = nvc0_sp_state_delete;
1451
1452    pipe->create_compute_state = nvc0_cp_state_create;
1453    pipe->bind_compute_state = nvc0_cp_state_bind;
1454    pipe->delete_compute_state = nvc0_sp_state_delete;
1455
1456    pipe->set_blend_color = nvc0_set_blend_color;
1457    pipe->set_stencil_ref = nvc0_set_stencil_ref;
1458    pipe->set_clip_state = nvc0_set_clip_state;
1459    pipe->set_sample_mask = nvc0_set_sample_mask;
1460    pipe->set_min_samples = nvc0_set_min_samples;
1461    pipe->set_constant_buffer = nvc0_set_constant_buffer;
1462    pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1463    pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1464    pipe->set_scissor_states = nvc0_set_scissor_states;
1465    pipe->set_viewport_states = nvc0_set_viewport_states;
1466    pipe->set_tess_state = nvc0_set_tess_state;
1467
1468    pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1469    pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1470    pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1471
1472    pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1473    pipe->set_index_buffer = nvc0_set_index_buffer;
1474
1475    pipe->create_stream_output_target = nvc0_so_target_create;
1476    pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1477    pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1478
1479    pipe->set_global_binding = nvc0_set_global_bindings;
1480    pipe->set_compute_resources = nvc0_set_compute_resources;
1481    pipe->set_shader_images = nvc0_set_shader_images;
1482    pipe->set_shader_buffers = nvc0_set_shader_buffers;
1483
1484    nvc0->sample_mask = ~0;
1485    nvc0->min_samples = 1;
1486    nvc0->default_tess_outer[0] =
1487    nvc0->default_tess_outer[1] =
1488    nvc0->default_tess_outer[2] =
1489    nvc0->default_tess_outer[3] = 1.0;
1490    nvc0->default_tess_inner[0] =
1491    nvc0->default_tess_inner[1] = 1.0;
1492 }