src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_formats.h"
  24 #include "r600_shader.h"
  25 #include "evergreend.h"
  26
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_framebuffer.h"
  31 #include "util/u_dual_blend.h"
  32 #include "evergreen_compute.h"
  33 #include "util/u_math.h"
  34
  35 static inline unsigned evergreen_array_mode(unsigned mode)
  36 {
  37         switch (mode) {
  38         default:
  39         case RADEON_SURF_MODE_LINEAR_ALIGNED:   return V_028C70_ARRAY_LINEAR_ALIGNED;
  40                 break;
  41         case RADEON_SURF_MODE_1D:               return V_028C70_ARRAY_1D_TILED_THIN1;
  42                 break;
  43         case RADEON_SURF_MODE_2D:               return V_028C70_ARRAY_2D_TILED_THIN1;
  44         }
  45 }
  46
  47 static uint32_t eg_num_banks(uint32_t nbanks)
  48 {
  49         switch (nbanks) {
  50         case 2:
  51                 return 0;
  52         case 4:
  53                 return 1;
  54         case 8:
  55         default:
  56                 return 2;
  57         case 16:
  58                 return 3;
  59         }
  60 }
  61
  62
  63 static unsigned eg_tile_split(unsigned tile_split)
  64 {
  65         switch (tile_split) {
  66         case 64:        tile_split = 0; break;
  67         case 128:       tile_split = 1; break;
  68         case 256:       tile_split = 2; break;
  69         case 512:       tile_split = 3; break;
  70         default:
  71         case 1024:      tile_split = 4; break;
  72         case 2048:      tile_split = 5; break;
  73         case 4096:      tile_split = 6; break;
  74         }
  75         return tile_split;
  76 }
  77
  78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
  79 {
  80         switch (macro_tile_aspect) {
  81         default:
  82         case 1: macro_tile_aspect = 0;  break;
  83         case 2: macro_tile_aspect = 1;  break;
  84         case 4: macro_tile_aspect = 2;  break;
  85         case 8: macro_tile_aspect = 3;  break;
  86         }
  87         return macro_tile_aspect;
  88 }
  89
  90 static unsigned eg_bank_wh(unsigned bankwh)
  91 {
  92         switch (bankwh) {
  93         default:
  94         case 1: bankwh = 0;     break;
  95         case 2: bankwh = 1;     break;
  96         case 4: bankwh = 2;     break;
  97         case 8: bankwh = 3;     break;
  98         }
  99         return bankwh;
 100 }
 101
 102 static uint32_t r600_translate_blend_function(int blend_func)
 103 {
 104         switch (blend_func) {
 105         case PIPE_BLEND_ADD:
 106                 return V_028780_COMB_DST_PLUS_SRC;
 107         case PIPE_BLEND_SUBTRACT:
 108                 return V_028780_COMB_SRC_MINUS_DST;
 109         case PIPE_BLEND_REVERSE_SUBTRACT:
 110                 return V_028780_COMB_DST_MINUS_SRC;
 111         case PIPE_BLEND_MIN:
 112                 return V_028780_COMB_MIN_DST_SRC;
 113         case PIPE_BLEND_MAX:
 114                 return V_028780_COMB_MAX_DST_SRC;
 115         default:
 116                 R600_ERR("Unknown blend function %d\n", blend_func);
 117                 assert(0);
 118                 break;
 119         }
 120         return 0;
 121 }
 122
 123 static uint32_t r600_translate_blend_factor(int blend_fact)
 124 {
 125         switch (blend_fact) {
 126         case PIPE_BLENDFACTOR_ONE:
 127                 return V_028780_BLEND_ONE;
 128         case PIPE_BLENDFACTOR_SRC_COLOR:
 129                 return V_028780_BLEND_SRC_COLOR;
 130         case PIPE_BLENDFACTOR_SRC_ALPHA:
 131                 return V_028780_BLEND_SRC_ALPHA;
 132         case PIPE_BLENDFACTOR_DST_ALPHA:
 133                 return V_028780_BLEND_DST_ALPHA;
 134         case PIPE_BLENDFACTOR_DST_COLOR:
 135                 return V_028780_BLEND_DST_COLOR;
 136         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 137                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 138         case PIPE_BLENDFACTOR_CONST_COLOR:
 139                 return V_028780_BLEND_CONST_COLOR;
 140         case PIPE_BLENDFACTOR_CONST_ALPHA:
 141                 return V_028780_BLEND_CONST_ALPHA;
 142         case PIPE_BLENDFACTOR_ZERO:
 143                 return V_028780_BLEND_ZERO;
 144         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 145                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 146         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 147                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 148         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 149                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 150         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 151                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 152         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 153                 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
 154         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 155                 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
 156         case PIPE_BLENDFACTOR_SRC1_COLOR:
 157                 return V_028780_BLEND_SRC1_COLOR;
 158         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 159                 return V_028780_BLEND_SRC1_ALPHA;
 160         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 161                 return V_028780_BLEND_INV_SRC1_COLOR;
 162         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 163                 return V_028780_BLEND_INV_SRC1_ALPHA;
 164         default:
 165                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 166                 assert(0);
 167                 break;
 168         }
 169         return 0;
 170 }
 171
 172 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
 173 {
 174         switch (dim) {
 175         default:
 176         case PIPE_TEXTURE_1D:
 177                 return V_030000_SQ_TEX_DIM_1D;
 178         case PIPE_TEXTURE_1D_ARRAY:
 179                 return V_030000_SQ_TEX_DIM_1D_ARRAY;
 180         case PIPE_TEXTURE_2D:
 181         case PIPE_TEXTURE_RECT:
 182                 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
 183                                         V_030000_SQ_TEX_DIM_2D;
 184         case PIPE_TEXTURE_2D_ARRAY:
 185                 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
 186                                         V_030000_SQ_TEX_DIM_2D_ARRAY;
 187         case PIPE_TEXTURE_3D:
 188                 return V_030000_SQ_TEX_DIM_3D;
 189         case PIPE_TEXTURE_CUBE:
 190         case PIPE_TEXTURE_CUBE_ARRAY:
 191                 return V_030000_SQ_TEX_DIM_CUBEMAP;
 192         }
 193 }
 194
 195 static uint32_t r600_translate_dbformat(enum pipe_format format)
 196 {
 197         switch (format) {
 198         case PIPE_FORMAT_Z16_UNORM:
 199                 return V_028040_Z_16;
 200         case PIPE_FORMAT_Z24X8_UNORM:
 201         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 202         case PIPE_FORMAT_X8Z24_UNORM:
 203         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 204                 return V_028040_Z_24;
 205         case PIPE_FORMAT_Z32_FLOAT:
 206         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 207                 return V_028040_Z_32_FLOAT;
 208         default:
 209                 return ~0U;
 210         }
 211 }
 212
 213 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 214 {
 215         return r600_translate_texformat(screen, format, NULL, NULL, NULL,
 216                                    FALSE) != ~0U;
 217 }
 218
 219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
 220 {
 221         return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
 222                 r600_translate_colorswap(format, FALSE) != ~0U;
 223 }
 224
 225 static bool r600_is_zs_format_supported(enum pipe_format format)
 226 {
 227         return r600_translate_dbformat(format) != ~0U;
 228 }
 229
 230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 231                                       enum pipe_format format,
 232                                       enum pipe_texture_target target,
 233                                       unsigned sample_count,
 234                                       unsigned usage)
 235 {
 236         struct r600_screen *rscreen = (struct r600_screen*)screen;
 237         unsigned retval = 0;
 238
 239         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 240                 R600_ERR("r600: unsupported texture type %d\n", target);
 241                 return FALSE;
 242         }
 243
 244         if (!util_format_is_supported(format, usage))
 245                 return FALSE;
 246
 247         if (sample_count > 1) {
 248                 if (!rscreen->has_msaa)
 249                         return FALSE;
 250
 251                 switch (sample_count) {
 252                 case 2:
 253                 case 4:
 254                 case 8:
 255                         break;
 256                 default:
 257                         return FALSE;
 258                 }
 259         }
 260
 261         if (usage & PIPE_BIND_SAMPLER_VIEW) {
 262                 if (target == PIPE_BUFFER) {
 263                         if (r600_is_vertex_format_supported(format))
 264                                 retval |= PIPE_BIND_SAMPLER_VIEW;
 265                 } else {
 266                         if (r600_is_sampler_format_supported(screen, format))
 267                                 retval |= PIPE_BIND_SAMPLER_VIEW;
 268                 }
 269         }
 270
 271         if ((usage & (PIPE_BIND_RENDER_TARGET |
 272                       PIPE_BIND_DISPLAY_TARGET |
 273                       PIPE_BIND_SCANOUT |
 274                       PIPE_BIND_SHARED |
 275                       PIPE_BIND_BLENDABLE)) &&
 276             r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
 277                 retval |= usage &
 278                           (PIPE_BIND_RENDER_TARGET |
 279                            PIPE_BIND_DISPLAY_TARGET |
 280                            PIPE_BIND_SCANOUT |
 281                            PIPE_BIND_SHARED);
 282                 if (!util_format_is_pure_integer(format) &&
 283                     !util_format_is_depth_or_stencil(format))
 284                         retval |= usage & PIPE_BIND_BLENDABLE;
 285         }
 286
 287         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 288             r600_is_zs_format_supported(format)) {
 289                 retval |= PIPE_BIND_DEPTH_STENCIL;
 290         }
 291
 292         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 293             r600_is_vertex_format_supported(format)) {
 294                 retval |= PIPE_BIND_VERTEX_BUFFER;
 295         }
 296
 297         if (usage & PIPE_BIND_TRANSFER_READ)
 298                 retval |= PIPE_BIND_TRANSFER_READ;
 299         if (usage & PIPE_BIND_TRANSFER_WRITE)
 300                 retval |= PIPE_BIND_TRANSFER_WRITE;
 301
 302         if ((usage & PIPE_BIND_LINEAR) &&
 303             !util_format_is_compressed(format) &&
 304             !(usage & PIPE_BIND_DEPTH_STENCIL))
 305                 retval |= PIPE_BIND_LINEAR;
 306
 307         return retval == usage;
 308 }
 309
 310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
 311                                                const struct pipe_blend_state *state, int mode)
 312 {
 313         uint32_t color_control = 0, target_mask = 0;
 314         struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
 315
 316         if (!blend) {
 317                 return NULL;
 318         }
 319
 320         r600_init_command_buffer(&blend->buffer, 20);
 321         r600_init_command_buffer(&blend->buffer_no_blend, 20);
 322
 323         if (state->logicop_enable) {
 324                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 325         } else {
 326                 color_control |= (0xcc << 16);
 327         }
 328         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 329         if (state->independent_blend_enable) {
 330                 for (int i = 0; i < 8; i++) {
 331                         target_mask |= (state->rt[i].colormask << (4 * i));
 332                 }
 333         } else {
 334                 for (int i = 0; i < 8; i++) {
 335                         target_mask |= (state->rt[0].colormask << (4 * i));
 336                 }
 337         }
 338
 339         /* only have dual source on MRT0 */
 340         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 341         blend->cb_target_mask = target_mask;
 342         blend->alpha_to_one = state->alpha_to_one;
 343
 344         if (target_mask)
 345                 color_control |= S_028808_MODE(mode);
 346         else
 347                 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 348
 349
 350         r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
 351         r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
 352                                S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 353                                S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
 354                                S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
 355                                S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
 356                                S_028B70_ALPHA_TO_MASK_OFFSET3(2));
 357         r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
 358
 359         /* Copy over the dwords set so far into buffer_no_blend.
 360          * Only the CB_BLENDi_CONTROL registers must be set after this. */
 361         memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
 362         blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
 363
 364         for (int i = 0; i < 8; i++) {
 365                 /* state->rt entries > 0 only written if independent blending */
 366                 const int j = state->independent_blend_enable ? i : 0;
 367
 368                 unsigned eqRGB = state->rt[j].rgb_func;
 369                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 370                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 371                 unsigned eqA = state->rt[j].alpha_func;
 372                 unsigned srcA = state->rt[j].alpha_src_factor;
 373                 unsigned dstA = state->rt[j].alpha_dst_factor;
 374                 uint32_t bc = 0;
 375
 376                 r600_store_value(&blend->buffer_no_blend, 0);
 377
 378                 if (!state->rt[j].blend_enable) {
 379                         r600_store_value(&blend->buffer, 0);
 380                         continue;
 381                 }
 382
 383                 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
 384                 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 385                 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 386                 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 387
 388                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 389                         bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
 390                         bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 391                         bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 392                         bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 393                 }
 394                 r600_store_value(&blend->buffer, bc);
 395         }
 396         return blend;
 397 }
 398
 399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
 400                                         const struct pipe_blend_state *state)
 401 {
 402
 403         return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
 404 }
 405
 406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 407                                    const struct pipe_depth_stencil_alpha_state *state)
 408 {
 409         unsigned db_depth_control, alpha_test_control, alpha_ref;
 410         struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
 411
 412         if (!dsa) {
 413                 return NULL;
 414         }
 415
 416         r600_init_command_buffer(&dsa->buffer, 3);
 417
 418         dsa->valuemask[0] = state->stencil[0].valuemask;
 419         dsa->valuemask[1] = state->stencil[1].valuemask;
 420         dsa->writemask[0] = state->stencil[0].writemask;
 421         dsa->writemask[1] = state->stencil[1].writemask;
 422         dsa->zwritemask = state->depth.writemask;
 423
 424         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 425                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 426                 S_028800_ZFUNC(state->depth.func);
 427
 428         /* stencil */
 429         if (state->stencil[0].enabled) {
 430                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 431                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 432                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 433                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 434                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 435
 436                 if (state->stencil[1].enabled) {
 437                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 438                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 439                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 440                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 441                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 442                 }
 443         }
 444
 445         /* alpha */
 446         alpha_test_control = 0;
 447         alpha_ref = 0;
 448         if (state->alpha.enabled) {
 449                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 450                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 451                 alpha_ref = fui(state->alpha.ref_value);
 452         }
 453         dsa->sx_alpha_test_control = alpha_test_control & 0xff;
 454         dsa->alpha_ref = alpha_ref;
 455
 456         /* misc */
 457         r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 458         return dsa;
 459 }
 460
 461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 462                                         const struct pipe_rasterizer_state *state)
 463 {
 464         struct r600_context *rctx = (struct r600_context *)ctx;
 465         unsigned tmp, spi_interp;
 466         float psize_min, psize_max;
 467         struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
 468
 469         if (!rs) {
 470                 return NULL;
 471         }
 472
 473         r600_init_command_buffer(&rs->buffer, 30);
 474
 475         rs->scissor_enable = state->scissor;
 476         rs->flatshade = state->flatshade;
 477         rs->sprite_coord_enable = state->sprite_coord_enable;
 478         rs->two_side = state->light_twoside;
 479         rs->clip_plane_enable = state->clip_plane_enable;
 480         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 481                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 482                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 483         rs->pa_cl_clip_cntl =
 484                 S_028810_PS_UCP_MODE(3) |
 485                 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
 486                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 487                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 488                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
 489                 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
 490         rs->multisample_enable = state->multisample;
 491
 492         /* offset */
 493         rs->offset_units = state->offset_units;
 494         rs->offset_scale = state->offset_scale * 16.0f;
 495         rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
 496
 497         if (state->point_size_per_vertex) {
 498                 psize_min = util_get_min_point_size(state);
 499                 psize_max = 8192;
 500         } else {
 501                 /* Force the point size to be as if the vertex output was disabled. */
 502                 psize_min = state->point_size;
 503                 psize_max = state->point_size;
 504         }
 505
 506         spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
 507         if (state->sprite_coord_enable) {
 508                 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
 509                               S_0286D4_PNT_SPRITE_OVRD_X(2) |
 510                               S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 511                               S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 512                               S_0286D4_PNT_SPRITE_OVRD_W(1);
 513                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 514                         spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 515                 }
 516         }
 517
 518         r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
 519         /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
 520         tmp = r600_pack_float_12p4(state->point_size/2);
 521         r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
 522                          S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 523         r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
 524                          S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 525                          S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
 526         r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
 527                          S_028A08_WIDTH((unsigned)(state->line_width * 8)));
 528
 529         r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
 530         r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
 531                                S_028A48_MSAA_ENABLE(state->multisample) |
 532                                S_028A48_VPORT_SCISSOR_ENABLE(1) |
 533                                S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
 534
 535         if (rctx->b.chip_class == CAYMAN) {
 536                 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
 537                                        S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
 538                                        S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 539         } else {
 540                 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
 541                                        S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
 542                                        S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 543         }
 544
 545         r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 546         r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
 547                                S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 548                                S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 549                                S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 550                                S_028814_FACE(!state->front_ccw) |
 551                                S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
 552                                S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
 553                                S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
 554                                S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
 555                                                   state->fill_back != PIPE_POLYGON_MODE_FILL) |
 556                                S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 557                                S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
 558         return rs;
 559 }
 560
 561 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 562                                         const struct pipe_sampler_state *state)
 563 {
 564         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 565         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 566         unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
 567                                                        : state->max_anisotropy;
 568         unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
 569
 570         if (!ss) {
 571                 return NULL;
 572         }
 573
 574         ss->border_color_use = sampler_state_needs_border_color(state);
 575
 576         /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
 577         ss->tex_sampler_words[0] =
 578                 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 579                 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 580                 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 581                 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
 582                 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
 583                 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 584                 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
 585                 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 586                 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
 587         /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
 588         ss->tex_sampler_words[1] =
 589                 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
 590                 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
 591         /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
 592         ss->tex_sampler_words[2] =
 593                 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
 594                 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
 595                 S_03C008_TYPE(1);
 596
 597         if (ss->border_color_use) {
 598                 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
 599         }
 600         return ss;
 601 }
 602
 603 static struct pipe_sampler_view *
 604 texture_buffer_sampler_view(struct r600_context *rctx,
 605                             struct r600_pipe_sampler_view *view,
 606                             unsigned width0, unsigned height0)
 607
 608 {
 609         struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
 610         uint64_t va;
 611         int stride = util_format_get_blocksize(view->base.format);
 612         unsigned format, num_format, format_comp, endian;
 613         unsigned swizzle_res;
 614         unsigned char swizzle[4];
 615         const struct util_format_description *desc;
 616         unsigned offset = view->base.u.buf.first_element * stride;
 617         unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
 618
 619         swizzle[0] = view->base.swizzle_r;
 620         swizzle[1] = view->base.swizzle_g;
 621         swizzle[2] = view->base.swizzle_b;
 622         swizzle[3] = view->base.swizzle_a;
 623
 624         r600_vertex_data_type(view->base.format,
 625                               &format, &num_format, &format_comp,
 626                               &endian);
 627
 628         desc = util_format_description(view->base.format);
 629
 630         swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
 631
 632         va = tmp->resource.gpu_address + offset;
 633         view->tex_resource = &tmp->resource;
 634
 635         view->skip_mip_address_reloc = true;
 636         view->tex_resource_words[0] = va;
 637         view->tex_resource_words[1] = size - 1;
 638         view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
 639                 S_030008_STRIDE(stride) |
 640                 S_030008_DATA_FORMAT(format) |
 641                 S_030008_NUM_FORMAT_ALL(num_format) |
 642                 S_030008_FORMAT_COMP_ALL(format_comp) |
 643                 S_030008_ENDIAN_SWAP(endian);
 644         view->tex_resource_words[3] = swizzle_res;
 645         /*
 646          * in theory dword 4 is for number of elements, for use with resinfo,
 647          * but it seems to utterly fail to work, the amd gpu shader analyser
 648          * uses a const buffer to store the element sizes for buffer txq
 649          */
 650         view->tex_resource_words[4] = 0;
 651         view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
 652         view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
 653
 654         if (tmp->resource.gpu_address)
 655                 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
 656         return &view->base;
 657 }
 658
 659 struct pipe_sampler_view *
 660 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 661                                      struct pipe_resource *texture,
 662                                      const struct pipe_sampler_view *state,
 663                                      unsigned width0, unsigned height0,
 664                                      unsigned force_level)
 665 {
 666         struct r600_context *rctx = (struct r600_context*)ctx;
 667         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 668         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
 669         struct r600_texture *tmp = (struct r600_texture*)texture;
 670         unsigned format, endian;
 671         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 672         unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
 673         unsigned height, depth, width;
 674         unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
 675         enum pipe_format pipe_format = state->format;
 676         struct radeon_surf_level *surflevel;
 677         unsigned base_level, first_level, last_level;
 678         unsigned dim, last_layer;
 679         uint64_t va;
 680         bool do_endian_swap = FALSE;
 681
 682         if (!view)
 683                 return NULL;
 684
 685         /* initialize base object */
 686         view->base = *state;
 687         view->base.texture = NULL;
 688         pipe_reference(NULL, &texture->reference);
 689         view->base.texture = texture;
 690         view->base.reference.count = 1;
 691         view->base.context = ctx;
 692
 693         if (state->target == PIPE_BUFFER)
 694                 return texture_buffer_sampler_view(rctx, view, width0, height0);
 695
 696         swizzle[0] = state->swizzle_r;
 697         swizzle[1] = state->swizzle_g;
 698         swizzle[2] = state->swizzle_b;
 699         swizzle[3] = state->swizzle_a;
 700
 701         tile_split = tmp->surface.tile_split;
 702         surflevel = tmp->surface.level;
 703
 704         /* Texturing with separate depth and stencil. */
 705         if (tmp->is_depth && !tmp->is_flushing_texture) {
 706                 switch (pipe_format) {
 707                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 708                         pipe_format = PIPE_FORMAT_Z32_FLOAT;
 709                         break;
 710                 case PIPE_FORMAT_X8Z24_UNORM:
 711                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 712                         /* Z24 is always stored like this. */
 713                         pipe_format = PIPE_FORMAT_Z24X8_UNORM;
 714                         break;
 715                 case PIPE_FORMAT_X24S8_UINT:
 716                 case PIPE_FORMAT_S8X24_UINT:
 717                 case PIPE_FORMAT_X32_S8X24_UINT:
 718                         pipe_format = PIPE_FORMAT_S8_UINT;
 719                         tile_split = tmp->surface.stencil_tile_split;
 720                         surflevel = tmp->surface.stencil_level;
 721                         break;
 722                 default:;
 723                 }
 724         }
 725
 726         if (R600_BIG_ENDIAN)
 727                 do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
 728
 729         format = r600_translate_texformat(ctx->screen, pipe_format,
 730                                           swizzle,
 731                                           &word4, &yuv_format, do_endian_swap);
 732         assert(format != ~0);
 733         if (format == ~0) {
 734                 FREE(view);
 735                 return NULL;
 736         }
 737
 738         endian = r600_colorformat_endian_swap(format, do_endian_swap);
 739
 740         base_level = 0;
 741         first_level = state->u.tex.first_level;
 742         last_level = state->u.tex.last_level;
 743         width = width0;
 744         height = height0;
 745         depth = texture->depth0;
 746
 747         if (force_level) {
 748                 base_level = force_level;
 749                 first_level = 0;
 750                 last_level = 0;
 751                 width = u_minify(width, force_level);
 752                 height = u_minify(height, force_level);
 753                 depth = u_minify(depth, force_level);
 754         }
 755
 756         pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
 757         non_disp_tiling = tmp->non_disp_tiling;
 758
 759         switch (surflevel[base_level].mode) {
 760         default:
 761         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 762                 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
 763                 break;
 764         case RADEON_SURF_MODE_2D:
 765                 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
 766                 break;
 767         case RADEON_SURF_MODE_1D:
 768                 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
 769                 break;
 770         }
 771         macro_aspect = tmp->surface.mtilea;
 772         bankw = tmp->surface.bankw;
 773         bankh = tmp->surface.bankh;
 774         tile_split = eg_tile_split(tile_split);
 775         macro_aspect = eg_macro_tile_aspect(macro_aspect);
 776         bankw = eg_bank_wh(bankw);
 777         bankh = eg_bank_wh(bankh);
 778         fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
 779
 780         /* 128 bit formats require tile type = 1 */
 781         if (rscreen->b.chip_class == CAYMAN) {
 782                 if (util_format_get_blocksize(pipe_format) >= 16)
 783                         non_disp_tiling = 1;
 784         }
 785         nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
 786
 787         if (state->target == PIPE_TEXTURE_1D_ARRAY) {
 788                 height = 1;
 789                 depth = texture->array_size;
 790         } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
 791                 depth = texture->array_size;
 792         } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
 793                 depth = texture->array_size / 6;
 794
 795         va = tmp->resource.gpu_address;
 796
 797         if (state->format == PIPE_FORMAT_X24S8_UINT ||
 798             state->format == PIPE_FORMAT_S8X24_UINT ||
 799             state->format == PIPE_FORMAT_X32_S8X24_UINT ||
 800             state->format == PIPE_FORMAT_S8_UINT)
 801                 view->is_stencil_sampler = true;
 802
 803         view->tex_resource = &tmp->resource;
 804
 805         /* array type views and views into array types need to use layer offset */
 806         dim = state->target;
 807         if (state->target != PIPE_TEXTURE_CUBE)
 808                 dim = MAX2(state->target, texture->target);
 809
 810         view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
 811                                        S_030000_PITCH((pitch / 8) - 1) |
 812                                        S_030000_TEX_WIDTH(width - 1));
 813         if (rscreen->b.chip_class == CAYMAN)
 814                 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
 815         else
 816                 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
 817         view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
 818                                        S_030004_TEX_DEPTH(depth - 1) |
 819                                        S_030004_ARRAY_MODE(array_mode));
 820         view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
 821
 822         /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
 823         if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
 824                 if (tmp->is_depth) {
 825                         /* disable FMASK (0 = disabled) */
 826                         view->tex_resource_words[3] = 0;
 827                         view->skip_mip_address_reloc = true;
 828                 } else {
 829                         /* FMASK should be in MIP_ADDRESS for multisample textures */
 830                         view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
 831                 }
 832         } else if (last_level && texture->nr_samples <= 1) {
 833                 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
 834         } else {
 835                 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
 836         }
 837
 838         last_layer = state->u.tex.last_layer;
 839         if (state->target != texture->target && depth == 1) {
 840                 last_layer = state->u.tex.first_layer;
 841         }
 842         view->tex_resource_words[4] = (word4 |
 843                                        S_030010_ENDIAN_SWAP(endian));
 844         view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
 845                                       S_030014_LAST_ARRAY(last_layer);
 846         view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
 847
 848         if (texture->nr_samples > 1) {
 849                 unsigned log_samples = util_logbase2(texture->nr_samples);
 850                 if (rscreen->b.chip_class == CAYMAN) {
 851                         view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
 852                 }
 853                 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
 854                 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
 855                 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
 856         } else {
 857                 bool no_mip = first_level == last_level;
 858
 859                 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
 860                 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
 861                 /* aniso max 16 samples */
 862                 view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
 863         }
 864
 865         view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
 866                                       S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
 867                                       S_03001C_BANK_WIDTH(bankw) |
 868                                       S_03001C_BANK_HEIGHT(bankh) |
 869                                       S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
 870                                       S_03001C_NUM_BANKS(nbanks) |
 871                                       S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
 872         return &view->base;
 873 }
 874
 875 static struct pipe_sampler_view *
 876 evergreen_create_sampler_view(struct pipe_context *ctx,
 877                               struct pipe_resource *tex,
 878                               const struct pipe_sampler_view *state)
 879 {
 880         return evergreen_create_sampler_view_custom(ctx, tex, state,
 881                                                     tex->width0, tex->height0, 0);
 882 }
 883
 884 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
 885 {
 886         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 887         struct r600_config_state *a = (struct r600_config_state*)atom;
 888
 889         radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
 890         if (a->dyn_gpr_enabled) {
 891                 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
 892                 radeon_emit(cs, 0);
 893                 radeon_emit(cs, 0);
 894         } else {
 895                 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
 896                 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
 897                 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
 898         }
 899         radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
 900         if (a->dyn_gpr_enabled) {
 901                 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
 902                                        S_028838_PS_GPRS(0x1e) |
 903                                        S_028838_VS_GPRS(0x1e) |
 904                                        S_028838_GS_GPRS(0x1e) |
 905                                        S_028838_ES_GPRS(0x1e) |
 906                                        S_028838_HS_GPRS(0x1e) |
 907                                        S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
 908         }
 909 }
 910
 911 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
 912 {
 913         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 914         struct pipe_clip_state *state = &rctx->clip_state.state;
 915
 916         radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
 917         radeon_emit_array(cs, (unsigned*)state, 6*4);
 918 }
 919
 920 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
 921                                          const struct pipe_poly_stipple *state)
 922 {
 923 }
 924
 925 static void evergreen_get_scissor_rect(struct r600_context *rctx,
 926                                        unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
 927                                        uint32_t *tl, uint32_t *br)
 928 {
 929         struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
 930
 931         evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
 932
 933         *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
 934         *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
 935 }
 936
 937 /**
 938  * This function intializes the CB* register values for RATs.  It is meant
 939  * to be used for 1D aligned buffers that do not have an associated
 940  * radeon_surf.
 941  */
 942 void evergreen_init_color_surface_rat(struct r600_context *rctx,
 943                                         struct r600_surface *surf)
 944 {
 945         struct pipe_resource *pipe_buffer = surf->base.texture;
 946         unsigned format = r600_translate_colorformat(rctx->b.chip_class,
 947                                                      surf->base.format, FALSE);
 948         unsigned endian = r600_colorformat_endian_swap(format, FALSE);
 949         unsigned swap = r600_translate_colorswap(surf->base.format, FALSE);
 950         unsigned block_size =
 951                 align(util_format_get_blocksize(pipe_buffer->format), 4);
 952         unsigned pitch_alignment =
 953                 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
 954         unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
 955
 956         surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
 957
 958         surf->cb_color_pitch = (pitch / 8) - 1;
 959
 960         surf->cb_color_slice = 0;
 961
 962         surf->cb_color_view = 0;
 963
 964         surf->cb_color_info =
 965                   S_028C70_ENDIAN(endian)
 966                 | S_028C70_FORMAT(format)
 967                 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
 968                 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
 969                 | S_028C70_COMP_SWAP(swap)
 970                 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
 971                                             * are using NUMBER_UINT */
 972                 | S_028C70_RAT(1)
 973                 ;
 974
 975         surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
 976
 977         /* For buffers, CB_COLOR0_DIM needs to be set to the number of
 978          * elements. */
 979         surf->cb_color_dim = pipe_buffer->width0;
 980
 981         /* Set the buffer range the GPU will have access to: */
 982         util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
 983                        0, pipe_buffer->width0);
 984
 985         surf->cb_color_fmask = surf->cb_color_base;
 986         surf->cb_color_fmask_slice = 0;
 987 }
 988
 989 void evergreen_init_color_surface(struct r600_context *rctx,
 990                                   struct r600_surface *surf)
 991 {
 992         struct r600_screen *rscreen = rctx->screen;
 993         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
 994         unsigned level = surf->base.u.tex.level;
 995         unsigned pitch, slice;
 996         unsigned color_info, color_attrib, color_dim = 0, color_view;
 997         unsigned format, swap, ntype, endian;
 998         uint64_t offset, base_offset;
 999         unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1000         const struct util_format_description *desc;
1001         int i;
1002         bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1003
1004         offset = rtex->surface.level[level].offset;
1005         color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1006                      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1007
1008         pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1009         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1010         if (slice) {
1011                 slice = slice - 1;
1012         }
1013         color_info = 0;
1014         switch (rtex->surface.level[level].mode) {
1015         default:
1016         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1017                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1018                 non_disp_tiling = 1;
1019                 break;
1020         case RADEON_SURF_MODE_1D:
1021                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1022                 non_disp_tiling = rtex->non_disp_tiling;
1023                 break;
1024         case RADEON_SURF_MODE_2D:
1025                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1026                 non_disp_tiling = rtex->non_disp_tiling;
1027                 break;
1028         }
1029         tile_split = rtex->surface.tile_split;
1030         macro_aspect = rtex->surface.mtilea;
1031         bankw = rtex->surface.bankw;
1032         bankh = rtex->surface.bankh;
1033         if (rtex->fmask.size)
1034                 fmask_bankh = rtex->fmask.bank_height;
1035         else
1036                 fmask_bankh = rtex->surface.bankh;
1037         tile_split = eg_tile_split(tile_split);
1038         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1039         bankw = eg_bank_wh(bankw);
1040         bankh = eg_bank_wh(bankh);
1041         fmask_bankh = eg_bank_wh(fmask_bankh);
1042
1043         /* 128 bit formats require tile type = 1 */
1044         if (rscreen->b.chip_class == CAYMAN) {
1045                 if (util_format_get_blocksize(surf->base.format) >= 16)
1046                         non_disp_tiling = 1;
1047         }
1048         nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1049         desc = util_format_description(surf->base.format);
1050         for (i = 0; i < 4; i++) {
1051                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1052                         break;
1053                 }
1054         }
1055
1056         color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1057                         S_028C74_NUM_BANKS(nbanks) |
1058                         S_028C74_BANK_WIDTH(bankw) |
1059                         S_028C74_BANK_HEIGHT(bankh) |
1060                         S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1061                         S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1062                         S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1063
1064         if (rctx->b.chip_class == CAYMAN) {
1065                 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1066                                                            PIPE_SWIZZLE_1);
1067
1068                 if (rtex->resource.b.b.nr_samples > 1) {
1069                         unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1070                         color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1071                                         S_028C74_NUM_FRAGMENTS(log_samples);
1072                 }
1073         }
1074
1075         ntype = V_028C70_NUMBER_UNORM;
1076         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1077                 ntype = V_028C70_NUMBER_SRGB;
1078         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1079                 if (desc->channel[i].normalized)
1080                         ntype = V_028C70_NUMBER_SNORM;
1081                 else if (desc->channel[i].pure_integer)
1082                         ntype = V_028C70_NUMBER_SINT;
1083         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1084                 if (desc->channel[i].normalized)
1085                         ntype = V_028C70_NUMBER_UNORM;
1086                 else if (desc->channel[i].pure_integer)
1087                         ntype = V_028C70_NUMBER_UINT;
1088         }
1089
1090         if (R600_BIG_ENDIAN)
1091                 do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
1092
1093         format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
1094                                                       do_endian_swap);
1095         assert(format != ~0);
1096
1097         swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
1098         assert(swap != ~0);
1099
1100         endian = r600_colorformat_endian_swap(format, do_endian_swap);
1101
1102         /* blend clamp should be set for all NORM/SRGB types */
1103         if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1104             ntype == V_028C70_NUMBER_SRGB)
1105                 blend_clamp = 1;
1106
1107         /* set blend bypass according to docs if SINT/UINT or
1108            8/24 COLOR variants */
1109         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1110             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1111             format == V_028C70_COLOR_X24_8_32_FLOAT) {
1112                 blend_clamp = 0;
1113                 blend_bypass = 1;
1114         }
1115
1116         surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1117
1118         color_info |= S_028C70_FORMAT(format) |
1119                 S_028C70_COMP_SWAP(swap) |
1120                 S_028C70_BLEND_CLAMP(blend_clamp) |
1121                 S_028C70_BLEND_BYPASS(blend_bypass) |
1122                 S_028C70_NUMBER_TYPE(ntype) |
1123                 S_028C70_ENDIAN(endian);
1124
1125         /* EXPORT_NORM is an optimzation that can be enabled for better
1126          * performance in certain cases.
1127          * EXPORT_NORM can be enabled if:
1128          * - 11-bit or smaller UNORM/SNORM/SRGB
1129          * - 16-bit or smaller FLOAT
1130          */
1131         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1132             ((desc->channel[i].size < 12 &&
1133               desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1134               ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1135              (desc->channel[i].size < 17 &&
1136               desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1137                 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1138                 surf->export_16bpc = true;
1139         }
1140
1141         if (rtex->fmask.size) {
1142                 color_info |= S_028C70_COMPRESSION(1);
1143         }
1144
1145         base_offset = rtex->resource.gpu_address;
1146
1147         /* XXX handle enabling of CB beyond BASE8 which has different offset */
1148         surf->cb_color_base = (base_offset + offset) >> 8;
1149         surf->cb_color_dim = color_dim;
1150         surf->cb_color_info = color_info;
1151         surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1152         surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1153         surf->cb_color_view = color_view;
1154         surf->cb_color_attrib = color_attrib;
1155         if (rtex->fmask.size) {
1156                 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1157                 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1158         } else {
1159                 surf->cb_color_fmask = surf->cb_color_base;
1160                 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1161         }
1162
1163         surf->color_initialized = true;
1164 }
1165
1166 static void evergreen_init_depth_surface(struct r600_context *rctx,
1167                                          struct r600_surface *surf)
1168 {
1169         struct r600_screen *rscreen = rctx->screen;
1170         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1171         unsigned level = surf->base.u.tex.level;
1172         struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1173         uint64_t offset;
1174         unsigned format, array_mode;
1175         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1176
1177
1178         format = r600_translate_dbformat(surf->base.format);
1179         assert(format != ~0);
1180
1181         offset = rtex->resource.gpu_address;
1182         offset += rtex->surface.level[level].offset;
1183
1184         switch (rtex->surface.level[level].mode) {
1185         case RADEON_SURF_MODE_2D:
1186                 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1187                 break;
1188         case RADEON_SURF_MODE_1D:
1189         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1190         default:
1191                 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1192                 break;
1193         }
1194         tile_split = rtex->surface.tile_split;
1195         macro_aspect = rtex->surface.mtilea;
1196         bankw = rtex->surface.bankw;
1197         bankh = rtex->surface.bankh;
1198         tile_split = eg_tile_split(tile_split);
1199         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1200         bankw = eg_bank_wh(bankw);
1201         bankh = eg_bank_wh(bankh);
1202         nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1203         offset >>= 8;
1204
1205         surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1206                           S_028040_FORMAT(format) |
1207                           S_028040_TILE_SPLIT(tile_split)|
1208                           S_028040_NUM_BANKS(nbanks) |
1209                           S_028040_BANK_WIDTH(bankw) |
1210                           S_028040_BANK_HEIGHT(bankh) |
1211                           S_028040_MACRO_TILE_ASPECT(macro_aspect);
1212         if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1213                 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1214         }
1215
1216         assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1217
1218         surf->db_depth_base = offset;
1219         surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1220                               S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1221         surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1222                               S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1223         surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1224                                                        levelinfo->nblk_y / 64 - 1);
1225
1226         switch (surf->base.format) {
1227         case PIPE_FORMAT_Z24X8_UNORM:
1228         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1229         case PIPE_FORMAT_X8Z24_UNORM:
1230         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1231                 surf->pa_su_poly_offset_db_fmt_cntl =
1232                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1233                 break;
1234         case PIPE_FORMAT_Z32_FLOAT:
1235         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1236                 surf->pa_su_poly_offset_db_fmt_cntl =
1237                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1238                         S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1239                 break;
1240         case PIPE_FORMAT_Z16_UNORM:
1241                 surf->pa_su_poly_offset_db_fmt_cntl =
1242                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1243                 break;
1244         default:;
1245         }
1246
1247         if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1248                 uint64_t stencil_offset;
1249                 unsigned stile_split = rtex->surface.stencil_tile_split;
1250
1251                 stile_split = eg_tile_split(stile_split);
1252
1253                 stencil_offset = rtex->surface.stencil_level[level].offset;
1254                 stencil_offset += rtex->resource.gpu_address;
1255
1256                 surf->db_stencil_base = stencil_offset >> 8;
1257                 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1258                                         S_028044_TILE_SPLIT(stile_split);
1259         } else {
1260                 surf->db_stencil_base = offset;
1261                 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1262                  * Older kernels are out of luck. */
1263                 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1264                                         S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1265                                         S_028044_FORMAT(V_028044_STENCIL_8);
1266         }
1267
1268         /* use htile only for first level */
1269         if (rtex->htile_buffer && !level) {
1270                 uint64_t va = rtex->htile_buffer->gpu_address;
1271                 surf->db_htile_data_base = va >> 8;
1272                 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1273                                          S_028ABC_HTILE_HEIGHT(1) |
1274                                          S_028ABC_FULL_CACHE(1);
1275                 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1276                 surf->db_preload_control = 0;
1277         }
1278
1279         surf->depth_initialized = true;
1280 }
1281
1282 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1283                                             const struct pipe_framebuffer_state *state)
1284 {
1285         struct r600_context *rctx = (struct r600_context *)ctx;
1286         struct r600_surface *surf;
1287         struct r600_texture *rtex;
1288         uint32_t i, log_samples;
1289
1290         if (rctx->framebuffer.state.nr_cbufs) {
1291                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1292                 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1293                                  R600_CONTEXT_FLUSH_AND_INV_CB_META;
1294         }
1295         if (rctx->framebuffer.state.zsbuf) {
1296                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1297                 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1298
1299                 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1300                 if (rtex->htile_buffer) {
1301                         rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1302                 }
1303         }
1304
1305         util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1306
1307         /* Colorbuffers. */
1308         rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1309         rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1310                                            util_format_is_pure_integer(state->cbufs[0]->format);
1311         rctx->framebuffer.compressed_cb_mask = 0;
1312         rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1313
1314         for (i = 0; i < state->nr_cbufs; i++) {
1315                 surf = (struct r600_surface*)state->cbufs[i];
1316                 if (!surf)
1317                         continue;
1318
1319                 rtex = (struct r600_texture*)surf->base.texture;
1320
1321                 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1322
1323                 if (!surf->color_initialized) {
1324                         evergreen_init_color_surface(rctx, surf);
1325                 }
1326
1327                 if (!surf->export_16bpc) {
1328                         rctx->framebuffer.export_16bpc = false;
1329                 }
1330
1331                 if (rtex->fmask.size && rtex->cmask.size) {
1332                         rctx->framebuffer.compressed_cb_mask |= 1 << i;
1333                 }
1334         }
1335
1336         /* Update alpha-test state dependencies.
1337          * Alpha-test is done on the first colorbuffer only. */
1338         if (state->nr_cbufs) {
1339                 bool alphatest_bypass = false;
1340                 bool export_16bpc = true;
1341
1342                 surf = (struct r600_surface*)state->cbufs[0];
1343                 if (surf) {
1344                         alphatest_bypass = surf->alphatest_bypass;
1345                         export_16bpc = surf->export_16bpc;
1346                 }
1347
1348                 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1349                         rctx->alphatest_state.bypass = alphatest_bypass;
1350                         r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1351                 }
1352                 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1353                         rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1354                         r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1355                 }
1356         }
1357
1358         /* ZS buffer. */
1359         if (state->zsbuf) {
1360                 surf = (struct r600_surface*)state->zsbuf;
1361
1362                 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1363
1364                 if (!surf->depth_initialized) {
1365                         evergreen_init_depth_surface(rctx, surf);
1366                 }
1367
1368                 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1369                         rctx->poly_offset_state.zs_format = state->zsbuf->format;
1370                         r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1371                 }
1372
1373                 if (rctx->db_state.rsurf != surf) {
1374                         rctx->db_state.rsurf = surf;
1375                         r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1376                         r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1377                 }
1378         } else if (rctx->db_state.rsurf) {
1379                 rctx->db_state.rsurf = NULL;
1380                 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1381                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1382         }
1383
1384         if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1385                 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1386                 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1387         }
1388
1389         if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1390                 rctx->alphatest_state.bypass = false;
1391                 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1392         }
1393
1394         log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1395         /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1396         if ((rctx->b.chip_class == CAYMAN ||
1397              rctx->b.family == CHIP_RV770) &&
1398             rctx->db_misc_state.log_samples != log_samples) {
1399                 rctx->db_misc_state.log_samples = log_samples;
1400                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1401         }
1402
1403
1404         /* Calculate the CS size. */
1405         rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1406
1407         /* MSAA. */
1408         if (rctx->b.chip_class == EVERGREEN)
1409                 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1410         else
1411                 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1412
1413         /* Colorbuffers. */
1414         rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1415         rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1416         rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1417
1418         /* ZS buffer. */
1419         if (state->zsbuf) {
1420                 rctx->framebuffer.atom.num_dw += 24;
1421                 rctx->framebuffer.atom.num_dw += 2;
1422         } else if (rctx->screen->b.info.drm_minor >= 18) {
1423                 rctx->framebuffer.atom.num_dw += 4;
1424         }
1425
1426         r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1427
1428         r600_set_sample_locations_constant_buffer(rctx);
1429 }
1430
1431 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1432 {
1433         struct r600_context *rctx = (struct r600_context *)ctx;
1434
1435         if (rctx->ps_iter_samples == min_samples)
1436                 return;
1437
1438         rctx->ps_iter_samples = min_samples;
1439         if (rctx->framebuffer.nr_samples > 1) {
1440                 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1441         }
1442 }
1443
1444 /* 8xMSAA */
1445 static uint32_t sample_locs_8x[] = {
1446         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1447         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1448         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1449         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1450         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1451         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1452         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1453         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1454 };
1455 static unsigned max_dist_8x = 7;
1456
1457 static void evergreen_get_sample_position(struct pipe_context *ctx,
1458                                      unsigned sample_count,
1459                                      unsigned sample_index,
1460                                      float *out_value)
1461 {
1462         int offset, index;
1463         struct {
1464                 int idx:4;
1465         } val;
1466         switch (sample_count) {
1467         case 1:
1468         default:
1469                 out_value[0] = out_value[1] = 0.5;
1470                 break;
1471         case 2:
1472                 offset = 4 * (sample_index * 2);
1473                 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1474                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1475                 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1476                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1477                 break;
1478         case 4:
1479                 offset = 4 * (sample_index * 2);
1480                 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1481                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1482                 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1483                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1484                 break;
1485         case 8:
1486                 offset = 4 * (sample_index % 4 * 2);
1487                 index = (sample_index / 4);
1488                 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1489                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1490                 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1491                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1492                 break;
1493         }
1494 }
1495
1496 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1497 {
1498
1499         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1500         unsigned max_dist = 0;
1501
1502         switch (nr_samples) {
1503         default:
1504                 nr_samples = 0;
1505                 break;
1506         case 2:
1507                 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1508                 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1509                 max_dist = eg_max_dist_2x;
1510                 break;
1511         case 4:
1512                 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1513                 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1514                 max_dist = eg_max_dist_4x;
1515                 break;
1516         case 8:
1517                 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1518                 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1519                 max_dist = max_dist_8x;
1520                 break;
1521         }
1522
1523         if (nr_samples > 1) {
1524                 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1525                 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1526                                      S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1527                 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1528                                      S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1529                 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1530                                        EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1531                                        EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1532                                        EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1533         } else {
1534                 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1535                 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1536                 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1537                 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1538                                        EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1539                                        EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1540         }
1541 }
1542
1543 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1544 {
1545         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1546         struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1547         unsigned nr_cbufs = state->nr_cbufs;
1548         unsigned i, tl, br;
1549         struct r600_texture *tex = NULL;
1550         struct r600_surface *cb = NULL;
1551
1552         /* XXX support more colorbuffers once we need them */
1553         assert(nr_cbufs <= 8);
1554         if (nr_cbufs > 8)
1555                 nr_cbufs = 8;
1556
1557         /* Colorbuffers. */
1558         for (i = 0; i < nr_cbufs; i++) {
1559                 unsigned reloc, cmask_reloc;
1560
1561                 cb = (struct r600_surface*)state->cbufs[i];
1562                 if (!cb) {
1563                         radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1564                                                S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1565                         continue;
1566                 }
1567
1568                 tex = (struct r600_texture *)cb->base.texture;
1569                 reloc = radeon_add_to_buffer_list(&rctx->b,
1570                                               &rctx->b.gfx,
1571                                               (struct r600_resource*)cb->base.texture,
1572                                               RADEON_USAGE_READWRITE,
1573                                               tex->surface.nsamples > 1 ?
1574                                                       RADEON_PRIO_COLOR_BUFFER_MSAA :
1575                                                       RADEON_PRIO_COLOR_BUFFER);
1576
1577                 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1578                         cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1579                                 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1580                                 RADEON_PRIO_CMASK);
1581                 } else {
1582                         cmask_reloc = reloc;
1583                 }
1584
1585                 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1586                 radeon_emit(cs, cb->cb_color_base);     /* R_028C60_CB_COLOR0_BASE */
1587                 radeon_emit(cs, cb->cb_color_pitch);    /* R_028C64_CB_COLOR0_PITCH */
1588                 radeon_emit(cs, cb->cb_color_slice);    /* R_028C68_CB_COLOR0_SLICE */
1589                 radeon_emit(cs, cb->cb_color_view);     /* R_028C6C_CB_COLOR0_VIEW */
1590                 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1591                 radeon_emit(cs, cb->cb_color_attrib);   /* R_028C74_CB_COLOR0_ATTRIB */
1592                 radeon_emit(cs, cb->cb_color_dim);              /* R_028C78_CB_COLOR0_DIM */
1593                 radeon_emit(cs, tex->cmask.base_address_reg);   /* R_028C7C_CB_COLOR0_CMASK */
1594                 radeon_emit(cs, tex->cmask.slice_tile_max);     /* R_028C80_CB_COLOR0_CMASK_SLICE */
1595                 radeon_emit(cs, cb->cb_color_fmask);    /* R_028C84_CB_COLOR0_FMASK */
1596                 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1597                 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1598                 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1599
1600                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1601                 radeon_emit(cs, reloc);
1602
1603                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1604                 radeon_emit(cs, reloc);
1605
1606                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1607                 radeon_emit(cs, cmask_reloc);
1608
1609                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1610                 radeon_emit(cs, reloc);
1611         }
1612         /* set CB_COLOR1_INFO for possible dual-src blending */
1613         if (i == 1 && state->cbufs[0]) {
1614                 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1615                                        cb->cb_color_info | tex->cb_color_info);
1616                 i++;
1617         }
1618         for (; i < 8 ; i++)
1619                 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1620         for (; i < 12; i++)
1621                 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1622
1623         /* ZS buffer. */
1624         if (state->zsbuf) {
1625                 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1626                 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1627                                                        &rctx->b.gfx,
1628                                                        (struct r600_resource*)state->zsbuf->texture,
1629                                                        RADEON_USAGE_READWRITE,
1630                                                        zb->base.texture->nr_samples > 1 ?
1631                                                                RADEON_PRIO_DEPTH_BUFFER_MSAA :
1632                                                                RADEON_PRIO_DEPTH_BUFFER);
1633
1634                 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1635                                        zb->pa_su_poly_offset_db_fmt_cntl);
1636                 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1637
1638                 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1639                 radeon_emit(cs, zb->db_z_info);         /* R_028040_DB_Z_INFO */
1640                 radeon_emit(cs, zb->db_stencil_info);   /* R_028044_DB_STENCIL_INFO */
1641                 radeon_emit(cs, zb->db_depth_base);     /* R_028048_DB_Z_READ_BASE */
1642                 radeon_emit(cs, zb->db_stencil_base);   /* R_02804C_DB_STENCIL_READ_BASE */
1643                 radeon_emit(cs, zb->db_depth_base);     /* R_028050_DB_Z_WRITE_BASE */
1644                 radeon_emit(cs, zb->db_stencil_base);   /* R_028054_DB_STENCIL_WRITE_BASE */
1645                 radeon_emit(cs, zb->db_depth_size);     /* R_028058_DB_DEPTH_SIZE */
1646                 radeon_emit(cs, zb->db_depth_slice);    /* R_02805C_DB_DEPTH_SLICE */
1647
1648                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1649                 radeon_emit(cs, reloc);
1650
1651                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1652                 radeon_emit(cs, reloc);
1653
1654                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1655                 radeon_emit(cs, reloc);
1656
1657                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1658                 radeon_emit(cs, reloc);
1659         } else if (rctx->screen->b.info.drm_minor >= 18) {
1660                 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1661                  * Older kernels are out of luck. */
1662                 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1663                 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1664                 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1665         }
1666
1667         /* Framebuffer dimensions. */
1668         evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1669
1670         radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1671         radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1672         radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1673
1674         if (rctx->b.chip_class == EVERGREEN) {
1675                 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1676         } else {
1677                 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1678                 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1679         }
1680 }
1681
1682 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1683 {
1684         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1685         struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1686         float offset_units = state->offset_units;
1687         float offset_scale = state->offset_scale;
1688
1689         switch (state->zs_format) {
1690         case PIPE_FORMAT_Z24X8_UNORM:
1691         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1692         case PIPE_FORMAT_X8Z24_UNORM:
1693         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1694                 offset_units *= 2.0f;
1695                 break;
1696         case PIPE_FORMAT_Z16_UNORM:
1697                 offset_units *= 4.0f;
1698                 break;
1699         default:;
1700         }
1701
1702         radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1703         radeon_emit(cs, fui(offset_scale));
1704         radeon_emit(cs, fui(offset_units));
1705         radeon_emit(cs, fui(offset_scale));
1706         radeon_emit(cs, fui(offset_units));
1707 }
1708
1709 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1710 {
1711         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1712         struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1713         unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1714         unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1715
1716         radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1717         radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1718         /* This must match the used export instructions exactly.
1719          * Other values may lead to undefined behavior and hangs.
1720          */
1721         radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1722 }
1723
1724 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1725 {
1726         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1727         struct r600_db_state *a = (struct r600_db_state*)atom;
1728
1729         if (a->rsurf && a->rsurf->db_htile_surface) {
1730                 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1731                 unsigned reloc_idx;
1732
1733                 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1734                 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1735                 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1736                 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1737                 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1738                                                   RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1739                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1740                 cs->buf[cs->cdw++] = reloc_idx;
1741         } else {
1742                 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1743                 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1744         }
1745 }
1746
1747 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1748 {
1749         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1750         struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1751         unsigned db_render_control = 0;
1752         unsigned db_count_control = 0;
1753         unsigned db_render_override =
1754                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1755                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1756
1757         if (rctx->b.num_occlusion_queries > 0 &&
1758             !a->occlusion_queries_disabled) {
1759                 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1760                 if (rctx->b.chip_class == CAYMAN) {
1761                         db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1762                 }
1763                 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1764         } else {
1765                 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1766         }
1767
1768         /* This is to fix a lockup when hyperz and alpha test are enabled at
1769          * the same time somehow GPU get confuse on which order to pick for
1770          * z test
1771          */
1772         if (rctx->alphatest_state.sx_alpha_test_control)
1773                 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1774
1775         if (a->flush_depthstencil_through_cb) {
1776                 assert(a->copy_depth || a->copy_stencil);
1777
1778                 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1779                                      S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1780                                      S_028000_COPY_CENTROID(1) |
1781                                      S_028000_COPY_SAMPLE(a->copy_sample);
1782         } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1783                 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1784                                      S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1785                 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1786         }
1787         if (a->htile_clear) {
1788                 /* FIXME we might want to disable cliprect here */
1789                 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1790         }
1791
1792         radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1793         radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1794         radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1795         radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1796         radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1797 }
1798
1799 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1800                                           struct r600_vertexbuf_state *state,
1801                                           unsigned resource_offset,
1802                                           unsigned pkt_flags)
1803 {
1804         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1805         uint32_t dirty_mask = state->dirty_mask;
1806
1807         while (dirty_mask) {
1808                 struct pipe_vertex_buffer *vb;
1809                 struct r600_resource *rbuffer;
1810                 uint64_t va;
1811                 unsigned buffer_index = u_bit_scan(&dirty_mask);
1812
1813                 vb = &state->vb[buffer_index];
1814                 rbuffer = (struct r600_resource*)vb->buffer;
1815                 assert(rbuffer);
1816
1817                 va = rbuffer->gpu_address + vb->buffer_offset;
1818
1819                 /* fetch resources start at index 992 */
1820                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1821                 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1822                 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1823                 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1824                 radeon_emit(cs, /* RESOURCEi_WORD2 */
1825                                  S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1826                                  S_030008_STRIDE(vb->stride) |
1827                                  S_030008_BASE_ADDRESS_HI(va >> 32UL));
1828                 radeon_emit(cs, /* RESOURCEi_WORD3 */
1829                                  S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1830                                  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1831                                  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1832                                  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1833                 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1834                 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1835                 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1836                 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1837
1838                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1839                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1840                                                       RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1841         }
1842         state->dirty_mask = 0;
1843 }
1844
1845 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1846 {
1847         evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1848 }
1849
1850 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1851 {
1852         evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1853                                       RADEON_CP_PACKET3_COMPUTE_MODE);
1854 }
1855
1856 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1857                                             struct r600_constbuf_state *state,
1858                                             unsigned buffer_id_base,
1859                                             unsigned reg_alu_constbuf_size,
1860                                             unsigned reg_alu_const_cache,
1861                                             unsigned pkt_flags)
1862 {
1863         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1864         uint32_t dirty_mask = state->dirty_mask;
1865
1866         while (dirty_mask) {
1867                 struct pipe_constant_buffer *cb;
1868                 struct r600_resource *rbuffer;
1869                 uint64_t va;
1870                 unsigned buffer_index = ffs(dirty_mask) - 1;
1871                 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1872
1873                 cb = &state->cb[buffer_index];
1874                 rbuffer = (struct r600_resource*)cb->buffer;
1875                 assert(rbuffer);
1876
1877                 va = rbuffer->gpu_address + cb->buffer_offset;
1878
1879                 if (!gs_ring_buffer) {
1880                         radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1881                                                     DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1882                         radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1883                                                     pkt_flags);
1884                 }
1885
1886                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1887                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1888                                                       RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1889
1890                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1891                 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1892                 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1893                 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1894                 radeon_emit(cs, /* RESOURCEi_WORD2 */
1895                             S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1896                             S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1897                             S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1898                             S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1899                 radeon_emit(cs, /* RESOURCEi_WORD3 */
1900                                  S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1901                                  S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1902                                  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1903                                  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1904                                  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1905                 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1906                 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1907                 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1908                 radeon_emit(cs, /* RESOURCEi_WORD7 */
1909                             S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1910
1911                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1912                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1913                                                       RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1914
1915                 dirty_mask &= ~(1 << buffer_index);
1916         }
1917         state->dirty_mask = 0;
1918 }
1919
1920 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1921 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1922 {
1923         if (rctx->vs_shader->current->shader.vs_as_ls) {
1924                 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1925                                                 EG_FETCH_CONSTANTS_OFFSET_LS,
1926                                                 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1927                                                 R_028F40_ALU_CONST_CACHE_LS_0,
1928                                                 0 /* PKT3 flags */);
1929         } else {
1930                 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1931                                                 EG_FETCH_CONSTANTS_OFFSET_VS,
1932                                                 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1933                                                 R_028980_ALU_CONST_CACHE_VS_0,
1934                                                 0 /* PKT3 flags */);
1935         }
1936 }
1937
1938 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1939 {
1940         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1941                                         EG_FETCH_CONSTANTS_OFFSET_GS,
1942                                         R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1943                                         R_0289C0_ALU_CONST_CACHE_GS_0,
1944                                         0 /* PKT3 flags */);
1945 }
1946
1947 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1948 {
1949         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1950                                         EG_FETCH_CONSTANTS_OFFSET_PS,
1951                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1952                                         R_028940_ALU_CONST_CACHE_PS_0,
1953                                         0 /* PKT3 flags */);
1954 }
1955
1956 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1957 {
1958         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
1959                                         EG_FETCH_CONSTANTS_OFFSET_CS,
1960                                         R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1961                                         R_028F40_ALU_CONST_CACHE_LS_0,
1962                                         RADEON_CP_PACKET3_COMPUTE_MODE);
1963 }
1964
1965 /* tes constants can be emitted to VS or ES - which are common */
1966 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1967 {
1968         if (!rctx->tes_shader)
1969                 return;
1970         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
1971                                         EG_FETCH_CONSTANTS_OFFSET_VS,
1972                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1973                                         R_028980_ALU_CONST_CACHE_VS_0,
1974                                         0);
1975 }
1976
1977 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1978 {
1979         if (!rctx->tes_shader)
1980                 return;
1981         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
1982                                         EG_FETCH_CONSTANTS_OFFSET_HS,
1983                                         R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
1984                                         R_028F00_ALU_CONST_CACHE_HS_0,
1985                                         0);
1986 }
1987
1988 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1989                                          struct r600_samplerview_state *state,
1990                                          unsigned resource_id_base, unsigned pkt_flags)
1991 {
1992         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1993         uint32_t dirty_mask = state->dirty_mask;
1994
1995         while (dirty_mask) {
1996                 struct r600_pipe_sampler_view *rview;
1997                 unsigned resource_index = u_bit_scan(&dirty_mask);
1998                 unsigned reloc;
1999
2000                 rview = state->views[resource_index];
2001                 assert(rview);
2002
2003                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2004                 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2005                 radeon_emit_array(cs, rview->tex_resource_words, 8);
2006
2007                 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2008                                               RADEON_USAGE_READ,
2009                                               r600_get_sampler_view_priority(rview->tex_resource));
2010                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2011                 radeon_emit(cs, reloc);
2012
2013                 if (!rview->skip_mip_address_reloc) {
2014                         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2015                         radeon_emit(cs, reloc);
2016                 }
2017         }
2018         state->dirty_mask = 0;
2019 }
2020
2021 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2022 {
2023         if (rctx->vs_shader->current->shader.vs_as_ls) {
2024                 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2025                                              EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2026         } else {
2027                 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2028                                              EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2029         }
2030 }
2031
2032 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2033 {
2034         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2035                                      EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2036 }
2037
2038 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2039 {
2040         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2041                                      EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2042 }
2043
2044 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2045 {
2046         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2047                                      EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2048 }
2049
2050 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2051 {
2052         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2053                                      EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2054 }
2055
2056 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2057 {
2058         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2059                                      EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2060 }
2061
2062 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2063                                 struct r600_textures_info *texinfo,
2064                                 unsigned resource_id_base,
2065                                 unsigned border_index_reg,
2066                                 unsigned pkt_flags)
2067 {
2068         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2069         uint32_t dirty_mask = texinfo->states.dirty_mask;
2070
2071         while (dirty_mask) {
2072                 struct r600_pipe_sampler_state *rstate;
2073                 unsigned i = u_bit_scan(&dirty_mask);
2074
2075                 rstate = texinfo->states.states[i];
2076                 assert(rstate);
2077
2078                 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2079                 radeon_emit(cs, (resource_id_base + i) * 3);
2080                 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2081
2082                 if (rstate->border_color_use) {
2083                         radeon_set_config_reg_seq(cs, border_index_reg, 5);
2084                         radeon_emit(cs, i);
2085                         radeon_emit_array(cs, rstate->border_color.ui, 4);
2086                 }
2087         }
2088         texinfo->states.dirty_mask = 0;
2089 }
2090
2091 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2092 {
2093         if (rctx->vs_shader->current->shader.vs_as_ls) {
2094                 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2095                                               R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2096         } else {
2097                 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2098                                               R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2099         }
2100 }
2101
2102 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2103 {
2104         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2105                                       R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2106 }
2107
2108 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2109 {
2110         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2111                                       R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2112 }
2113
2114 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2115 {
2116         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2117                                       R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2118 }
2119
2120 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2121 {
2122         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2123                                       R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2124 }
2125
2126 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2127 {
2128         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2129                                       R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2130                                       RADEON_CP_PACKET3_COMPUTE_MODE);
2131 }
2132
2133 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2134 {
2135         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2136         uint8_t mask = s->sample_mask;
2137
2138         radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2139                                mask | (mask << 8) | (mask << 16) | (mask << 24));
2140 }
2141
2142 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2143 {
2144         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2145         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2146         uint16_t mask = s->sample_mask;
2147
2148         radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2149         radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2150         radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2151 }
2152
2153 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2154 {
2155         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2156         struct r600_cso_state *state = (struct r600_cso_state*)a;
2157         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2158
2159         radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2160                                (shader->buffer->gpu_address + shader->offset) >> 8);
2161         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2162         radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2163                                                   RADEON_USAGE_READ,
2164                                                   RADEON_PRIO_INTERNAL_SHADER));
2165 }
2166
2167 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2168 {
2169         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2170         struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2171
2172         uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2173
2174         if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2175                 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2176                 primid = 1;
2177         }
2178
2179         if (state->geom_enable) {
2180                 uint32_t cut_val;
2181
2182                 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2183                         cut_val = V_028A40_GS_CUT_128;
2184                 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2185                         cut_val = V_028A40_GS_CUT_256;
2186                 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2187                         cut_val = V_028A40_GS_CUT_512;
2188                 else
2189                         cut_val = V_028A40_GS_CUT_1024;
2190
2191                 v = S_028B54_GS_EN(1) |
2192                     S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2193                 if (!rctx->tes_shader)
2194                         v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2195
2196                 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2197                         S_028A40_CUT_MODE(cut_val);
2198
2199                 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2200                         primid = 1;
2201         }
2202
2203         if (rctx->tes_shader) {
2204                 uint32_t type, partitioning, topology;
2205                 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2206                 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2207                 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2208                 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2209                 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2210                 switch (tes_prim_mode) {
2211                 case PIPE_PRIM_LINES:
2212                         type = V_028B6C_TESS_ISOLINE;
2213                         break;
2214                 case PIPE_PRIM_TRIANGLES:
2215                         type = V_028B6C_TESS_TRIANGLE;
2216                         break;
2217                 case PIPE_PRIM_QUADS:
2218                         type = V_028B6C_TESS_QUAD;
2219                         break;
2220                 default:
2221                         assert(0);
2222                         return;
2223                 }
2224
2225                 switch (tes_spacing) {
2226                 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2227                         partitioning = V_028B6C_PART_FRAC_ODD;
2228                         break;
2229                 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2230                         partitioning = V_028B6C_PART_FRAC_EVEN;
2231                         break;
2232                 case PIPE_TESS_SPACING_EQUAL:
2233                         partitioning = V_028B6C_PART_INTEGER;
2234                         break;
2235                 default:
2236                         assert(0);
2237                         return;
2238                 }
2239
2240                 if (tes_point_mode)
2241                         topology = V_028B6C_OUTPUT_POINT;
2242                 else if (tes_prim_mode == PIPE_PRIM_LINES)
2243                         topology = V_028B6C_OUTPUT_LINE;
2244                 else if (tes_vertex_order_cw)
2245                         /* XXX follow radeonsi and invert */
2246                         topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2247                 else
2248                         topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2249
2250                 tf_param = S_028B6C_TYPE(type) |
2251                         S_028B6C_PARTITIONING(partitioning) |
2252                         S_028B6C_TOPOLOGY(topology);
2253         }
2254
2255         if (rctx->tes_shader) {
2256                 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2257                      S_028B54_HS_EN(1);
2258                 if (!state->geom_enable)
2259                         v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2260                 else
2261                         v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2262         }
2263
2264         radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2265         radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2266         radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2267         radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2268         radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2269 }
2270
2271 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2272 {
2273         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2274         struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2275         struct r600_resource *rbuffer;
2276
2277         radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2278         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2279         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2280
2281         if (state->enable) {
2282                 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2283                 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2284                                 rbuffer->gpu_address >> 8);
2285                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2286                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2287                                                       RADEON_USAGE_READWRITE,
2288                                                       RADEON_PRIO_RINGS_STREAMOUT));
2289                 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2290                                 state->esgs_ring.buffer_size >> 8);
2291
2292                 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2293                 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2294                                 rbuffer->gpu_address >> 8);
2295                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2296                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2297                                                       RADEON_USAGE_READWRITE,
2298                                                       RADEON_PRIO_RINGS_STREAMOUT));
2299                 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2300                                 state->gsvs_ring.buffer_size >> 8);
2301         } else {
2302                 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2303                 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2304         }
2305
2306         radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2307         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2308         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2309 }
2310
2311 void cayman_init_common_regs(struct r600_command_buffer *cb,
2312                              enum chip_class ctx_chip_class,
2313                              enum radeon_family ctx_family,
2314                              int ctx_drm_minor)
2315 {
2316         r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2317         r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2318         /* always set the temp clauses */
2319         r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2320
2321         r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2322         r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2323         r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2324
2325         r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2326
2327         r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2328         r600_store_value(cb, 0);
2329         r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2330
2331         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2332 }
2333
2334 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2335 {
2336         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2337         int tmp, i;
2338
2339         r600_init_command_buffer(cb, 338);
2340
2341         /* This must be first. */
2342         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2343         r600_store_value(cb, 0x80000000);
2344         r600_store_value(cb, 0x80000000);
2345
2346         /* We're setting config registers here. */
2347         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2348         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2349
2350         /* This enables pipeline stat & streamout queries.
2351          * They are only disabled by blits.
2352          */
2353         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2354         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2355
2356         cayman_init_common_regs(cb, rctx->b.chip_class,
2357                                 rctx->b.family, rctx->screen->b.info.drm_minor);
2358
2359         r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2360         r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2361
2362         /* remove LS/HS from one SIMD for hw workaround */
2363         r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2364         r600_store_value(cb, 0xffffffff);
2365         r600_store_value(cb, 0xffffffff);
2366         r600_store_value(cb, 0xfffffffe);
2367
2368         r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2369         r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2370         r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2371         r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2372         r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2373         r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2374         r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2375
2376         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2377         r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2378         r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2379         r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2380         r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2381
2382         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2383         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2384         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2385         r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2386         r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2387         r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2388         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2389         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2390         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2391         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2392         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2393         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2394         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2395         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2396
2397         r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2398
2399         r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2400
2401         r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2402         r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2403         r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2404
2405         r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2406         r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2407         r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2408
2409         r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2410
2411         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2412         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2413         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2414
2415         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2416
2417         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2418
2419         r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2420
2421         r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2422         r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2423         r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2424         r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2425
2426         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2427         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2428
2429         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2430         for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2431                 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2432                 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2433         }
2434
2435         r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2436         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2437
2438         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2439         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2440         r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2441
2442         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2443         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2444         r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2445
2446         r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2447         r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2448         r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2449         r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2450         r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2451         r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2452
2453         r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2454
2455         /* to avoid GPU doing any preloading of constant from random address */
2456         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2457         for (i = 0; i < 16; i++)
2458                 r600_store_value(cb, 0);
2459
2460         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2461         for (i = 0; i < 16; i++)
2462                 r600_store_value(cb, 0);
2463
2464         r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2465         for (i = 0; i < 16; i++)
2466                 r600_store_value(cb, 0);
2467
2468         r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2469         for (i = 0; i < 16; i++)
2470                 r600_store_value(cb, 0);
2471
2472         r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2473         for (i = 0; i < 16; i++)
2474                 r600_store_value(cb, 0);
2475
2476         if (rctx->screen->b.has_streamout) {
2477                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2478         }
2479
2480         r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2481         r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2482         r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2483         r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2484         r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2485         r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2486
2487         r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2488         r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2489         r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2490         r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2491         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2492         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2493         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2494         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2495         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2496 }
2497
2498 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2499                                 enum chip_class ctx_chip_class,
2500                                 enum radeon_family ctx_family,
2501                                 int ctx_drm_minor)
2502 {
2503         int ps_prio;
2504         int vs_prio;
2505         int gs_prio;
2506         int es_prio;
2507
2508         int hs_prio;
2509         int cs_prio;
2510         int ls_prio;
2511
2512         unsigned tmp;
2513
2514         ps_prio = 0;
2515         vs_prio = 1;
2516         gs_prio = 2;
2517         es_prio = 3;
2518         hs_prio = 3;
2519         ls_prio = 3;
2520         cs_prio = 0;
2521
2522         rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2523         rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2524         rctx->r6xx_num_clause_temp_gprs = 4;
2525         rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2526         rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2527         rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2528         rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2529
2530         tmp = 0;
2531         switch (ctx_family) {
2532         case CHIP_CEDAR:
2533         case CHIP_PALM:
2534         case CHIP_SUMO:
2535         case CHIP_SUMO2:
2536         case CHIP_CAICOS:
2537                 break;
2538         default:
2539                 tmp |= S_008C00_VC_ENABLE(1);
2540                 break;
2541         }
2542         tmp |= S_008C00_EXPORT_SRC_C(1);
2543         tmp |= S_008C00_CS_PRIO(cs_prio);
2544         tmp |= S_008C00_LS_PRIO(ls_prio);
2545         tmp |= S_008C00_HS_PRIO(hs_prio);
2546         tmp |= S_008C00_PS_PRIO(ps_prio);
2547         tmp |= S_008C00_VS_PRIO(vs_prio);
2548         tmp |= S_008C00_GS_PRIO(gs_prio);
2549         tmp |= S_008C00_ES_PRIO(es_prio);
2550
2551         r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2552         r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2553
2554         r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2555         r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2556         r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2557
2558         /* The cs checker requires this register to be set. */
2559         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2560
2561         r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2562         r600_store_value(cb, 0);
2563         r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2564
2565         return;
2566 }
2567
2568 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2569 {
2570         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2571         int num_ps_threads;
2572         int num_vs_threads;
2573         int num_gs_threads;
2574         int num_es_threads;
2575         int num_hs_threads;
2576         int num_ls_threads;
2577
2578         int num_ps_stack_entries;
2579         int num_vs_stack_entries;
2580         int num_gs_stack_entries;
2581         int num_es_stack_entries;
2582         int num_hs_stack_entries;
2583         int num_ls_stack_entries;
2584         enum radeon_family family;
2585         unsigned tmp, i;
2586
2587         if (rctx->b.chip_class == CAYMAN) {
2588                 cayman_init_atom_start_cs(rctx);
2589                 return;
2590         }
2591
2592         r600_init_command_buffer(cb, 338);
2593
2594         /* This must be first. */
2595         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2596         r600_store_value(cb, 0x80000000);
2597         r600_store_value(cb, 0x80000000);
2598
2599         /* We're setting config registers here. */
2600         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2601         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2602
2603         /* This enables pipeline stat & streamout queries.
2604          * They are only disabled by blits.
2605          */
2606         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2607         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2608
2609         evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2610                                    rctx->b.family, rctx->screen->b.info.drm_minor);
2611
2612         family = rctx->b.family;
2613         switch (family) {
2614         case CHIP_CEDAR:
2615         default:
2616                 num_ps_threads = 96;
2617                 num_vs_threads = 16;
2618                 num_gs_threads = 16;
2619                 num_es_threads = 16;
2620                 num_hs_threads = 16;
2621                 num_ls_threads = 16;
2622                 num_ps_stack_entries = 42;
2623                 num_vs_stack_entries = 42;
2624                 num_gs_stack_entries = 42;
2625                 num_es_stack_entries = 42;
2626                 num_hs_stack_entries = 42;
2627                 num_ls_stack_entries = 42;
2628                 break;
2629         case CHIP_REDWOOD:
2630                 num_ps_threads = 128;
2631                 num_vs_threads = 20;
2632                 num_gs_threads = 20;
2633                 num_es_threads = 20;
2634                 num_hs_threads = 20;
2635                 num_ls_threads = 20;
2636                 num_ps_stack_entries = 42;
2637                 num_vs_stack_entries = 42;
2638                 num_gs_stack_entries = 42;
2639                 num_es_stack_entries = 42;
2640                 num_hs_stack_entries = 42;
2641                 num_ls_stack_entries = 42;
2642                 break;
2643         case CHIP_JUNIPER:
2644                 num_ps_threads = 128;
2645                 num_vs_threads = 20;
2646                 num_gs_threads = 20;
2647                 num_es_threads = 20;
2648                 num_hs_threads = 20;
2649                 num_ls_threads = 20;
2650                 num_ps_stack_entries = 85;
2651                 num_vs_stack_entries = 85;
2652                 num_gs_stack_entries = 85;
2653                 num_es_stack_entries = 85;
2654                 num_hs_stack_entries = 85;
2655                 num_ls_stack_entries = 85;
2656                 break;
2657         case CHIP_CYPRESS:
2658         case CHIP_HEMLOCK:
2659                 num_ps_threads = 128;
2660                 num_vs_threads = 20;
2661                 num_gs_threads = 20;
2662                 num_es_threads = 20;
2663                 num_hs_threads = 20;
2664                 num_ls_threads = 20;
2665                 num_ps_stack_entries = 85;
2666                 num_vs_stack_entries = 85;
2667                 num_gs_stack_entries = 85;
2668                 num_es_stack_entries = 85;
2669                 num_hs_stack_entries = 85;
2670                 num_ls_stack_entries = 85;
2671                 break;
2672         case CHIP_PALM:
2673                 num_ps_threads = 96;
2674                 num_vs_threads = 16;
2675                 num_gs_threads = 16;
2676                 num_es_threads = 16;
2677                 num_hs_threads = 16;
2678                 num_ls_threads = 16;
2679                 num_ps_stack_entries = 42;
2680                 num_vs_stack_entries = 42;
2681                 num_gs_stack_entries = 42;
2682                 num_es_stack_entries = 42;
2683                 num_hs_stack_entries = 42;
2684                 num_ls_stack_entries = 42;
2685                 break;
2686         case CHIP_SUMO:
2687                 num_ps_threads = 96;
2688                 num_vs_threads = 25;
2689                 num_gs_threads = 25;
2690                 num_es_threads = 25;
2691                 num_hs_threads = 16;
2692                 num_ls_threads = 16;
2693                 num_ps_stack_entries = 42;
2694                 num_vs_stack_entries = 42;
2695                 num_gs_stack_entries = 42;
2696                 num_es_stack_entries = 42;
2697                 num_hs_stack_entries = 42;
2698                 num_ls_stack_entries = 42;
2699                 break;
2700         case CHIP_SUMO2:
2701                 num_ps_threads = 96;
2702                 num_vs_threads = 25;
2703                 num_gs_threads = 25;
2704                 num_es_threads = 25;
2705                 num_hs_threads = 16;
2706                 num_ls_threads = 16;
2707                 num_ps_stack_entries = 85;
2708                 num_vs_stack_entries = 85;
2709                 num_gs_stack_entries = 85;
2710                 num_es_stack_entries = 85;
2711                 num_hs_stack_entries = 85;
2712                 num_ls_stack_entries = 85;
2713                 break;
2714         case CHIP_BARTS:
2715                 num_ps_threads = 128;
2716                 num_vs_threads = 20;
2717                 num_gs_threads = 20;
2718                 num_es_threads = 20;
2719                 num_hs_threads = 20;
2720                 num_ls_threads = 20;
2721                 num_ps_stack_entries = 85;
2722                 num_vs_stack_entries = 85;
2723                 num_gs_stack_entries = 85;
2724                 num_es_stack_entries = 85;
2725                 num_hs_stack_entries = 85;
2726                 num_ls_stack_entries = 85;
2727                 break;
2728         case CHIP_TURKS:
2729                 num_ps_threads = 128;
2730                 num_vs_threads = 20;
2731                 num_gs_threads = 20;
2732                 num_es_threads = 20;
2733                 num_hs_threads = 20;
2734                 num_ls_threads = 20;
2735                 num_ps_stack_entries = 42;
2736                 num_vs_stack_entries = 42;
2737                 num_gs_stack_entries = 42;
2738                 num_es_stack_entries = 42;
2739                 num_hs_stack_entries = 42;
2740                 num_ls_stack_entries = 42;
2741                 break;
2742         case CHIP_CAICOS:
2743                 num_ps_threads = 96;
2744                 num_vs_threads = 10;
2745                 num_gs_threads = 10;
2746                 num_es_threads = 10;
2747                 num_hs_threads = 10;
2748                 num_ls_threads = 10;
2749                 num_ps_stack_entries = 42;
2750                 num_vs_stack_entries = 42;
2751                 num_gs_stack_entries = 42;
2752                 num_es_stack_entries = 42;
2753                 num_hs_stack_entries = 42;
2754                 num_ls_stack_entries = 42;
2755                 break;
2756         }
2757
2758         tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2759         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2760         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2761         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2762
2763         r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2764         r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2765
2766         tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2767         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2768         r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2769
2770         tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2771         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2772         r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2773
2774         tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2775         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2776         r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2777
2778         tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2779         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2780         r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2781
2782         r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2783                               S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2784
2785         /* remove LS/HS from one SIMD for hw workaround */
2786         r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2787         r600_store_value(cb, 0xffffffff);
2788         r600_store_value(cb, 0xffffffff);
2789         r600_store_value(cb, 0xfffffffe);
2790
2791         r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2792         r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2793
2794         r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2795         r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2796         r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2797         r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2798         r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2799         r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2800         r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2801
2802         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2803         r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2804         r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2805         r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2806         r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2807
2808         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2809         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2810         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2811         r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2812         r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2813         r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2814         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2815         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2816         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2817         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2818         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2819         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2820         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2821         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2822
2823         r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2824
2825         r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2826
2827         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2828         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2829         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2830
2831         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2832
2833         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2834
2835         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2836         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2837         r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2838
2839         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2840         for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2841                 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2842                 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2843         }
2844
2845         r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2846         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2847
2848         r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2849         r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2850         r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2851         r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2852
2853         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2854         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2855         r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2856
2857         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2858         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2859         r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2860
2861         r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2862         r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2863         r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2864         r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2865         r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2866         r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2867         r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2868
2869         /* to avoid GPU doing any preloading of constant from random address */
2870         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2871         for (i = 0; i < 16; i++)
2872                 r600_store_value(cb, 0);
2873
2874         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2875         for (i = 0; i < 16; i++)
2876                 r600_store_value(cb, 0);
2877
2878         r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2879         for (i = 0; i < 16; i++)
2880                 r600_store_value(cb, 0);
2881
2882         r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2883         for (i = 0; i < 16; i++)
2884                 r600_store_value(cb, 0);
2885
2886         r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2887         for (i = 0; i < 16; i++)
2888                 r600_store_value(cb, 0);
2889
2890         r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2891
2892         if (rctx->screen->b.has_streamout) {
2893                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2894         }
2895
2896         r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2897         r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2898         r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2899         r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2900         r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2901         r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2902
2903         r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2904         r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2905         r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2906
2907         if (rctx->b.family == CHIP_CAICOS) {
2908                 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2909                 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2910                 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2911                 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2912         } else {
2913                 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2914                 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2915                 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2916                 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2917                 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2918                 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2919                 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2920                 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2921         }
2922
2923         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2924         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2925         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2926         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2927         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2928 }
2929
2930 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2931 {
2932         struct r600_context *rctx = (struct r600_context *)ctx;
2933         struct r600_command_buffer *cb = &shader->command_buffer;
2934         struct r600_shader *rshader = &shader->shader;
2935         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2936         int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2937         int ninterp = 0;
2938         boolean have_perspective = FALSE, have_linear = FALSE;
2939         static const unsigned spi_baryc_enable_bit[6] = {
2940                 S_0286E0_PERSP_SAMPLE_ENA(1),
2941                 S_0286E0_PERSP_CENTER_ENA(1),
2942                 S_0286E0_PERSP_CENTROID_ENA(1),
2943                 S_0286E0_LINEAR_SAMPLE_ENA(1),
2944                 S_0286E0_LINEAR_CENTER_ENA(1),
2945                 S_0286E0_LINEAR_CENTROID_ENA(1)
2946         };
2947         unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2948         unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2949         unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2950         uint32_t spi_ps_input_cntl[32];
2951
2952         if (!cb->buf) {
2953                 r600_init_command_buffer(cb, 64);
2954         } else {
2955                 cb->num_dw = 0;
2956         }
2957
2958         for (i = 0; i < rshader->ninput; i++) {
2959                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2960                    POSITION goes via GPRs from the SC so isn't counted */
2961                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2962                         pos_index = i;
2963                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2964                         if (face_index == -1)
2965                                 face_index = i;
2966                 }
2967                 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2968                         if (face_index == -1)
2969                                 face_index = i; /* lives in same register, same enable bit */
2970                 }
2971                 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
2972                         fixed_pt_position_index = i;
2973                 }
2974                 else {
2975                         ninterp++;
2976                         int k = eg_get_interpolator_index(
2977                                 rshader->input[i].interpolate,
2978                                 rshader->input[i].interpolate_location);
2979                         if (k >= 0) {
2980                                 spi_baryc_cntl |= spi_baryc_enable_bit[k];
2981                                 have_perspective |= k < 3;
2982                                 have_linear |= !(k < 3);
2983                         }
2984                 }
2985
2986                 sid = rshader->input[i].spi_sid;
2987
2988                 if (sid) {
2989                         tmp = S_028644_SEMANTIC(sid);
2990
2991                         if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2992                                 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2993                                 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2994                                         rctx->rasterizer && rctx->rasterizer->flatshade)) {
2995                                 tmp |= S_028644_FLAT_SHADE(1);
2996                         }
2997
2998                         if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2999                             (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3000                                 tmp |= S_028644_PT_SPRITE_TEX(1);
3001                         }
3002
3003                         spi_ps_input_cntl[num++] = tmp;
3004                 }
3005         }
3006
3007         r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3008         r600_store_array(cb, num, spi_ps_input_cntl);
3009
3010         for (i = 0; i < rshader->noutput; i++) {
3011                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3012                         z_export = 1;
3013                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3014                         stencil_export = 1;
3015                 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3016                         rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3017                         mask_export = 1;
3018         }
3019         if (rshader->uses_kill)
3020                 db_shader_control |= S_02880C_KILL_ENABLE(1);
3021
3022         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3023         db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3024         db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3025
3026         switch (rshader->ps_conservative_z) {
3027         default: /* fall through */
3028         case TGSI_FS_DEPTH_LAYOUT_ANY:
3029                 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3030                 break;
3031         case TGSI_FS_DEPTH_LAYOUT_GREATER:
3032                 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3033                 break;
3034         case TGSI_FS_DEPTH_LAYOUT_LESS:
3035                 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3036                 break;
3037         }
3038
3039         exports_ps = 0;
3040         for (i = 0; i < rshader->noutput; i++) {
3041                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3042                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3043                     rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3044                         exports_ps |= 1;
3045         }
3046
3047         num_cout = rshader->nr_ps_color_exports;
3048
3049         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3050         if (!exports_ps) {
3051                 /* always at least export 1 component per pixel */
3052                 exports_ps = 2;
3053         }
3054         shader->nr_ps_color_outputs = num_cout;
3055         if (ninterp == 0) {
3056                 ninterp = 1;
3057                 have_perspective = TRUE;
3058         }
3059         if (!spi_baryc_cntl)
3060                 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3061
3062         if (!have_perspective && !have_linear)
3063                 have_perspective = TRUE;
3064
3065         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3066                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3067                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3068         spi_input_z = 0;
3069         if (pos_index != -1) {
3070                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
3071                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3072                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3073                 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3074         }
3075
3076         spi_ps_in_control_1 = 0;
3077         if (face_index != -1) {
3078                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3079                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3080         }
3081         if (fixed_pt_position_index != -1) {
3082                 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3083                         S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3084         }
3085
3086         r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3087         r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3088         r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3089
3090         r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3091         r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3092         r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3093
3094         r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3095         r600_store_value(cb, shader->bo->gpu_address >> 8);
3096         r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3097                          S_028844_NUM_GPRS(rshader->bc.ngpr) |
3098                          S_028844_PRIME_CACHE_ON_DRAW(1) |
3099                          S_028844_STACK_SIZE(rshader->bc.nstack));
3100         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3101
3102         shader->db_shader_control = db_shader_control;
3103         shader->ps_depth_export = z_export | stencil_export | mask_export;
3104
3105         shader->sprite_coord_enable = sprite_coord_enable;
3106         if (rctx->rasterizer)
3107                 shader->flatshade = rctx->rasterizer->flatshade;
3108 }
3109
3110 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3111 {
3112         struct r600_command_buffer *cb = &shader->command_buffer;
3113         struct r600_shader *rshader = &shader->shader;
3114
3115         r600_init_command_buffer(cb, 32);
3116
3117         r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3118                                S_028890_NUM_GPRS(rshader->bc.ngpr) |
3119                                S_028890_STACK_SIZE(rshader->bc.nstack));
3120         r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3121                                shader->bo->gpu_address >> 8);
3122         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3123 }
3124
3125 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3126 {
3127         struct r600_context *rctx = (struct r600_context *)ctx;
3128         struct r600_command_buffer *cb = &shader->command_buffer;
3129         struct r600_shader *rshader = &shader->shader;
3130         struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3131         unsigned gsvs_itemsizes[4] = {
3132                         (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3133                         (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3134                         (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3135                         (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3136         };
3137
3138         r600_init_command_buffer(cb, 64);
3139
3140         /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3141
3142
3143         r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3144                                S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3145         r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3146                                r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3147
3148         if (rctx->screen->b.info.drm_minor >= 35) {
3149                 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3150                                 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3151                                 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3152         }
3153         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3154         r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3155         r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3156         r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3157         r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3158
3159         r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3160                                (rshader->ring_item_sizes[0]) >> 2);
3161
3162         r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3163                                gsvs_itemsizes[0] +
3164                                gsvs_itemsizes[1] +
3165                                gsvs_itemsizes[2] +
3166                                gsvs_itemsizes[3]);
3167
3168         r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3169         r600_store_value(cb, gsvs_itemsizes[0]);
3170         r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3171         r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3172
3173         /* FIXME calculate these values somehow ??? */
3174         r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3175         r600_store_value(cb, 0x80); /* GS_PER_ES */
3176         r600_store_value(cb, 0x100); /* ES_PER_GS */
3177         r600_store_value(cb, 0x2); /* GS_PER_VS */
3178
3179         r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3180                                S_028878_NUM_GPRS(rshader->bc.ngpr) |
3181                                S_028878_STACK_SIZE(rshader->bc.nstack));
3182         r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3183                                shader->bo->gpu_address >> 8);
3184         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3185 }
3186
3187
3188 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3189 {
3190         struct r600_command_buffer *cb = &shader->command_buffer;
3191         struct r600_shader *rshader = &shader->shader;
3192         unsigned spi_vs_out_id[10] = {};
3193         unsigned i, tmp, nparams = 0;
3194
3195         for (i = 0; i < rshader->noutput; i++) {
3196                 if (rshader->output[i].spi_sid) {
3197                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3198                         spi_vs_out_id[nparams / 4] |= tmp;
3199                         nparams++;
3200                 }
3201         }
3202
3203         r600_init_command_buffer(cb, 32);
3204
3205         r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3206         for (i = 0; i < 10; i++) {
3207                 r600_store_value(cb, spi_vs_out_id[i]);
3208         }
3209
3210         /* Certain attributes (position, psize, etc.) don't count as params.
3211          * VS is required to export at least one param and r600_shader_from_tgsi()
3212          * takes care of adding a dummy export.
3213          */
3214         if (nparams < 1)
3215                 nparams = 1;
3216
3217         r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3218                                S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3219         r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3220                                S_028860_NUM_GPRS(rshader->bc.ngpr) |
3221                                S_028860_STACK_SIZE(rshader->bc.nstack));
3222         if (rshader->vs_position_window_space) {
3223                 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3224                         S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3225         } else {
3226                 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3227                         S_028818_VTX_W0_FMT(1) |
3228                         S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3229                         S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3230                         S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3231
3232         }
3233         r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3234                                shader->bo->gpu_address >> 8);
3235         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3236
3237         shader->pa_cl_vs_out_cntl =
3238                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3239                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3240                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3241                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3242                 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3243                 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3244                 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3245 }
3246
3247 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3248 {
3249         struct r600_command_buffer *cb = &shader->command_buffer;
3250         struct r600_shader *rshader = &shader->shader;
3251
3252         r600_init_command_buffer(cb, 32);
3253         r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3254                                S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3255                                S_0288BC_STACK_SIZE(rshader->bc.nstack));
3256         r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3257                                shader->bo->gpu_address >> 8);
3258 }
3259
3260 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3261 {
3262         struct r600_command_buffer *cb = &shader->command_buffer;
3263         struct r600_shader *rshader = &shader->shader;
3264
3265         r600_init_command_buffer(cb, 32);
3266         r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3267                                S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3268                                S_0288D4_STACK_SIZE(rshader->bc.nstack));
3269         r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3270                                shader->bo->gpu_address >> 8);
3271 }
3272 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3273 {
3274         struct pipe_blend_state blend;
3275
3276         memset(&blend, 0, sizeof(blend));
3277         blend.independent_blend_enable = true;
3278         blend.rt[0].colormask = 0xf;
3279         return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3280 }
3281
3282 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3283 {
3284         struct pipe_blend_state blend;
3285         unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3286                         V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3287
3288         memset(&blend, 0, sizeof(blend));
3289         blend.independent_blend_enable = true;
3290         blend.rt[0].colormask = 0xf;
3291         return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3292 }
3293
3294 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3295 {
3296         struct pipe_blend_state blend;
3297         unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3298
3299         memset(&blend, 0, sizeof(blend));
3300         blend.independent_blend_enable = true;
3301         blend.rt[0].colormask = 0xf;
3302         return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3303 }
3304
3305 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3306 {
3307         struct pipe_depth_stencil_alpha_state dsa = {{0}};
3308
3309         return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3310 }
3311
3312 void evergreen_update_db_shader_control(struct r600_context * rctx)
3313 {
3314         bool dual_export;
3315         unsigned db_shader_control;
3316
3317         if (!rctx->ps_shader) {
3318                 return;
3319         }
3320
3321         dual_export = rctx->framebuffer.export_16bpc &&
3322                       !rctx->ps_shader->current->ps_depth_export;
3323
3324         db_shader_control = rctx->ps_shader->current->db_shader_control |
3325                             S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3326                             S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3327                                                                     V_02880C_EXPORT_DB_FULL) |
3328                             S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3329
3330         /* When alpha test is enabled we can't trust the hw to make the proper
3331          * decision on the order in which ztest should be run related to fragment
3332          * shader execution.
3333          *
3334          * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3335          * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3336          * execution and thus after alpha test so if discarded by the alpha test
3337          * the z value is not written.
3338          * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3339          * get a hang unless you flush the DB in between.  For now just use
3340          * LATE_Z.
3341          */
3342         if (rctx->alphatest_state.sx_alpha_test_control) {
3343                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3344         } else {
3345                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3346         }
3347
3348         if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3349                 rctx->db_misc_state.db_shader_control = db_shader_control;
3350                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3351         }
3352 }
3353
3354 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3355                                 struct pipe_resource *dst,
3356                                 unsigned dst_level,
3357                                 unsigned dst_x,
3358                                 unsigned dst_y,
3359                                 unsigned dst_z,
3360                                 struct pipe_resource *src,
3361                                 unsigned src_level,
3362                                 unsigned src_x,
3363                                 unsigned src_y,
3364                                 unsigned src_z,
3365                                 unsigned copy_height,
3366                                 unsigned pitch,
3367                                 unsigned bpp)
3368 {
3369         struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3370         struct r600_texture *rsrc = (struct r600_texture*)src;
3371         struct r600_texture *rdst = (struct r600_texture*)dst;
3372         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3373         unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3374         unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3375         uint64_t base, addr;
3376
3377         dst_mode = rdst->surface.level[dst_level].mode;
3378         src_mode = rsrc->surface.level[src_level].mode;
3379         assert(dst_mode != src_mode);
3380
3381         /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3382         if (util_format_has_depth(util_format_description(src->format)))
3383                 non_disp_tiling = 1;
3384
3385         y = 0;
3386         sub_cmd = EG_DMA_COPY_TILED;
3387         lbpp = util_logbase2(bpp);
3388         pitch_tile_max = ((pitch / bpp) / 8) - 1;
3389         nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3390
3391         if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3392                 /* T2L */
3393                 array_mode = evergreen_array_mode(src_mode);
3394                 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3395                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3396                 /* linear height must be the same as the slice tile max height, it's ok even
3397                  * if the linear destination/source have smaller heigh as the size of the
3398                  * dma packet will be using the copy_height which is always smaller or equal
3399                  * to the linear height
3400                  */
3401                 height = rsrc->surface.level[src_level].npix_y;
3402                 detile = 1;
3403                 x = src_x;
3404                 y = src_y;
3405                 z = src_z;
3406                 base = rsrc->surface.level[src_level].offset;
3407                 addr = rdst->surface.level[dst_level].offset;
3408                 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3409                 addr += dst_y * pitch + dst_x * bpp;
3410                 bank_h = eg_bank_wh(rsrc->surface.bankh);
3411                 bank_w = eg_bank_wh(rsrc->surface.bankw);
3412                 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3413                 tile_split = eg_tile_split(rsrc->surface.tile_split);
3414                 base += rsrc->resource.gpu_address;
3415                 addr += rdst->resource.gpu_address;
3416         } else {
3417                 /* L2T */
3418                 array_mode = evergreen_array_mode(dst_mode);
3419                 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3420                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3421                 /* linear height must be the same as the slice tile max height, it's ok even
3422                  * if the linear destination/source have smaller heigh as the size of the
3423                  * dma packet will be using the copy_height which is always smaller or equal
3424                  * to the linear height
3425                  */
3426                 height = rdst->surface.level[dst_level].npix_y;
3427                 detile = 0;
3428                 x = dst_x;
3429                 y = dst_y;
3430                 z = dst_z;
3431                 base = rdst->surface.level[dst_level].offset;
3432                 addr = rsrc->surface.level[src_level].offset;
3433                 addr += rsrc->surface.level[src_level].slice_size * src_z;
3434                 addr += src_y * pitch + src_x * bpp;
3435                 bank_h = eg_bank_wh(rdst->surface.bankh);
3436                 bank_w = eg_bank_wh(rdst->surface.bankw);
3437                 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3438                 tile_split = eg_tile_split(rdst->surface.tile_split);
3439                 base += rdst->resource.gpu_address;
3440                 addr += rsrc->resource.gpu_address;
3441         }
3442
3443         size = (copy_height * pitch) / 4;
3444         ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3445         r600_need_dma_space(&rctx->b, ncopy * 9);
3446
3447         for (i = 0; i < ncopy; i++) {
3448                 cheight = copy_height;
3449                 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3450                         cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3451                 }
3452                 size = (cheight * pitch) / 4;
3453                 /* emit reloc before writing cs so that cs is always in consistent state */
3454                 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3455                                       RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3456                 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3457                                       RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3458                 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3459                 cs->buf[cs->cdw++] = base >> 8;
3460                 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3461                                         (lbpp << 24) | (bank_h << 21) |
3462                                         (bank_w << 18) | (mt_aspect << 16);
3463                 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3464                 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3465                 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3466                 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3467                 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3468                 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3469                 copy_height -= cheight;
3470                 addr += cheight * pitch;
3471                 y += cheight;
3472         }
3473 }
3474
3475 static void evergreen_dma_copy(struct pipe_context *ctx,
3476                                struct pipe_resource *dst,
3477                                unsigned dst_level,
3478                                unsigned dstx, unsigned dsty, unsigned dstz,
3479                                struct pipe_resource *src,
3480                                unsigned src_level,
3481                                const struct pipe_box *src_box)
3482 {
3483         struct r600_context *rctx = (struct r600_context *)ctx;
3484         struct r600_texture *rsrc = (struct r600_texture*)src;
3485         struct r600_texture *rdst = (struct r600_texture*)dst;
3486         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3487         unsigned src_w, dst_w;
3488         unsigned src_x, src_y;
3489         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3490
3491         if (rctx->b.dma.cs == NULL) {
3492                 goto fallback;
3493         }
3494
3495         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3496                 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3497                 return;
3498         }
3499
3500         if (src->format != dst->format || src_box->depth > 1 ||
3501             (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3502                 goto fallback;
3503         }
3504
3505         if (rsrc->dirty_level_mask & (1 << src_level)) {
3506                 ctx->flush_resource(ctx, src);
3507         }
3508
3509         src_x = util_format_get_nblocksx(src->format, src_box->x);
3510         dst_x = util_format_get_nblocksx(src->format, dst_x);
3511         src_y = util_format_get_nblocksy(src->format, src_box->y);
3512         dst_y = util_format_get_nblocksy(src->format, dst_y);
3513
3514         bpp = rdst->surface.bpe;
3515         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3516         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3517         src_w = rsrc->surface.level[src_level].npix_x;
3518         dst_w = rdst->surface.level[dst_level].npix_x;
3519         copy_height = src_box->height / rsrc->surface.blk_h;
3520
3521         dst_mode = rdst->surface.level[dst_level].mode;
3522         src_mode = rsrc->surface.level[src_level].mode;
3523
3524         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3525                 /* FIXME evergreen can do partial blit */
3526                 goto fallback;
3527         }
3528         /* the x test here are currently useless (because we don't support partial blit)
3529          * but keep them around so we don't forget about those
3530          */
3531         if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3532                 goto fallback;
3533         }
3534
3535         /* 128 bpp surfaces require non_disp_tiling for both
3536          * tiled and linear buffers on cayman.  However, async
3537          * DMA only supports it on the tiled side.  As such
3538          * the tile order is backwards after a L2T/T2L packet.
3539          */
3540         if ((rctx->b.chip_class == CAYMAN) &&
3541             (src_mode != dst_mode) &&
3542             (util_format_get_blocksize(src->format) >= 16)) {
3543                 goto fallback;
3544         }
3545
3546         if (src_mode == dst_mode) {
3547                 uint64_t dst_offset, src_offset;
3548                 /* simple dma blit would do NOTE code here assume :
3549                  *   src_box.x/y == 0
3550                  *   dst_x/y == 0
3551                  *   dst_pitch == src_pitch
3552                  */
3553                 src_offset= rsrc->surface.level[src_level].offset;
3554                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3555                 src_offset += src_y * src_pitch + src_x * bpp;
3556                 dst_offset = rdst->surface.level[dst_level].offset;
3557                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3558                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3559                 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3560                                         src_box->height * src_pitch);
3561         } else {
3562                 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3563                                         src, src_level, src_x, src_y, src_box->z,
3564                                         copy_height, dst_pitch, bpp);
3565         }
3566         return;
3567
3568 fallback:
3569         r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3570                                   src, src_level, src_box);
3571 }
3572
3573 static void evergreen_set_tess_state(struct pipe_context *ctx,
3574                                      const float default_outer_level[4],
3575                                      const float default_inner_level[2])
3576 {
3577         struct r600_context *rctx = (struct r600_context *)ctx;
3578
3579         memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3580         memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3581         rctx->tess_state_dirty = true;
3582 }
3583
3584 void evergreen_init_state_functions(struct r600_context *rctx)
3585 {
3586         unsigned id = 1;
3587         unsigned i;
3588         /* !!!
3589          *  To avoid GPU lockup registers must be emitted in a specific order
3590          * (no kidding ...). The order below is important and have been
3591          * partially inferred from analyzing fglrx command stream.
3592          *
3593          * Don't reorder atom without carefully checking the effect (GPU lockup
3594          * or piglit regression).
3595          * !!!
3596          */
3597         if (rctx->b.chip_class == EVERGREEN) {
3598                 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3599                 rctx->config_state.dyn_gpr_enabled = true;
3600         }
3601         r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3602         /* shader const */
3603         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3604         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3605         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3606         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3607         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3608         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3609         /* shader program */
3610         r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3611         /* sampler */
3612         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3613         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3614         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3615         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3616         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3617         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3618         /* resources */
3619         r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3620         r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3621         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3622         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3623         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3624         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3625         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3626         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3627
3628         r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3629
3630         if (rctx->b.chip_class == EVERGREEN) {
3631                 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3632         } else {
3633                 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3634         }
3635         rctx->sample_mask.sample_mask = ~0;
3636
3637         r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3638         r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3639         r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3640         r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3641         r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3642         r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3643         r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3644         r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3645         r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3646         r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3647         r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3648         r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3649         r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3650         r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3651         r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3652         r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3653         r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3654         r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3655         for (i = 0; i < EG_NUM_HW_STAGES; i++)
3656                 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3657         r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3658         r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3659
3660         rctx->b.b.create_blend_state = evergreen_create_blend_state;
3661         rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3662         rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3663         rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3664         rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3665         rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3666         rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3667         rctx->b.b.set_min_samples = evergreen_set_min_samples;
3668         rctx->b.b.set_tess_state = evergreen_set_tess_state;
3669         if (rctx->b.chip_class == EVERGREEN)
3670                 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3671         else
3672                 rctx->b.b.get_sample_position = cayman_get_sample_position;
3673         rctx->b.dma_copy = evergreen_dma_copy;
3674
3675         evergreen_init_compute_state_functions(rctx);
3676 }
3677
3678 /**
3679  * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3680  *
3681  * The information about LDS and other non-compile-time parameters is then
3682  * written to the const buffer.
3683
3684  * const buffer contains -
3685  * uint32_t input_patch_size
3686  * uint32_t input_vertex_size
3687  * uint32_t num_tcs_input_cp
3688  * uint32_t num_tcs_output_cp;
3689  * uint32_t output_patch_size
3690  * uint32_t output_vertex_size
3691  * uint32_t output_patch0_offset
3692  * uint32_t perpatch_output_offset
3693  * and the same constbuf is bound to LS/HS/VS(ES).
3694  */
3695 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3696 {
3697         struct pipe_constant_buffer constbuf = {0};
3698         struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3699         struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3700         unsigned num_tcs_input_cp = info->vertices_per_patch;
3701         unsigned num_tcs_outputs;
3702         unsigned num_tcs_output_cp;
3703         unsigned num_tcs_patch_outputs;
3704         unsigned num_tcs_inputs;
3705         unsigned input_vertex_size, output_vertex_size;
3706         unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3707         unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3708         uint32_t values[16];
3709         unsigned num_waves;
3710         unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3711         unsigned wave_divisor = (16 * num_pipes);
3712
3713         *num_patches = 1;
3714
3715         if (!rctx->tes_shader) {
3716                 rctx->lds_alloc = 0;
3717                 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3718                                               R600_LDS_INFO_CONST_BUFFER, NULL);
3719                 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3720                                               R600_LDS_INFO_CONST_BUFFER, NULL);
3721                 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3722                                               R600_LDS_INFO_CONST_BUFFER, NULL);
3723                 return;
3724         }
3725
3726         if (rctx->lds_alloc != 0 &&
3727             rctx->last_ls == ls &&
3728             !rctx->tess_state_dirty &&
3729             rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3730             rctx->last_tcs == tcs)
3731                 return;
3732
3733         num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3734
3735         if (rctx->tcs_shader) {
3736                 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3737                 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3738                 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3739         } else {
3740                 num_tcs_outputs = num_tcs_inputs;
3741                 num_tcs_output_cp = num_tcs_input_cp;
3742                 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3743         }
3744
3745         /* size in bytes */
3746         input_vertex_size = num_tcs_inputs * 16;
3747         output_vertex_size = num_tcs_outputs * 16;
3748
3749         input_patch_size = num_tcs_input_cp * input_vertex_size;
3750
3751         pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3752         output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3753
3754         output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3755         perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3756
3757         lds_size = output_patch0_offset + output_patch_size * *num_patches;
3758
3759         values[0] = input_patch_size;
3760         values[1] = input_vertex_size;
3761         values[2] = num_tcs_input_cp;
3762         values[3] = num_tcs_output_cp;
3763
3764         values[4] = output_patch_size;
3765         values[5] = output_vertex_size;
3766         values[6] = output_patch0_offset;
3767         values[7] = perpatch_output_offset;
3768
3769         /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3770            LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3771         num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3772
3773         rctx->lds_alloc = (lds_size | (num_waves << 14));
3774
3775         memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3776         values[14] = 0;
3777         values[15] = 0;
3778
3779         rctx->tess_state_dirty = false;
3780         rctx->last_ls = ls;
3781         rctx->last_tcs = tcs;
3782         rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3783
3784         constbuf.user_buffer = values;
3785         constbuf.buffer_size = 16 * 4;
3786
3787         rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3788                                       R600_LDS_INFO_CONST_BUFFER, &constbuf);
3789         rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3790                                       R600_LDS_INFO_CONST_BUFFER, &constbuf);
3791         rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3792                                       R600_LDS_INFO_CONST_BUFFER, &constbuf);
3793         pipe_resource_reference(&constbuf.buffer, NULL);
3794 }
3795
3796 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3797                                     const struct pipe_draw_info *info,
3798                                     unsigned num_patches)
3799 {
3800         unsigned num_output_cp;
3801
3802         if (!rctx->tes_shader)
3803                 return 0;
3804
3805         num_output_cp = rctx->tcs_shader ?
3806                 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3807                 info->vertices_per_patch;
3808
3809         return S_028B58_NUM_PATCHES(num_patches) |
3810                 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3811                 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3812 }
3813
3814 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3815                                 struct radeon_winsys_cs *cs,
3816                                 uint32_t ls_hs_config)
3817 {
3818         radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3819 }
3820
3821 void evergreen_set_lds_alloc(struct r600_context *rctx,
3822                              struct radeon_winsys_cs *cs,
3823                              uint32_t lds_alloc)
3824 {
3825         radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3826 }
3827
3828 /* on evergreen if you are running tessellation you need to disable dynamic
3829    GPRs to workaround a hardware bug.*/
3830 bool evergreen_adjust_gprs(struct r600_context *rctx)
3831 {
3832         unsigned num_gprs[EG_NUM_HW_STAGES];
3833         unsigned def_gprs[EG_NUM_HW_STAGES];
3834         unsigned cur_gprs[EG_NUM_HW_STAGES];
3835         unsigned new_gprs[EG_NUM_HW_STAGES];
3836         unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3837         unsigned max_gprs;
3838         unsigned i;
3839         unsigned total_gprs;
3840         unsigned tmp[3];
3841         bool rework = false, set_default = false, set_dirty = false;
3842         max_gprs = 0;
3843         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3844                 def_gprs[i] = rctx->default_gprs[i];
3845                 max_gprs += def_gprs[i];
3846         }
3847         max_gprs += def_num_clause_temp_gprs * 2;
3848
3849         /* if we have no TESS and dyn gpr is enabled then do nothing. */
3850         if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3851                 if (rctx->config_state.dyn_gpr_enabled)
3852                         return true;
3853
3854                 /* transition back to dyn gpr enabled state */
3855                 rctx->config_state.dyn_gpr_enabled = true;
3856                 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3857                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3858                 return true;
3859         }
3860
3861
3862         /* gather required shader gprs */
3863         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3864                 if (rctx->hw_shader_stages[i].shader)
3865                         num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3866                 else
3867                         num_gprs[i] = 0;
3868         }
3869
3870         cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3871         cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3872         cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3873         cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3874         cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3875         cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3876
3877         total_gprs = 0;
3878         for (i = 0; i < EG_NUM_HW_STAGES; i++)  {
3879                 new_gprs[i] = num_gprs[i];
3880                 total_gprs += num_gprs[i];
3881         }
3882
3883         if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3884                 return false;
3885
3886         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3887                 if (new_gprs[i] > cur_gprs[i]) {
3888                         rework = true;
3889                         break;
3890                 }
3891         }
3892
3893         if (rctx->config_state.dyn_gpr_enabled) {
3894                 set_dirty = true;
3895                 rctx->config_state.dyn_gpr_enabled = false;
3896         }
3897
3898         if (rework) {
3899                 set_default = true;
3900                 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3901                         if (new_gprs[i] > def_gprs[i])
3902                                 set_default = false;
3903                 }
3904
3905                 if (set_default) {
3906                         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3907                                 new_gprs[i] = def_gprs[i];
3908                         }
3909                 } else {
3910                         unsigned ps_value = max_gprs;
3911
3912                         ps_value -= (def_num_clause_temp_gprs * 2);
3913                         for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3914                                 ps_value -= new_gprs[i];
3915
3916                         new_gprs[R600_HW_STAGE_PS] = ps_value;
3917                 }
3918
3919                 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3920                         S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3921                         S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3922
3923                 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3924                         S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3925
3926                 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3927                         S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3928
3929                 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3930                     rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3931                     rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3932                         rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3933                         rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3934                         rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3935                         set_dirty = true;
3936                 }
3937         }
3938
3939
3940         if (set_dirty) {
3941                 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3942                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3943         }
3944         return true;
3945 }