src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_formats.h"
  24 #include "r600_shader.h"
  25 #include "evergreend.h"
  26
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_framebuffer.h"
  31 #include "util/u_dual_blend.h"
  32 #include "evergreen_compute.h"
  33
  34 static uint32_t eg_num_banks(uint32_t nbanks)
  35 {
  36         switch (nbanks) {
  37         case 2:
  38                 return 0;
  39         case 4:
  40                 return 1;
  41         case 8:
  42         default:
  43                 return 2;
  44         case 16:
  45                 return 3;
  46         }
  47 }
  48
  49
  50 static unsigned eg_tile_split(unsigned tile_split)
  51 {
  52         switch (tile_split) {
  53         case 64:        tile_split = 0; break;
  54         case 128:       tile_split = 1; break;
  55         case 256:       tile_split = 2; break;
  56         case 512:       tile_split = 3; break;
  57         default:
  58         case 1024:      tile_split = 4; break;
  59         case 2048:      tile_split = 5; break;
  60         case 4096:      tile_split = 6; break;
  61         }
  62         return tile_split;
  63 }
  64
  65 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
  66 {
  67         switch (macro_tile_aspect) {
  68         default:
  69         case 1: macro_tile_aspect = 0;  break;
  70         case 2: macro_tile_aspect = 1;  break;
  71         case 4: macro_tile_aspect = 2;  break;
  72         case 8: macro_tile_aspect = 3;  break;
  73         }
  74         return macro_tile_aspect;
  75 }
  76
  77 static unsigned eg_bank_wh(unsigned bankwh)
  78 {
  79         switch (bankwh) {
  80         default:
  81         case 1: bankwh = 0;     break;
  82         case 2: bankwh = 1;     break;
  83         case 4: bankwh = 2;     break;
  84         case 8: bankwh = 3;     break;
  85         }
  86         return bankwh;
  87 }
  88
  89 static uint32_t r600_translate_blend_function(int blend_func)
  90 {
  91         switch (blend_func) {
  92         case PIPE_BLEND_ADD:
  93                 return V_028780_COMB_DST_PLUS_SRC;
  94         case PIPE_BLEND_SUBTRACT:
  95                 return V_028780_COMB_SRC_MINUS_DST;
  96         case PIPE_BLEND_REVERSE_SUBTRACT:
  97                 return V_028780_COMB_DST_MINUS_SRC;
  98         case PIPE_BLEND_MIN:
  99                 return V_028780_COMB_MIN_DST_SRC;
 100         case PIPE_BLEND_MAX:
 101                 return V_028780_COMB_MAX_DST_SRC;
 102         default:
 103                 R600_ERR("Unknown blend function %d\n", blend_func);
 104                 assert(0);
 105                 break;
 106         }
 107         return 0;
 108 }
 109
 110 static uint32_t r600_translate_blend_factor(int blend_fact)
 111 {
 112         switch (blend_fact) {
 113         case PIPE_BLENDFACTOR_ONE:
 114                 return V_028780_BLEND_ONE;
 115         case PIPE_BLENDFACTOR_SRC_COLOR:
 116                 return V_028780_BLEND_SRC_COLOR;
 117         case PIPE_BLENDFACTOR_SRC_ALPHA:
 118                 return V_028780_BLEND_SRC_ALPHA;
 119         case PIPE_BLENDFACTOR_DST_ALPHA:
 120                 return V_028780_BLEND_DST_ALPHA;
 121         case PIPE_BLENDFACTOR_DST_COLOR:
 122                 return V_028780_BLEND_DST_COLOR;
 123         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 124                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 125         case PIPE_BLENDFACTOR_CONST_COLOR:
 126                 return V_028780_BLEND_CONST_COLOR;
 127         case PIPE_BLENDFACTOR_CONST_ALPHA:
 128                 return V_028780_BLEND_CONST_ALPHA;
 129         case PIPE_BLENDFACTOR_ZERO:
 130                 return V_028780_BLEND_ZERO;
 131         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 132                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 133         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 134                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 135         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 136                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 137         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 138                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 139         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 140                 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
 141         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 142                 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
 143         case PIPE_BLENDFACTOR_SRC1_COLOR:
 144                 return V_028780_BLEND_SRC1_COLOR;
 145         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 146                 return V_028780_BLEND_SRC1_ALPHA;
 147         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 148                 return V_028780_BLEND_INV_SRC1_COLOR;
 149         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 150                 return V_028780_BLEND_INV_SRC1_ALPHA;
 151         default:
 152                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 153                 assert(0);
 154                 break;
 155         }
 156         return 0;
 157 }
 158
 159 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
 160 {
 161         switch (dim) {
 162         default:
 163         case PIPE_TEXTURE_1D:
 164                 return V_030000_SQ_TEX_DIM_1D;
 165         case PIPE_TEXTURE_1D_ARRAY:
 166                 return V_030000_SQ_TEX_DIM_1D_ARRAY;
 167         case PIPE_TEXTURE_2D:
 168         case PIPE_TEXTURE_RECT:
 169                 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
 170                                         V_030000_SQ_TEX_DIM_2D;
 171         case PIPE_TEXTURE_2D_ARRAY:
 172                 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
 173                                         V_030000_SQ_TEX_DIM_2D_ARRAY;
 174         case PIPE_TEXTURE_3D:
 175                 return V_030000_SQ_TEX_DIM_3D;
 176         case PIPE_TEXTURE_CUBE:
 177         case PIPE_TEXTURE_CUBE_ARRAY:
 178                 return V_030000_SQ_TEX_DIM_CUBEMAP;
 179         }
 180 }
 181
 182 static uint32_t r600_translate_dbformat(enum pipe_format format)
 183 {
 184         switch (format) {
 185         case PIPE_FORMAT_Z16_UNORM:
 186                 return V_028040_Z_16;
 187         case PIPE_FORMAT_Z24X8_UNORM:
 188         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 189                 return V_028040_Z_24;
 190         case PIPE_FORMAT_Z32_FLOAT:
 191         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 192                 return V_028040_Z_32_FLOAT;
 193         default:
 194                 return ~0U;
 195         }
 196 }
 197
 198 static uint32_t r600_translate_colorswap(enum pipe_format format)
 199 {
 200         switch (format) {
 201         /* 8-bit buffers. */
 202         case PIPE_FORMAT_L4A4_UNORM:
 203         case PIPE_FORMAT_A4R4_UNORM:
 204                 return V_028C70_SWAP_ALT;
 205
 206         case PIPE_FORMAT_A8_UNORM:
 207         case PIPE_FORMAT_A8_SNORM:
 208         case PIPE_FORMAT_A8_UINT:
 209         case PIPE_FORMAT_A8_SINT:
 210         case PIPE_FORMAT_A16_UNORM:
 211         case PIPE_FORMAT_A16_SNORM:
 212         case PIPE_FORMAT_A16_UINT:
 213         case PIPE_FORMAT_A16_SINT:
 214         case PIPE_FORMAT_A16_FLOAT:
 215         case PIPE_FORMAT_A32_UINT:
 216         case PIPE_FORMAT_A32_SINT:
 217         case PIPE_FORMAT_A32_FLOAT:
 218         case PIPE_FORMAT_R4A4_UNORM:
 219                 return V_028C70_SWAP_ALT_REV;
 220         case PIPE_FORMAT_I8_UNORM:
 221         case PIPE_FORMAT_I8_SNORM:
 222         case PIPE_FORMAT_I8_UINT:
 223         case PIPE_FORMAT_I8_SINT:
 224         case PIPE_FORMAT_I16_UNORM:
 225         case PIPE_FORMAT_I16_SNORM:
 226         case PIPE_FORMAT_I16_UINT:
 227         case PIPE_FORMAT_I16_SINT:
 228         case PIPE_FORMAT_I16_FLOAT:
 229         case PIPE_FORMAT_I32_UINT:
 230         case PIPE_FORMAT_I32_SINT:
 231         case PIPE_FORMAT_I32_FLOAT:
 232         case PIPE_FORMAT_L8_UNORM:
 233         case PIPE_FORMAT_L8_SNORM:
 234         case PIPE_FORMAT_L8_UINT:
 235         case PIPE_FORMAT_L8_SINT:
 236         case PIPE_FORMAT_L8_SRGB:
 237         case PIPE_FORMAT_L16_UNORM:
 238         case PIPE_FORMAT_L16_SNORM:
 239         case PIPE_FORMAT_L16_UINT:
 240         case PIPE_FORMAT_L16_SINT:
 241         case PIPE_FORMAT_L16_FLOAT:
 242         case PIPE_FORMAT_L32_UINT:
 243         case PIPE_FORMAT_L32_SINT:
 244         case PIPE_FORMAT_L32_FLOAT:
 245         case PIPE_FORMAT_R8_UNORM:
 246         case PIPE_FORMAT_R8_SNORM:
 247         case PIPE_FORMAT_R8_UINT:
 248         case PIPE_FORMAT_R8_SINT:
 249                 return V_028C70_SWAP_STD;
 250
 251         /* 16-bit buffers. */
 252         case PIPE_FORMAT_B5G6R5_UNORM:
 253                 return V_028C70_SWAP_STD_REV;
 254
 255         case PIPE_FORMAT_B5G5R5A1_UNORM:
 256         case PIPE_FORMAT_B5G5R5X1_UNORM:
 257                 return V_028C70_SWAP_ALT;
 258
 259         case PIPE_FORMAT_B4G4R4A4_UNORM:
 260         case PIPE_FORMAT_B4G4R4X4_UNORM:
 261                 return V_028C70_SWAP_ALT;
 262
 263         case PIPE_FORMAT_Z16_UNORM:
 264                 return V_028C70_SWAP_STD;
 265
 266         case PIPE_FORMAT_L8A8_UNORM:
 267         case PIPE_FORMAT_L8A8_SNORM:
 268         case PIPE_FORMAT_L8A8_UINT:
 269         case PIPE_FORMAT_L8A8_SINT:
 270         case PIPE_FORMAT_L8A8_SRGB:
 271         case PIPE_FORMAT_L16A16_UNORM:
 272         case PIPE_FORMAT_L16A16_SNORM:
 273         case PIPE_FORMAT_L16A16_UINT:
 274         case PIPE_FORMAT_L16A16_SINT:
 275         case PIPE_FORMAT_L16A16_FLOAT:
 276         case PIPE_FORMAT_L32A32_UINT:
 277         case PIPE_FORMAT_L32A32_SINT:
 278         case PIPE_FORMAT_L32A32_FLOAT:
 279                 return V_028C70_SWAP_ALT;
 280         case PIPE_FORMAT_R8G8_UNORM:
 281         case PIPE_FORMAT_R8G8_SNORM:
 282         case PIPE_FORMAT_R8G8_UINT:
 283         case PIPE_FORMAT_R8G8_SINT:
 284                 return V_028C70_SWAP_STD;
 285
 286         case PIPE_FORMAT_R16_UNORM:
 287         case PIPE_FORMAT_R16_SNORM:
 288         case PIPE_FORMAT_R16_UINT:
 289         case PIPE_FORMAT_R16_SINT:
 290         case PIPE_FORMAT_R16_FLOAT:
 291                 return V_028C70_SWAP_STD;
 292
 293         /* 32-bit buffers. */
 294         case PIPE_FORMAT_A8B8G8R8_SRGB:
 295                 return V_028C70_SWAP_STD_REV;
 296         case PIPE_FORMAT_B8G8R8A8_SRGB:
 297                 return V_028C70_SWAP_ALT;
 298
 299         case PIPE_FORMAT_B8G8R8A8_UNORM:
 300         case PIPE_FORMAT_B8G8R8X8_UNORM:
 301                 return V_028C70_SWAP_ALT;
 302
 303         case PIPE_FORMAT_A8R8G8B8_UNORM:
 304         case PIPE_FORMAT_X8R8G8B8_UNORM:
 305                 return V_028C70_SWAP_ALT_REV;
 306         case PIPE_FORMAT_R8G8B8A8_SNORM:
 307         case PIPE_FORMAT_R8G8B8A8_UNORM:
 308         case PIPE_FORMAT_R8G8B8A8_SINT:
 309         case PIPE_FORMAT_R8G8B8A8_UINT:
 310         case PIPE_FORMAT_R8G8B8X8_UNORM:
 311                 return V_028C70_SWAP_STD;
 312
 313         case PIPE_FORMAT_A8B8G8R8_UNORM:
 314         case PIPE_FORMAT_X8B8G8R8_UNORM:
 315         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 316                 return V_028C70_SWAP_STD_REV;
 317
 318         case PIPE_FORMAT_Z24X8_UNORM:
 319         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 320                 return V_028C70_SWAP_STD;
 321
 322         case PIPE_FORMAT_X8Z24_UNORM:
 323         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 324                 return V_028C70_SWAP_STD;
 325
 326         case PIPE_FORMAT_R10G10B10A2_UNORM:
 327         case PIPE_FORMAT_R10G10B10X2_SNORM:
 328         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 329                 return V_028C70_SWAP_STD;
 330
 331         case PIPE_FORMAT_B10G10R10A2_UNORM:
 332         case PIPE_FORMAT_B10G10R10A2_UINT:
 333                 return V_028C70_SWAP_ALT;
 334
 335         case PIPE_FORMAT_R11G11B10_FLOAT:
 336         case PIPE_FORMAT_R32_FLOAT:
 337         case PIPE_FORMAT_R32_UINT:
 338         case PIPE_FORMAT_R32_SINT:
 339         case PIPE_FORMAT_Z32_FLOAT:
 340         case PIPE_FORMAT_R16G16_FLOAT:
 341         case PIPE_FORMAT_R16G16_UNORM:
 342         case PIPE_FORMAT_R16G16_SNORM:
 343         case PIPE_FORMAT_R16G16_UINT:
 344         case PIPE_FORMAT_R16G16_SINT:
 345                 return V_028C70_SWAP_STD;
 346
 347         /* 64-bit buffers. */
 348         case PIPE_FORMAT_R32G32_FLOAT:
 349         case PIPE_FORMAT_R32G32_UINT:
 350         case PIPE_FORMAT_R32G32_SINT:
 351         case PIPE_FORMAT_R16G16B16A16_UNORM:
 352         case PIPE_FORMAT_R16G16B16A16_SNORM:
 353         case PIPE_FORMAT_R16G16B16A16_UINT:
 354         case PIPE_FORMAT_R16G16B16A16_SINT:
 355         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 356         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 357
 358         /* 128-bit buffers. */
 359         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 360         case PIPE_FORMAT_R32G32B32A32_SNORM:
 361         case PIPE_FORMAT_R32G32B32A32_UNORM:
 362         case PIPE_FORMAT_R32G32B32A32_SINT:
 363         case PIPE_FORMAT_R32G32B32A32_UINT:
 364                 return V_028C70_SWAP_STD;
 365         default:
 366                 R600_ERR("unsupported colorswap format %d\n", format);
 367                 return ~0U;
 368         }
 369         return ~0U;
 370 }
 371
 372 static uint32_t r600_translate_colorformat(enum pipe_format format)
 373 {
 374         switch (format) {
 375         /* 8-bit buffers. */
 376         case PIPE_FORMAT_A8_UNORM:
 377         case PIPE_FORMAT_A8_SNORM:
 378         case PIPE_FORMAT_A8_UINT:
 379         case PIPE_FORMAT_A8_SINT:
 380         case PIPE_FORMAT_I8_UNORM:
 381         case PIPE_FORMAT_I8_SNORM:
 382         case PIPE_FORMAT_I8_UINT:
 383         case PIPE_FORMAT_I8_SINT:
 384         case PIPE_FORMAT_L8_UNORM:
 385         case PIPE_FORMAT_L8_SNORM:
 386         case PIPE_FORMAT_L8_UINT:
 387         case PIPE_FORMAT_L8_SINT:
 388         case PIPE_FORMAT_L8_SRGB:
 389         case PIPE_FORMAT_R8_UNORM:
 390         case PIPE_FORMAT_R8_SNORM:
 391         case PIPE_FORMAT_R8_UINT:
 392         case PIPE_FORMAT_R8_SINT:
 393                 return V_028C70_COLOR_8;
 394
 395         /* 16-bit buffers. */
 396         case PIPE_FORMAT_B5G6R5_UNORM:
 397                 return V_028C70_COLOR_5_6_5;
 398
 399         case PIPE_FORMAT_B5G5R5A1_UNORM:
 400         case PIPE_FORMAT_B5G5R5X1_UNORM:
 401                 return V_028C70_COLOR_1_5_5_5;
 402
 403         case PIPE_FORMAT_B4G4R4A4_UNORM:
 404         case PIPE_FORMAT_B4G4R4X4_UNORM:
 405                 return V_028C70_COLOR_4_4_4_4;
 406
 407         case PIPE_FORMAT_Z16_UNORM:
 408                 return V_028C70_COLOR_16;
 409
 410         case PIPE_FORMAT_L8A8_UNORM:
 411         case PIPE_FORMAT_L8A8_SNORM:
 412         case PIPE_FORMAT_L8A8_UINT:
 413         case PIPE_FORMAT_L8A8_SINT:
 414         case PIPE_FORMAT_L8A8_SRGB:
 415         case PIPE_FORMAT_R8G8_UNORM:
 416         case PIPE_FORMAT_R8G8_SNORM:
 417         case PIPE_FORMAT_R8G8_UINT:
 418         case PIPE_FORMAT_R8G8_SINT:
 419                 return V_028C70_COLOR_8_8;
 420
 421         case PIPE_FORMAT_R16_UNORM:
 422         case PIPE_FORMAT_R16_SNORM:
 423         case PIPE_FORMAT_R16_UINT:
 424         case PIPE_FORMAT_R16_SINT:
 425         case PIPE_FORMAT_A16_UNORM:
 426         case PIPE_FORMAT_A16_SNORM:
 427         case PIPE_FORMAT_A16_UINT:
 428         case PIPE_FORMAT_A16_SINT:
 429         case PIPE_FORMAT_L16_UNORM:
 430         case PIPE_FORMAT_L16_SNORM:
 431         case PIPE_FORMAT_L16_UINT:
 432         case PIPE_FORMAT_L16_SINT:
 433         case PIPE_FORMAT_I16_UNORM:
 434         case PIPE_FORMAT_I16_SNORM:
 435         case PIPE_FORMAT_I16_UINT:
 436         case PIPE_FORMAT_I16_SINT:
 437                 return V_028C70_COLOR_16;
 438
 439         case PIPE_FORMAT_R16_FLOAT:
 440         case PIPE_FORMAT_A16_FLOAT:
 441         case PIPE_FORMAT_L16_FLOAT:
 442         case PIPE_FORMAT_I16_FLOAT:
 443                 return V_028C70_COLOR_16_FLOAT;
 444
 445         /* 32-bit buffers. */
 446         case PIPE_FORMAT_A8B8G8R8_SRGB:
 447         case PIPE_FORMAT_A8B8G8R8_UNORM:
 448         case PIPE_FORMAT_A8R8G8B8_UNORM:
 449         case PIPE_FORMAT_B8G8R8A8_SRGB:
 450         case PIPE_FORMAT_B8G8R8A8_UNORM:
 451         case PIPE_FORMAT_B8G8R8X8_UNORM:
 452         case PIPE_FORMAT_R8G8B8A8_SNORM:
 453         case PIPE_FORMAT_R8G8B8A8_UNORM:
 454         case PIPE_FORMAT_R8G8B8X8_UNORM:
 455         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 456         case PIPE_FORMAT_X8B8G8R8_UNORM:
 457         case PIPE_FORMAT_X8R8G8B8_UNORM:
 458         case PIPE_FORMAT_R8G8B8_UNORM:
 459         case PIPE_FORMAT_R8G8B8A8_SINT:
 460         case PIPE_FORMAT_R8G8B8A8_UINT:
 461                 return V_028C70_COLOR_8_8_8_8;
 462
 463         case PIPE_FORMAT_R10G10B10A2_UNORM:
 464         case PIPE_FORMAT_R10G10B10X2_SNORM:
 465         case PIPE_FORMAT_B10G10R10A2_UNORM:
 466         case PIPE_FORMAT_B10G10R10A2_UINT:
 467         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 468                 return V_028C70_COLOR_2_10_10_10;
 469
 470         case PIPE_FORMAT_Z24X8_UNORM:
 471         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 472                 return V_028C70_COLOR_8_24;
 473
 474         case PIPE_FORMAT_X8Z24_UNORM:
 475         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 476                 return V_028C70_COLOR_24_8;
 477
 478         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 479                 return V_028C70_COLOR_X24_8_32_FLOAT;
 480
 481         case PIPE_FORMAT_R32_UINT:
 482         case PIPE_FORMAT_R32_SINT:
 483         case PIPE_FORMAT_A32_UINT:
 484         case PIPE_FORMAT_A32_SINT:
 485         case PIPE_FORMAT_L32_UINT:
 486         case PIPE_FORMAT_L32_SINT:
 487         case PIPE_FORMAT_I32_UINT:
 488         case PIPE_FORMAT_I32_SINT:
 489                 return V_028C70_COLOR_32;
 490
 491         case PIPE_FORMAT_R32_FLOAT:
 492         case PIPE_FORMAT_A32_FLOAT:
 493         case PIPE_FORMAT_L32_FLOAT:
 494         case PIPE_FORMAT_I32_FLOAT:
 495         case PIPE_FORMAT_Z32_FLOAT:
 496                 return V_028C70_COLOR_32_FLOAT;
 497
 498         case PIPE_FORMAT_R16G16_FLOAT:
 499         case PIPE_FORMAT_L16A16_FLOAT:
 500                 return V_028C70_COLOR_16_16_FLOAT;
 501
 502         case PIPE_FORMAT_R16G16_UNORM:
 503         case PIPE_FORMAT_R16G16_SNORM:
 504         case PIPE_FORMAT_R16G16_UINT:
 505         case PIPE_FORMAT_R16G16_SINT:
 506         case PIPE_FORMAT_L16A16_UNORM:
 507         case PIPE_FORMAT_L16A16_SNORM:
 508         case PIPE_FORMAT_L16A16_UINT:
 509         case PIPE_FORMAT_L16A16_SINT:
 510                 return V_028C70_COLOR_16_16;
 511
 512         case PIPE_FORMAT_R11G11B10_FLOAT:
 513                 return V_028C70_COLOR_10_11_11_FLOAT;
 514
 515         /* 64-bit buffers. */
 516         case PIPE_FORMAT_R16G16B16A16_UINT:
 517         case PIPE_FORMAT_R16G16B16A16_SINT:
 518         case PIPE_FORMAT_R16G16B16A16_UNORM:
 519         case PIPE_FORMAT_R16G16B16A16_SNORM:
 520                 return V_028C70_COLOR_16_16_16_16;
 521
 522         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 523                 return V_028C70_COLOR_16_16_16_16_FLOAT;
 524
 525         case PIPE_FORMAT_R32G32_FLOAT:
 526         case PIPE_FORMAT_L32A32_FLOAT:
 527                 return V_028C70_COLOR_32_32_FLOAT;
 528
 529         case PIPE_FORMAT_R32G32_SINT:
 530         case PIPE_FORMAT_R32G32_UINT:
 531         case PIPE_FORMAT_L32A32_UINT:
 532         case PIPE_FORMAT_L32A32_SINT:
 533                 return V_028C70_COLOR_32_32;
 534
 535         /* 128-bit buffers. */
 536         case PIPE_FORMAT_R32G32B32A32_SNORM:
 537         case PIPE_FORMAT_R32G32B32A32_UNORM:
 538         case PIPE_FORMAT_R32G32B32A32_SINT:
 539         case PIPE_FORMAT_R32G32B32A32_UINT:
 540                 return V_028C70_COLOR_32_32_32_32;
 541         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 542                 return V_028C70_COLOR_32_32_32_32_FLOAT;
 543
 544         /* YUV buffers. */
 545         case PIPE_FORMAT_UYVY:
 546         case PIPE_FORMAT_YUYV:
 547         default:
 548                 return ~0U; /* Unsupported. */
 549         }
 550 }
 551
 552 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 553 {
 554         if (R600_BIG_ENDIAN) {
 555                 switch(colorformat) {
 556
 557                 /* 8-bit buffers. */
 558                 case V_028C70_COLOR_8:
 559                         return ENDIAN_NONE;
 560
 561                 /* 16-bit buffers. */
 562                 case V_028C70_COLOR_5_6_5:
 563                 case V_028C70_COLOR_1_5_5_5:
 564                 case V_028C70_COLOR_4_4_4_4:
 565                 case V_028C70_COLOR_16:
 566                 case V_028C70_COLOR_8_8:
 567                         return ENDIAN_8IN16;
 568
 569                 /* 32-bit buffers. */
 570                 case V_028C70_COLOR_8_8_8_8:
 571                 case V_028C70_COLOR_2_10_10_10:
 572                 case V_028C70_COLOR_8_24:
 573                 case V_028C70_COLOR_24_8:
 574                 case V_028C70_COLOR_32_FLOAT:
 575                 case V_028C70_COLOR_16_16_FLOAT:
 576                 case V_028C70_COLOR_16_16:
 577                         return ENDIAN_8IN32;
 578
 579                 /* 64-bit buffers. */
 580                 case V_028C70_COLOR_16_16_16_16:
 581                 case V_028C70_COLOR_16_16_16_16_FLOAT:
 582                         return ENDIAN_8IN16;
 583
 584                 case V_028C70_COLOR_32_32_FLOAT:
 585                 case V_028C70_COLOR_32_32:
 586                 case V_028C70_COLOR_X24_8_32_FLOAT:
 587                         return ENDIAN_8IN32;
 588
 589                 /* 96-bit buffers. */
 590                 case V_028C70_COLOR_32_32_32_FLOAT:
 591                 /* 128-bit buffers. */
 592                 case V_028C70_COLOR_32_32_32_32_FLOAT:
 593                 case V_028C70_COLOR_32_32_32_32:
 594                         return ENDIAN_8IN32;
 595                 default:
 596                         return ENDIAN_NONE; /* Unsupported. */
 597                 }
 598         } else {
 599                 return ENDIAN_NONE;
 600         }
 601 }
 602
 603 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 604 {
 605         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 606 }
 607
 608 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 609 {
 610         return r600_translate_colorformat(format) != ~0U &&
 611                 r600_translate_colorswap(format) != ~0U;
 612 }
 613
 614 static bool r600_is_zs_format_supported(enum pipe_format format)
 615 {
 616         return r600_translate_dbformat(format) != ~0U;
 617 }
 618
 619 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 620                                       enum pipe_format format,
 621                                       enum pipe_texture_target target,
 622                                       unsigned sample_count,
 623                                       unsigned usage)
 624 {
 625         struct r600_screen *rscreen = (struct r600_screen*)screen;
 626         unsigned retval = 0;
 627
 628         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 629                 R600_ERR("r600: unsupported texture type %d\n", target);
 630                 return FALSE;
 631         }
 632
 633         if (!util_format_is_supported(format, usage))
 634                 return FALSE;
 635
 636         if (sample_count > 1) {
 637                 if (!rscreen->has_msaa)
 638                         return FALSE;
 639
 640                 switch (sample_count) {
 641                 case 2:
 642                 case 4:
 643                 case 8:
 644                         break;
 645                 default:
 646                         return FALSE;
 647                 }
 648         }
 649
 650         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 651             r600_is_sampler_format_supported(screen, format)) {
 652                 retval |= PIPE_BIND_SAMPLER_VIEW;
 653         }
 654
 655         if ((usage & (PIPE_BIND_RENDER_TARGET |
 656                       PIPE_BIND_DISPLAY_TARGET |
 657                       PIPE_BIND_SCANOUT |
 658                       PIPE_BIND_SHARED)) &&
 659             r600_is_colorbuffer_format_supported(format)) {
 660                 retval |= usage &
 661                           (PIPE_BIND_RENDER_TARGET |
 662                            PIPE_BIND_DISPLAY_TARGET |
 663                            PIPE_BIND_SCANOUT |
 664                            PIPE_BIND_SHARED);
 665         }
 666
 667         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 668             r600_is_zs_format_supported(format)) {
 669                 retval |= PIPE_BIND_DEPTH_STENCIL;
 670         }
 671
 672         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 673             r600_is_vertex_format_supported(format)) {
 674                 retval |= PIPE_BIND_VERTEX_BUFFER;
 675         }
 676
 677         if (usage & PIPE_BIND_TRANSFER_READ)
 678                 retval |= PIPE_BIND_TRANSFER_READ;
 679         if (usage & PIPE_BIND_TRANSFER_WRITE)
 680                 retval |= PIPE_BIND_TRANSFER_WRITE;
 681
 682         return retval == usage;
 683 }
 684
 685 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
 686                                                const struct pipe_blend_state *state, int mode)
 687 {
 688         uint32_t color_control = 0, target_mask = 0;
 689         struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
 690
 691         if (!blend) {
 692                 return NULL;
 693         }
 694
 695         r600_init_command_buffer(&blend->buffer, 20);
 696         r600_init_command_buffer(&blend->buffer_no_blend, 20);
 697
 698         if (state->logicop_enable) {
 699                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 700         } else {
 701                 color_control |= (0xcc << 16);
 702         }
 703         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 704         if (state->independent_blend_enable) {
 705                 for (int i = 0; i < 8; i++) {
 706                         target_mask |= (state->rt[i].colormask << (4 * i));
 707                 }
 708         } else {
 709                 for (int i = 0; i < 8; i++) {
 710                         target_mask |= (state->rt[0].colormask << (4 * i));
 711                 }
 712         }
 713
 714         /* only have dual source on MRT0 */
 715         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 716         blend->cb_target_mask = target_mask;
 717         blend->alpha_to_one = state->alpha_to_one;
 718
 719         if (target_mask)
 720                 color_control |= S_028808_MODE(mode);
 721         else
 722                 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 723
 724
 725         r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
 726         r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
 727                                S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 728                                S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
 729                                S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
 730                                S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
 731                                S_028B70_ALPHA_TO_MASK_OFFSET3(2));
 732         r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
 733
 734         /* Copy over the dwords set so far into buffer_no_blend.
 735          * Only the CB_BLENDi_CONTROL registers must be set after this. */
 736         memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
 737         blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
 738
 739         for (int i = 0; i < 8; i++) {
 740                 /* state->rt entries > 0 only written if independent blending */
 741                 const int j = state->independent_blend_enable ? i : 0;
 742
 743                 unsigned eqRGB = state->rt[j].rgb_func;
 744                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 745                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 746                 unsigned eqA = state->rt[j].alpha_func;
 747                 unsigned srcA = state->rt[j].alpha_src_factor;
 748                 unsigned dstA = state->rt[j].alpha_dst_factor;
 749                 uint32_t bc = 0;
 750
 751                 r600_store_value(&blend->buffer_no_blend, 0);
 752
 753                 if (!state->rt[j].blend_enable) {
 754                         r600_store_value(&blend->buffer, 0);
 755                         continue;
 756                 }
 757
 758                 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
 759                 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 760                 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 761                 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 762
 763                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 764                         bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
 765                         bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 766                         bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 767                         bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 768                 }
 769                 r600_store_value(&blend->buffer, bc);
 770         }
 771         return blend;
 772 }
 773
 774 static void *evergreen_create_blend_state(struct pipe_context *ctx,
 775                                         const struct pipe_blend_state *state)
 776 {
 777
 778         return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
 779 }
 780
 781 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 782                                    const struct pipe_depth_stencil_alpha_state *state)
 783 {
 784         unsigned db_depth_control, alpha_test_control, alpha_ref;
 785         struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
 786
 787         if (dsa == NULL) {
 788                 return NULL;
 789         }
 790
 791         r600_init_command_buffer(&dsa->buffer, 3);
 792
 793         dsa->valuemask[0] = state->stencil[0].valuemask;
 794         dsa->valuemask[1] = state->stencil[1].valuemask;
 795         dsa->writemask[0] = state->stencil[0].writemask;
 796         dsa->writemask[1] = state->stencil[1].writemask;
 797
 798         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 799                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 800                 S_028800_ZFUNC(state->depth.func);
 801
 802         /* stencil */
 803         if (state->stencil[0].enabled) {
 804                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 805                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 806                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 807                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 808                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 809
 810                 if (state->stencil[1].enabled) {
 811                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 812                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 813                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 814                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 815                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 816                 }
 817         }
 818
 819         /* alpha */
 820         alpha_test_control = 0;
 821         alpha_ref = 0;
 822         if (state->alpha.enabled) {
 823                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 824                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 825                 alpha_ref = fui(state->alpha.ref_value);
 826         }
 827         dsa->sx_alpha_test_control = alpha_test_control & 0xff;
 828         dsa->alpha_ref = alpha_ref;
 829
 830         /* misc */
 831         r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 832         return dsa;
 833 }
 834
 835 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 836                                         const struct pipe_rasterizer_state *state)
 837 {
 838         struct r600_context *rctx = (struct r600_context *)ctx;
 839         unsigned tmp, spi_interp;
 840         float psize_min, psize_max;
 841         struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
 842
 843         if (rs == NULL) {
 844                 return NULL;
 845         }
 846
 847         r600_init_command_buffer(&rs->buffer, 30);
 848
 849         rs->flatshade = state->flatshade;
 850         rs->sprite_coord_enable = state->sprite_coord_enable;
 851         rs->two_side = state->light_twoside;
 852         rs->clip_plane_enable = state->clip_plane_enable;
 853         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 854                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 855                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 856         rs->pa_cl_clip_cntl =
 857                 S_028810_PS_UCP_MODE(3) |
 858                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 859                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 860                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 861         rs->multisample_enable = state->multisample;
 862
 863         /* offset */
 864         rs->offset_units = state->offset_units;
 865         rs->offset_scale = state->offset_scale * 12.0f;
 866         rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
 867
 868         if (state->point_size_per_vertex) {
 869                 psize_min = util_get_min_point_size(state);
 870                 psize_max = 8192;
 871         } else {
 872                 /* Force the point size to be as if the vertex output was disabled. */
 873                 psize_min = state->point_size;
 874                 psize_max = state->point_size;
 875         }
 876
 877         spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
 878         if (state->sprite_coord_enable) {
 879                 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
 880                               S_0286D4_PNT_SPRITE_OVRD_X(2) |
 881                               S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 882                               S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 883                               S_0286D4_PNT_SPRITE_OVRD_W(1);
 884                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 885                         spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 886                 }
 887         }
 888
 889         r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
 890         /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
 891         tmp = r600_pack_float_12p4(state->point_size/2);
 892         r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
 893                          S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 894         r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
 895                          S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 896                          S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
 897         r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
 898                          S_028A08_WIDTH((unsigned)(state->line_width * 8)));
 899
 900         r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
 901         r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
 902                                S_028A48_MSAA_ENABLE(state->multisample) |
 903                                S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
 904                                S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
 905
 906         if (rctx->chip_class == CAYMAN) {
 907                 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
 908                                        S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
 909                                        S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 910         } else {
 911                 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
 912                                        S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
 913                                        S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 914         }
 915
 916         r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 917         r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
 918                                S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 919                                S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 920                                S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 921                                S_028814_FACE(!state->front_ccw) |
 922                                S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 923                                S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 924                                S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 925                                S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
 926                                                   state->fill_back != PIPE_POLYGON_MODE_FILL) |
 927                                S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 928                                S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
 929         r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
 930         return rs;
 931 }
 932
 933 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 934                                         const struct pipe_sampler_state *state)
 935 {
 936         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 937         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
 938
 939         if (ss == NULL) {
 940                 return NULL;
 941         }
 942
 943         ss->border_color_use = sampler_state_needs_border_color(state);
 944
 945         /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
 946         ss->tex_sampler_words[0] =
 947                 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 948                 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 949                 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 950                 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
 951                 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 952                 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 953                 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 954                 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 955                 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
 956         /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
 957         ss->tex_sampler_words[1] =
 958                 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
 959                 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
 960         /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
 961         ss->tex_sampler_words[2] =
 962                 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
 963                 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
 964                 S_03C008_TYPE(1);
 965
 966         if (ss->border_color_use) {
 967                 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
 968         }
 969         return ss;
 970 }
 971
 972 struct pipe_sampler_view *
 973 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 974                                      struct pipe_resource *texture,
 975                                      const struct pipe_sampler_view *state,
 976                                      unsigned width0, unsigned height0)
 977 {
 978         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 979         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
 980         struct r600_texture *tmp = (struct r600_texture*)texture;
 981         unsigned format, endian;
 982         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 983         unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
 984         unsigned height, depth, width;
 985         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
 986         enum pipe_format pipe_format = state->format;
 987         struct radeon_surface_level *surflevel;
 988
 989         if (view == NULL)
 990                 return NULL;
 991
 992         /* initialize base object */
 993         view->base = *state;
 994         view->base.texture = NULL;
 995         pipe_reference(NULL, &texture->reference);
 996         view->base.texture = texture;
 997         view->base.reference.count = 1;
 998         view->base.context = ctx;
 999
1000         swizzle[0] = state->swizzle_r;
1001         swizzle[1] = state->swizzle_g;
1002         swizzle[2] = state->swizzle_b;
1003         swizzle[3] = state->swizzle_a;
1004
1005         tile_split = tmp->surface.tile_split;
1006         surflevel = tmp->surface.level;
1007
1008         /* Texturing with separate depth and stencil. */
1009         if (tmp->is_depth && !tmp->is_flushing_texture) {
1010                 switch (pipe_format) {
1011                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1012                         pipe_format = PIPE_FORMAT_Z32_FLOAT;
1013                         break;
1014                 case PIPE_FORMAT_X24S8_UINT:
1015                 case PIPE_FORMAT_S8X24_UINT:
1016                 case PIPE_FORMAT_X32_S8X24_UINT:
1017                         pipe_format = PIPE_FORMAT_S8_UINT;
1018                         tile_split = tmp->surface.stencil_tile_split;
1019                         surflevel = tmp->surface.stencil_level;
1020                         break;
1021                 default:;
1022                 }
1023         }
1024
1025         format = r600_translate_texformat(ctx->screen, pipe_format,
1026                                           swizzle,
1027                                           &word4, &yuv_format);
1028         assert(format != ~0);
1029         if (format == ~0) {
1030                 FREE(view);
1031                 return NULL;
1032         }
1033
1034         endian = r600_colorformat_endian_swap(format);
1035
1036         width = width0;
1037         height = height0;
1038         depth = surflevel[0].npix_z;
1039         pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
1040         non_disp_tiling = tmp->non_disp_tiling;
1041
1042         switch (surflevel[0].mode) {
1043         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1044                 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1045                 break;
1046         case RADEON_SURF_MODE_2D:
1047                 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1048                 break;
1049         case RADEON_SURF_MODE_1D:
1050                 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1051                 break;
1052         case RADEON_SURF_MODE_LINEAR:
1053         default:
1054                 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1055                 break;
1056         }
1057         macro_aspect = tmp->surface.mtilea;
1058         bankw = tmp->surface.bankw;
1059         bankh = tmp->surface.bankh;
1060         tile_split = eg_tile_split(tile_split);
1061         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1062         bankw = eg_bank_wh(bankw);
1063         bankh = eg_bank_wh(bankh);
1064
1065         /* 128 bit formats require tile type = 1 */
1066         if (rscreen->chip_class == CAYMAN) {
1067                 if (util_format_get_blocksize(pipe_format) >= 16)
1068                         non_disp_tiling = 1;
1069         }
1070         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1071
1072         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1073                 height = 1;
1074                 depth = texture->array_size;
1075         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1076                 depth = texture->array_size;
1077         } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1078                 depth = texture->array_size / 6;
1079
1080         view->tex_resource = &tmp->resource;
1081         view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1082                                        S_030000_PITCH((pitch / 8) - 1) |
1083                                        S_030000_TEX_WIDTH(width - 1));
1084         if (rscreen->chip_class == CAYMAN)
1085                 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1086         else
1087                 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1088         view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1089                                        S_030004_TEX_DEPTH(depth - 1) |
1090                                        S_030004_ARRAY_MODE(array_mode));
1091         view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1092
1093         /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1094         if (texture->nr_samples > 1 && rscreen->msaa_texture_support == MSAA_TEXTURE_COMPRESSED) {
1095                 /* XXX the 2x and 4x cases are broken. */
1096                 if (tmp->is_depth || tmp->resource.b.b.nr_samples != 8) {
1097                         /* disable FMASK (0 = disabled) */
1098                         view->tex_resource_words[3] = 0;
1099                         view->skip_mip_address_reloc = true;
1100                 } else {
1101                         /* FMASK should be in MIP_ADDRESS for multisample textures */
1102                         view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
1103                 }
1104         } else if (state->u.tex.last_level && texture->nr_samples <= 1) {
1105                 view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1106         } else {
1107                 view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1108         }
1109
1110         view->tex_resource_words[4] = (word4 |
1111                                        S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1112                                        S_030010_ENDIAN_SWAP(endian));
1113         view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1114                                       S_030014_LAST_ARRAY(state->u.tex.last_layer);
1115         if (texture->nr_samples > 1) {
1116                 unsigned log_samples = util_logbase2(texture->nr_samples);
1117                 if (rscreen->chip_class == CAYMAN) {
1118                         view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1119                 }
1120                 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1121                 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1122         } else {
1123                 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1124                 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1125         }
1126         /* aniso max 16 samples */
1127         view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1128                                       (S_030018_TILE_SPLIT(tile_split));
1129         view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1130                                       S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1131                                       S_03001C_BANK_WIDTH(bankw) |
1132                                       S_03001C_BANK_HEIGHT(bankh) |
1133                                       S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1134                                       S_03001C_NUM_BANKS(nbanks) |
1135                                       S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
1136         return &view->base;
1137 }
1138
1139 static struct pipe_sampler_view *
1140 evergreen_create_sampler_view(struct pipe_context *ctx,
1141                               struct pipe_resource *tex,
1142                               const struct pipe_sampler_view *state)
1143 {
1144         return evergreen_create_sampler_view_custom(ctx, tex, state,
1145                                                     tex->width0, tex->height0);
1146 }
1147
1148 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1149 {
1150         struct radeon_winsys_cs *cs = rctx->cs;
1151         struct pipe_clip_state *state = &rctx->clip_state.state;
1152
1153         r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1154         r600_write_array(cs, 6*4, (unsigned*)state);
1155 }
1156
1157 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1158                                          const struct pipe_poly_stipple *state)
1159 {
1160 }
1161
1162 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1163                                        unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1164                                        uint32_t *tl, uint32_t *br)
1165 {
1166         /* EG hw workaround */
1167         if (br_x == 0)
1168                 tl_x = 1;
1169         if (br_y == 0)
1170                 tl_y = 1;
1171
1172         /* cayman hw workaround */
1173         if (rctx->chip_class == CAYMAN) {
1174                 if (br_x == 1 && br_y == 1)
1175                         br_x = 2;
1176         }
1177
1178         *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1179         *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1180 }
1181
1182 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1183                                         const struct pipe_scissor_state *state)
1184 {
1185         struct r600_context *rctx = (struct r600_context *)ctx;
1186
1187         rctx->scissor.scissor = *state;
1188         rctx->scissor.atom.dirty = true;
1189 }
1190
1191 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1192 {
1193         struct radeon_winsys_cs *cs = rctx->cs;
1194         struct pipe_scissor_state *state = &rctx->scissor.scissor;
1195         uint32_t tl, br;
1196
1197         evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1198
1199         r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1200         r600_write_value(cs, tl);
1201         r600_write_value(cs, br);
1202 }
1203
1204 /**
1205  * This function intializes the CB* register values for RATs.  It is meant
1206  * to be used for 1D aligned buffers that do not have an associated
1207  * radeon_surface.
1208  */
1209 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1210                                         struct r600_surface *surf)
1211 {
1212         struct pipe_resource *pipe_buffer = surf->base.texture;
1213         unsigned format = r600_translate_colorformat(surf->base.format);
1214         unsigned endian = r600_colorformat_endian_swap(format);
1215         unsigned swap = r600_translate_colorswap(surf->base.format);
1216         unsigned block_size =
1217                 align(util_format_get_blocksize(pipe_buffer->format), 4);
1218         unsigned pitch_alignment =
1219                 MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
1220         unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1221
1222         /* XXX: This is copied from evergreen_init_color_surface().  I don't
1223          * know why this is necessary.
1224          */
1225         if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1226                 endian = ENDIAN_NONE;
1227         }
1228
1229         surf->cb_color_base =
1230                 r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
1231
1232         surf->cb_color_pitch = (pitch / 8) - 1;
1233
1234         surf->cb_color_slice = 0;
1235
1236         surf->cb_color_view = 0;
1237
1238         surf->cb_color_info =
1239                   S_028C70_ENDIAN(endian)
1240                 | S_028C70_FORMAT(format)
1241                 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1242                 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1243                 | S_028C70_COMP_SWAP(swap)
1244                 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1245                                             * are using NUMBER_UINT */
1246                 | S_028C70_RAT(1)
1247                 ;
1248
1249         surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1250
1251         /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1252          * elements. */
1253         surf->cb_color_dim = pipe_buffer->width0;
1254
1255         surf->cb_color_cmask = surf->cb_color_base;
1256         surf->cb_color_cmask_slice = 0;
1257         surf->cb_color_fmask = surf->cb_color_base;
1258         surf->cb_color_fmask_slice = 0;
1259 }
1260
1261 void evergreen_init_color_surface(struct r600_context *rctx,
1262                                   struct r600_surface *surf)
1263 {
1264         struct r600_screen *rscreen = rctx->screen;
1265         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1266         struct pipe_resource *pipe_tex = surf->base.texture;
1267         unsigned level = surf->base.u.tex.level;
1268         unsigned pitch, slice;
1269         unsigned color_info, color_attrib, color_dim = 0;
1270         unsigned format, swap, ntype, endian;
1271         uint64_t offset, base_offset;
1272         unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1273         const struct util_format_description *desc;
1274         int i;
1275         bool blend_clamp = 0, blend_bypass = 0;
1276
1277         offset = rtex->surface.level[level].offset;
1278         if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1279                 offset += rtex->surface.level[level].slice_size *
1280                           surf->base.u.tex.first_layer;
1281         }
1282         pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1283         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1284         if (slice) {
1285                 slice = slice - 1;
1286         }
1287         color_info = 0;
1288         switch (rtex->surface.level[level].mode) {
1289         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1290                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1291                 non_disp_tiling = 1;
1292                 break;
1293         case RADEON_SURF_MODE_1D:
1294                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1295                 non_disp_tiling = rtex->non_disp_tiling;
1296                 break;
1297         case RADEON_SURF_MODE_2D:
1298                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1299                 non_disp_tiling = rtex->non_disp_tiling;
1300                 break;
1301         case RADEON_SURF_MODE_LINEAR:
1302         default:
1303                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1304                 non_disp_tiling = 1;
1305                 break;
1306         }
1307         tile_split = rtex->surface.tile_split;
1308         macro_aspect = rtex->surface.mtilea;
1309         bankw = rtex->surface.bankw;
1310         bankh = rtex->surface.bankh;
1311         fmask_bankh = rtex->fmask_bank_height;
1312         tile_split = eg_tile_split(tile_split);
1313         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1314         bankw = eg_bank_wh(bankw);
1315         bankh = eg_bank_wh(bankh);
1316         fmask_bankh = eg_bank_wh(fmask_bankh);
1317
1318         /* 128 bit formats require tile type = 1 */
1319         if (rscreen->chip_class == CAYMAN) {
1320                 if (util_format_get_blocksize(surf->base.format) >= 16)
1321                         non_disp_tiling = 1;
1322         }
1323         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1324         desc = util_format_description(surf->base.format);
1325         for (i = 0; i < 4; i++) {
1326                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1327                         break;
1328                 }
1329         }
1330
1331         color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1332                         S_028C74_NUM_BANKS(nbanks) |
1333                         S_028C74_BANK_WIDTH(bankw) |
1334                         S_028C74_BANK_HEIGHT(bankh) |
1335                         S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1336                         S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1337                         S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1338
1339         if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1340                 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1341                 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1342                                 S_028C74_NUM_FRAGMENTS(log_samples);
1343         }
1344
1345         ntype = V_028C70_NUMBER_UNORM;
1346         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1347                 ntype = V_028C70_NUMBER_SRGB;
1348         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1349                 if (desc->channel[i].normalized)
1350                         ntype = V_028C70_NUMBER_SNORM;
1351                 else if (desc->channel[i].pure_integer)
1352                         ntype = V_028C70_NUMBER_SINT;
1353         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1354                 if (desc->channel[i].normalized)
1355                         ntype = V_028C70_NUMBER_UNORM;
1356                 else if (desc->channel[i].pure_integer)
1357                         ntype = V_028C70_NUMBER_UINT;
1358         }
1359
1360         format = r600_translate_colorformat(surf->base.format);
1361         assert(format != ~0);
1362
1363         swap = r600_translate_colorswap(surf->base.format);
1364         assert(swap != ~0);
1365
1366         if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1367                 endian = ENDIAN_NONE;
1368         } else {
1369                 endian = r600_colorformat_endian_swap(format);
1370         }
1371
1372         /* blend clamp should be set for all NORM/SRGB types */
1373         if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1374             ntype == V_028C70_NUMBER_SRGB)
1375                 blend_clamp = 1;
1376
1377         /* set blend bypass according to docs if SINT/UINT or
1378            8/24 COLOR variants */
1379         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1380             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1381             format == V_028C70_COLOR_X24_8_32_FLOAT) {
1382                 blend_clamp = 0;
1383                 blend_bypass = 1;
1384         }
1385
1386         surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1387
1388         color_info |= S_028C70_FORMAT(format) |
1389                 S_028C70_COMP_SWAP(swap) |
1390                 S_028C70_BLEND_CLAMP(blend_clamp) |
1391                 S_028C70_BLEND_BYPASS(blend_bypass) |
1392                 S_028C70_NUMBER_TYPE(ntype) |
1393                 S_028C70_ENDIAN(endian);
1394
1395         if (rtex->is_rat) {
1396                 color_info |= S_028C70_RAT(1);
1397                 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1398                         | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1399         }
1400
1401         /* EXPORT_NORM is an optimzation that can be enabled for better
1402          * performance in certain cases.
1403          * EXPORT_NORM can be enabled if:
1404          * - 11-bit or smaller UNORM/SNORM/SRGB
1405          * - 16-bit or smaller FLOAT
1406          */
1407         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1408             ((desc->channel[i].size < 12 &&
1409               desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1410               ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1411              (desc->channel[i].size < 17 &&
1412               desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1413                 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1414                 surf->export_16bpc = true;
1415         }
1416
1417         if (rtex->fmask_size && rtex->cmask_size) {
1418                 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1419         }
1420
1421         base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1422
1423         /* XXX handle enabling of CB beyond BASE8 which has different offset */
1424         surf->cb_color_base = (base_offset + offset) >> 8;
1425         surf->cb_color_dim = color_dim;
1426         surf->cb_color_info = color_info;
1427         surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1428         surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1429         if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1430                 surf->cb_color_view = 0;
1431         } else {
1432                 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1433                                       S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1434         }
1435         surf->cb_color_attrib = color_attrib;
1436         if (rtex->fmask_size && rtex->cmask_size) {
1437                 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1438                 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1439         } else {
1440                 surf->cb_color_fmask = surf->cb_color_base;
1441                 surf->cb_color_cmask = surf->cb_color_base;
1442         }
1443         surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1444         surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1445
1446         surf->color_initialized = true;
1447 }
1448
1449 static void evergreen_init_depth_surface(struct r600_context *rctx,
1450                                          struct r600_surface *surf)
1451 {
1452         struct r600_screen *rscreen = rctx->screen;
1453         struct pipe_screen *screen = &rscreen->screen;
1454         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1455         uint64_t offset;
1456         unsigned level, pitch, slice, format, array_mode;
1457         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1458
1459         level = surf->base.u.tex.level;
1460         format = r600_translate_dbformat(surf->base.format);
1461         assert(format != ~0);
1462
1463         offset = r600_resource_va(screen, surf->base.texture);
1464         offset += rtex->surface.level[level].offset;
1465         pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1466         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1467         if (slice) {
1468                 slice = slice - 1;
1469         }
1470         switch (rtex->surface.level[level].mode) {
1471         case RADEON_SURF_MODE_2D:
1472                 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1473                 break;
1474         case RADEON_SURF_MODE_1D:
1475         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1476         case RADEON_SURF_MODE_LINEAR:
1477         default:
1478                 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1479                 break;
1480         }
1481         tile_split = rtex->surface.tile_split;
1482         macro_aspect = rtex->surface.mtilea;
1483         bankw = rtex->surface.bankw;
1484         bankh = rtex->surface.bankh;
1485         tile_split = eg_tile_split(tile_split);
1486         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1487         bankw = eg_bank_wh(bankw);
1488         bankh = eg_bank_wh(bankh);
1489         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1490         offset >>= 8;
1491
1492         surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1493                               S_028040_FORMAT(format) |
1494                               S_028040_TILE_SPLIT(tile_split)|
1495                               S_028040_NUM_BANKS(nbanks) |
1496                               S_028040_BANK_WIDTH(bankw) |
1497                               S_028040_BANK_HEIGHT(bankh) |
1498                               S_028040_MACRO_TILE_ASPECT(macro_aspect);
1499         if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1500                 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1501         }
1502         surf->db_depth_base = offset;
1503         surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1504                               S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1505         surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1506         surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1507
1508         switch (surf->base.format) {
1509         case PIPE_FORMAT_Z24X8_UNORM:
1510         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1511                 surf->pa_su_poly_offset_db_fmt_cntl =
1512                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1513                 break;
1514         case PIPE_FORMAT_Z32_FLOAT:
1515         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1516                 surf->pa_su_poly_offset_db_fmt_cntl =
1517                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1518                         S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1519                 break;
1520         case PIPE_FORMAT_Z16_UNORM:
1521                 surf->pa_su_poly_offset_db_fmt_cntl =
1522                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1523                 break;
1524         default:;
1525         }
1526
1527         if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1528                 uint64_t stencil_offset;
1529                 unsigned stile_split = rtex->surface.stencil_tile_split;
1530
1531                 stile_split = eg_tile_split(stile_split);
1532
1533                 stencil_offset = rtex->surface.stencil_level[level].offset;
1534                 stencil_offset += r600_resource_va(screen, surf->base.texture);
1535
1536                 surf->db_stencil_base = stencil_offset >> 8;
1537                 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1538                                         S_028044_TILE_SPLIT(stile_split);
1539         } else {
1540                 surf->db_stencil_base = offset;
1541                 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1542                  * Older kernels are out of luck. */
1543                 surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
1544                                         S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1545                                         S_028044_FORMAT(V_028044_STENCIL_8);
1546         }
1547
1548         surf->htile_enabled = 0;
1549         /* use htile only for first level */
1550         if (rtex->htile && !level) {
1551                 uint64_t va = r600_resource_va(rctx->screen, rtex->htile);
1552                 surf->htile_enabled = 1;
1553                 surf->db_htile_data_base = va >> 8;
1554                 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1555                                         S_028ABC_HTILE_HEIGHT(1) |
1556                                         S_028ABC_LINEAR(1);
1557                 surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
1558                 surf->db_preload_control = 0;
1559         }
1560
1561         surf->depth_initialized = true;
1562 }
1563
1564 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1565                                             const struct pipe_framebuffer_state *state)
1566 {
1567         struct r600_context *rctx = (struct r600_context *)ctx;
1568         struct r600_surface *surf;
1569         struct r600_texture *rtex;
1570         uint32_t i, log_samples;
1571
1572         if (rctx->framebuffer.state.nr_cbufs) {
1573                 rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1574
1575                 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1576                         rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1577                 }
1578         }
1579         if (rctx->framebuffer.state.zsbuf) {
1580                 rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1581         }
1582
1583         util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1584
1585         /* Colorbuffers. */
1586         rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1587         rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1588                                            util_format_is_pure_integer(state->cbufs[0]->format);
1589         rctx->framebuffer.compressed_cb_mask = 0;
1590
1591         if (state->nr_cbufs)
1592                 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1593         else if (state->zsbuf)
1594                 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1595         else
1596                 rctx->framebuffer.nr_samples = 0;
1597
1598         for (i = 0; i < state->nr_cbufs; i++) {
1599                 surf = (struct r600_surface*)state->cbufs[i];
1600                 rtex = (struct r600_texture*)surf->base.texture;
1601
1602                 if (!surf->color_initialized) {
1603                         evergreen_init_color_surface(rctx, surf);
1604                 }
1605
1606                 if (!surf->export_16bpc) {
1607                         rctx->framebuffer.export_16bpc = false;
1608                 }
1609
1610                 if (rtex->fmask_size && rtex->cmask_size) {
1611                         rctx->framebuffer.compressed_cb_mask |= 1 << i;
1612                 }
1613         }
1614
1615         /* Update alpha-test state dependencies.
1616          * Alpha-test is done on the first colorbuffer only. */
1617         if (state->nr_cbufs) {
1618                 surf = (struct r600_surface*)state->cbufs[0];
1619                 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1620                         rctx->alphatest_state.bypass = surf->alphatest_bypass;
1621                         rctx->alphatest_state.atom.dirty = true;
1622                 }
1623                 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1624                         rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1625                         rctx->alphatest_state.atom.dirty = true;
1626                 }
1627         }
1628
1629         /* ZS buffer. */
1630         if (state->zsbuf) {
1631                 surf = (struct r600_surface*)state->zsbuf;
1632
1633                 if (!surf->depth_initialized) {
1634                         evergreen_init_depth_surface(rctx, surf);
1635                 }
1636
1637                 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1638                         rctx->poly_offset_state.zs_format = state->zsbuf->format;
1639                         rctx->poly_offset_state.atom.dirty = true;
1640                 }
1641
1642                 if (rctx->db_state.rsurf != surf) {
1643                         rctx->db_state.rsurf = surf;
1644                         rctx->db_state.atom.dirty = true;
1645                         rctx->db_misc_state.atom.dirty = true;
1646                 }
1647         } else if (rctx->db_state.rsurf) {
1648                 rctx->db_state.rsurf = NULL;
1649                 rctx->db_state.atom.dirty = true;
1650                 rctx->db_misc_state.atom.dirty = true;
1651         }
1652
1653         if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1654                 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1655                 rctx->cb_misc_state.atom.dirty = true;
1656         }
1657
1658         if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1659                 rctx->alphatest_state.bypass = false;
1660                 rctx->alphatest_state.atom.dirty = true;
1661         }
1662
1663         log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1664         if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1665                 rctx->db_misc_state.log_samples = log_samples;
1666                 rctx->db_misc_state.atom.dirty = true;
1667         }
1668
1669         evergreen_update_db_shader_control(rctx);
1670
1671         /* Calculate the CS size. */
1672         rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1673
1674         /* MSAA. */
1675         if (rctx->chip_class == EVERGREEN) {
1676                 switch (rctx->framebuffer.nr_samples) {
1677                 case 2:
1678                 case 4:
1679                         rctx->framebuffer.atom.num_dw += 6;
1680                         break;
1681                 case 8:
1682                         rctx->framebuffer.atom.num_dw += 10;
1683                         break;
1684                 }
1685                 rctx->framebuffer.atom.num_dw += 4;
1686         } else {
1687                 switch (rctx->framebuffer.nr_samples) {
1688                 case 2:
1689                 case 4:
1690                         rctx->framebuffer.atom.num_dw += 12;
1691                         break;
1692                 case 8:
1693                         rctx->framebuffer.atom.num_dw += 16;
1694                         break;
1695                 case 16:
1696                         rctx->framebuffer.atom.num_dw += 18;
1697                         break;
1698                 }
1699                 rctx->framebuffer.atom.num_dw += 7;
1700         }
1701
1702         /* Colorbuffers. */
1703         rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
1704         if (rctx->keep_tiling_flags)
1705                 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1706         rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1707
1708         /* ZS buffer. */
1709         if (state->zsbuf) {
1710                 rctx->framebuffer.atom.num_dw += 24;
1711                 if (rctx->keep_tiling_flags)
1712                         rctx->framebuffer.atom.num_dw += 2;
1713         } else if (rctx->screen->info.drm_minor >= 18) {
1714                 rctx->framebuffer.atom.num_dw += 4;
1715         }
1716
1717         rctx->framebuffer.atom.dirty = true;
1718 }
1719
1720 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1721         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
1722         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
1723         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
1724          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1725
1726 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1727 {
1728         /* 2xMSAA
1729          * There are two locations (-4, 4), (4, -4). */
1730         static uint32_t sample_locs_2x[] = {
1731                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1732                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1733                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1734                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1735         };
1736         static unsigned max_dist_2x = 4;
1737         /* 4xMSAA
1738          * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1739         static uint32_t sample_locs_4x[] = {
1740                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1741                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1742                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1743                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1744         };
1745         static unsigned max_dist_4x = 6;
1746         /* 8xMSAA */
1747         static uint32_t sample_locs_8x[] = {
1748                 FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1749                 FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1750                 FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1751                 FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1752                 FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1753                 FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1754                 FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1755                 FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1756         };
1757         static unsigned max_dist_8x = 7;
1758
1759         struct radeon_winsys_cs *cs = rctx->cs;
1760         unsigned max_dist = 0;
1761
1762         switch (nr_samples) {
1763         default:
1764                 nr_samples = 0;
1765                 break;
1766         case 2:
1767                 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1768                 r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
1769                 max_dist = max_dist_2x;
1770                 break;
1771         case 4:
1772                 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1773                 r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
1774                 max_dist = max_dist_4x;
1775                 break;
1776         case 8:
1777                 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1778                 r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
1779                 max_dist = max_dist_8x;
1780                 break;
1781         }
1782
1783         if (nr_samples > 1) {
1784                 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1785                 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1786                                      S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1787                 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1788                                      S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1789         } else {
1790                 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1791                 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1792                 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1793         }
1794 }
1795
1796 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1797 {
1798         /* 2xMSAA
1799          * There are two locations (-4, 4), (4, -4). */
1800         static uint32_t sample_locs_2x[] = {
1801                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1802                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1803                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1804                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1805         };
1806         static unsigned max_dist_2x = 4;
1807         /* 4xMSAA
1808          * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1809         static uint32_t sample_locs_4x[] = {
1810                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1811                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1812                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1813                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1814         };
1815         static unsigned max_dist_4x = 6;
1816         /* 8xMSAA */
1817         static uint32_t sample_locs_8x[] = {
1818                 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1819                 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1820                 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1821                 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1822                 FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1823                 FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1824                 FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1825                 FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1826         };
1827         static unsigned max_dist_8x = 8;
1828         /* 16xMSAA */
1829         static uint32_t sample_locs_16x[] = {
1830                 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1831                 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1832                 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1833                 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1834                 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1835                 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1836                 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1837                 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1838                 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1839                 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1840                 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1841                 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1842                 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1843                 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1844                 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1845                 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1846         };
1847         static unsigned max_dist_16x = 8;
1848
1849         struct radeon_winsys_cs *cs = rctx->cs;
1850         unsigned max_dist = 0;
1851
1852         switch (nr_samples) {
1853         default:
1854                 nr_samples = 0;
1855                 break;
1856         case 2:
1857                 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1858                 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1859                 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1860                 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1861                 max_dist = max_dist_2x;
1862                 break;
1863         case 4:
1864                 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1865                 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1866                 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1867                 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1868                 max_dist = max_dist_4x;
1869                 break;
1870         case 8:
1871                 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1872                 r600_write_value(cs, sample_locs_8x[0]);
1873                 r600_write_value(cs, sample_locs_8x[4]);
1874                 r600_write_value(cs, 0);
1875                 r600_write_value(cs, 0);
1876                 r600_write_value(cs, sample_locs_8x[1]);
1877                 r600_write_value(cs, sample_locs_8x[5]);
1878                 r600_write_value(cs, 0);
1879                 r600_write_value(cs, 0);
1880                 r600_write_value(cs, sample_locs_8x[2]);
1881                 r600_write_value(cs, sample_locs_8x[6]);
1882                 r600_write_value(cs, 0);
1883                 r600_write_value(cs, 0);
1884                 r600_write_value(cs, sample_locs_8x[3]);
1885                 r600_write_value(cs, sample_locs_8x[7]);
1886                 max_dist = max_dist_8x;
1887                 break;
1888         case 16:
1889                 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1890                 r600_write_value(cs, sample_locs_16x[0]);
1891                 r600_write_value(cs, sample_locs_16x[4]);
1892                 r600_write_value(cs, sample_locs_16x[8]);
1893                 r600_write_value(cs, sample_locs_16x[12]);
1894                 r600_write_value(cs, sample_locs_16x[1]);
1895                 r600_write_value(cs, sample_locs_16x[5]);
1896                 r600_write_value(cs, sample_locs_16x[9]);
1897                 r600_write_value(cs, sample_locs_16x[13]);
1898                 r600_write_value(cs, sample_locs_16x[2]);
1899                 r600_write_value(cs, sample_locs_16x[6]);
1900                 r600_write_value(cs, sample_locs_16x[10]);
1901                 r600_write_value(cs, sample_locs_16x[14]);
1902                 r600_write_value(cs, sample_locs_16x[3]);
1903                 r600_write_value(cs, sample_locs_16x[7]);
1904                 r600_write_value(cs, sample_locs_16x[11]);
1905                 r600_write_value(cs, sample_locs_16x[15]);
1906                 max_dist = max_dist_16x;
1907                 break;
1908         }
1909
1910         if (nr_samples > 1) {
1911                 unsigned log_samples = util_logbase2(nr_samples);
1912
1913                 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1914                 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1915                                      S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1916                 r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1917                                      S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1918                                      S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1919
1920                 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1921                                        S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1922                                        S_028804_PS_ITER_SAMPLES(log_samples) |
1923                                        S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1924                                        S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1925                                        S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1926                                        S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1927         } else {
1928                 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1929                 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1930                 r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1931
1932                 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1933                                        S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1934                                        S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1935         }
1936 }
1937
1938 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1939 {
1940         struct radeon_winsys_cs *cs = rctx->cs;
1941         struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1942         unsigned nr_cbufs = state->nr_cbufs;
1943         unsigned i, tl, br;
1944
1945         /* XXX support more colorbuffers once we need them */
1946         assert(nr_cbufs <= 8);
1947         if (nr_cbufs > 8)
1948                 nr_cbufs = 8;
1949
1950         /* Colorbuffers. */
1951         for (i = 0; i < nr_cbufs; i++) {
1952                 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
1953                 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
1954                                                        RADEON_USAGE_READWRITE);
1955
1956                 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
1957                 r600_write_value(cs, cb->cb_color_base);        /* R_028C60_CB_COLOR0_BASE */
1958                 r600_write_value(cs, cb->cb_color_pitch);       /* R_028C64_CB_COLOR0_PITCH */
1959                 r600_write_value(cs, cb->cb_color_slice);       /* R_028C68_CB_COLOR0_SLICE */
1960                 r600_write_value(cs, cb->cb_color_view);        /* R_028C6C_CB_COLOR0_VIEW */
1961                 r600_write_value(cs, cb->cb_color_info);        /* R_028C70_CB_COLOR0_INFO */
1962                 r600_write_value(cs, cb->cb_color_attrib);      /* R_028C74_CB_COLOR0_ATTRIB */
1963                 r600_write_value(cs, cb->cb_color_dim);         /* R_028C78_CB_COLOR0_DIM */
1964                 r600_write_value(cs, cb->cb_color_cmask);       /* R_028C7C_CB_COLOR0_CMASK */
1965                 r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1966                 r600_write_value(cs, cb->cb_color_fmask);       /* R_028C84_CB_COLOR0_FMASK */
1967                 r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1968
1969                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1970                 r600_write_value(cs, reloc);
1971
1972                 if (!rctx->keep_tiling_flags) {
1973                         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1974                         r600_write_value(cs, reloc);
1975                 }
1976
1977                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1978                 r600_write_value(cs, reloc);
1979
1980                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1981                 r600_write_value(cs, reloc);
1982
1983                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1984                 r600_write_value(cs, reloc);
1985         }
1986         /* set CB_COLOR1_INFO for possible dual-src blending */
1987         if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
1988                 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1989                                        ((struct r600_surface*)state->cbufs[0])->cb_color_info);
1990
1991                 if (!rctx->keep_tiling_flags) {
1992                         unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
1993                                                                RADEON_USAGE_READWRITE);
1994
1995                         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1996                         r600_write_value(cs, reloc);
1997                 }
1998                 i++;
1999         }
2000         if (rctx->keep_tiling_flags) {
2001                 for (; i < 8 ; i++) {
2002                         r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2003                 }
2004                 for (; i < 12; i++) {
2005                         r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
2006                 }
2007         }
2008
2009         /* ZS buffer. */
2010         if (state->zsbuf) {
2011                 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2012                 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
2013                                                        RADEON_USAGE_READWRITE);
2014
2015                 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2016                                        zb->pa_su_poly_offset_db_fmt_cntl);
2017                 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2018
2019                 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
2020                 r600_write_value(cs, zb->db_depth_info);        /* R_028040_DB_Z_INFO */
2021                 r600_write_value(cs, zb->db_stencil_info);      /* R_028044_DB_STENCIL_INFO */
2022                 r600_write_value(cs, zb->db_depth_base);        /* R_028048_DB_Z_READ_BASE */
2023                 r600_write_value(cs, zb->db_stencil_base);      /* R_02804C_DB_STENCIL_READ_BASE */
2024                 r600_write_value(cs, zb->db_depth_base);        /* R_028050_DB_Z_WRITE_BASE */
2025                 r600_write_value(cs, zb->db_stencil_base);      /* R_028054_DB_STENCIL_WRITE_BASE */
2026                 r600_write_value(cs, zb->db_depth_size);        /* R_028058_DB_DEPTH_SIZE */
2027                 r600_write_value(cs, zb->db_depth_slice);       /* R_02805C_DB_DEPTH_SLICE */
2028
2029                 if (!rctx->keep_tiling_flags) {
2030                         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
2031                         r600_write_value(cs, reloc);
2032                 }
2033
2034                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2035                 r600_write_value(cs, reloc);
2036
2037                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2038                 r600_write_value(cs, reloc);
2039
2040                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2041                 r600_write_value(cs, reloc);
2042
2043                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2044                 r600_write_value(cs, reloc);
2045         } else if (rctx->screen->info.drm_minor >= 18) {
2046                 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2047                  * Older kernels are out of luck. */
2048                 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2049                 r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2050                 r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2051         }
2052
2053         /* Framebuffer dimensions. */
2054         evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2055
2056         r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2057         r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2058         r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2059
2060         if (rctx->chip_class == EVERGREEN) {
2061                 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2062         } else {
2063                 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2064         }
2065 }
2066
2067 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
2068 {
2069         struct radeon_winsys_cs *cs = rctx->cs;
2070         struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
2071         float offset_units = state->offset_units;
2072         float offset_scale = state->offset_scale;
2073
2074         switch (state->zs_format) {
2075         case PIPE_FORMAT_Z24X8_UNORM:
2076         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2077                 offset_units *= 2.0f;
2078                 break;
2079         case PIPE_FORMAT_Z16_UNORM:
2080                 offset_units *= 4.0f;
2081                 break;
2082         default:;
2083         }
2084
2085         r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2086         r600_write_value(cs, fui(offset_scale));
2087         r600_write_value(cs, fui(offset_units));
2088         r600_write_value(cs, fui(offset_scale));
2089         r600_write_value(cs, fui(offset_units));
2090 }
2091
2092 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2093 {
2094         struct radeon_winsys_cs *cs = rctx->cs;
2095         struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2096         unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2097         unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2098
2099         r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2100         r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2101         /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2102          * will assure that the alpha-test will work even if there is
2103          * no colorbuffer bound. */
2104         r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2105 }
2106
2107 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2108 {
2109         struct radeon_winsys_cs *cs = rctx->cs;
2110         struct r600_db_state *a = (struct r600_db_state*)atom;
2111
2112         if (a->rsurf && a->rsurf->htile_enabled) {
2113                 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2114                 unsigned reloc_idx;
2115
2116                 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
2117                 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2118                 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2119                 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2120                 reloc_idx = r600_context_bo_reloc(rctx, rtex->htile, RADEON_USAGE_READWRITE);
2121                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2122                 cs->buf[cs->cdw++] = reloc_idx;
2123         } else {
2124                 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2125                 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2126         }
2127 }
2128
2129 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2130 {
2131         struct radeon_winsys_cs *cs = rctx->cs;
2132         struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2133         unsigned db_render_control = 0;
2134         unsigned db_count_control = 0;
2135         unsigned db_render_override =
2136                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2137                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2138
2139         if (a->occlusion_query_enabled) {
2140                 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2141                 if (rctx->chip_class == CAYMAN) {
2142                         db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2143                 }
2144                 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2145         }
2146         if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
2147                 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2148                 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
2149         } else {
2150                 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
2151         }
2152         if (a->flush_depthstencil_through_cb) {
2153                 assert(a->copy_depth || a->copy_stencil);
2154
2155                 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2156                                      S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2157                                      S_028000_COPY_CENTROID(1) |
2158                                      S_028000_COPY_SAMPLE(a->copy_sample);
2159         } else if (a->flush_depthstencil_in_place) {
2160                 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2161                                      S_028000_STENCIL_COMPRESS_DISABLE(1);
2162                 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2163         }
2164         if (a->htile_clear) {
2165                 /* FIXME we might want to disable cliprect here */
2166                 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2167         }
2168
2169         r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2170         r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2171         r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2172         r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2173         r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2174 }
2175
2176 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2177                                           struct r600_vertexbuf_state *state,
2178                                           unsigned resource_offset,
2179                                           unsigned pkt_flags)
2180 {
2181         struct radeon_winsys_cs *cs = rctx->cs;
2182         uint32_t dirty_mask = state->dirty_mask;
2183
2184         while (dirty_mask) {
2185                 struct pipe_vertex_buffer *vb;
2186                 struct r600_resource *rbuffer;
2187                 uint64_t va;
2188                 unsigned buffer_index = u_bit_scan(&dirty_mask);
2189
2190                 vb = &state->vb[buffer_index];
2191                 rbuffer = (struct r600_resource*)vb->buffer;
2192                 assert(rbuffer);
2193
2194                 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2195                 va += vb->buffer_offset;
2196
2197                 /* fetch resources start at index 992 */
2198                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2199                 r600_write_value(cs, (resource_offset + buffer_index) * 8);
2200                 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2201                 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2202                 r600_write_value(cs, /* RESOURCEi_WORD2 */
2203                                  S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2204                                  S_030008_STRIDE(vb->stride) |
2205                                  S_030008_BASE_ADDRESS_HI(va >> 32UL));
2206                 r600_write_value(cs, /* RESOURCEi_WORD3 */
2207                                  S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2208                                  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2209                                  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2210                                  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2211                 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2212                 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2213                 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2214                 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2215
2216                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2217                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2218         }
2219         state->dirty_mask = 0;
2220 }
2221
2222 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2223 {
2224         evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2225 }
2226
2227 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2228 {
2229         evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2230                                       RADEON_CP_PACKET3_COMPUTE_MODE);
2231 }
2232
2233 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2234                                             struct r600_constbuf_state *state,
2235                                             unsigned buffer_id_base,
2236                                             unsigned reg_alu_constbuf_size,
2237                                             unsigned reg_alu_const_cache)
2238 {
2239         struct radeon_winsys_cs *cs = rctx->cs;
2240         uint32_t dirty_mask = state->dirty_mask;
2241
2242         while (dirty_mask) {
2243                 struct pipe_constant_buffer *cb;
2244                 struct r600_resource *rbuffer;
2245                 uint64_t va;
2246                 unsigned buffer_index = ffs(dirty_mask) - 1;
2247
2248                 cb = &state->cb[buffer_index];
2249                 rbuffer = (struct r600_resource*)cb->buffer;
2250                 assert(rbuffer);
2251
2252                 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2253                 va += cb->buffer_offset;
2254
2255                 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2256                                        ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2257                 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2258
2259                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2260                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2261
2262                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2263                 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2264                 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2265                 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2266                 r600_write_value(cs, /* RESOURCEi_WORD2 */
2267                                  S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2268                                  S_030008_STRIDE(16) |
2269                                  S_030008_BASE_ADDRESS_HI(va >> 32UL));
2270                 r600_write_value(cs, /* RESOURCEi_WORD3 */
2271                                  S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2272                                  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2273                                  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2274                                  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2275                 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2276                 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2277                 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2278                 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2279
2280                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2281                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2282
2283                 dirty_mask &= ~(1 << buffer_index);
2284         }
2285         state->dirty_mask = 0;
2286 }
2287
2288 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2289 {
2290         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2291                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2292                                         R_028980_ALU_CONST_CACHE_VS_0);
2293 }
2294
2295 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2296 {
2297         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2298                                         R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2299                                         R_0289C0_ALU_CONST_CACHE_GS_0);
2300 }
2301
2302 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2303 {
2304         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2305                                        R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2306                                        R_028940_ALU_CONST_CACHE_PS_0);
2307 }
2308
2309 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2310                                          struct r600_samplerview_state *state,
2311                                          unsigned resource_id_base)
2312 {
2313         struct radeon_winsys_cs *cs = rctx->cs;
2314         uint32_t dirty_mask = state->dirty_mask;
2315
2316         while (dirty_mask) {
2317                 struct r600_pipe_sampler_view *rview;
2318                 unsigned resource_index = u_bit_scan(&dirty_mask);
2319                 unsigned reloc;
2320
2321                 rview = state->views[resource_index];
2322                 assert(rview);
2323
2324                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2325                 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2326                 r600_write_array(cs, 8, rview->tex_resource_words);
2327
2328                 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2329                                               RADEON_USAGE_READ);
2330                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2331                 r600_write_value(cs, reloc);
2332
2333                 if (!rview->skip_mip_address_reloc) {
2334                         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2335                         r600_write_value(cs, reloc);
2336                 }
2337         }
2338         state->dirty_mask = 0;
2339 }
2340
2341 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2342 {
2343         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2344 }
2345
2346 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2347 {
2348         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2349 }
2350
2351 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2352 {
2353         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2354 }
2355
2356 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2357                                 struct r600_textures_info *texinfo,
2358                                 unsigned resource_id_base,
2359                                 unsigned border_index_reg)
2360 {
2361         struct radeon_winsys_cs *cs = rctx->cs;
2362         uint32_t dirty_mask = texinfo->states.dirty_mask;
2363
2364         while (dirty_mask) {
2365                 struct r600_pipe_sampler_state *rstate;
2366                 unsigned i = u_bit_scan(&dirty_mask);
2367
2368                 rstate = texinfo->states.states[i];
2369                 assert(rstate);
2370
2371                 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2372                 r600_write_value(cs, (resource_id_base + i) * 3);
2373                 r600_write_array(cs, 3, rstate->tex_sampler_words);
2374
2375                 if (rstate->border_color_use) {
2376                         r600_write_config_reg_seq(cs, border_index_reg, 5);
2377                         r600_write_value(cs, i);
2378                         r600_write_array(cs, 4, rstate->border_color.ui);
2379                 }
2380         }
2381         texinfo->states.dirty_mask = 0;
2382 }
2383
2384 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2385 {
2386         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2387 }
2388
2389 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2390 {
2391         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2392 }
2393
2394 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2395 {
2396         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2397 }
2398
2399 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2400 {
2401         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2402         uint8_t mask = s->sample_mask;
2403
2404         r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2405                                mask | (mask << 8) | (mask << 16) | (mask << 24));
2406 }
2407
2408 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2409 {
2410         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2411         struct radeon_winsys_cs *cs = rctx->cs;
2412         uint16_t mask = s->sample_mask;
2413
2414         r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2415         r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2416         r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2417 }
2418
2419 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2420 {
2421         struct radeon_winsys_cs *cs = rctx->cs;
2422         struct r600_cso_state *state = (struct r600_cso_state*)a;
2423         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2424
2425         r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2426                                (r600_resource_va(rctx->context.screen, &shader->buffer->b.b) + shader->offset) >> 8);
2427         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2428         r600_write_value(cs, r600_context_bo_reloc(rctx, shader->buffer, RADEON_USAGE_READ));
2429 }
2430
2431 void evergreen_init_state_functions(struct r600_context *rctx)
2432 {
2433         unsigned id = 4;
2434
2435         /* !!!
2436          *  To avoid GPU lockup registers must be emited in a specific order
2437          * (no kidding ...). The order below is important and have been
2438          * partialy infered from analyzing fglrx command stream.
2439          *
2440          * Don't reorder atom without carefully checking the effect (GPU lockup
2441          * or piglit regression).
2442          * !!!
2443          */
2444
2445         r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
2446         /* shader const */
2447         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2448         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2449         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2450         /* shader program */
2451         r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2452         /* sampler */
2453         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2454         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2455         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2456         /* resources */
2457         r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2458         r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2459         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2460         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2461         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2462
2463         r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2464         r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2465
2466         if (rctx->chip_class == EVERGREEN) {
2467                 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2468         } else {
2469                 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2470         }
2471         rctx->sample_mask.sample_mask = ~0;
2472
2473         r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2474         r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2475         r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2476         r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
2477         r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2478         r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2479         r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
2480         r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
2481         r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2482         r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
2483         r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2484         r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
2485         r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2486         r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2487         r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
2488
2489         rctx->context.create_blend_state = evergreen_create_blend_state;
2490         rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2491         rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2492         rctx->context.create_sampler_state = evergreen_create_sampler_state;
2493         rctx->context.create_sampler_view = evergreen_create_sampler_view;
2494         rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2495         rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2496         rctx->context.set_scissor_state = evergreen_set_scissor_state;
2497         evergreen_init_compute_state_functions(rctx);
2498 }
2499
2500 void cayman_init_common_regs(struct r600_command_buffer *cb,
2501                              enum chip_class ctx_chip_class,
2502                              enum radeon_family ctx_family,
2503                              int ctx_drm_minor)
2504 {
2505         r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2506         r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2507         /* always set the temp clauses */
2508         r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2509
2510         r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2511         r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2512         r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2513
2514         r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2515
2516         r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2517
2518         r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2519
2520         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2521 }
2522
2523 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2524 {
2525         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2526
2527         r600_init_command_buffer(cb, 256);
2528
2529         /* This must be first. */
2530         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2531         r600_store_value(cb, 0x80000000);
2532         r600_store_value(cb, 0x80000000);
2533
2534         /* We're setting config registers here. */
2535         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2536         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2537
2538         cayman_init_common_regs(cb, rctx->chip_class,
2539                                 rctx->family, rctx->screen->info.drm_minor);
2540
2541         r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2542         r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2543
2544         r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2545         r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2546         r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2547         r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2548         r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2549         r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2550         r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2551
2552         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2553         r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2554         r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2555         r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2556         r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2557
2558         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2559         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2560         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2561         r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2562         r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2563         r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2564         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2565         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2566         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2567         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2568         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2569         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2570         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2571         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2572
2573         r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2574         r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2575         r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2576
2577         r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2578         r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2579         r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2580
2581         r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2582
2583         r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2584
2585         r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2586         r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2587         r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2588
2589         r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2590         r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2591         r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2592
2593         r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2594
2595         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2596         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2597         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2598
2599         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2600
2601         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2602
2603         r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2604
2605         r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2606         r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2607         r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2608         r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2609
2610         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2611         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2612
2613         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2614         r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2615         r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2616
2617         r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2618         r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2619         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2620
2621         r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2622         r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2623         r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2624         r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2625         r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2626
2627         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2628         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2629         r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2630
2631         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2632         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2633         r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2634
2635         r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2636         r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2637         r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2638
2639         /* to avoid GPU doing any preloading of constant from random address */
2640         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2641         r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2642         r600_store_value(cb, 0);
2643         r600_store_value(cb, 0);
2644         r600_store_value(cb, 0);
2645         r600_store_value(cb, 0);
2646         r600_store_value(cb, 0);
2647         r600_store_value(cb, 0);
2648         r600_store_value(cb, 0);
2649         r600_store_value(cb, 0);
2650         r600_store_value(cb, 0);
2651         r600_store_value(cb, 0);
2652         r600_store_value(cb, 0);
2653         r600_store_value(cb, 0);
2654         r600_store_value(cb, 0);
2655         r600_store_value(cb, 0);
2656         r600_store_value(cb, 0);
2657
2658         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2659         r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2660         r600_store_value(cb, 0);
2661         r600_store_value(cb, 0);
2662         r600_store_value(cb, 0);
2663         r600_store_value(cb, 0);
2664         r600_store_value(cb, 0);
2665         r600_store_value(cb, 0);
2666         r600_store_value(cb, 0);
2667         r600_store_value(cb, 0);
2668         r600_store_value(cb, 0);
2669         r600_store_value(cb, 0);
2670         r600_store_value(cb, 0);
2671         r600_store_value(cb, 0);
2672         r600_store_value(cb, 0);
2673         r600_store_value(cb, 0);
2674         r600_store_value(cb, 0);
2675
2676         if (rctx->screen->has_streamout) {
2677                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2678         }
2679
2680         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2681         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2682 }
2683
2684 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2685         enum chip_class ctx_chip_class,
2686         enum radeon_family ctx_family,
2687         int ctx_drm_minor)
2688 {
2689         int ps_prio;
2690         int vs_prio;
2691         int gs_prio;
2692         int es_prio;
2693
2694         int hs_prio;
2695         int cs_prio;
2696         int ls_prio;
2697
2698         int num_ps_gprs;
2699         int num_vs_gprs;
2700         int num_gs_gprs;
2701         int num_es_gprs;
2702         int num_hs_gprs;
2703         int num_ls_gprs;
2704         int num_temp_gprs;
2705
2706         unsigned tmp;
2707
2708         ps_prio = 0;
2709         vs_prio = 1;
2710         gs_prio = 2;
2711         es_prio = 3;
2712         hs_prio = 0;
2713         ls_prio = 0;
2714         cs_prio = 0;
2715
2716         num_ps_gprs = 93;
2717         num_vs_gprs = 46;
2718         num_temp_gprs = 4;
2719         num_gs_gprs = 31;
2720         num_es_gprs = 31;
2721         num_hs_gprs = 23;
2722         num_ls_gprs = 23;
2723
2724         tmp = 0;
2725         switch (ctx_family) {
2726         case CHIP_CEDAR:
2727         case CHIP_PALM:
2728         case CHIP_SUMO:
2729         case CHIP_SUMO2:
2730         case CHIP_CAICOS:
2731                 break;
2732         default:
2733                 tmp |= S_008C00_VC_ENABLE(1);
2734                 break;
2735         }
2736         tmp |= S_008C00_EXPORT_SRC_C(1);
2737         tmp |= S_008C00_CS_PRIO(cs_prio);
2738         tmp |= S_008C00_LS_PRIO(ls_prio);
2739         tmp |= S_008C00_HS_PRIO(hs_prio);
2740         tmp |= S_008C00_PS_PRIO(ps_prio);
2741         tmp |= S_008C00_VS_PRIO(vs_prio);
2742         tmp |= S_008C00_GS_PRIO(gs_prio);
2743         tmp |= S_008C00_ES_PRIO(es_prio);
2744
2745         /* enable dynamic GPR resource management */
2746         if (ctx_drm_minor >= 7) {
2747                 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2748                 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2749                 /* always set temp clauses */
2750                 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2751                 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2752                 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2753                 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2754                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2755                 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2756                                         S_028838_PS_GPRS(0x1e) |
2757                                         S_028838_VS_GPRS(0x1e) |
2758                                         S_028838_GS_GPRS(0x1e) |
2759                                         S_028838_ES_GPRS(0x1e) |
2760                                         S_028838_HS_GPRS(0x1e) |
2761                                         S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2762         } else {
2763                 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2764                 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2765
2766                 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2767                 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2768                 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2769                 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2770
2771                 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2772                 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2773                 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2774
2775                 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2776                 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2777                 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2778         }
2779
2780         r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2781                               S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2782
2783         r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2784
2785         /* The cs checker requires this register to be set. */
2786         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2787
2788         r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2789
2790         return;
2791 }
2792
2793 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2794 {
2795         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2796         int num_ps_threads;
2797         int num_vs_threads;
2798         int num_gs_threads;
2799         int num_es_threads;
2800         int num_hs_threads;
2801         int num_ls_threads;
2802
2803         int num_ps_stack_entries;
2804         int num_vs_stack_entries;
2805         int num_gs_stack_entries;
2806         int num_es_stack_entries;
2807         int num_hs_stack_entries;
2808         int num_ls_stack_entries;
2809         enum radeon_family family;
2810         unsigned tmp;
2811
2812         if (rctx->chip_class == CAYMAN) {
2813                 cayman_init_atom_start_cs(rctx);
2814                 return;
2815         }
2816
2817         r600_init_command_buffer(cb, 256);
2818
2819         /* This must be first. */
2820         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2821         r600_store_value(cb, 0x80000000);
2822         r600_store_value(cb, 0x80000000);
2823
2824         /* We're setting config registers here. */
2825         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2826         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2827
2828         evergreen_init_common_regs(cb, rctx->chip_class,
2829                                    rctx->family, rctx->screen->info.drm_minor);
2830
2831         family = rctx->family;
2832         switch (family) {
2833         case CHIP_CEDAR:
2834         default:
2835                 num_ps_threads = 96;
2836                 num_vs_threads = 16;
2837                 num_gs_threads = 16;
2838                 num_es_threads = 16;
2839                 num_hs_threads = 16;
2840                 num_ls_threads = 16;
2841                 num_ps_stack_entries = 42;
2842                 num_vs_stack_entries = 42;
2843                 num_gs_stack_entries = 42;
2844                 num_es_stack_entries = 42;
2845                 num_hs_stack_entries = 42;
2846                 num_ls_stack_entries = 42;
2847                 break;
2848         case CHIP_REDWOOD:
2849                 num_ps_threads = 128;
2850                 num_vs_threads = 20;
2851                 num_gs_threads = 20;
2852                 num_es_threads = 20;
2853                 num_hs_threads = 20;
2854                 num_ls_threads = 20;
2855                 num_ps_stack_entries = 42;
2856                 num_vs_stack_entries = 42;
2857                 num_gs_stack_entries = 42;
2858                 num_es_stack_entries = 42;
2859                 num_hs_stack_entries = 42;
2860                 num_ls_stack_entries = 42;
2861                 break;
2862         case CHIP_JUNIPER:
2863                 num_ps_threads = 128;
2864                 num_vs_threads = 20;
2865                 num_gs_threads = 20;
2866                 num_es_threads = 20;
2867                 num_hs_threads = 20;
2868                 num_ls_threads = 20;
2869                 num_ps_stack_entries = 85;
2870                 num_vs_stack_entries = 85;
2871                 num_gs_stack_entries = 85;
2872                 num_es_stack_entries = 85;
2873                 num_hs_stack_entries = 85;
2874                 num_ls_stack_entries = 85;
2875                 break;
2876         case CHIP_CYPRESS:
2877         case CHIP_HEMLOCK:
2878                 num_ps_threads = 128;
2879                 num_vs_threads = 20;
2880                 num_gs_threads = 20;
2881                 num_es_threads = 20;
2882                 num_hs_threads = 20;
2883                 num_ls_threads = 20;
2884                 num_ps_stack_entries = 85;
2885                 num_vs_stack_entries = 85;
2886                 num_gs_stack_entries = 85;
2887                 num_es_stack_entries = 85;
2888                 num_hs_stack_entries = 85;
2889                 num_ls_stack_entries = 85;
2890                 break;
2891         case CHIP_PALM:
2892                 num_ps_threads = 96;
2893                 num_vs_threads = 16;
2894                 num_gs_threads = 16;
2895                 num_es_threads = 16;
2896                 num_hs_threads = 16;
2897                 num_ls_threads = 16;
2898                 num_ps_stack_entries = 42;
2899                 num_vs_stack_entries = 42;
2900                 num_gs_stack_entries = 42;
2901                 num_es_stack_entries = 42;
2902                 num_hs_stack_entries = 42;
2903                 num_ls_stack_entries = 42;
2904                 break;
2905         case CHIP_SUMO:
2906                 num_ps_threads = 96;
2907                 num_vs_threads = 25;
2908                 num_gs_threads = 25;
2909                 num_es_threads = 25;
2910                 num_hs_threads = 25;
2911                 num_ls_threads = 25;
2912                 num_ps_stack_entries = 42;
2913                 num_vs_stack_entries = 42;
2914                 num_gs_stack_entries = 42;
2915                 num_es_stack_entries = 42;
2916                 num_hs_stack_entries = 42;
2917                 num_ls_stack_entries = 42;
2918                 break;
2919         case CHIP_SUMO2:
2920                 num_ps_threads = 96;
2921                 num_vs_threads = 25;
2922                 num_gs_threads = 25;
2923                 num_es_threads = 25;
2924                 num_hs_threads = 25;
2925                 num_ls_threads = 25;
2926                 num_ps_stack_entries = 85;
2927                 num_vs_stack_entries = 85;
2928                 num_gs_stack_entries = 85;
2929                 num_es_stack_entries = 85;
2930                 num_hs_stack_entries = 85;
2931                 num_ls_stack_entries = 85;
2932                 break;
2933         case CHIP_BARTS:
2934                 num_ps_threads = 128;
2935                 num_vs_threads = 20;
2936                 num_gs_threads = 20;
2937                 num_es_threads = 20;
2938                 num_hs_threads = 20;
2939                 num_ls_threads = 20;
2940                 num_ps_stack_entries = 85;
2941                 num_vs_stack_entries = 85;
2942                 num_gs_stack_entries = 85;
2943                 num_es_stack_entries = 85;
2944                 num_hs_stack_entries = 85;
2945                 num_ls_stack_entries = 85;
2946                 break;
2947         case CHIP_TURKS:
2948                 num_ps_threads = 128;
2949                 num_vs_threads = 20;
2950                 num_gs_threads = 20;
2951                 num_es_threads = 20;
2952                 num_hs_threads = 20;
2953                 num_ls_threads = 20;
2954                 num_ps_stack_entries = 42;
2955                 num_vs_stack_entries = 42;
2956                 num_gs_stack_entries = 42;
2957                 num_es_stack_entries = 42;
2958                 num_hs_stack_entries = 42;
2959                 num_ls_stack_entries = 42;
2960                 break;
2961         case CHIP_CAICOS:
2962                 num_ps_threads = 128;
2963                 num_vs_threads = 10;
2964                 num_gs_threads = 10;
2965                 num_es_threads = 10;
2966                 num_hs_threads = 10;
2967                 num_ls_threads = 10;
2968                 num_ps_stack_entries = 42;
2969                 num_vs_stack_entries = 42;
2970                 num_gs_stack_entries = 42;
2971                 num_es_stack_entries = 42;
2972                 num_hs_stack_entries = 42;
2973                 num_ls_stack_entries = 42;
2974                 break;
2975         }
2976
2977         tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2978         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2979         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2980         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2981
2982         r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2983         r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2984
2985         tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2986         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2987         r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2988
2989         tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2990         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2991         r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2992
2993         tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2994         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2995         r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2996
2997         tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2998         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2999         r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3000
3001         r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3002         r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3003
3004         r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3005         r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3006         r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3007         r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3008         r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3009         r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3010         r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3011
3012         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3013         r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3014         r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3015         r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3016         r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3017
3018         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3019         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3020         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3021         r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3022         r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3023         r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3024         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3025         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3026         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3027         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3028         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3029         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3030         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3031         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3032
3033         r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
3034         r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
3035         r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3036
3037         r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3038
3039         r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3040
3041         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3042         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3043         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3044
3045         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3046
3047         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3048
3049         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3050         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3051         r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3052
3053         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
3054         r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3055         r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3056
3057         r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3058         r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3059         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3060
3061         r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3062         r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3063         r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3064         r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3065
3066         r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3067         r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3068         r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3069         r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3070         r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3071
3072         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3073         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3074         r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3075
3076         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3077         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3078         r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3079
3080         r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3081         r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3082         r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3083
3084         /* to avoid GPU doing any preloading of constant from random address */
3085         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3086         r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3087         r600_store_value(cb, 0);
3088         r600_store_value(cb, 0);
3089         r600_store_value(cb, 0);
3090         r600_store_value(cb, 0);
3091         r600_store_value(cb, 0);
3092         r600_store_value(cb, 0);
3093         r600_store_value(cb, 0);
3094         r600_store_value(cb, 0);
3095         r600_store_value(cb, 0);
3096         r600_store_value(cb, 0);
3097         r600_store_value(cb, 0);
3098         r600_store_value(cb, 0);
3099         r600_store_value(cb, 0);
3100         r600_store_value(cb, 0);
3101         r600_store_value(cb, 0);
3102
3103         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3104         r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3105         r600_store_value(cb, 0);
3106         r600_store_value(cb, 0);
3107         r600_store_value(cb, 0);
3108         r600_store_value(cb, 0);
3109         r600_store_value(cb, 0);
3110         r600_store_value(cb, 0);
3111         r600_store_value(cb, 0);
3112         r600_store_value(cb, 0);
3113         r600_store_value(cb, 0);
3114         r600_store_value(cb, 0);
3115         r600_store_value(cb, 0);
3116         r600_store_value(cb, 0);
3117         r600_store_value(cb, 0);
3118         r600_store_value(cb, 0);
3119         r600_store_value(cb, 0);
3120
3121         r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
3122         r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3123         r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3124
3125         if (rctx->screen->has_streamout) {
3126                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3127         }
3128
3129         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3130         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3131 }
3132
3133 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3134 {
3135         struct r600_context *rctx = (struct r600_context *)ctx;
3136         struct r600_pipe_state *rstate = &shader->rstate;
3137         struct r600_shader *rshader = &shader->shader;
3138         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
3139         int pos_index = -1, face_index = -1;
3140         int ninterp = 0;
3141         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3142         unsigned spi_baryc_cntl, sid, tmp, idx = 0;
3143         unsigned z_export = 0, stencil_export = 0;
3144         unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3145
3146         rstate->nregs = 0;
3147
3148         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3149         for (i = 0; i < rshader->ninput; i++) {
3150                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3151                    POSITION goes via GPRs from the SC so isn't counted */
3152                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3153                         pos_index = i;
3154                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3155                         face_index = i;
3156                 else {
3157                         ninterp++;
3158                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3159                                 have_linear = TRUE;
3160                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3161                                 have_perspective = TRUE;
3162                         if (rshader->input[i].centroid)
3163                                 have_centroid = TRUE;
3164                 }
3165
3166                 sid = rshader->input[i].spi_sid;
3167
3168                 if (sid) {
3169
3170                         tmp = S_028644_SEMANTIC(sid);
3171
3172                         if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3173                                 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3174                                 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3175                                         rctx->rasterizer && rctx->rasterizer->flatshade)) {
3176                                 tmp |= S_028644_FLAT_SHADE(1);
3177                         }
3178
3179                         if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3180                             (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3181                                 tmp |= S_028644_PT_SPRITE_TEX(1);
3182                         }
3183
3184                         r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3185                                         tmp);
3186
3187                         idx++;
3188                 }
3189         }
3190
3191         for (i = 0; i < rshader->noutput; i++) {
3192                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3193                         z_export = 1;
3194                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3195                         stencil_export = 1;
3196         }
3197         if (rshader->uses_kill)
3198                 db_shader_control |= S_02880C_KILL_ENABLE(1);
3199
3200         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3201         db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3202
3203         exports_ps = 0;
3204         for (i = 0; i < rshader->noutput; i++) {
3205                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3206                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3207                         exports_ps |= 1;
3208         }
3209
3210         num_cout = rshader->nr_ps_color_exports;
3211
3212         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3213         if (!exports_ps) {
3214                 /* always at least export 1 component per pixel */
3215                 exports_ps = 2;
3216         }
3217         shader->nr_ps_color_outputs = num_cout;
3218         if (ninterp == 0) {
3219                 ninterp = 1;
3220                 have_perspective = TRUE;
3221         }
3222
3223         if (!have_perspective && !have_linear)
3224                 have_perspective = TRUE;
3225
3226         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3227                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3228                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3229         spi_input_z = 0;
3230         if (pos_index != -1) {
3231                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
3232                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3233                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3234                 spi_input_z |= 1;
3235         }
3236
3237         spi_ps_in_control_1 = 0;
3238         if (face_index != -1) {
3239                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3240                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3241         }
3242
3243         spi_baryc_cntl = 0;
3244         if (have_perspective)
3245                 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3246                                   S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3247         if (have_linear)
3248                 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3249                                   S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3250
3251         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3252                                 spi_ps_in_control_0);
3253         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3254                                 spi_ps_in_control_1);
3255         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3256                                 0);
3257         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3258         r600_pipe_state_add_reg(rstate,
3259                                 R_0286E0_SPI_BARYC_CNTL,
3260                                 spi_baryc_cntl);
3261
3262         r600_pipe_state_add_reg_bo(rstate,
3263                                 R_028840_SQ_PGM_START_PS,
3264                                 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3265                                 shader->bo, RADEON_USAGE_READ);
3266         r600_pipe_state_add_reg(rstate,
3267                                 R_028844_SQ_PGM_RESOURCES_PS,
3268                                 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3269                                 S_028844_PRIME_CACHE_ON_DRAW(1) |
3270                                 S_028844_STACK_SIZE(rshader->bc.nstack));
3271         r600_pipe_state_add_reg(rstate,
3272                                 R_02884C_SQ_PGM_EXPORTS_PS,
3273                                 exports_ps);
3274
3275         shader->db_shader_control = db_shader_control;
3276         shader->ps_depth_export = z_export | stencil_export;
3277
3278         shader->sprite_coord_enable = sprite_coord_enable;
3279         if (rctx->rasterizer)
3280                 shader->flatshade = rctx->rasterizer->flatshade;
3281 }
3282
3283 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3284 {
3285         struct r600_context *rctx = (struct r600_context *)ctx;
3286         struct r600_pipe_state *rstate = &shader->rstate;
3287         struct r600_shader *rshader = &shader->shader;
3288         unsigned spi_vs_out_id[10] = {};
3289         unsigned i, tmp, nparams = 0;
3290
3291         /* clear previous register */
3292         rstate->nregs = 0;
3293
3294         for (i = 0; i < rshader->noutput; i++) {
3295                 if (rshader->output[i].spi_sid) {
3296                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3297                         spi_vs_out_id[nparams / 4] |= tmp;
3298                         nparams++;
3299                 }
3300         }
3301
3302         for (i = 0; i < 10; i++) {
3303                 r600_pipe_state_add_reg(rstate,
3304                                         R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3305                                         spi_vs_out_id[i]);
3306         }
3307
3308         /* Certain attributes (position, psize, etc.) don't count as params.
3309          * VS is required to export at least one param and r600_shader_from_tgsi()
3310          * takes care of adding a dummy export.
3311          */
3312         if (nparams < 1)
3313                 nparams = 1;
3314
3315         r600_pipe_state_add_reg(rstate,
3316                         R_0286C4_SPI_VS_OUT_CONFIG,
3317                         S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3318         r600_pipe_state_add_reg(rstate,
3319                         R_028860_SQ_PGM_RESOURCES_VS,
3320                         S_028860_NUM_GPRS(rshader->bc.ngpr) |
3321                         S_028860_STACK_SIZE(rshader->bc.nstack));
3322         r600_pipe_state_add_reg_bo(rstate,
3323                         R_02885C_SQ_PGM_START_VS,
3324                         r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3325                         shader->bo, RADEON_USAGE_READ);
3326
3327         shader->pa_cl_vs_out_cntl =
3328                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3329                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3330                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3331                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3332 }
3333
3334 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3335 {
3336         struct pipe_blend_state blend;
3337
3338         memset(&blend, 0, sizeof(blend));
3339         blend.independent_blend_enable = true;
3340         blend.rt[0].colormask = 0xf;
3341         return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3342 }
3343
3344 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3345 {
3346         struct pipe_blend_state blend;
3347
3348         memset(&blend, 0, sizeof(blend));
3349         blend.independent_blend_enable = true;
3350         blend.rt[0].colormask = 0xf;
3351         return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3352 }
3353
3354 void *evergreen_create_fmask_decompress_blend(struct r600_context *rctx)
3355 {
3356         struct pipe_blend_state blend;
3357
3358         memset(&blend, 0, sizeof(blend));
3359         blend.independent_blend_enable = true;
3360         blend.rt[0].colormask = 0xf;
3361         return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_FMASK_DECOMPRESS);
3362 }
3363
3364 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3365 {
3366         struct pipe_depth_stencil_alpha_state dsa = {{0}};
3367
3368         return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3369 }
3370
3371 void evergreen_update_db_shader_control(struct r600_context * rctx)
3372 {
3373         bool dual_export = rctx->framebuffer.export_16bpc &&
3374                            !rctx->ps_shader->current->ps_depth_export;
3375
3376         unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3377                         S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3378                         S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3379                                                                 V_02880C_EXPORT_DB_FULL) |
3380                         S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3381
3382         if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3383                 rctx->db_misc_state.db_shader_control = db_shader_control;
3384                 rctx->db_misc_state.atom.dirty = true;
3385         }
3386 }