src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_formats.h"
  24 #include "r600_shader.h"
  25 #include "evergreend.h"
  26
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_framebuffer.h"
  31 #include "util/u_dual_blend.h"
  32 #include "evergreen_compute.h"
  33 #include "util/u_math.h"
  34
  35 static inline unsigned evergreen_array_mode(unsigned mode)
  36 {
  37         switch (mode) {
  38         case RADEON_SURF_MODE_LINEAR_ALIGNED:   return V_028C70_ARRAY_LINEAR_ALIGNED;
  39                 break;
  40         case RADEON_SURF_MODE_1D:               return V_028C70_ARRAY_1D_TILED_THIN1;
  41                 break;
  42         case RADEON_SURF_MODE_2D:               return V_028C70_ARRAY_2D_TILED_THIN1;
  43         default:
  44         case RADEON_SURF_MODE_LINEAR:           return V_028C70_ARRAY_LINEAR_GENERAL;
  45         }
  46 }
  47
  48 static uint32_t eg_num_banks(uint32_t nbanks)
  49 {
  50         switch (nbanks) {
  51         case 2:
  52                 return 0;
  53         case 4:
  54                 return 1;
  55         case 8:
  56         default:
  57                 return 2;
  58         case 16:
  59                 return 3;
  60         }
  61 }
  62
  63
  64 static unsigned eg_tile_split(unsigned tile_split)
  65 {
  66         switch (tile_split) {
  67         case 64:        tile_split = 0; break;
  68         case 128:       tile_split = 1; break;
  69         case 256:       tile_split = 2; break;
  70         case 512:       tile_split = 3; break;
  71         default:
  72         case 1024:      tile_split = 4; break;
  73         case 2048:      tile_split = 5; break;
  74         case 4096:      tile_split = 6; break;
  75         }
  76         return tile_split;
  77 }
  78
  79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
  80 {
  81         switch (macro_tile_aspect) {
  82         default:
  83         case 1: macro_tile_aspect = 0;  break;
  84         case 2: macro_tile_aspect = 1;  break;
  85         case 4: macro_tile_aspect = 2;  break;
  86         case 8: macro_tile_aspect = 3;  break;
  87         }
  88         return macro_tile_aspect;
  89 }
  90
  91 static unsigned eg_bank_wh(unsigned bankwh)
  92 {
  93         switch (bankwh) {
  94         default:
  95         case 1: bankwh = 0;     break;
  96         case 2: bankwh = 1;     break;
  97         case 4: bankwh = 2;     break;
  98         case 8: bankwh = 3;     break;
  99         }
 100         return bankwh;
 101 }
 102
 103 static uint32_t r600_translate_blend_function(int blend_func)
 104 {
 105         switch (blend_func) {
 106         case PIPE_BLEND_ADD:
 107                 return V_028780_COMB_DST_PLUS_SRC;
 108         case PIPE_BLEND_SUBTRACT:
 109                 return V_028780_COMB_SRC_MINUS_DST;
 110         case PIPE_BLEND_REVERSE_SUBTRACT:
 111                 return V_028780_COMB_DST_MINUS_SRC;
 112         case PIPE_BLEND_MIN:
 113                 return V_028780_COMB_MIN_DST_SRC;
 114         case PIPE_BLEND_MAX:
 115                 return V_028780_COMB_MAX_DST_SRC;
 116         default:
 117                 R600_ERR("Unknown blend function %d\n", blend_func);
 118                 assert(0);
 119                 break;
 120         }
 121         return 0;
 122 }
 123
 124 static uint32_t r600_translate_blend_factor(int blend_fact)
 125 {
 126         switch (blend_fact) {
 127         case PIPE_BLENDFACTOR_ONE:
 128                 return V_028780_BLEND_ONE;
 129         case PIPE_BLENDFACTOR_SRC_COLOR:
 130                 return V_028780_BLEND_SRC_COLOR;
 131         case PIPE_BLENDFACTOR_SRC_ALPHA:
 132                 return V_028780_BLEND_SRC_ALPHA;
 133         case PIPE_BLENDFACTOR_DST_ALPHA:
 134                 return V_028780_BLEND_DST_ALPHA;
 135         case PIPE_BLENDFACTOR_DST_COLOR:
 136                 return V_028780_BLEND_DST_COLOR;
 137         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 138                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 139         case PIPE_BLENDFACTOR_CONST_COLOR:
 140                 return V_028780_BLEND_CONST_COLOR;
 141         case PIPE_BLENDFACTOR_CONST_ALPHA:
 142                 return V_028780_BLEND_CONST_ALPHA;
 143         case PIPE_BLENDFACTOR_ZERO:
 144                 return V_028780_BLEND_ZERO;
 145         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 146                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 147         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 148                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 149         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 150                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 151         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 152                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 153         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 154                 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
 155         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 156                 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
 157         case PIPE_BLENDFACTOR_SRC1_COLOR:
 158                 return V_028780_BLEND_SRC1_COLOR;
 159         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 160                 return V_028780_BLEND_SRC1_ALPHA;
 161         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 162                 return V_028780_BLEND_INV_SRC1_COLOR;
 163         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 164                 return V_028780_BLEND_INV_SRC1_ALPHA;
 165         default:
 166                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 167                 assert(0);
 168                 break;
 169         }
 170         return 0;
 171 }
 172
 173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
 174 {
 175         switch (dim) {
 176         default:
 177         case PIPE_TEXTURE_1D:
 178                 return V_030000_SQ_TEX_DIM_1D;
 179         case PIPE_TEXTURE_1D_ARRAY:
 180                 return V_030000_SQ_TEX_DIM_1D_ARRAY;
 181         case PIPE_TEXTURE_2D:
 182         case PIPE_TEXTURE_RECT:
 183                 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
 184                                         V_030000_SQ_TEX_DIM_2D;
 185         case PIPE_TEXTURE_2D_ARRAY:
 186                 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
 187                                         V_030000_SQ_TEX_DIM_2D_ARRAY;
 188         case PIPE_TEXTURE_3D:
 189                 return V_030000_SQ_TEX_DIM_3D;
 190         case PIPE_TEXTURE_CUBE:
 191         case PIPE_TEXTURE_CUBE_ARRAY:
 192                 return V_030000_SQ_TEX_DIM_CUBEMAP;
 193         }
 194 }
 195
 196 static uint32_t r600_translate_dbformat(enum pipe_format format)
 197 {
 198         switch (format) {
 199         case PIPE_FORMAT_Z16_UNORM:
 200                 return V_028040_Z_16;
 201         case PIPE_FORMAT_Z24X8_UNORM:
 202         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 203         case PIPE_FORMAT_X8Z24_UNORM:
 204         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 205                 return V_028040_Z_24;
 206         case PIPE_FORMAT_Z32_FLOAT:
 207         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 208                 return V_028040_Z_32_FLOAT;
 209         default:
 210                 return ~0U;
 211         }
 212 }
 213
 214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 215 {
 216         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 217 }
 218
 219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
 220 {
 221         return r600_translate_colorformat(chip, format) != ~0U &&
 222                 r600_translate_colorswap(format) != ~0U;
 223 }
 224
 225 static bool r600_is_zs_format_supported(enum pipe_format format)
 226 {
 227         return r600_translate_dbformat(format) != ~0U;
 228 }
 229
 230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 231                                       enum pipe_format format,
 232                                       enum pipe_texture_target target,
 233                                       unsigned sample_count,
 234                                       unsigned usage)
 235 {
 236         struct r600_screen *rscreen = (struct r600_screen*)screen;
 237         unsigned retval = 0;
 238
 239         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 240                 R600_ERR("r600: unsupported texture type %d\n", target);
 241                 return FALSE;
 242         }
 243
 244         if (!util_format_is_supported(format, usage))
 245                 return FALSE;
 246
 247         if (sample_count > 1) {
 248                 if (!rscreen->has_msaa)
 249                         return FALSE;
 250
 251                 switch (sample_count) {
 252                 case 2:
 253                 case 4:
 254                 case 8:
 255                         break;
 256                 default:
 257                         return FALSE;
 258                 }
 259         }
 260
 261         if (usage & PIPE_BIND_SAMPLER_VIEW) {
 262                 if (target == PIPE_BUFFER) {
 263                         if (r600_is_vertex_format_supported(format))
 264                                 retval |= PIPE_BIND_SAMPLER_VIEW;
 265                 } else {
 266                         if (r600_is_sampler_format_supported(screen, format))
 267                                 retval |= PIPE_BIND_SAMPLER_VIEW;
 268                 }
 269         }
 270
 271         if ((usage & (PIPE_BIND_RENDER_TARGET |
 272                       PIPE_BIND_DISPLAY_TARGET |
 273                       PIPE_BIND_SCANOUT |
 274                       PIPE_BIND_SHARED |
 275                       PIPE_BIND_BLENDABLE)) &&
 276             r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
 277                 retval |= usage &
 278                           (PIPE_BIND_RENDER_TARGET |
 279                            PIPE_BIND_DISPLAY_TARGET |
 280                            PIPE_BIND_SCANOUT |
 281                            PIPE_BIND_SHARED);
 282                 if (!util_format_is_pure_integer(format) &&
 283                     !util_format_is_depth_or_stencil(format))
 284                         retval |= usage & PIPE_BIND_BLENDABLE;
 285         }
 286
 287         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 288             r600_is_zs_format_supported(format)) {
 289                 retval |= PIPE_BIND_DEPTH_STENCIL;
 290         }
 291
 292         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 293             r600_is_vertex_format_supported(format)) {
 294                 retval |= PIPE_BIND_VERTEX_BUFFER;
 295         }
 296
 297         if (usage & PIPE_BIND_TRANSFER_READ)
 298                 retval |= PIPE_BIND_TRANSFER_READ;
 299         if (usage & PIPE_BIND_TRANSFER_WRITE)
 300                 retval |= PIPE_BIND_TRANSFER_WRITE;
 301
 302         return retval == usage;
 303 }
 304
 305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
 306                                                const struct pipe_blend_state *state, int mode)
 307 {
 308         uint32_t color_control = 0, target_mask = 0;
 309         struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
 310
 311         if (!blend) {
 312                 return NULL;
 313         }
 314
 315         r600_init_command_buffer(&blend->buffer, 20);
 316         r600_init_command_buffer(&blend->buffer_no_blend, 20);
 317
 318         if (state->logicop_enable) {
 319                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 320         } else {
 321                 color_control |= (0xcc << 16);
 322         }
 323         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 324         if (state->independent_blend_enable) {
 325                 for (int i = 0; i < 8; i++) {
 326                         target_mask |= (state->rt[i].colormask << (4 * i));
 327                 }
 328         } else {
 329                 for (int i = 0; i < 8; i++) {
 330                         target_mask |= (state->rt[0].colormask << (4 * i));
 331                 }
 332         }
 333
 334         /* only have dual source on MRT0 */
 335         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 336         blend->cb_target_mask = target_mask;
 337         blend->alpha_to_one = state->alpha_to_one;
 338
 339         if (target_mask)
 340                 color_control |= S_028808_MODE(mode);
 341         else
 342                 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 343
 344
 345         r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
 346         r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
 347                                S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 348                                S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
 349                                S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
 350                                S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
 351                                S_028B70_ALPHA_TO_MASK_OFFSET3(2));
 352         r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
 353
 354         /* Copy over the dwords set so far into buffer_no_blend.
 355          * Only the CB_BLENDi_CONTROL registers must be set after this. */
 356         memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
 357         blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
 358
 359         for (int i = 0; i < 8; i++) {
 360                 /* state->rt entries > 0 only written if independent blending */
 361                 const int j = state->independent_blend_enable ? i : 0;
 362
 363                 unsigned eqRGB = state->rt[j].rgb_func;
 364                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 365                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 366                 unsigned eqA = state->rt[j].alpha_func;
 367                 unsigned srcA = state->rt[j].alpha_src_factor;
 368                 unsigned dstA = state->rt[j].alpha_dst_factor;
 369                 uint32_t bc = 0;
 370
 371                 r600_store_value(&blend->buffer_no_blend, 0);
 372
 373                 if (!state->rt[j].blend_enable) {
 374                         r600_store_value(&blend->buffer, 0);
 375                         continue;
 376                 }
 377
 378                 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
 379                 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 380                 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 381                 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 382
 383                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 384                         bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
 385                         bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 386                         bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 387                         bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 388                 }
 389                 r600_store_value(&blend->buffer, bc);
 390         }
 391         return blend;
 392 }
 393
 394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
 395                                         const struct pipe_blend_state *state)
 396 {
 397
 398         return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
 399 }
 400
 401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 402                                    const struct pipe_depth_stencil_alpha_state *state)
 403 {
 404         unsigned db_depth_control, alpha_test_control, alpha_ref;
 405         struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
 406
 407         if (!dsa) {
 408                 return NULL;
 409         }
 410
 411         r600_init_command_buffer(&dsa->buffer, 3);
 412
 413         dsa->valuemask[0] = state->stencil[0].valuemask;
 414         dsa->valuemask[1] = state->stencil[1].valuemask;
 415         dsa->writemask[0] = state->stencil[0].writemask;
 416         dsa->writemask[1] = state->stencil[1].writemask;
 417         dsa->zwritemask = state->depth.writemask;
 418
 419         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 420                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 421                 S_028800_ZFUNC(state->depth.func);
 422
 423         /* stencil */
 424         if (state->stencil[0].enabled) {
 425                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 426                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 427                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 428                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 429                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 430
 431                 if (state->stencil[1].enabled) {
 432                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 433                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 434                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 435                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 436                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 437                 }
 438         }
 439
 440         /* alpha */
 441         alpha_test_control = 0;
 442         alpha_ref = 0;
 443         if (state->alpha.enabled) {
 444                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 445                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 446                 alpha_ref = fui(state->alpha.ref_value);
 447         }
 448         dsa->sx_alpha_test_control = alpha_test_control & 0xff;
 449         dsa->alpha_ref = alpha_ref;
 450
 451         /* misc */
 452         r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 453         return dsa;
 454 }
 455
 456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 457                                         const struct pipe_rasterizer_state *state)
 458 {
 459         struct r600_context *rctx = (struct r600_context *)ctx;
 460         unsigned tmp, spi_interp;
 461         float psize_min, psize_max;
 462         struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
 463
 464         if (!rs) {
 465                 return NULL;
 466         }
 467
 468         r600_init_command_buffer(&rs->buffer, 30);
 469
 470         rs->flatshade = state->flatshade;
 471         rs->sprite_coord_enable = state->sprite_coord_enable;
 472         rs->two_side = state->light_twoside;
 473         rs->clip_plane_enable = state->clip_plane_enable;
 474         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 475                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 476                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 477         rs->pa_cl_clip_cntl =
 478                 S_028810_PS_UCP_MODE(3) |
 479                 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
 480                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 481                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 482                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
 483                 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
 484         rs->multisample_enable = state->multisample;
 485
 486         /* offset */
 487         rs->offset_units = state->offset_units;
 488         rs->offset_scale = state->offset_scale * 16.0f;
 489         rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
 490
 491         if (state->point_size_per_vertex) {
 492                 psize_min = util_get_min_point_size(state);
 493                 psize_max = 8192;
 494         } else {
 495                 /* Force the point size to be as if the vertex output was disabled. */
 496                 psize_min = state->point_size;
 497                 psize_max = state->point_size;
 498         }
 499
 500         spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
 501         if (state->sprite_coord_enable) {
 502                 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
 503                               S_0286D4_PNT_SPRITE_OVRD_X(2) |
 504                               S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 505                               S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 506                               S_0286D4_PNT_SPRITE_OVRD_W(1);
 507                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 508                         spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 509                 }
 510         }
 511
 512         r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
 513         /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
 514         tmp = r600_pack_float_12p4(state->point_size/2);
 515         r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
 516                          S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 517         r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
 518                          S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 519                          S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
 520         r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
 521                          S_028A08_WIDTH((unsigned)(state->line_width * 8)));
 522
 523         r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
 524         r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
 525                                S_028A48_MSAA_ENABLE(state->multisample) |
 526                                S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
 527                                S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
 528
 529         if (rctx->b.chip_class == CAYMAN) {
 530                 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
 531                                        S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
 532                                        S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 533         } else {
 534                 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
 535                                        S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
 536                                        S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 537         }
 538
 539         r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 540         r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
 541                                S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 542                                S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 543                                S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 544                                S_028814_FACE(!state->front_ccw) |
 545                                S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
 546                                S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
 547                                S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
 548                                S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
 549                                                   state->fill_back != PIPE_POLYGON_MODE_FILL) |
 550                                S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 551                                S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
 552         return rs;
 553 }
 554
 555 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 556                                         const struct pipe_sampler_state *state)
 557 {
 558         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 559         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
 560
 561         if (!ss) {
 562                 return NULL;
 563         }
 564
 565         ss->border_color_use = sampler_state_needs_border_color(state);
 566
 567         /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
 568         ss->tex_sampler_words[0] =
 569                 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 570                 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 571                 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 572                 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
 573                 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 574                 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 575                 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 576                 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 577                 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
 578         /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
 579         ss->tex_sampler_words[1] =
 580                 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
 581                 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
 582         /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
 583         ss->tex_sampler_words[2] =
 584                 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
 585                 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
 586                 S_03C008_TYPE(1);
 587
 588         if (ss->border_color_use) {
 589                 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
 590         }
 591         return ss;
 592 }
 593
 594 static struct pipe_sampler_view *
 595 texture_buffer_sampler_view(struct r600_context *rctx,
 596                             struct r600_pipe_sampler_view *view,
 597                             unsigned width0, unsigned height0)
 598
 599 {
 600         struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
 601         uint64_t va;
 602         int stride = util_format_get_blocksize(view->base.format);
 603         unsigned format, num_format, format_comp, endian;
 604         unsigned swizzle_res;
 605         unsigned char swizzle[4];
 606         const struct util_format_description *desc;
 607         unsigned offset = view->base.u.buf.first_element * stride;
 608         unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
 609
 610         swizzle[0] = view->base.swizzle_r;
 611         swizzle[1] = view->base.swizzle_g;
 612         swizzle[2] = view->base.swizzle_b;
 613         swizzle[3] = view->base.swizzle_a;
 614
 615         r600_vertex_data_type(view->base.format,
 616                               &format, &num_format, &format_comp,
 617                               &endian);
 618
 619         desc = util_format_description(view->base.format);
 620
 621         swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
 622
 623         va = tmp->resource.gpu_address + offset;
 624         view->tex_resource = &tmp->resource;
 625
 626         view->skip_mip_address_reloc = true;
 627         view->tex_resource_words[0] = va;
 628         view->tex_resource_words[1] = size - 1;
 629         view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
 630                 S_030008_STRIDE(stride) |
 631                 S_030008_DATA_FORMAT(format) |
 632                 S_030008_NUM_FORMAT_ALL(num_format) |
 633                 S_030008_FORMAT_COMP_ALL(format_comp) |
 634                 S_030008_ENDIAN_SWAP(endian);
 635         view->tex_resource_words[3] = swizzle_res;
 636         /*
 637          * in theory dword 4 is for number of elements, for use with resinfo,
 638          * but it seems to utterly fail to work, the amd gpu shader analyser
 639          * uses a const buffer to store the element sizes for buffer txq
 640          */
 641         view->tex_resource_words[4] = 0;
 642         view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
 643         view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
 644
 645         if (tmp->resource.gpu_address)
 646                 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
 647         return &view->base;
 648 }
 649
 650 struct pipe_sampler_view *
 651 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 652                                      struct pipe_resource *texture,
 653                                      const struct pipe_sampler_view *state,
 654                                      unsigned width0, unsigned height0,
 655                                      unsigned force_level)
 656 {
 657         struct r600_context *rctx = (struct r600_context*)ctx;
 658         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 659         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
 660         struct r600_texture *tmp = (struct r600_texture*)texture;
 661         unsigned format, endian;
 662         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 663         unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
 664         unsigned height, depth, width;
 665         unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
 666         enum pipe_format pipe_format = state->format;
 667         struct radeon_surf_level *surflevel;
 668         unsigned base_level, first_level, last_level;
 669         unsigned dim, last_layer;
 670         uint64_t va;
 671
 672         if (!view)
 673                 return NULL;
 674
 675         /* initialize base object */
 676         view->base = *state;
 677         view->base.texture = NULL;
 678         pipe_reference(NULL, &texture->reference);
 679         view->base.texture = texture;
 680         view->base.reference.count = 1;
 681         view->base.context = ctx;
 682
 683         if (state->target == PIPE_BUFFER)
 684                 return texture_buffer_sampler_view(rctx, view, width0, height0);
 685
 686         swizzle[0] = state->swizzle_r;
 687         swizzle[1] = state->swizzle_g;
 688         swizzle[2] = state->swizzle_b;
 689         swizzle[3] = state->swizzle_a;
 690
 691         tile_split = tmp->surface.tile_split;
 692         surflevel = tmp->surface.level;
 693
 694         /* Texturing with separate depth and stencil. */
 695         if (tmp->is_depth && !tmp->is_flushing_texture) {
 696                 switch (pipe_format) {
 697                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 698                         pipe_format = PIPE_FORMAT_Z32_FLOAT;
 699                         break;
 700                 case PIPE_FORMAT_X8Z24_UNORM:
 701                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 702                         /* Z24 is always stored like this. */
 703                         pipe_format = PIPE_FORMAT_Z24X8_UNORM;
 704                         break;
 705                 case PIPE_FORMAT_X24S8_UINT:
 706                 case PIPE_FORMAT_S8X24_UINT:
 707                 case PIPE_FORMAT_X32_S8X24_UINT:
 708                         pipe_format = PIPE_FORMAT_S8_UINT;
 709                         tile_split = tmp->surface.stencil_tile_split;
 710                         surflevel = tmp->surface.stencil_level;
 711                         break;
 712                 default:;
 713                 }
 714         }
 715
 716         format = r600_translate_texformat(ctx->screen, pipe_format,
 717                                           swizzle,
 718                                           &word4, &yuv_format);
 719         assert(format != ~0);
 720         if (format == ~0) {
 721                 FREE(view);
 722                 return NULL;
 723         }
 724
 725         endian = r600_colorformat_endian_swap(format);
 726
 727         base_level = 0;
 728         first_level = state->u.tex.first_level;
 729         last_level = state->u.tex.last_level;
 730         width = width0;
 731         height = height0;
 732         depth = texture->depth0;
 733
 734         if (force_level) {
 735                 base_level = force_level;
 736                 first_level = 0;
 737                 last_level = 0;
 738                 width = u_minify(width, force_level);
 739                 height = u_minify(height, force_level);
 740                 depth = u_minify(depth, force_level);
 741         }
 742
 743         pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
 744         non_disp_tiling = tmp->non_disp_tiling;
 745
 746         switch (surflevel[base_level].mode) {
 747         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 748                 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
 749                 break;
 750         case RADEON_SURF_MODE_2D:
 751                 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
 752                 break;
 753         case RADEON_SURF_MODE_1D:
 754                 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
 755                 break;
 756         case RADEON_SURF_MODE_LINEAR:
 757         default:
 758                 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
 759                 break;
 760         }
 761         macro_aspect = tmp->surface.mtilea;
 762         bankw = tmp->surface.bankw;
 763         bankh = tmp->surface.bankh;
 764         tile_split = eg_tile_split(tile_split);
 765         macro_aspect = eg_macro_tile_aspect(macro_aspect);
 766         bankw = eg_bank_wh(bankw);
 767         bankh = eg_bank_wh(bankh);
 768         fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
 769
 770         /* 128 bit formats require tile type = 1 */
 771         if (rscreen->b.chip_class == CAYMAN) {
 772                 if (util_format_get_blocksize(pipe_format) >= 16)
 773                         non_disp_tiling = 1;
 774         }
 775         nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
 776
 777         if (state->target == PIPE_TEXTURE_1D_ARRAY) {
 778                 height = 1;
 779                 depth = texture->array_size;
 780         } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
 781                 depth = texture->array_size;
 782         } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
 783                 depth = texture->array_size / 6;
 784
 785         va = tmp->resource.gpu_address;
 786
 787         if (state->format == PIPE_FORMAT_X24S8_UINT ||
 788             state->format == PIPE_FORMAT_S8X24_UINT ||
 789             state->format == PIPE_FORMAT_X32_S8X24_UINT ||
 790             state->format == PIPE_FORMAT_S8_UINT)
 791                 view->is_stencil_sampler = true;
 792
 793         view->tex_resource = &tmp->resource;
 794
 795         /* array type views and views into array types need to use layer offset */
 796         dim = state->target;
 797         if (state->target != PIPE_TEXTURE_CUBE)
 798                 dim = MAX2(state->target, texture->target);
 799
 800         view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
 801                                        S_030000_PITCH((pitch / 8) - 1) |
 802                                        S_030000_TEX_WIDTH(width - 1));
 803         if (rscreen->b.chip_class == CAYMAN)
 804                 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
 805         else
 806                 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
 807         view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
 808                                        S_030004_TEX_DEPTH(depth - 1) |
 809                                        S_030004_ARRAY_MODE(array_mode));
 810         view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
 811
 812         /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
 813         if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
 814                 if (tmp->is_depth) {
 815                         /* disable FMASK (0 = disabled) */
 816                         view->tex_resource_words[3] = 0;
 817                         view->skip_mip_address_reloc = true;
 818                 } else {
 819                         /* FMASK should be in MIP_ADDRESS for multisample textures */
 820                         view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
 821                 }
 822         } else if (last_level && texture->nr_samples <= 1) {
 823                 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
 824         } else {
 825                 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
 826         }
 827
 828         last_layer = state->u.tex.last_layer;
 829         if (state->target != texture->target && depth == 1) {
 830                 last_layer = state->u.tex.first_layer;
 831         }
 832         view->tex_resource_words[4] = (word4 |
 833                                        S_030010_ENDIAN_SWAP(endian));
 834         view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
 835                                       S_030014_LAST_ARRAY(last_layer);
 836         view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
 837
 838         if (texture->nr_samples > 1) {
 839                 unsigned log_samples = util_logbase2(texture->nr_samples);
 840                 if (rscreen->b.chip_class == CAYMAN) {
 841                         view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
 842                 }
 843                 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
 844                 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
 845                 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
 846         } else {
 847                 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
 848                 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
 849                 /* aniso max 16 samples */
 850                 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
 851         }
 852
 853         view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
 854                                       S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
 855                                       S_03001C_BANK_WIDTH(bankw) |
 856                                       S_03001C_BANK_HEIGHT(bankh) |
 857                                       S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
 858                                       S_03001C_NUM_BANKS(nbanks) |
 859                                       S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
 860         return &view->base;
 861 }
 862
 863 static struct pipe_sampler_view *
 864 evergreen_create_sampler_view(struct pipe_context *ctx,
 865                               struct pipe_resource *tex,
 866                               const struct pipe_sampler_view *state)
 867 {
 868         return evergreen_create_sampler_view_custom(ctx, tex, state,
 869                                                     tex->width0, tex->height0, 0);
 870 }
 871
 872 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
 873 {
 874         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 875         struct r600_config_state *a = (struct r600_config_state*)atom;
 876
 877         radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
 878         if (a->dyn_gpr_enabled) {
 879                 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
 880                 radeon_emit(cs, 0);
 881                 radeon_emit(cs, 0);
 882         } else {
 883                 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
 884                 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
 885                 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
 886         }
 887         radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
 888         if (a->dyn_gpr_enabled) {
 889                 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
 890                                        S_028838_PS_GPRS(0x1e) |
 891                                        S_028838_VS_GPRS(0x1e) |
 892                                        S_028838_GS_GPRS(0x1e) |
 893                                        S_028838_ES_GPRS(0x1e) |
 894                                        S_028838_HS_GPRS(0x1e) |
 895                                        S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
 896         }
 897 }
 898
 899 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
 900 {
 901         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 902         struct pipe_clip_state *state = &rctx->clip_state.state;
 903
 904         radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
 905         radeon_emit_array(cs, (unsigned*)state, 6*4);
 906 }
 907
 908 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
 909                                          const struct pipe_poly_stipple *state)
 910 {
 911 }
 912
 913 static void evergreen_get_scissor_rect(struct r600_context *rctx,
 914                                        unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
 915                                        uint32_t *tl, uint32_t *br)
 916 {
 917         /* EG hw workaround */
 918         if (br_x == 0)
 919                 tl_x = 1;
 920         if (br_y == 0)
 921                 tl_y = 1;
 922
 923         /* cayman hw workaround */
 924         if (rctx->b.chip_class == CAYMAN) {
 925                 if (br_x == 1 && br_y == 1)
 926                         br_x = 2;
 927         }
 928
 929         *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
 930         *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
 931 }
 932
 933 static void evergreen_set_scissor_states(struct pipe_context *ctx,
 934                                          unsigned start_slot,
 935                                          unsigned num_scissors,
 936                                         const struct pipe_scissor_state *state)
 937 {
 938         struct r600_context *rctx = (struct r600_context *)ctx;
 939         struct r600_scissor_state *rstate = &rctx->scissor;
 940         int i;
 941
 942         for (i = start_slot; i < start_slot + num_scissors; i++)
 943                 rstate->scissor[i] = state[i - start_slot];
 944         rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
 945         rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
 946         r600_mark_atom_dirty(rctx, &rstate->atom);
 947 }
 948
 949 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
 950 {
 951         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 952         struct r600_scissor_state *rstate = &rctx->scissor;
 953         struct pipe_scissor_state *state;
 954         uint32_t dirty_mask;
 955         unsigned i, offset;
 956         uint32_t tl, br;
 957
 958         dirty_mask = rstate->dirty_mask;
 959         while (dirty_mask != 0) {
 960                 i = u_bit_scan(&dirty_mask);
 961                 state = &rstate->scissor[i];
 962                 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
 963
 964                 offset = i * 4 * 2;
 965                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
 966                 radeon_emit(cs, tl);
 967                 radeon_emit(cs, br);
 968         }
 969         rstate->dirty_mask = 0;
 970         rstate->atom.num_dw = 0;
 971 }
 972
 973 /**
 974  * This function intializes the CB* register values for RATs.  It is meant
 975  * to be used for 1D aligned buffers that do not have an associated
 976  * radeon_surf.
 977  */
 978 void evergreen_init_color_surface_rat(struct r600_context *rctx,
 979                                         struct r600_surface *surf)
 980 {
 981         struct pipe_resource *pipe_buffer = surf->base.texture;
 982         unsigned format = r600_translate_colorformat(rctx->b.chip_class,
 983                                                      surf->base.format);
 984         unsigned endian = r600_colorformat_endian_swap(format);
 985         unsigned swap = r600_translate_colorswap(surf->base.format);
 986         unsigned block_size =
 987                 align(util_format_get_blocksize(pipe_buffer->format), 4);
 988         unsigned pitch_alignment =
 989                 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
 990         unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
 991
 992         surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
 993
 994         surf->cb_color_pitch = (pitch / 8) - 1;
 995
 996         surf->cb_color_slice = 0;
 997
 998         surf->cb_color_view = 0;
 999
1000         surf->cb_color_info =
1001                   S_028C70_ENDIAN(endian)
1002                 | S_028C70_FORMAT(format)
1003                 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1004                 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1005                 | S_028C70_COMP_SWAP(swap)
1006                 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1007                                             * are using NUMBER_UINT */
1008                 | S_028C70_RAT(1)
1009                 ;
1010
1011         surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1012
1013         /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1014          * elements. */
1015         surf->cb_color_dim = pipe_buffer->width0;
1016
1017         /* Set the buffer range the GPU will have access to: */
1018         util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1019                        0, pipe_buffer->width0);
1020
1021         surf->cb_color_fmask = surf->cb_color_base;
1022         surf->cb_color_fmask_slice = 0;
1023 }
1024
1025 void evergreen_init_color_surface(struct r600_context *rctx,
1026                                   struct r600_surface *surf)
1027 {
1028         struct r600_screen *rscreen = rctx->screen;
1029         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1030         unsigned level = surf->base.u.tex.level;
1031         unsigned pitch, slice;
1032         unsigned color_info, color_attrib, color_dim = 0, color_view;
1033         unsigned format, swap, ntype, endian;
1034         uint64_t offset, base_offset;
1035         unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1036         const struct util_format_description *desc;
1037         int i;
1038         bool blend_clamp = 0, blend_bypass = 0;
1039
1040         offset = rtex->surface.level[level].offset;
1041         if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1042                 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1043                 offset += rtex->surface.level[level].slice_size *
1044                           surf->base.u.tex.first_layer;
1045                 color_view = 0;
1046         } else
1047                 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1048                              S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1049
1050         pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1051         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1052         if (slice) {
1053                 slice = slice - 1;
1054         }
1055         color_info = 0;
1056         switch (rtex->surface.level[level].mode) {
1057         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1058                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1059                 non_disp_tiling = 1;
1060                 break;
1061         case RADEON_SURF_MODE_1D:
1062                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1063                 non_disp_tiling = rtex->non_disp_tiling;
1064                 break;
1065         case RADEON_SURF_MODE_2D:
1066                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1067                 non_disp_tiling = rtex->non_disp_tiling;
1068                 break;
1069         case RADEON_SURF_MODE_LINEAR:
1070         default:
1071                 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1072                 non_disp_tiling = 1;
1073                 break;
1074         }
1075         tile_split = rtex->surface.tile_split;
1076         macro_aspect = rtex->surface.mtilea;
1077         bankw = rtex->surface.bankw;
1078         bankh = rtex->surface.bankh;
1079         if (rtex->fmask.size)
1080                 fmask_bankh = rtex->fmask.bank_height;
1081         else
1082                 fmask_bankh = rtex->surface.bankh;
1083         tile_split = eg_tile_split(tile_split);
1084         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1085         bankw = eg_bank_wh(bankw);
1086         bankh = eg_bank_wh(bankh);
1087         fmask_bankh = eg_bank_wh(fmask_bankh);
1088
1089         /* 128 bit formats require tile type = 1 */
1090         if (rscreen->b.chip_class == CAYMAN) {
1091                 if (util_format_get_blocksize(surf->base.format) >= 16)
1092                         non_disp_tiling = 1;
1093         }
1094         nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1095         desc = util_format_description(surf->base.format);
1096         for (i = 0; i < 4; i++) {
1097                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1098                         break;
1099                 }
1100         }
1101
1102         color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1103                         S_028C74_NUM_BANKS(nbanks) |
1104                         S_028C74_BANK_WIDTH(bankw) |
1105                         S_028C74_BANK_HEIGHT(bankh) |
1106                         S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1107                         S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1108                         S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1109
1110         if (rctx->b.chip_class == CAYMAN) {
1111                 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1112                                                            UTIL_FORMAT_SWIZZLE_1);
1113
1114                 if (rtex->resource.b.b.nr_samples > 1) {
1115                         unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1116                         color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1117                                         S_028C74_NUM_FRAGMENTS(log_samples);
1118                 }
1119         }
1120
1121         ntype = V_028C70_NUMBER_UNORM;
1122         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1123                 ntype = V_028C70_NUMBER_SRGB;
1124         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1125                 if (desc->channel[i].normalized)
1126                         ntype = V_028C70_NUMBER_SNORM;
1127                 else if (desc->channel[i].pure_integer)
1128                         ntype = V_028C70_NUMBER_SINT;
1129         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1130                 if (desc->channel[i].normalized)
1131                         ntype = V_028C70_NUMBER_UNORM;
1132                 else if (desc->channel[i].pure_integer)
1133                         ntype = V_028C70_NUMBER_UINT;
1134         }
1135
1136         format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1137         assert(format != ~0);
1138
1139         swap = r600_translate_colorswap(surf->base.format);
1140         assert(swap != ~0);
1141
1142         endian = r600_colorformat_endian_swap(format);
1143
1144         /* blend clamp should be set for all NORM/SRGB types */
1145         if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1146             ntype == V_028C70_NUMBER_SRGB)
1147                 blend_clamp = 1;
1148
1149         /* set blend bypass according to docs if SINT/UINT or
1150            8/24 COLOR variants */
1151         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1152             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1153             format == V_028C70_COLOR_X24_8_32_FLOAT) {
1154                 blend_clamp = 0;
1155                 blend_bypass = 1;
1156         }
1157
1158         surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1159
1160         color_info |= S_028C70_FORMAT(format) |
1161                 S_028C70_COMP_SWAP(swap) |
1162                 S_028C70_BLEND_CLAMP(blend_clamp) |
1163                 S_028C70_BLEND_BYPASS(blend_bypass) |
1164                 S_028C70_NUMBER_TYPE(ntype) |
1165                 S_028C70_ENDIAN(endian);
1166
1167         /* EXPORT_NORM is an optimzation that can be enabled for better
1168          * performance in certain cases.
1169          * EXPORT_NORM can be enabled if:
1170          * - 11-bit or smaller UNORM/SNORM/SRGB
1171          * - 16-bit or smaller FLOAT
1172          */
1173         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1174             ((desc->channel[i].size < 12 &&
1175               desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1176               ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1177              (desc->channel[i].size < 17 &&
1178               desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1179                 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1180                 surf->export_16bpc = true;
1181         }
1182
1183         if (rtex->fmask.size) {
1184                 color_info |= S_028C70_COMPRESSION(1);
1185         }
1186
1187         base_offset = rtex->resource.gpu_address;
1188
1189         /* XXX handle enabling of CB beyond BASE8 which has different offset */
1190         surf->cb_color_base = (base_offset + offset) >> 8;
1191         surf->cb_color_dim = color_dim;
1192         surf->cb_color_info = color_info;
1193         surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1194         surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1195         surf->cb_color_view = color_view;
1196         surf->cb_color_attrib = color_attrib;
1197         if (rtex->fmask.size) {
1198                 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1199                 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1200         } else {
1201                 surf->cb_color_fmask = surf->cb_color_base;
1202                 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1203         }
1204
1205         surf->color_initialized = true;
1206 }
1207
1208 static void evergreen_init_depth_surface(struct r600_context *rctx,
1209                                          struct r600_surface *surf)
1210 {
1211         struct r600_screen *rscreen = rctx->screen;
1212         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1213         unsigned level = surf->base.u.tex.level;
1214         struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1215         uint64_t offset;
1216         unsigned format, array_mode;
1217         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1218
1219
1220         format = r600_translate_dbformat(surf->base.format);
1221         assert(format != ~0);
1222
1223         offset = rtex->resource.gpu_address;
1224         offset += rtex->surface.level[level].offset;
1225
1226         switch (rtex->surface.level[level].mode) {
1227         case RADEON_SURF_MODE_2D:
1228                 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1229                 break;
1230         case RADEON_SURF_MODE_1D:
1231         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1232         case RADEON_SURF_MODE_LINEAR:
1233         default:
1234                 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1235                 break;
1236         }
1237         tile_split = rtex->surface.tile_split;
1238         macro_aspect = rtex->surface.mtilea;
1239         bankw = rtex->surface.bankw;
1240         bankh = rtex->surface.bankh;
1241         tile_split = eg_tile_split(tile_split);
1242         macro_aspect = eg_macro_tile_aspect(macro_aspect);
1243         bankw = eg_bank_wh(bankw);
1244         bankh = eg_bank_wh(bankh);
1245         nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1246         offset >>= 8;
1247
1248         surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1249                           S_028040_FORMAT(format) |
1250                           S_028040_TILE_SPLIT(tile_split)|
1251                           S_028040_NUM_BANKS(nbanks) |
1252                           S_028040_BANK_WIDTH(bankw) |
1253                           S_028040_BANK_HEIGHT(bankh) |
1254                           S_028040_MACRO_TILE_ASPECT(macro_aspect);
1255         if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1256                 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1257         }
1258
1259         assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1260
1261         surf->db_depth_base = offset;
1262         surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1263                               S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1264         surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1265                               S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1266         surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1267                                                        levelinfo->nblk_y / 64 - 1);
1268
1269         switch (surf->base.format) {
1270         case PIPE_FORMAT_Z24X8_UNORM:
1271         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1272         case PIPE_FORMAT_X8Z24_UNORM:
1273         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1274                 surf->pa_su_poly_offset_db_fmt_cntl =
1275                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1276                 break;
1277         case PIPE_FORMAT_Z32_FLOAT:
1278         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1279                 surf->pa_su_poly_offset_db_fmt_cntl =
1280                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1281                         S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1282                 break;
1283         case PIPE_FORMAT_Z16_UNORM:
1284                 surf->pa_su_poly_offset_db_fmt_cntl =
1285                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1286                 break;
1287         default:;
1288         }
1289
1290         if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1291                 uint64_t stencil_offset;
1292                 unsigned stile_split = rtex->surface.stencil_tile_split;
1293
1294                 stile_split = eg_tile_split(stile_split);
1295
1296                 stencil_offset = rtex->surface.stencil_level[level].offset;
1297                 stencil_offset += rtex->resource.gpu_address;
1298
1299                 surf->db_stencil_base = stencil_offset >> 8;
1300                 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1301                                         S_028044_TILE_SPLIT(stile_split);
1302         } else {
1303                 surf->db_stencil_base = offset;
1304                 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1305                  * Older kernels are out of luck. */
1306                 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1307                                         S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1308                                         S_028044_FORMAT(V_028044_STENCIL_8);
1309         }
1310
1311         /* use htile only for first level */
1312         if (rtex->htile_buffer && !level) {
1313                 uint64_t va = rtex->htile_buffer->gpu_address;
1314                 surf->db_htile_data_base = va >> 8;
1315                 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1316                                          S_028ABC_HTILE_HEIGHT(1) |
1317                                          S_028ABC_FULL_CACHE(1);
1318                 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1319                 surf->db_preload_control = 0;
1320         }
1321
1322         surf->depth_initialized = true;
1323 }
1324
1325 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1326                                             const struct pipe_framebuffer_state *state)
1327 {
1328         struct r600_context *rctx = (struct r600_context *)ctx;
1329         struct r600_surface *surf;
1330         struct r600_texture *rtex;
1331         uint32_t i, log_samples;
1332
1333         if (rctx->framebuffer.state.nr_cbufs) {
1334                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1335                 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1336                                  R600_CONTEXT_FLUSH_AND_INV_CB_META;
1337         }
1338         if (rctx->framebuffer.state.zsbuf) {
1339                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1340                 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1341
1342                 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1343                 if (rtex->htile_buffer) {
1344                         rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1345                 }
1346         }
1347
1348         util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1349
1350         /* Colorbuffers. */
1351         rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1352         rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1353                                            util_format_is_pure_integer(state->cbufs[0]->format);
1354         rctx->framebuffer.compressed_cb_mask = 0;
1355         rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1356
1357         for (i = 0; i < state->nr_cbufs; i++) {
1358                 surf = (struct r600_surface*)state->cbufs[i];
1359                 if (!surf)
1360                         continue;
1361
1362                 rtex = (struct r600_texture*)surf->base.texture;
1363
1364                 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1365
1366                 if (!surf->color_initialized) {
1367                         evergreen_init_color_surface(rctx, surf);
1368                 }
1369
1370                 if (!surf->export_16bpc) {
1371                         rctx->framebuffer.export_16bpc = false;
1372                 }
1373
1374                 if (rtex->fmask.size && rtex->cmask.size) {
1375                         rctx->framebuffer.compressed_cb_mask |= 1 << i;
1376                 }
1377         }
1378
1379         /* Update alpha-test state dependencies.
1380          * Alpha-test is done on the first colorbuffer only. */
1381         if (state->nr_cbufs) {
1382                 bool alphatest_bypass = false;
1383                 bool export_16bpc = true;
1384
1385                 surf = (struct r600_surface*)state->cbufs[0];
1386                 if (surf) {
1387                         alphatest_bypass = surf->alphatest_bypass;
1388                         export_16bpc = surf->export_16bpc;
1389                 }
1390
1391                 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1392                         rctx->alphatest_state.bypass = alphatest_bypass;
1393                         r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1394                 }
1395                 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1396                         rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1397                         r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1398                 }
1399         }
1400
1401         /* ZS buffer. */
1402         if (state->zsbuf) {
1403                 surf = (struct r600_surface*)state->zsbuf;
1404
1405                 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1406
1407                 if (!surf->depth_initialized) {
1408                         evergreen_init_depth_surface(rctx, surf);
1409                 }
1410
1411                 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1412                         rctx->poly_offset_state.zs_format = state->zsbuf->format;
1413                         r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1414                 }
1415
1416                 if (rctx->db_state.rsurf != surf) {
1417                         rctx->db_state.rsurf = surf;
1418                         r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1419                         r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1420                 }
1421         } else if (rctx->db_state.rsurf) {
1422                 rctx->db_state.rsurf = NULL;
1423                 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1424                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1425         }
1426
1427         if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1428                 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1429                 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1430         }
1431
1432         if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1433                 rctx->alphatest_state.bypass = false;
1434                 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1435         }
1436
1437         log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1438         /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1439         if ((rctx->b.chip_class == CAYMAN ||
1440              rctx->b.family == CHIP_RV770) &&
1441             rctx->db_misc_state.log_samples != log_samples) {
1442                 rctx->db_misc_state.log_samples = log_samples;
1443                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1444         }
1445
1446
1447         /* Calculate the CS size. */
1448         rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1449
1450         /* MSAA. */
1451         if (rctx->b.chip_class == EVERGREEN)
1452                 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1453         else
1454                 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1455
1456         /* Colorbuffers. */
1457         rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1458         rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1459         rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1460
1461         /* ZS buffer. */
1462         if (state->zsbuf) {
1463                 rctx->framebuffer.atom.num_dw += 24;
1464                 rctx->framebuffer.atom.num_dw += 2;
1465         } else if (rctx->screen->b.info.drm_minor >= 18) {
1466                 rctx->framebuffer.atom.num_dw += 4;
1467         }
1468
1469         r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1470
1471         r600_set_sample_locations_constant_buffer(rctx);
1472 }
1473
1474 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1475 {
1476         struct r600_context *rctx = (struct r600_context *)ctx;
1477
1478         if (rctx->ps_iter_samples == min_samples)
1479                 return;
1480
1481         rctx->ps_iter_samples = min_samples;
1482         if (rctx->framebuffer.nr_samples > 1) {
1483                 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1484         }
1485 }
1486
1487 /* 8xMSAA */
1488 static uint32_t sample_locs_8x[] = {
1489         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1490         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1491         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1492         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1493         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1494         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1495         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1496         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1497 };
1498 static unsigned max_dist_8x = 7;
1499
1500 static void evergreen_get_sample_position(struct pipe_context *ctx,
1501                                      unsigned sample_count,
1502                                      unsigned sample_index,
1503                                      float *out_value)
1504 {
1505         int offset, index;
1506         struct {
1507                 int idx:4;
1508         } val;
1509         switch (sample_count) {
1510         case 1:
1511         default:
1512                 out_value[0] = out_value[1] = 0.5;
1513                 break;
1514         case 2:
1515                 offset = 4 * (sample_index * 2);
1516                 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1517                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1518                 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1519                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1520                 break;
1521         case 4:
1522                 offset = 4 * (sample_index * 2);
1523                 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1524                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1525                 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1526                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1527                 break;
1528         case 8:
1529                 offset = 4 * (sample_index % 4 * 2);
1530                 index = (sample_index / 4);
1531                 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1532                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1533                 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1534                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1535                 break;
1536         }
1537 }
1538
1539 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1540 {
1541
1542         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1543         unsigned max_dist = 0;
1544
1545         switch (nr_samples) {
1546         default:
1547                 nr_samples = 0;
1548                 break;
1549         case 2:
1550                 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1551                 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1552                 max_dist = eg_max_dist_2x;
1553                 break;
1554         case 4:
1555                 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1556                 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1557                 max_dist = eg_max_dist_4x;
1558                 break;
1559         case 8:
1560                 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1561                 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1562                 max_dist = max_dist_8x;
1563                 break;
1564         }
1565
1566         if (nr_samples > 1) {
1567                 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1568                 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1569                                      S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1570                 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1571                                      S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1572                 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1573                                        EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1574                                        EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1575                                        EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1576         } else {
1577                 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1578                 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1579                 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1580                 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1581                                        EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1582                                        EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1583         }
1584 }
1585
1586 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1587 {
1588         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1589         struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1590         unsigned nr_cbufs = state->nr_cbufs;
1591         unsigned i, tl, br;
1592         struct r600_texture *tex = NULL;
1593         struct r600_surface *cb = NULL;
1594
1595         /* XXX support more colorbuffers once we need them */
1596         assert(nr_cbufs <= 8);
1597         if (nr_cbufs > 8)
1598                 nr_cbufs = 8;
1599
1600         /* Colorbuffers. */
1601         for (i = 0; i < nr_cbufs; i++) {
1602                 unsigned reloc, cmask_reloc;
1603
1604                 cb = (struct r600_surface*)state->cbufs[i];
1605                 if (!cb) {
1606                         radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1607                                                S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1608                         continue;
1609                 }
1610
1611                 tex = (struct r600_texture *)cb->base.texture;
1612                 reloc = radeon_add_to_buffer_list(&rctx->b,
1613                                               &rctx->b.gfx,
1614                                               (struct r600_resource*)cb->base.texture,
1615                                               RADEON_USAGE_READWRITE,
1616                                               tex->surface.nsamples > 1 ?
1617                                                       RADEON_PRIO_COLOR_BUFFER_MSAA :
1618                                                       RADEON_PRIO_COLOR_BUFFER);
1619
1620                 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1621                         cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1622                                 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1623                                 RADEON_PRIO_CMASK);
1624                 } else {
1625                         cmask_reloc = reloc;
1626                 }
1627
1628                 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1629                 radeon_emit(cs, cb->cb_color_base);     /* R_028C60_CB_COLOR0_BASE */
1630                 radeon_emit(cs, cb->cb_color_pitch);    /* R_028C64_CB_COLOR0_PITCH */
1631                 radeon_emit(cs, cb->cb_color_slice);    /* R_028C68_CB_COLOR0_SLICE */
1632                 radeon_emit(cs, cb->cb_color_view);     /* R_028C6C_CB_COLOR0_VIEW */
1633                 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1634                 radeon_emit(cs, cb->cb_color_attrib);   /* R_028C74_CB_COLOR0_ATTRIB */
1635                 radeon_emit(cs, cb->cb_color_dim);              /* R_028C78_CB_COLOR0_DIM */
1636                 radeon_emit(cs, tex->cmask.base_address_reg);   /* R_028C7C_CB_COLOR0_CMASK */
1637                 radeon_emit(cs, tex->cmask.slice_tile_max);     /* R_028C80_CB_COLOR0_CMASK_SLICE */
1638                 radeon_emit(cs, cb->cb_color_fmask);    /* R_028C84_CB_COLOR0_FMASK */
1639                 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1640                 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1641                 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1642
1643                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1644                 radeon_emit(cs, reloc);
1645
1646                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1647                 radeon_emit(cs, reloc);
1648
1649                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1650                 radeon_emit(cs, cmask_reloc);
1651
1652                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1653                 radeon_emit(cs, reloc);
1654         }
1655         /* set CB_COLOR1_INFO for possible dual-src blending */
1656         if (i == 1 && state->cbufs[0]) {
1657                 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1658                                        cb->cb_color_info | tex->cb_color_info);
1659                 i++;
1660         }
1661         for (; i < 8 ; i++)
1662                 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1663         for (; i < 12; i++)
1664                 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1665
1666         /* ZS buffer. */
1667         if (state->zsbuf) {
1668                 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1669                 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1670                                                        &rctx->b.gfx,
1671                                                        (struct r600_resource*)state->zsbuf->texture,
1672                                                        RADEON_USAGE_READWRITE,
1673                                                        zb->base.texture->nr_samples > 1 ?
1674                                                                RADEON_PRIO_DEPTH_BUFFER_MSAA :
1675                                                                RADEON_PRIO_DEPTH_BUFFER);
1676
1677                 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1678                                        zb->pa_su_poly_offset_db_fmt_cntl);
1679                 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1680
1681                 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1682                 radeon_emit(cs, zb->db_z_info);         /* R_028040_DB_Z_INFO */
1683                 radeon_emit(cs, zb->db_stencil_info);   /* R_028044_DB_STENCIL_INFO */
1684                 radeon_emit(cs, zb->db_depth_base);     /* R_028048_DB_Z_READ_BASE */
1685                 radeon_emit(cs, zb->db_stencil_base);   /* R_02804C_DB_STENCIL_READ_BASE */
1686                 radeon_emit(cs, zb->db_depth_base);     /* R_028050_DB_Z_WRITE_BASE */
1687                 radeon_emit(cs, zb->db_stencil_base);   /* R_028054_DB_STENCIL_WRITE_BASE */
1688                 radeon_emit(cs, zb->db_depth_size);     /* R_028058_DB_DEPTH_SIZE */
1689                 radeon_emit(cs, zb->db_depth_slice);    /* R_02805C_DB_DEPTH_SLICE */
1690
1691                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1692                 radeon_emit(cs, reloc);
1693
1694                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1695                 radeon_emit(cs, reloc);
1696
1697                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1698                 radeon_emit(cs, reloc);
1699
1700                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1701                 radeon_emit(cs, reloc);
1702         } else if (rctx->screen->b.info.drm_minor >= 18) {
1703                 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1704                  * Older kernels are out of luck. */
1705                 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1706                 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1707                 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1708         }
1709
1710         /* Framebuffer dimensions. */
1711         evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1712
1713         radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1714         radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1715         radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1716
1717         if (rctx->b.chip_class == EVERGREEN) {
1718                 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1719         } else {
1720                 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1721                 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1722         }
1723 }
1724
1725 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1726 {
1727         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1728         struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1729         float offset_units = state->offset_units;
1730         float offset_scale = state->offset_scale;
1731
1732         switch (state->zs_format) {
1733         case PIPE_FORMAT_Z24X8_UNORM:
1734         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1735         case PIPE_FORMAT_X8Z24_UNORM:
1736         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1737                 offset_units *= 2.0f;
1738                 break;
1739         case PIPE_FORMAT_Z16_UNORM:
1740                 offset_units *= 4.0f;
1741                 break;
1742         default:;
1743         }
1744
1745         radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1746         radeon_emit(cs, fui(offset_scale));
1747         radeon_emit(cs, fui(offset_units));
1748         radeon_emit(cs, fui(offset_scale));
1749         radeon_emit(cs, fui(offset_units));
1750 }
1751
1752 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1753 {
1754         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1755         struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1756         unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1757         unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1758
1759         radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1760         radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1761         /* This must match the used export instructions exactly.
1762          * Other values may lead to undefined behavior and hangs.
1763          */
1764         radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1765 }
1766
1767 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1768 {
1769         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1770         struct r600_db_state *a = (struct r600_db_state*)atom;
1771
1772         if (a->rsurf && a->rsurf->db_htile_surface) {
1773                 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1774                 unsigned reloc_idx;
1775
1776                 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1777                 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1778                 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1779                 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1780                 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1781                                                   RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1782                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1783                 cs->buf[cs->cdw++] = reloc_idx;
1784         } else {
1785                 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1786                 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1787         }
1788 }
1789
1790 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1791 {
1792         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1793         struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1794         unsigned db_render_control = 0;
1795         unsigned db_count_control = 0;
1796         unsigned db_render_override =
1797                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1798                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1799
1800         if (a->occlusion_query_enabled) {
1801                 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1802                 if (rctx->b.chip_class == CAYMAN) {
1803                         db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1804                 }
1805                 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1806         }
1807
1808         /* This is to fix a lockup when hyperz and alpha test are enabled at
1809          * the same time somehow GPU get confuse on which order to pick for
1810          * z test
1811          */
1812         if (rctx->alphatest_state.sx_alpha_test_control)
1813                 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1814
1815         if (a->flush_depthstencil_through_cb) {
1816                 assert(a->copy_depth || a->copy_stencil);
1817
1818                 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1819                                      S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1820                                      S_028000_COPY_CENTROID(1) |
1821                                      S_028000_COPY_SAMPLE(a->copy_sample);
1822         } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1823                 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1824                                      S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1825                 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1826         }
1827         if (a->htile_clear) {
1828                 /* FIXME we might want to disable cliprect here */
1829                 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1830         }
1831
1832         radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1833         radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1834         radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1835         radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1836         radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1837 }
1838
1839 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1840                                           struct r600_vertexbuf_state *state,
1841                                           unsigned resource_offset,
1842                                           unsigned pkt_flags)
1843 {
1844         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1845         uint32_t dirty_mask = state->dirty_mask;
1846
1847         while (dirty_mask) {
1848                 struct pipe_vertex_buffer *vb;
1849                 struct r600_resource *rbuffer;
1850                 uint64_t va;
1851                 unsigned buffer_index = u_bit_scan(&dirty_mask);
1852
1853                 vb = &state->vb[buffer_index];
1854                 rbuffer = (struct r600_resource*)vb->buffer;
1855                 assert(rbuffer);
1856
1857                 va = rbuffer->gpu_address + vb->buffer_offset;
1858
1859                 /* fetch resources start at index 992 */
1860                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1861                 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1862                 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1863                 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1864                 radeon_emit(cs, /* RESOURCEi_WORD2 */
1865                                  S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1866                                  S_030008_STRIDE(vb->stride) |
1867                                  S_030008_BASE_ADDRESS_HI(va >> 32UL));
1868                 radeon_emit(cs, /* RESOURCEi_WORD3 */
1869                                  S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1870                                  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1871                                  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1872                                  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1873                 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1874                 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1875                 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1876                 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1877
1878                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1879                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1880                                                       RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1881         }
1882         state->dirty_mask = 0;
1883 }
1884
1885 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1886 {
1887         evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1888 }
1889
1890 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1891 {
1892         evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1893                                       RADEON_CP_PACKET3_COMPUTE_MODE);
1894 }
1895
1896 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1897                                             struct r600_constbuf_state *state,
1898                                             unsigned buffer_id_base,
1899                                             unsigned reg_alu_constbuf_size,
1900                                             unsigned reg_alu_const_cache,
1901                                             unsigned pkt_flags)
1902 {
1903         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1904         uint32_t dirty_mask = state->dirty_mask;
1905
1906         while (dirty_mask) {
1907                 struct pipe_constant_buffer *cb;
1908                 struct r600_resource *rbuffer;
1909                 uint64_t va;
1910                 unsigned buffer_index = ffs(dirty_mask) - 1;
1911                 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1912
1913                 cb = &state->cb[buffer_index];
1914                 rbuffer = (struct r600_resource*)cb->buffer;
1915                 assert(rbuffer);
1916
1917                 va = rbuffer->gpu_address + cb->buffer_offset;
1918
1919                 if (!gs_ring_buffer) {
1920                         radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1921                                                     DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1922                         radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1923                                                     pkt_flags);
1924                 }
1925
1926                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1927                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1928                                                       RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1929
1930                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1931                 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1932                 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1933                 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1934                 radeon_emit(cs, /* RESOURCEi_WORD2 */
1935                             S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1936                             S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1937                             S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1938                             S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1939                 radeon_emit(cs, /* RESOURCEi_WORD3 */
1940                                  S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1941                                  S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1942                                  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1943                                  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1944                                  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1945                 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1946                 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1947                 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1948                 radeon_emit(cs, /* RESOURCEi_WORD7 */
1949                             S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1950
1951                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1952                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1953                                                       RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1954
1955                 dirty_mask &= ~(1 << buffer_index);
1956         }
1957         state->dirty_mask = 0;
1958 }
1959
1960 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1961 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1962 {
1963         if (rctx->vs_shader->current->shader.vs_as_ls) {
1964                 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1965                                                 EG_FETCH_CONSTANTS_OFFSET_LS,
1966                                                 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1967                                                 R_028F40_ALU_CONST_CACHE_LS_0,
1968                                                 0 /* PKT3 flags */);
1969         } else {
1970                 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1971                                                 EG_FETCH_CONSTANTS_OFFSET_VS,
1972                                                 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1973                                                 R_028980_ALU_CONST_CACHE_VS_0,
1974                                                 0 /* PKT3 flags */);
1975         }
1976 }
1977
1978 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1979 {
1980         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1981                                         EG_FETCH_CONSTANTS_OFFSET_GS,
1982                                         R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1983                                         R_0289C0_ALU_CONST_CACHE_GS_0,
1984                                         0 /* PKT3 flags */);
1985 }
1986
1987 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1988 {
1989         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1990                                         EG_FETCH_CONSTANTS_OFFSET_PS,
1991                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1992                                         R_028940_ALU_CONST_CACHE_PS_0,
1993                                         0 /* PKT3 flags */);
1994 }
1995
1996 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1997 {
1998         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
1999                                         EG_FETCH_CONSTANTS_OFFSET_CS,
2000                                         R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2001                                         R_028F40_ALU_CONST_CACHE_LS_0,
2002                                         RADEON_CP_PACKET3_COMPUTE_MODE);
2003 }
2004
2005 /* tes constants can be emitted to VS or ES - which are common */
2006 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2007 {
2008         if (!rctx->tes_shader)
2009                 return;
2010         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2011                                         EG_FETCH_CONSTANTS_OFFSET_VS,
2012                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2013                                         R_028980_ALU_CONST_CACHE_VS_0,
2014                                         0);
2015 }
2016
2017 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2018 {
2019         if (!rctx->tes_shader)
2020                 return;
2021         evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2022                                         EG_FETCH_CONSTANTS_OFFSET_HS,
2023                                         R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2024                                         R_028F00_ALU_CONST_CACHE_HS_0,
2025                                         0);
2026 }
2027
2028 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2029                                          struct r600_samplerview_state *state,
2030                                          unsigned resource_id_base, unsigned pkt_flags)
2031 {
2032         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2033         uint32_t dirty_mask = state->dirty_mask;
2034
2035         while (dirty_mask) {
2036                 struct r600_pipe_sampler_view *rview;
2037                 unsigned resource_index = u_bit_scan(&dirty_mask);
2038                 unsigned reloc;
2039
2040                 rview = state->views[resource_index];
2041                 assert(rview);
2042
2043                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2044                 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2045                 radeon_emit_array(cs, rview->tex_resource_words, 8);
2046
2047                 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2048                                               RADEON_USAGE_READ,
2049                                               r600_get_sampler_view_priority(rview->tex_resource));
2050                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2051                 radeon_emit(cs, reloc);
2052
2053                 if (!rview->skip_mip_address_reloc) {
2054                         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2055                         radeon_emit(cs, reloc);
2056                 }
2057         }
2058         state->dirty_mask = 0;
2059 }
2060
2061 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2062 {
2063         if (rctx->vs_shader->current->shader.vs_as_ls) {
2064                 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2065                                              EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2066         } else {
2067                 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2068                                              EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2069         }
2070 }
2071
2072 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2073 {
2074         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2075                                      EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2076 }
2077
2078 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2079 {
2080         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2081                                      EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2082 }
2083
2084 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2085 {
2086         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2087                                      EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2088 }
2089
2090 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2091 {
2092         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2093                                      EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2094 }
2095
2096 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2097 {
2098         evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2099                                      EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2100 }
2101
2102 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2103                                 struct r600_textures_info *texinfo,
2104                                 unsigned resource_id_base,
2105                                 unsigned border_index_reg,
2106                                 unsigned pkt_flags)
2107 {
2108         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2109         uint32_t dirty_mask = texinfo->states.dirty_mask;
2110
2111         while (dirty_mask) {
2112                 struct r600_pipe_sampler_state *rstate;
2113                 unsigned i = u_bit_scan(&dirty_mask);
2114
2115                 rstate = texinfo->states.states[i];
2116                 assert(rstate);
2117
2118                 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2119                 radeon_emit(cs, (resource_id_base + i) * 3);
2120                 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2121
2122                 if (rstate->border_color_use) {
2123                         radeon_set_config_reg_seq(cs, border_index_reg, 5);
2124                         radeon_emit(cs, i);
2125                         radeon_emit_array(cs, rstate->border_color.ui, 4);
2126                 }
2127         }
2128         texinfo->states.dirty_mask = 0;
2129 }
2130
2131 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2132 {
2133         if (rctx->vs_shader->current->shader.vs_as_ls) {
2134                 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2135                                               R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2136         } else {
2137                 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2138                                               R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2139         }
2140 }
2141
2142 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2143 {
2144         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2145                                       R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2146 }
2147
2148 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2149 {
2150         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2151                                       R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2152 }
2153
2154 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2155 {
2156         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2157                                       R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2158 }
2159
2160 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2161 {
2162         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2163                                       R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2164 }
2165
2166 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2167 {
2168         evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2169                                       R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2170                                       RADEON_CP_PACKET3_COMPUTE_MODE);
2171 }
2172
2173 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2174 {
2175         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2176         uint8_t mask = s->sample_mask;
2177
2178         radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2179                                mask | (mask << 8) | (mask << 16) | (mask << 24));
2180 }
2181
2182 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2183 {
2184         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2185         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2186         uint16_t mask = s->sample_mask;
2187
2188         radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2189         radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2190         radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2191 }
2192
2193 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2194 {
2195         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2196         struct r600_cso_state *state = (struct r600_cso_state*)a;
2197         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2198
2199         radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2200                                (shader->buffer->gpu_address + shader->offset) >> 8);
2201         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2202         radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2203                                                   RADEON_USAGE_READ,
2204                                                   RADEON_PRIO_INTERNAL_SHADER));
2205 }
2206
2207 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2208 {
2209         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2210         struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2211
2212         uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2213
2214         if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2215                 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2216                 primid = 1;
2217         }
2218
2219         if (state->geom_enable) {
2220                 uint32_t cut_val;
2221
2222                 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2223                         cut_val = V_028A40_GS_CUT_128;
2224                 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2225                         cut_val = V_028A40_GS_CUT_256;
2226                 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2227                         cut_val = V_028A40_GS_CUT_512;
2228                 else
2229                         cut_val = V_028A40_GS_CUT_1024;
2230
2231                 v = S_028B54_GS_EN(1) |
2232                     S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2233                 if (!rctx->tes_shader)
2234                         v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2235
2236                 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2237                         S_028A40_CUT_MODE(cut_val);
2238
2239                 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2240                         primid = 1;
2241         }
2242
2243         if (rctx->tes_shader) {
2244                 uint32_t type, partitioning, topology;
2245                 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2246                 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2247                 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2248                 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2249                 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2250                 switch (tes_prim_mode) {
2251                 case PIPE_PRIM_LINES:
2252                         type = V_028B6C_TESS_ISOLINE;
2253                         break;
2254                 case PIPE_PRIM_TRIANGLES:
2255                         type = V_028B6C_TESS_TRIANGLE;
2256                         break;
2257                 case PIPE_PRIM_QUADS:
2258                         type = V_028B6C_TESS_QUAD;
2259                         break;
2260                 default:
2261                         assert(0);
2262                         return;
2263                 }
2264
2265                 switch (tes_spacing) {
2266                 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2267                         partitioning = V_028B6C_PART_FRAC_ODD;
2268                         break;
2269                 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2270                         partitioning = V_028B6C_PART_FRAC_EVEN;
2271                         break;
2272                 case PIPE_TESS_SPACING_EQUAL:
2273                         partitioning = V_028B6C_PART_INTEGER;
2274                         break;
2275                 default:
2276                         assert(0);
2277                         return;
2278                 }
2279
2280                 if (tes_point_mode)
2281                         topology = V_028B6C_OUTPUT_POINT;
2282                 else if (tes_prim_mode == PIPE_PRIM_LINES)
2283                         topology = V_028B6C_OUTPUT_LINE;
2284                 else if (tes_vertex_order_cw)
2285                         /* XXX follow radeonsi and invert */
2286                         topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2287                 else
2288                         topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2289
2290                 tf_param = S_028B6C_TYPE(type) |
2291                         S_028B6C_PARTITIONING(partitioning) |
2292                         S_028B6C_TOPOLOGY(topology);
2293         }
2294
2295         if (rctx->tes_shader) {
2296                 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2297                      S_028B54_HS_EN(1);
2298                 if (!state->geom_enable)
2299                         v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2300                 else
2301                         v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2302         }
2303
2304         radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2305         radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2306         radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2307         radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2308         radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2309 }
2310
2311 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2312 {
2313         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2314         struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2315         struct r600_resource *rbuffer;
2316
2317         radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2318         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2319         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2320
2321         if (state->enable) {
2322                 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2323                 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2324                                 rbuffer->gpu_address >> 8);
2325                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2326                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2327                                                       RADEON_USAGE_READWRITE,
2328                                                       RADEON_PRIO_RINGS_STREAMOUT));
2329                 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2330                                 state->esgs_ring.buffer_size >> 8);
2331
2332                 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2333                 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2334                                 rbuffer->gpu_address >> 8);
2335                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2336                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2337                                                       RADEON_USAGE_READWRITE,
2338                                                       RADEON_PRIO_RINGS_STREAMOUT));
2339                 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2340                                 state->gsvs_ring.buffer_size >> 8);
2341         } else {
2342                 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2343                 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2344         }
2345
2346         radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2347         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2348         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2349 }
2350
2351 void cayman_init_common_regs(struct r600_command_buffer *cb,
2352                              enum chip_class ctx_chip_class,
2353                              enum radeon_family ctx_family,
2354                              int ctx_drm_minor)
2355 {
2356         r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2357         r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2358         /* always set the temp clauses */
2359         r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2360
2361         r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2362         r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2363         r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2364
2365         r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2366
2367         r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2368         r600_store_value(cb, 0);
2369         r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2370
2371         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2372 }
2373
2374 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2375 {
2376         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2377         int tmp, i;
2378
2379         r600_init_command_buffer(cb, 338);
2380
2381         /* This must be first. */
2382         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2383         r600_store_value(cb, 0x80000000);
2384         r600_store_value(cb, 0x80000000);
2385
2386         /* We're setting config registers here. */
2387         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2388         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2389
2390         cayman_init_common_regs(cb, rctx->b.chip_class,
2391                                 rctx->b.family, rctx->screen->b.info.drm_minor);
2392
2393         r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2394         r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2395
2396         /* remove LS/HS from one SIMD for hw workaround */
2397         r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2398         r600_store_value(cb, 0xffffffff);
2399         r600_store_value(cb, 0xffffffff);
2400         r600_store_value(cb, 0xfffffffe);
2401
2402         r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2403         r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2404         r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2405         r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2406         r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2407         r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2408         r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2409
2410         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2411         r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2412         r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2413         r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2414         r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2415
2416         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2417         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2418         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2419         r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2420         r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2421         r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2422         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2423         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2424         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2425         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2426         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2427         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2428         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2429         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2430
2431         r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2432
2433         r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2434
2435         r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2436         r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2437         r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2438
2439         r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2440         r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2441         r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2442
2443         r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2444
2445         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2446         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2447         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2448
2449         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2450
2451         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2452
2453         r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2454
2455         r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2456         r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2457         r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2458         r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2459
2460         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2461         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2462
2463         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2464         for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2465                 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2466                 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2467         }
2468
2469         r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2470         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2471
2472         r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2473         r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2474         r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2475         r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2476         r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2477
2478         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2479         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2480         r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2481
2482         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2483         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2484         r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2485
2486         r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2487         r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2488         r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2489         r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2490         r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2491         r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2492
2493         r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2494
2495         /* to avoid GPU doing any preloading of constant from random address */
2496         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2497         for (i = 0; i < 16; i++)
2498                 r600_store_value(cb, 0);
2499
2500         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2501         for (i = 0; i < 16; i++)
2502                 r600_store_value(cb, 0);
2503
2504         r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2505         for (i = 0; i < 16; i++)
2506                 r600_store_value(cb, 0);
2507
2508         r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2509         for (i = 0; i < 16; i++)
2510                 r600_store_value(cb, 0);
2511
2512         r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2513         for (i = 0; i < 16; i++)
2514                 r600_store_value(cb, 0);
2515
2516         if (rctx->screen->b.has_streamout) {
2517                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2518         }
2519
2520         r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2521         r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2522         r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2523         r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2524         r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2525         r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2526
2527         r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2528         r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2529         r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2530         r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2531         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2532         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2533         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2534         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2535         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2536 }
2537
2538 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2539                                 enum chip_class ctx_chip_class,
2540                                 enum radeon_family ctx_family,
2541                                 int ctx_drm_minor)
2542 {
2543         int ps_prio;
2544         int vs_prio;
2545         int gs_prio;
2546         int es_prio;
2547
2548         int hs_prio;
2549         int cs_prio;
2550         int ls_prio;
2551
2552         unsigned tmp;
2553
2554         ps_prio = 0;
2555         vs_prio = 1;
2556         gs_prio = 2;
2557         es_prio = 3;
2558         hs_prio = 3;
2559         ls_prio = 3;
2560         cs_prio = 0;
2561
2562         rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2563         rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2564         rctx->r6xx_num_clause_temp_gprs = 4;
2565         rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2566         rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2567         rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2568         rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2569
2570         tmp = 0;
2571         switch (ctx_family) {
2572         case CHIP_CEDAR:
2573         case CHIP_PALM:
2574         case CHIP_SUMO:
2575         case CHIP_SUMO2:
2576         case CHIP_CAICOS:
2577                 break;
2578         default:
2579                 tmp |= S_008C00_VC_ENABLE(1);
2580                 break;
2581         }
2582         tmp |= S_008C00_EXPORT_SRC_C(1);
2583         tmp |= S_008C00_CS_PRIO(cs_prio);
2584         tmp |= S_008C00_LS_PRIO(ls_prio);
2585         tmp |= S_008C00_HS_PRIO(hs_prio);
2586         tmp |= S_008C00_PS_PRIO(ps_prio);
2587         tmp |= S_008C00_VS_PRIO(vs_prio);
2588         tmp |= S_008C00_GS_PRIO(gs_prio);
2589         tmp |= S_008C00_ES_PRIO(es_prio);
2590
2591         r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2592         r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2593
2594         r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2595         r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2596         r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2597
2598         /* The cs checker requires this register to be set. */
2599         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2600
2601         r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2602         r600_store_value(cb, 0);
2603         r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2604
2605         return;
2606 }
2607
2608 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2609 {
2610         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2611         int num_ps_threads;
2612         int num_vs_threads;
2613         int num_gs_threads;
2614         int num_es_threads;
2615         int num_hs_threads;
2616         int num_ls_threads;
2617
2618         int num_ps_stack_entries;
2619         int num_vs_stack_entries;
2620         int num_gs_stack_entries;
2621         int num_es_stack_entries;
2622         int num_hs_stack_entries;
2623         int num_ls_stack_entries;
2624         enum radeon_family family;
2625         unsigned tmp, i;
2626
2627         if (rctx->b.chip_class == CAYMAN) {
2628                 cayman_init_atom_start_cs(rctx);
2629                 return;
2630         }
2631
2632         r600_init_command_buffer(cb, 338);
2633
2634         /* This must be first. */
2635         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2636         r600_store_value(cb, 0x80000000);
2637         r600_store_value(cb, 0x80000000);
2638
2639         /* We're setting config registers here. */
2640         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2641         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2642
2643         evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2644                                    rctx->b.family, rctx->screen->b.info.drm_minor);
2645
2646         family = rctx->b.family;
2647         switch (family) {
2648         case CHIP_CEDAR:
2649         default:
2650                 num_ps_threads = 96;
2651                 num_vs_threads = 16;
2652                 num_gs_threads = 16;
2653                 num_es_threads = 16;
2654                 num_hs_threads = 16;
2655                 num_ls_threads = 16;
2656                 num_ps_stack_entries = 42;
2657                 num_vs_stack_entries = 42;
2658                 num_gs_stack_entries = 42;
2659                 num_es_stack_entries = 42;
2660                 num_hs_stack_entries = 42;
2661                 num_ls_stack_entries = 42;
2662                 break;
2663         case CHIP_REDWOOD:
2664                 num_ps_threads = 128;
2665                 num_vs_threads = 20;
2666                 num_gs_threads = 20;
2667                 num_es_threads = 20;
2668                 num_hs_threads = 20;
2669                 num_ls_threads = 20;
2670                 num_ps_stack_entries = 42;
2671                 num_vs_stack_entries = 42;
2672                 num_gs_stack_entries = 42;
2673                 num_es_stack_entries = 42;
2674                 num_hs_stack_entries = 42;
2675                 num_ls_stack_entries = 42;
2676                 break;
2677         case CHIP_JUNIPER:
2678                 num_ps_threads = 128;
2679                 num_vs_threads = 20;
2680                 num_gs_threads = 20;
2681                 num_es_threads = 20;
2682                 num_hs_threads = 20;
2683                 num_ls_threads = 20;
2684                 num_ps_stack_entries = 85;
2685                 num_vs_stack_entries = 85;
2686                 num_gs_stack_entries = 85;
2687                 num_es_stack_entries = 85;
2688                 num_hs_stack_entries = 85;
2689                 num_ls_stack_entries = 85;
2690                 break;
2691         case CHIP_CYPRESS:
2692         case CHIP_HEMLOCK:
2693                 num_ps_threads = 128;
2694                 num_vs_threads = 20;
2695                 num_gs_threads = 20;
2696                 num_es_threads = 20;
2697                 num_hs_threads = 20;
2698                 num_ls_threads = 20;
2699                 num_ps_stack_entries = 85;
2700                 num_vs_stack_entries = 85;
2701                 num_gs_stack_entries = 85;
2702                 num_es_stack_entries = 85;
2703                 num_hs_stack_entries = 85;
2704                 num_ls_stack_entries = 85;
2705                 break;
2706         case CHIP_PALM:
2707                 num_ps_threads = 96;
2708                 num_vs_threads = 16;
2709                 num_gs_threads = 16;
2710                 num_es_threads = 16;
2711                 num_hs_threads = 16;
2712                 num_ls_threads = 16;
2713                 num_ps_stack_entries = 42;
2714                 num_vs_stack_entries = 42;
2715                 num_gs_stack_entries = 42;
2716                 num_es_stack_entries = 42;
2717                 num_hs_stack_entries = 42;
2718                 num_ls_stack_entries = 42;
2719                 break;
2720         case CHIP_SUMO:
2721                 num_ps_threads = 96;
2722                 num_vs_threads = 25;
2723                 num_gs_threads = 25;
2724                 num_es_threads = 25;
2725                 num_hs_threads = 16;
2726                 num_ls_threads = 16;
2727                 num_ps_stack_entries = 42;
2728                 num_vs_stack_entries = 42;
2729                 num_gs_stack_entries = 42;
2730                 num_es_stack_entries = 42;
2731                 num_hs_stack_entries = 42;
2732                 num_ls_stack_entries = 42;
2733                 break;
2734         case CHIP_SUMO2:
2735                 num_ps_threads = 96;
2736                 num_vs_threads = 25;
2737                 num_gs_threads = 25;
2738                 num_es_threads = 25;
2739                 num_hs_threads = 16;
2740                 num_ls_threads = 16;
2741                 num_ps_stack_entries = 85;
2742                 num_vs_stack_entries = 85;
2743                 num_gs_stack_entries = 85;
2744                 num_es_stack_entries = 85;
2745                 num_hs_stack_entries = 85;
2746                 num_ls_stack_entries = 85;
2747                 break;
2748         case CHIP_BARTS:
2749                 num_ps_threads = 128;
2750                 num_vs_threads = 20;
2751                 num_gs_threads = 20;
2752                 num_es_threads = 20;
2753                 num_hs_threads = 20;
2754                 num_ls_threads = 20;
2755                 num_ps_stack_entries = 85;
2756                 num_vs_stack_entries = 85;
2757                 num_gs_stack_entries = 85;
2758                 num_es_stack_entries = 85;
2759                 num_hs_stack_entries = 85;
2760                 num_ls_stack_entries = 85;
2761                 break;
2762         case CHIP_TURKS:
2763                 num_ps_threads = 128;
2764                 num_vs_threads = 20;
2765                 num_gs_threads = 20;
2766                 num_es_threads = 20;
2767                 num_hs_threads = 20;
2768                 num_ls_threads = 20;
2769                 num_ps_stack_entries = 42;
2770                 num_vs_stack_entries = 42;
2771                 num_gs_stack_entries = 42;
2772                 num_es_stack_entries = 42;
2773                 num_hs_stack_entries = 42;
2774                 num_ls_stack_entries = 42;
2775                 break;
2776         case CHIP_CAICOS:
2777                 num_ps_threads = 96;
2778                 num_vs_threads = 10;
2779                 num_gs_threads = 10;
2780                 num_es_threads = 10;
2781                 num_hs_threads = 10;
2782                 num_ls_threads = 10;
2783                 num_ps_stack_entries = 42;
2784                 num_vs_stack_entries = 42;
2785                 num_gs_stack_entries = 42;
2786                 num_es_stack_entries = 42;
2787                 num_hs_stack_entries = 42;
2788                 num_ls_stack_entries = 42;
2789                 break;
2790         }
2791
2792         tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2793         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2794         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2795         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2796
2797         r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2798         r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2799
2800         tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2801         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2802         r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2803
2804         tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2805         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2806         r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2807
2808         tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2809         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2810         r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2811
2812         tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2813         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2814         r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2815
2816         r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2817                               S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2818
2819         /* remove LS/HS from one SIMD for hw workaround */
2820         r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2821         r600_store_value(cb, 0xffffffff);
2822         r600_store_value(cb, 0xffffffff);
2823         r600_store_value(cb, 0xfffffffe);
2824
2825         r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2826         r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2827
2828         r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2829         r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2830         r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2831         r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2832         r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2833         r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2834         r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2835
2836         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2837         r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2838         r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2839         r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2840         r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2841
2842         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2843         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2844         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2845         r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2846         r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2847         r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2848         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2849         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2850         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2851         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2852         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2853         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2854         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2855         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2856
2857         r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2858
2859         r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2860
2861         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2862         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2863         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2864
2865         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2866
2867         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2868
2869         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2870         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2871         r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2872
2873         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2874         for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2875                 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2876                 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2877         }
2878
2879         r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2880         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2881
2882         r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2883         r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2884         r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2885         r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2886
2887         r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2888         r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2889         r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2890         r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2891         r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2892
2893         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2894         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2895         r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2896
2897         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2898         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2899         r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2900
2901         r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2902         r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2903         r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2904         r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2905         r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2906         r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2907         r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2908
2909         /* to avoid GPU doing any preloading of constant from random address */
2910         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2911         for (i = 0; i < 16; i++)
2912                 r600_store_value(cb, 0);
2913
2914         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2915         for (i = 0; i < 16; i++)
2916                 r600_store_value(cb, 0);
2917
2918         r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2919         for (i = 0; i < 16; i++)
2920                 r600_store_value(cb, 0);
2921
2922         r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2923         for (i = 0; i < 16; i++)
2924                 r600_store_value(cb, 0);
2925
2926         r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2927         for (i = 0; i < 16; i++)
2928                 r600_store_value(cb, 0);
2929
2930         r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2931
2932         if (rctx->screen->b.has_streamout) {
2933                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2934         }
2935
2936         r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2937         r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2938         r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2939         r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2940         r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2941         r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2942
2943         r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2944         r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2945         r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2946
2947         if (rctx->b.family == CHIP_CAICOS) {
2948                 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2949                 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2950                 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2951                 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2952         } else {
2953                 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2954                 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2955                 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2956                 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2957                 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2958                 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2959                 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2960                 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2961         }
2962
2963         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2964         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2965         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2966         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2967         eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2968 }
2969
2970 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2971 {
2972         struct r600_context *rctx = (struct r600_context *)ctx;
2973         struct r600_command_buffer *cb = &shader->command_buffer;
2974         struct r600_shader *rshader = &shader->shader;
2975         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2976         int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2977         int ninterp = 0;
2978         boolean have_perspective = FALSE, have_linear = FALSE;
2979         static const unsigned spi_baryc_enable_bit[6] = {
2980                 S_0286E0_PERSP_SAMPLE_ENA(1),
2981                 S_0286E0_PERSP_CENTER_ENA(1),
2982                 S_0286E0_PERSP_CENTROID_ENA(1),
2983                 S_0286E0_LINEAR_SAMPLE_ENA(1),
2984                 S_0286E0_LINEAR_CENTER_ENA(1),
2985                 S_0286E0_LINEAR_CENTROID_ENA(1)
2986         };
2987         unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2988         unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2989         unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2990         uint32_t spi_ps_input_cntl[32];
2991
2992         if (!cb->buf) {
2993                 r600_init_command_buffer(cb, 64);
2994         } else {
2995                 cb->num_dw = 0;
2996         }
2997
2998         for (i = 0; i < rshader->ninput; i++) {
2999                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3000                    POSITION goes via GPRs from the SC so isn't counted */
3001                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3002                         pos_index = i;
3003                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3004                         if (face_index == -1)
3005                                 face_index = i;
3006                 }
3007                 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3008                         if (face_index == -1)
3009                                 face_index = i; /* lives in same register, same enable bit */
3010                 }
3011                 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3012                         fixed_pt_position_index = i;
3013                 }
3014                 else {
3015                         ninterp++;
3016                         int k = eg_get_interpolator_index(
3017                                 rshader->input[i].interpolate,
3018                                 rshader->input[i].interpolate_location);
3019                         if (k >= 0) {
3020                                 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3021                                 have_perspective |= k < 3;
3022                                 have_linear |= !(k < 3);
3023                         }
3024                 }
3025
3026                 sid = rshader->input[i].spi_sid;
3027
3028                 if (sid) {
3029                         tmp = S_028644_SEMANTIC(sid);
3030
3031                         if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3032                                 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3033                                 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3034                                         rctx->rasterizer && rctx->rasterizer->flatshade)) {
3035                                 tmp |= S_028644_FLAT_SHADE(1);
3036                         }
3037
3038                         if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3039                             (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3040                                 tmp |= S_028644_PT_SPRITE_TEX(1);
3041                         }
3042
3043                         spi_ps_input_cntl[num++] = tmp;
3044                 }
3045         }
3046
3047         r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3048         r600_store_array(cb, num, spi_ps_input_cntl);
3049
3050         for (i = 0; i < rshader->noutput; i++) {
3051                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3052                         z_export = 1;
3053                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3054                         stencil_export = 1;
3055                 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3056                         rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3057                         mask_export = 1;
3058         }
3059         if (rshader->uses_kill)
3060                 db_shader_control |= S_02880C_KILL_ENABLE(1);
3061
3062         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3063         db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3064         db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3065
3066         switch (rshader->ps_conservative_z) {
3067         default: /* fall through */
3068         case TGSI_FS_DEPTH_LAYOUT_ANY:
3069                 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3070                 break;
3071         case TGSI_FS_DEPTH_LAYOUT_GREATER:
3072                 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3073                 break;
3074         case TGSI_FS_DEPTH_LAYOUT_LESS:
3075                 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3076                 break;
3077         }
3078
3079         exports_ps = 0;
3080         for (i = 0; i < rshader->noutput; i++) {
3081                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3082                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3083                     rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3084                         exports_ps |= 1;
3085         }
3086
3087         num_cout = rshader->nr_ps_color_exports;
3088
3089         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3090         if (!exports_ps) {
3091                 /* always at least export 1 component per pixel */
3092                 exports_ps = 2;
3093         }
3094         shader->nr_ps_color_outputs = num_cout;
3095         if (ninterp == 0) {
3096                 ninterp = 1;
3097                 have_perspective = TRUE;
3098         }
3099         if (!spi_baryc_cntl)
3100                 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3101
3102         if (!have_perspective && !have_linear)
3103                 have_perspective = TRUE;
3104
3105         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3106                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3107                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3108         spi_input_z = 0;
3109         if (pos_index != -1) {
3110                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
3111                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3112                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3113                 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3114         }
3115
3116         spi_ps_in_control_1 = 0;
3117         if (face_index != -1) {
3118                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3119                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3120         }
3121         if (fixed_pt_position_index != -1) {
3122                 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3123                         S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3124         }
3125
3126         r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3127         r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3128         r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3129
3130         r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3131         r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3132         r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3133
3134         r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3135         r600_store_value(cb, shader->bo->gpu_address >> 8);
3136         r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3137                          S_028844_NUM_GPRS(rshader->bc.ngpr) |
3138                          S_028844_PRIME_CACHE_ON_DRAW(1) |
3139                          S_028844_STACK_SIZE(rshader->bc.nstack));
3140         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3141
3142         shader->db_shader_control = db_shader_control;
3143         shader->ps_depth_export = z_export | stencil_export | mask_export;
3144
3145         shader->sprite_coord_enable = sprite_coord_enable;
3146         if (rctx->rasterizer)
3147                 shader->flatshade = rctx->rasterizer->flatshade;
3148 }
3149
3150 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3151 {
3152         struct r600_command_buffer *cb = &shader->command_buffer;
3153         struct r600_shader *rshader = &shader->shader;
3154
3155         r600_init_command_buffer(cb, 32);
3156
3157         r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3158                                S_028890_NUM_GPRS(rshader->bc.ngpr) |
3159                                S_028890_STACK_SIZE(rshader->bc.nstack));
3160         r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3161                                shader->bo->gpu_address >> 8);
3162         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3163 }
3164
3165 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3166 {
3167         struct r600_context *rctx = (struct r600_context *)ctx;
3168         struct r600_command_buffer *cb = &shader->command_buffer;
3169         struct r600_shader *rshader = &shader->shader;
3170         struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3171         unsigned gsvs_itemsizes[4] = {
3172                         (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3173                         (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3174                         (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3175                         (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3176         };
3177
3178         r600_init_command_buffer(cb, 64);
3179
3180         /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3181
3182
3183         r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3184                                S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3185         r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3186                                r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3187
3188         if (rctx->screen->b.info.drm_minor >= 35) {
3189                 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3190                                 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3191                                 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3192         }
3193         r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3194         r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3195         r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3196         r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3197         r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3198
3199         r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3200                                (rshader->ring_item_sizes[0]) >> 2);
3201
3202         r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3203                                gsvs_itemsizes[0] +
3204                                gsvs_itemsizes[1] +
3205                                gsvs_itemsizes[2] +
3206                                gsvs_itemsizes[3]);
3207
3208         r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3209         r600_store_value(cb, gsvs_itemsizes[0]);
3210         r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3211         r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3212
3213         /* FIXME calculate these values somehow ??? */
3214         r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3215         r600_store_value(cb, 0x80); /* GS_PER_ES */
3216         r600_store_value(cb, 0x100); /* ES_PER_GS */
3217         r600_store_value(cb, 0x2); /* GS_PER_VS */
3218
3219         r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3220                                S_028878_NUM_GPRS(rshader->bc.ngpr) |
3221                                S_028878_STACK_SIZE(rshader->bc.nstack));
3222         r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3223                                shader->bo->gpu_address >> 8);
3224         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3225 }
3226
3227
3228 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3229 {
3230         struct r600_command_buffer *cb = &shader->command_buffer;
3231         struct r600_shader *rshader = &shader->shader;
3232         unsigned spi_vs_out_id[10] = {};
3233         unsigned i, tmp, nparams = 0;
3234
3235         for (i = 0; i < rshader->noutput; i++) {
3236                 if (rshader->output[i].spi_sid) {
3237                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3238                         spi_vs_out_id[nparams / 4] |= tmp;
3239                         nparams++;
3240                 }
3241         }
3242
3243         r600_init_command_buffer(cb, 32);
3244
3245         r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3246         for (i = 0; i < 10; i++) {
3247                 r600_store_value(cb, spi_vs_out_id[i]);
3248         }
3249
3250         /* Certain attributes (position, psize, etc.) don't count as params.
3251          * VS is required to export at least one param and r600_shader_from_tgsi()
3252          * takes care of adding a dummy export.
3253          */
3254         if (nparams < 1)
3255                 nparams = 1;
3256
3257         r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3258                                S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3259         r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3260                                S_028860_NUM_GPRS(rshader->bc.ngpr) |
3261                                S_028860_STACK_SIZE(rshader->bc.nstack));
3262         if (rshader->vs_position_window_space) {
3263                 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3264                         S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3265         } else {
3266                 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3267                         S_028818_VTX_W0_FMT(1) |
3268                         S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3269                         S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3270                         S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3271
3272         }
3273         r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3274                                shader->bo->gpu_address >> 8);
3275         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3276
3277         shader->pa_cl_vs_out_cntl =
3278                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3279                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3280                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3281                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3282                 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3283                 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3284                 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3285 }
3286
3287 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3288 {
3289         struct r600_command_buffer *cb = &shader->command_buffer;
3290         struct r600_shader *rshader = &shader->shader;
3291
3292         r600_init_command_buffer(cb, 32);
3293         r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3294                                S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3295                                S_0288BC_STACK_SIZE(rshader->bc.nstack));
3296         r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3297                                shader->bo->gpu_address >> 8);
3298 }
3299
3300 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3301 {
3302         struct r600_command_buffer *cb = &shader->command_buffer;
3303         struct r600_shader *rshader = &shader->shader;
3304
3305         r600_init_command_buffer(cb, 32);
3306         r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3307                                S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3308                                S_0288D4_STACK_SIZE(rshader->bc.nstack));
3309         r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3310                                shader->bo->gpu_address >> 8);
3311 }
3312 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3313 {
3314         struct pipe_blend_state blend;
3315
3316         memset(&blend, 0, sizeof(blend));
3317         blend.independent_blend_enable = true;
3318         blend.rt[0].colormask = 0xf;
3319         return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3320 }
3321
3322 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3323 {
3324         struct pipe_blend_state blend;
3325         unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3326                         V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3327
3328         memset(&blend, 0, sizeof(blend));
3329         blend.independent_blend_enable = true;
3330         blend.rt[0].colormask = 0xf;
3331         return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3332 }
3333
3334 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3335 {
3336         struct pipe_blend_state blend;
3337         unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3338
3339         memset(&blend, 0, sizeof(blend));
3340         blend.independent_blend_enable = true;
3341         blend.rt[0].colormask = 0xf;
3342         return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3343 }
3344
3345 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3346 {
3347         struct pipe_depth_stencil_alpha_state dsa = {{0}};
3348
3349         return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3350 }
3351
3352 void evergreen_update_db_shader_control(struct r600_context * rctx)
3353 {
3354         bool dual_export;
3355         unsigned db_shader_control;
3356
3357         if (!rctx->ps_shader) {
3358                 return;
3359         }
3360
3361         dual_export = rctx->framebuffer.export_16bpc &&
3362                       !rctx->ps_shader->current->ps_depth_export;
3363
3364         db_shader_control = rctx->ps_shader->current->db_shader_control |
3365                             S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3366                             S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3367                                                                     V_02880C_EXPORT_DB_FULL) |
3368                             S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3369
3370         /* When alpha test is enabled we can't trust the hw to make the proper
3371          * decision on the order in which ztest should be run related to fragment
3372          * shader execution.
3373          *
3374          * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3375          * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3376          * execution and thus after alpha test so if discarded by the alpha test
3377          * the z value is not written.
3378          * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3379          * get a hang unless you flush the DB in between.  For now just use
3380          * LATE_Z.
3381          */
3382         if (rctx->alphatest_state.sx_alpha_test_control) {
3383                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3384         } else {
3385                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3386         }
3387
3388         if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3389                 rctx->db_misc_state.db_shader_control = db_shader_control;
3390                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3391         }
3392 }
3393
3394 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3395                                 struct pipe_resource *dst,
3396                                 unsigned dst_level,
3397                                 unsigned dst_x,
3398                                 unsigned dst_y,
3399                                 unsigned dst_z,
3400                                 struct pipe_resource *src,
3401                                 unsigned src_level,
3402                                 unsigned src_x,
3403                                 unsigned src_y,
3404                                 unsigned src_z,
3405                                 unsigned copy_height,
3406                                 unsigned pitch,
3407                                 unsigned bpp)
3408 {
3409         struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3410         struct r600_texture *rsrc = (struct r600_texture*)src;
3411         struct r600_texture *rdst = (struct r600_texture*)dst;
3412         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3413         unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3414         unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3415         uint64_t base, addr;
3416
3417         dst_mode = rdst->surface.level[dst_level].mode;
3418         src_mode = rsrc->surface.level[src_level].mode;
3419         /* downcast linear aligned to linear to simplify test */
3420         src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3421         dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3422         assert(dst_mode != src_mode);
3423
3424         /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3425         if (util_format_has_depth(util_format_description(src->format)))
3426                 non_disp_tiling = 1;
3427
3428         y = 0;
3429         sub_cmd = EG_DMA_COPY_TILED;
3430         lbpp = util_logbase2(bpp);
3431         pitch_tile_max = ((pitch / bpp) / 8) - 1;
3432         nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3433
3434         if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3435                 /* T2L */
3436                 array_mode = evergreen_array_mode(src_mode);
3437                 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3438                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3439                 /* linear height must be the same as the slice tile max height, it's ok even
3440                  * if the linear destination/source have smaller heigh as the size of the
3441                  * dma packet will be using the copy_height which is always smaller or equal
3442                  * to the linear height
3443                  */
3444                 height = rsrc->surface.level[src_level].npix_y;
3445                 detile = 1;
3446                 x = src_x;
3447                 y = src_y;
3448                 z = src_z;
3449                 base = rsrc->surface.level[src_level].offset;
3450                 addr = rdst->surface.level[dst_level].offset;
3451                 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3452                 addr += dst_y * pitch + dst_x * bpp;
3453                 bank_h = eg_bank_wh(rsrc->surface.bankh);
3454                 bank_w = eg_bank_wh(rsrc->surface.bankw);
3455                 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3456                 tile_split = eg_tile_split(rsrc->surface.tile_split);
3457                 base += rsrc->resource.gpu_address;
3458                 addr += rdst->resource.gpu_address;
3459         } else {
3460                 /* L2T */
3461                 array_mode = evergreen_array_mode(dst_mode);
3462                 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3463                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3464                 /* linear height must be the same as the slice tile max height, it's ok even
3465                  * if the linear destination/source have smaller heigh as the size of the
3466                  * dma packet will be using the copy_height which is always smaller or equal
3467                  * to the linear height
3468                  */
3469                 height = rdst->surface.level[dst_level].npix_y;
3470                 detile = 0;
3471                 x = dst_x;
3472                 y = dst_y;
3473                 z = dst_z;
3474                 base = rdst->surface.level[dst_level].offset;
3475                 addr = rsrc->surface.level[src_level].offset;
3476                 addr += rsrc->surface.level[src_level].slice_size * src_z;
3477                 addr += src_y * pitch + src_x * bpp;
3478                 bank_h = eg_bank_wh(rdst->surface.bankh);
3479                 bank_w = eg_bank_wh(rdst->surface.bankw);
3480                 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3481                 tile_split = eg_tile_split(rdst->surface.tile_split);
3482                 base += rdst->resource.gpu_address;
3483                 addr += rsrc->resource.gpu_address;
3484         }
3485
3486         size = (copy_height * pitch) / 4;
3487         ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3488         r600_need_dma_space(&rctx->b, ncopy * 9);
3489
3490         for (i = 0; i < ncopy; i++) {
3491                 cheight = copy_height;
3492                 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3493                         cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3494                 }
3495                 size = (cheight * pitch) / 4;
3496                 /* emit reloc before writing cs so that cs is always in consistent state */
3497                 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3498                                       RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3499                 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3500                                       RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3501                 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3502                 cs->buf[cs->cdw++] = base >> 8;
3503                 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3504                                         (lbpp << 24) | (bank_h << 21) |
3505                                         (bank_w << 18) | (mt_aspect << 16);
3506                 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3507                 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3508                 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3509                 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3510                 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3511                 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3512                 copy_height -= cheight;
3513                 addr += cheight * pitch;
3514                 y += cheight;
3515         }
3516 }
3517
3518 static void evergreen_dma_copy(struct pipe_context *ctx,
3519                                struct pipe_resource *dst,
3520                                unsigned dst_level,
3521                                unsigned dstx, unsigned dsty, unsigned dstz,
3522                                struct pipe_resource *src,
3523                                unsigned src_level,
3524                                const struct pipe_box *src_box)
3525 {
3526         struct r600_context *rctx = (struct r600_context *)ctx;
3527         struct r600_texture *rsrc = (struct r600_texture*)src;
3528         struct r600_texture *rdst = (struct r600_texture*)dst;
3529         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3530         unsigned src_w, dst_w;
3531         unsigned src_x, src_y;
3532         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3533
3534         if (rctx->b.dma.cs == NULL) {
3535                 goto fallback;
3536         }
3537
3538         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3539                 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3540                 return;
3541         }
3542
3543         if (src->format != dst->format || src_box->depth > 1 ||
3544             (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3545                 goto fallback;
3546         }
3547
3548         if (rsrc->dirty_level_mask & (1 << src_level)) {
3549                 ctx->flush_resource(ctx, src);
3550         }
3551
3552         src_x = util_format_get_nblocksx(src->format, src_box->x);
3553         dst_x = util_format_get_nblocksx(src->format, dst_x);
3554         src_y = util_format_get_nblocksy(src->format, src_box->y);
3555         dst_y = util_format_get_nblocksy(src->format, dst_y);
3556
3557         bpp = rdst->surface.bpe;
3558         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3559         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3560         src_w = rsrc->surface.level[src_level].npix_x;
3561         dst_w = rdst->surface.level[dst_level].npix_x;
3562         copy_height = src_box->height / rsrc->surface.blk_h;
3563
3564         dst_mode = rdst->surface.level[dst_level].mode;
3565         src_mode = rsrc->surface.level[src_level].mode;
3566         /* downcast linear aligned to linear to simplify test */
3567         src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3568         dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3569
3570         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3571                 /* FIXME evergreen can do partial blit */
3572                 goto fallback;
3573         }
3574         /* the x test here are currently useless (because we don't support partial blit)
3575          * but keep them around so we don't forget about those
3576          */
3577         if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3578                 goto fallback;
3579         }
3580
3581         /* 128 bpp surfaces require non_disp_tiling for both
3582          * tiled and linear buffers on cayman.  However, async
3583          * DMA only supports it on the tiled side.  As such
3584          * the tile order is backwards after a L2T/T2L packet.
3585          */
3586         if ((rctx->b.chip_class == CAYMAN) &&
3587             (src_mode != dst_mode) &&
3588             (util_format_get_blocksize(src->format) >= 16)) {
3589                 goto fallback;
3590         }
3591
3592         if (src_mode == dst_mode) {
3593                 uint64_t dst_offset, src_offset;
3594                 /* simple dma blit would do NOTE code here assume :
3595                  *   src_box.x/y == 0
3596                  *   dst_x/y == 0
3597                  *   dst_pitch == src_pitch
3598                  */
3599                 src_offset= rsrc->surface.level[src_level].offset;
3600                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3601                 src_offset += src_y * src_pitch + src_x * bpp;
3602                 dst_offset = rdst->surface.level[dst_level].offset;
3603                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3604                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3605                 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3606                                         src_box->height * src_pitch);
3607         } else {
3608                 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3609                                         src, src_level, src_x, src_y, src_box->z,
3610                                         copy_height, dst_pitch, bpp);
3611         }
3612         return;
3613
3614 fallback:
3615         r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3616                                   src, src_level, src_box);
3617 }
3618
3619 static void evergreen_set_tess_state(struct pipe_context *ctx,
3620                                      const float default_outer_level[4],
3621                                      const float default_inner_level[2])
3622 {
3623         struct r600_context *rctx = (struct r600_context *)ctx;
3624
3625         memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3626         memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3627         rctx->tess_state_dirty = true;
3628 }
3629
3630 void evergreen_init_state_functions(struct r600_context *rctx)
3631 {
3632         unsigned id = 1;
3633         unsigned i;
3634         /* !!!
3635          *  To avoid GPU lockup registers must be emitted in a specific order
3636          * (no kidding ...). The order below is important and have been
3637          * partially inferred from analyzing fglrx command stream.
3638          *
3639          * Don't reorder atom without carefully checking the effect (GPU lockup
3640          * or piglit regression).
3641          * !!!
3642          */
3643         if (rctx->b.chip_class == EVERGREEN) {
3644                 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3645                 rctx->config_state.dyn_gpr_enabled = true;
3646         }
3647         r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3648         /* shader const */
3649         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3650         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3651         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3652         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3653         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3654         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3655         /* shader program */
3656         r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3657         /* sampler */
3658         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3659         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3660         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3661         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3662         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3663         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3664         /* resources */
3665         r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3666         r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3667         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3668         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3669         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3670         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3671         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3672         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3673
3674         r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3675
3676         if (rctx->b.chip_class == EVERGREEN) {
3677                 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3678         } else {
3679                 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3680         }
3681         rctx->sample_mask.sample_mask = ~0;
3682
3683         r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3684         r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3685         r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3686         r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3687         r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3688         r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3689         r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3690         r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3691         r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3692         r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3693         r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3694         r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0);
3695         r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3696         r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3697         r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3698         r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3699         r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3700         r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3701         for (i = 0; i < EG_NUM_HW_STAGES; i++)
3702                 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3703         r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3704         r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3705
3706         rctx->b.b.create_blend_state = evergreen_create_blend_state;
3707         rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3708         rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3709         rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3710         rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3711         rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3712         rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3713         rctx->b.b.set_min_samples = evergreen_set_min_samples;
3714         rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3715         rctx->b.b.set_tess_state = evergreen_set_tess_state;
3716         if (rctx->b.chip_class == EVERGREEN)
3717                 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3718         else
3719                 rctx->b.b.get_sample_position = cayman_get_sample_position;
3720         rctx->b.dma_copy = evergreen_dma_copy;
3721
3722         evergreen_init_compute_state_functions(rctx);
3723 }
3724
3725 /**
3726  * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3727  *
3728  * The information about LDS and other non-compile-time parameters is then
3729  * written to the const buffer.
3730
3731  * const buffer contains -
3732  * uint32_t input_patch_size
3733  * uint32_t input_vertex_size
3734  * uint32_t num_tcs_input_cp
3735  * uint32_t num_tcs_output_cp;
3736  * uint32_t output_patch_size
3737  * uint32_t output_vertex_size
3738  * uint32_t output_patch0_offset
3739  * uint32_t perpatch_output_offset
3740  * and the same constbuf is bound to LS/HS/VS(ES).
3741  */
3742 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3743 {
3744         struct pipe_constant_buffer constbuf = {0};
3745         struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3746         struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3747         unsigned num_tcs_input_cp = info->vertices_per_patch;
3748         unsigned num_tcs_outputs;
3749         unsigned num_tcs_output_cp;
3750         unsigned num_tcs_patch_outputs;
3751         unsigned num_tcs_inputs;
3752         unsigned input_vertex_size, output_vertex_size;
3753         unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3754         unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3755         uint32_t values[16];
3756         unsigned num_waves;
3757         unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3758         unsigned wave_divisor = (16 * num_pipes);
3759
3760         *num_patches = 1;
3761
3762         if (!rctx->tes_shader) {
3763                 rctx->lds_alloc = 0;
3764                 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3765                                               R600_LDS_INFO_CONST_BUFFER, NULL);
3766                 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3767                                               R600_LDS_INFO_CONST_BUFFER, NULL);
3768                 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3769                                               R600_LDS_INFO_CONST_BUFFER, NULL);
3770                 return;
3771         }
3772
3773         if (rctx->lds_alloc != 0 &&
3774             rctx->last_ls == ls &&
3775             !rctx->tess_state_dirty &&
3776             rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3777             rctx->last_tcs == tcs)
3778                 return;
3779
3780         num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3781
3782         if (rctx->tcs_shader) {
3783                 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3784                 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3785                 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3786         } else {
3787                 num_tcs_outputs = num_tcs_inputs;
3788                 num_tcs_output_cp = num_tcs_input_cp;
3789                 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3790         }
3791
3792         /* size in bytes */
3793         input_vertex_size = num_tcs_inputs * 16;
3794         output_vertex_size = num_tcs_outputs * 16;
3795
3796         input_patch_size = num_tcs_input_cp * input_vertex_size;
3797
3798         pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3799         output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3800
3801         output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3802         perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3803
3804         lds_size = output_patch0_offset + output_patch_size * *num_patches;
3805
3806         values[0] = input_patch_size;
3807         values[1] = input_vertex_size;
3808         values[2] = num_tcs_input_cp;
3809         values[3] = num_tcs_output_cp;
3810
3811         values[4] = output_patch_size;
3812         values[5] = output_vertex_size;
3813         values[6] = output_patch0_offset;
3814         values[7] = perpatch_output_offset;
3815
3816         /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3817            LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3818         num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3819
3820         rctx->lds_alloc = (lds_size | (num_waves << 14));
3821
3822         memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3823         values[14] = 0;
3824         values[15] = 0;
3825
3826         rctx->tess_state_dirty = false;
3827         rctx->last_ls = ls;
3828         rctx->last_tcs = tcs;
3829         rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3830
3831         constbuf.user_buffer = values;
3832         constbuf.buffer_size = 16 * 4;
3833
3834         rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3835                                       R600_LDS_INFO_CONST_BUFFER, &constbuf);
3836         rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3837                                       R600_LDS_INFO_CONST_BUFFER, &constbuf);
3838         rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3839                                       R600_LDS_INFO_CONST_BUFFER, &constbuf);
3840         pipe_resource_reference(&constbuf.buffer, NULL);
3841 }
3842
3843 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3844                                     const struct pipe_draw_info *info,
3845                                     unsigned num_patches)
3846 {
3847         unsigned num_output_cp;
3848
3849         if (!rctx->tes_shader)
3850                 return 0;
3851
3852         num_output_cp = rctx->tcs_shader ?
3853                 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3854                 info->vertices_per_patch;
3855
3856         return S_028B58_NUM_PATCHES(num_patches) |
3857                 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3858                 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3859 }
3860
3861 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3862                                 struct radeon_winsys_cs *cs,
3863                                 uint32_t ls_hs_config)
3864 {
3865         radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3866 }
3867
3868 void evergreen_set_lds_alloc(struct r600_context *rctx,
3869                              struct radeon_winsys_cs *cs,
3870                              uint32_t lds_alloc)
3871 {
3872         radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3873 }
3874
3875 /* on evergreen if you are running tessellation you need to disable dynamic
3876    GPRs to workaround a hardware bug.*/
3877 bool evergreen_adjust_gprs(struct r600_context *rctx)
3878 {
3879         unsigned num_gprs[EG_NUM_HW_STAGES];
3880         unsigned def_gprs[EG_NUM_HW_STAGES];
3881         unsigned cur_gprs[EG_NUM_HW_STAGES];
3882         unsigned new_gprs[EG_NUM_HW_STAGES];
3883         unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3884         unsigned max_gprs;
3885         unsigned i;
3886         unsigned total_gprs;
3887         unsigned tmp[3];
3888         bool rework = false, set_default = false, set_dirty = false;
3889         max_gprs = 0;
3890         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3891                 def_gprs[i] = rctx->default_gprs[i];
3892                 max_gprs += def_gprs[i];
3893         }
3894         max_gprs += def_num_clause_temp_gprs * 2;
3895
3896         /* if we have no TESS and dyn gpr is enabled then do nothing. */
3897         if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3898                 if (rctx->config_state.dyn_gpr_enabled)
3899                         return true;
3900
3901                 /* transition back to dyn gpr enabled state */
3902                 rctx->config_state.dyn_gpr_enabled = true;
3903                 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3904                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3905                 return true;
3906         }
3907
3908
3909         /* gather required shader gprs */
3910         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3911                 if (rctx->hw_shader_stages[i].shader)
3912                         num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3913                 else
3914                         num_gprs[i] = 0;
3915         }
3916
3917         cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3918         cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3919         cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3920         cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3921         cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3922         cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3923
3924         total_gprs = 0;
3925         for (i = 0; i < EG_NUM_HW_STAGES; i++)  {
3926                 new_gprs[i] = num_gprs[i];
3927                 total_gprs += num_gprs[i];
3928         }
3929
3930         if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3931                 return false;
3932
3933         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3934                 if (new_gprs[i] > cur_gprs[i]) {
3935                         rework = true;
3936                         break;
3937                 }
3938         }
3939
3940         if (rctx->config_state.dyn_gpr_enabled) {
3941                 set_dirty = true;
3942                 rctx->config_state.dyn_gpr_enabled = false;
3943         }
3944
3945         if (rework) {
3946                 set_default = true;
3947                 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3948                         if (new_gprs[i] > def_gprs[i])
3949                                 set_default = false;
3950                 }
3951
3952                 if (set_default) {
3953                         for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3954                                 new_gprs[i] = def_gprs[i];
3955                         }
3956                 } else {
3957                         unsigned ps_value = max_gprs;
3958
3959                         ps_value -= (def_num_clause_temp_gprs * 2);
3960                         for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3961                                 ps_value -= new_gprs[i];
3962
3963                         new_gprs[R600_HW_STAGE_PS] = ps_value;
3964                 }
3965
3966                 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3967                         S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3968                         S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3969
3970                 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3971                         S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3972
3973                 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3974                         S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3975
3976                 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3977                     rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3978                     rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3979                         rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3980                         rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3981                         rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3982                         set_dirty = true;
3983                 }
3984         }
3985
3986
3987         if (set_dirty) {
3988                 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3989                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3990         }
3991         return true;
3992 }