2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
32 #include <util/u_double_list.h>
33 #include <pipe/p_compiler.h>
35 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
37 #define R600_ERR(fmt, args...) \
38 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
116 struct r600_tiling_info {
117 unsigned num_channels;
119 unsigned group_bytes;
122 enum radeon_family r600_get_family(struct radeon *rw);
123 enum chip_class r600_get_family_class(struct radeon *radeon);
124 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
125 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
126 unsigned r600_get_minor_version(struct radeon *radeon);
127 unsigned r600_get_num_backends(struct radeon *radeon);
131 struct r600_bo *r600_bo(struct radeon *radeon,
132 unsigned size, unsigned alignment,
133 unsigned binding, unsigned usage);
134 struct r600_bo *r600_bo_handle(struct radeon *radeon,
135 unsigned handle, unsigned *array_mode);
136 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
137 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
138 void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
139 struct r600_bo *src);
140 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
141 unsigned stride, struct winsys_handle *whandle);
142 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
148 /* R600/R700 STATES */
149 #define R600_GROUP_MAX 16
150 #define R600_BLOCK_MAX_BO 32
151 #define R600_BLOCK_MAX_REG 128
153 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
154 /* there is a block entry for each register so 512 blocks */
155 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
156 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
157 #define RANGE_OFFSET_START 0x8000
159 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
161 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
162 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
164 struct r600_pipe_reg {
167 struct r600_block *block;
172 struct r600_pipe_state {
175 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG];
178 struct r600_pipe_resource_state {
181 struct r600_bo *bo[2];
184 #define R600_BLOCK_STATUS_ENABLED (1 << 0)
185 #define R600_BLOCK_STATUS_DIRTY (1 << 1)
187 struct r600_block_reloc {
189 unsigned flush_flags;
191 unsigned bo_pm4_index;
195 struct list_head list;
196 struct list_head enable_list;
199 unsigned start_offset;
200 unsigned pm4_ndwords;
201 unsigned pm4_flush_ndwords;
206 u32 pm4[R600_BLOCK_MAX_REG];
207 unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
208 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
212 struct r600_block **blocks;
221 uint32_t read_domain;
222 uint32_t write_domain;
232 /* The kind of query. Currently only OQ is supported. */
234 /* How many results have been written, in dwords. It's incremented
235 * after end_query and flush. */
236 unsigned num_results;
237 /* if we've flushed the query */
239 /* The buffer where query results are stored. */
240 struct r600_bo *buffer;
241 unsigned buffer_size;
242 /* linked list of queries */
243 struct list_head list;
246 #define R600_QUERY_STATE_STARTED (1 << 0)
247 #define R600_QUERY_STATE_ENDED (1 << 1)
248 #define R600_QUERY_STATE_SUSPENDED (1 << 2)
250 #define R600_CONTEXT_DRAW_PENDING (1 << 0)
251 #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
252 #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2)
254 struct r600_context {
255 struct radeon *radeon;
256 struct r600_range *range;
258 struct r600_block **blocks;
259 struct list_head dirty;
260 struct list_head enable_list;
261 unsigned pm4_ndwords;
262 unsigned pm4_cdwords;
263 unsigned pm4_dirty_cdwords;
264 unsigned ctx_pm4_ndwords;
267 struct r600_reloc *reloc;
268 struct radeon_bo **bo;
270 struct list_head query_list;
271 unsigned num_query_running;
272 struct list_head fenced_bo;
273 unsigned max_db; /* for OQ */
274 unsigned num_dest_buffers;
276 boolean predicate_drawing;
277 struct r600_range ps_resources;
278 struct r600_range vs_resources;
279 struct r600_range fs_resources;
280 int num_ps_resources, num_vs_resources, num_fs_resources;
285 u32 vgt_num_instances;
287 u32 vgt_draw_initiator;
288 u32 indices_bo_offset;
289 struct r600_bo *indices;
292 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
293 void r600_context_fini(struct r600_context *ctx);
294 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
295 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
296 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
297 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
298 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
299 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
300 void r600_context_flush(struct r600_context *ctx);
301 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
302 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
304 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
305 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
306 boolean r600_context_query_result(struct r600_context *ctx,
307 struct r600_query *query,
308 boolean wait, void *vresult);
309 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
310 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
311 void r600_context_queries_suspend(struct r600_context *ctx);
312 void r600_context_queries_resume(struct r600_context *ctx);
313 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
315 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
316 unsigned offset, unsigned value);
317 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
318 void r600_context_flush_dest_caches(struct r600_context *ctx);
320 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
321 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
322 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
323 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
324 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
325 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
326 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
327 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
329 struct radeon *radeon_decref(struct radeon *radeon);
331 void _r600_pipe_state_add_reg(struct r600_context *ctx,
332 struct r600_pipe_state *state,
333 u32 offset, u32 value, u32 mask,
334 u32 range_id, u32 block_id,
337 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
338 u32 offset, u32 value, u32 mask,
340 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
342 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
345 state->regs[state->nregs].value = value;
349 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
350 u32 value, struct r600_bo *bo)
352 state->regs[state->nregs].value = value;
353 state->regs[state->nregs].bo = bo;