src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include <errno.h>
  30 #include "pipe/p_shader_tokens.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_debug.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_uvd.h"
  41 #include "os/os_time.h"
  42
  43 static const struct debug_named_value debug_options[] = {
  44         /* logging */
  45         { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
  46         { "compute", DBG_COMPUTE, "Print compute info" },
  47         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
  48
  49         /* shaders */
  50         { "fs", DBG_FS, "Print fetch shaders" },
  51         { "vs", DBG_VS, "Print vertex shaders" },
  52         { "gs", DBG_GS, "Print geometry shaders" },
  53         { "ps", DBG_PS, "Print pixel shaders" },
  54         { "cs", DBG_CS, "Print compute shaders" },
  55
  56         /* features */
  57         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
  58 #if defined(R600_USE_LLVM)
  59         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  60 #endif
  61         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  62         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  63         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
  64         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
  65
  66         DEBUG_NAMED_VALUE_END /* must be last */
  67 };
  68
  69 /*
  70  * pipe_context
  71  */
  72 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  73 {
  74         struct r600_screen *rscreen = rctx->screen;
  75         struct r600_fence *fence = NULL;
  76
  77         pipe_mutex_lock(rscreen->fences.mutex);
  78
  79         if (!rscreen->fences.bo) {
  80                 /* Create the shared buffer object */
  81                 rscreen->fences.bo = (struct r600_resource*)
  82                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  83                                            PIPE_USAGE_STAGING, 4096);
  84                 if (!rscreen->fences.bo) {
  85                         R600_ERR("r600: failed to create bo for fence objects\n");
  86                         goto out;
  87                 }
  88                 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
  89         }
  90
  91         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  92                 struct r600_fence *entry;
  93
  94                 /* Try to find a freed fence that has been signalled */
  95                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  96                         if (rscreen->fences.data[entry->index] != 0) {
  97                                 LIST_DELINIT(&entry->head);
  98                                 fence = entry;
  99                                 break;
 100                         }
 101                 }
 102         }
 103
 104         if (!fence) {
 105                 /* Allocate a new fence */
 106                 struct r600_fence_block *block;
 107                 unsigned index;
 108
 109                 if ((rscreen->fences.next_index + 1) >= 1024) {
 110                         R600_ERR("r600: too many concurrent fences\n");
 111                         goto out;
 112                 }
 113
 114                 index = rscreen->fences.next_index++;
 115
 116                 if (!(index % FENCE_BLOCK_SIZE)) {
 117                         /* Allocate a new block */
 118                         block = CALLOC_STRUCT(r600_fence_block);
 119                         if (block == NULL)
 120                                 goto out;
 121
 122                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 123                 } else {
 124                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 125                 }
 126
 127                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 128                 fence->index = index;
 129         }
 130
 131         pipe_reference_init(&fence->reference, 1);
 132
 133         rscreen->fences.data[fence->index] = 0;
 134         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 135
 136         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 137         fence->sleep_bo = (struct r600_resource*)
 138                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 139                                            PIPE_USAGE_STAGING, 1);
 140         /* Add the fence as a dummy relocation. */
 141         r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 142
 143 out:
 144         pipe_mutex_unlock(rscreen->fences.mutex);
 145         return fence;
 146 }
 147
 148 static void r600_flush(struct pipe_context *ctx, unsigned flags)
 149 {
 150         struct r600_context *rctx = (struct r600_context *)ctx;
 151         struct pipe_query *render_cond = NULL;
 152         unsigned render_cond_mode = 0;
 153
 154         rctx->rings.gfx.flushing = true;
 155         /* Disable render condition. */
 156         if (rctx->current_render_cond) {
 157                 render_cond = rctx->current_render_cond;
 158                 render_cond_mode = rctx->current_render_cond_mode;
 159                 ctx->render_condition(ctx, NULL, 0);
 160         }
 161
 162         r600_context_flush(rctx, flags);
 163         rctx->rings.gfx.flushing = false;
 164         r600_begin_new_cs(rctx);
 165
 166         /* Re-enable render condition. */
 167         if (render_cond) {
 168                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 169         }
 170 }
 171
 172 static void r600_flush_from_st(struct pipe_context *ctx,
 173                                struct pipe_fence_handle **fence,
 174                                enum pipe_flush_flags flags)
 175 {
 176         struct r600_context *rctx = (struct r600_context *)ctx;
 177         struct r600_fence **rfence = (struct r600_fence**)fence;
 178         unsigned fflags;
 179
 180         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 181         if (rfence) {
 182                 *rfence = r600_create_fence(rctx);
 183         }
 184         /* flush gfx & dma ring, order does not matter as only one can be live */
 185         if (rctx->rings.dma.cs) {
 186                 rctx->rings.dma.flush(rctx, fflags);
 187         }
 188         rctx->rings.gfx.flush(rctx, fflags);
 189 }
 190
 191 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 192 {
 193         r600_flush((struct pipe_context*)ctx, flags);
 194 }
 195
 196 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 197 {
 198         struct r600_context *rctx = (struct r600_context *)ctx;
 199         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 200         unsigned padding_dw, i;
 201
 202         if (!cs->cdw) {
 203                 return;
 204         }
 205
 206         /* Pad the DMA CS to a multiple of 8 dwords. */
 207         padding_dw = 8 - cs->cdw % 8;
 208         if (padding_dw < 8) {
 209                 for (i = 0; i < padding_dw; i++) {
 210                         cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
 211                 }
 212         }
 213
 214         rctx->rings.dma.flushing = true;
 215         rctx->ws->cs_flush(cs, flags);
 216         rctx->rings.dma.flushing = false;
 217 }
 218
 219 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
 220                                         struct radeon_winsys_cs_handle *buf,
 221                                         enum radeon_bo_usage usage)
 222 {
 223         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
 224                 return TRUE;
 225         }
 226         if (ctx->rings.dma.cs) {
 227                 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
 228                         return TRUE;
 229                 }
 230         }
 231         return FALSE;
 232 }
 233
 234 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
 235                                         struct r600_resource *resource,
 236                                         unsigned usage)
 237 {
 238         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
 239         unsigned flags = 0;
 240         bool sync_flush = TRUE;
 241
 242         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 243                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 244         }
 245
 246         if (!(usage & PIPE_TRANSFER_WRITE)) {
 247                 /* have to wait for pending read */
 248                 rusage = RADEON_USAGE_WRITE;
 249         }
 250         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 251                 flags |= RADEON_FLUSH_ASYNC;
 252         }
 253
 254         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
 255                 ctx->rings.gfx.flush(ctx, flags);
 256                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
 257                         return NULL;
 258                 }
 259         }
 260         if (ctx->rings.dma.cs) {
 261                 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
 262                         ctx->rings.dma.flush(ctx, flags);
 263                         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 264                                 return NULL;
 265                         }
 266                 }
 267         }
 268
 269         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 270                 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
 271                         return NULL;
 272                 }
 273         }
 274         if (sync_flush) {
 275                 /* Try to avoid busy-waiting in radeon_bo_wait. */
 276                 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
 277                 if (ctx->rings.dma.cs) {
 278                         ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
 279                 }
 280         }
 281         ctx->ws->buffer_wait(resource->buf, rusage);
 282
 283         /* at this point everything is synchronized */
 284         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage | PIPE_TRANSFER_UNSYNCHRONIZED);
 285 }
 286
 287 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 288 {
 289         struct r600_context *rctx = (struct r600_context *)ctx;
 290
 291         rctx->rings.gfx.flush(rctx, flags);
 292 }
 293
 294 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 295 {
 296         struct r600_context *rctx = (struct r600_context *)ctx;
 297
 298         rctx->rings.dma.flush(rctx, flags);
 299 }
 300
 301 static void r600_destroy_context(struct pipe_context *context)
 302 {
 303         struct r600_context *rctx = (struct r600_context *)context;
 304
 305         r600_isa_destroy(rctx->isa);
 306
 307         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 308         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 309
 310         if (rctx->dummy_pixel_shader) {
 311                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 312         }
 313         if (rctx->custom_dsa_flush) {
 314                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 315         }
 316         if (rctx->custom_blend_resolve) {
 317                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
 318         }
 319         if (rctx->custom_blend_decompress) {
 320                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
 321         }
 322         if (rctx->custom_blend_fmask_decompress) {
 323                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
 324         }
 325         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 326
 327         if (rctx->blitter) {
 328                 util_blitter_destroy(rctx->blitter);
 329         }
 330         if (rctx->uploader) {
 331                 u_upload_destroy(rctx->uploader);
 332         }
 333         if (rctx->allocator_so_filled_size) {
 334                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 335         }
 336         if (rctx->allocator_fetch_shader) {
 337                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 338         }
 339         util_slab_destroy(&rctx->pool_transfers);
 340
 341         r600_release_command_buffer(&rctx->start_cs_cmd);
 342
 343         if (rctx->rings.gfx.cs) {
 344                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 345         }
 346         if (rctx->rings.dma.cs) {
 347                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 348         }
 349
 350         FREE(rctx);
 351 }
 352
 353 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 354 {
 355         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 356         struct r600_screen* rscreen = (struct r600_screen *)screen;
 357
 358         if (rctx == NULL)
 359                 return NULL;
 360
 361         util_slab_create(&rctx->pool_transfers,
 362                          sizeof(struct r600_transfer), 64,
 363                          UTIL_SLAB_SINGLETHREADED);
 364
 365         rctx->context.screen = screen;
 366         rctx->context.priv = priv;
 367         rctx->context.destroy = r600_destroy_context;
 368         rctx->context.flush = r600_flush_from_st;
 369
 370         /* Easy accessing of screen/winsys. */
 371         rctx->screen = rscreen;
 372         rctx->ws = rscreen->ws;
 373         rctx->family = rscreen->family;
 374         rctx->chip_class = rscreen->chip_class;
 375         rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
 376
 377         LIST_INITHEAD(&rctx->active_nontimer_queries);
 378
 379         r600_init_blit_functions(rctx);
 380         r600_init_query_functions(rctx);
 381         r600_init_context_resource_functions(rctx);
 382         r600_init_surface_functions(rctx);
 383
 384         if (rscreen->info.has_uvd) {
 385                 rctx->context.create_video_decoder = r600_uvd_create_decoder;
 386                 rctx->context.create_video_buffer = r600_video_buffer_create;
 387         } else {
 388                 rctx->context.create_video_decoder = vl_create_decoder;
 389                 rctx->context.create_video_buffer = vl_video_buffer_create;
 390         }
 391
 392         r600_init_common_state_functions(rctx);
 393
 394         switch (rctx->chip_class) {
 395         case R600:
 396         case R700:
 397                 r600_init_state_functions(rctx);
 398                 r600_init_atom_start_cs(rctx);
 399                 rctx->max_db = 4;
 400                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 401                 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
 402                                                                       : r600_create_resolve_blend(rctx);
 403                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 404                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 405                                            rctx->family == CHIP_RV620 ||
 406                                            rctx->family == CHIP_RS780 ||
 407                                            rctx->family == CHIP_RS880 ||
 408                                            rctx->family == CHIP_RV710);
 409                 break;
 410         case EVERGREEN:
 411         case CAYMAN:
 412                 evergreen_init_state_functions(rctx);
 413                 evergreen_init_atom_start_cs(rctx);
 414                 evergreen_init_atom_start_compute_cs(rctx);
 415                 rctx->max_db = 8;
 416                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 417                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 418                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 419                 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
 420                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 421                                            rctx->family == CHIP_PALM ||
 422                                            rctx->family == CHIP_SUMO ||
 423                                            rctx->family == CHIP_SUMO2 ||
 424                                            rctx->family == CHIP_CAICOS ||
 425                                            rctx->family == CHIP_CAYMAN ||
 426                                            rctx->family == CHIP_ARUBA);
 427                 break;
 428         default:
 429                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 430                 goto fail;
 431         }
 432
 433         rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX);
 434         rctx->rings.gfx.flush = r600_flush_gfx_ring;
 435         rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
 436         rctx->rings.gfx.flushing = false;
 437
 438         rctx->rings.dma.cs = NULL;
 439         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 440                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA);
 441                 rctx->rings.dma.flush = r600_flush_dma_ring;
 442                 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 443                 rctx->rings.dma.flushing = false;
 444         }
 445
 446         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 447                                         PIPE_BIND_INDEX_BUFFER |
 448                                         PIPE_BIND_CONSTANT_BUFFER);
 449         if (!rctx->uploader)
 450                 goto fail;
 451
 452         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
 453                                                              0, PIPE_USAGE_STATIC, FALSE);
 454         if (!rctx->allocator_fetch_shader)
 455                 goto fail;
 456
 457         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
 458                                                                 0, PIPE_USAGE_STATIC, TRUE);
 459         if (!rctx->allocator_so_filled_size)
 460                 goto fail;
 461
 462         rctx->isa = calloc(1, sizeof(struct r600_isa));
 463         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 464                 goto fail;
 465
 466         rctx->blitter = util_blitter_create(&rctx->context);
 467         if (rctx->blitter == NULL)
 468                 goto fail;
 469         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 470         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 471
 472         r600_begin_new_cs(rctx);
 473         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 474
 475         rctx->dummy_pixel_shader =
 476                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 477                                                      TGSI_SEMANTIC_GENERIC,
 478                                                      TGSI_INTERPOLATE_CONSTANT);
 479         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 480
 481         return &rctx->context;
 482
 483 fail:
 484         r600_destroy_context(&rctx->context);
 485         return NULL;
 486 }
 487
 488 /*
 489  * pipe_screen
 490  */
 491 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 492 {
 493         return "X.Org";
 494 }
 495
 496 static const char *r600_get_family_name(enum radeon_family family)
 497 {
 498         switch(family) {
 499         case CHIP_R600: return "AMD R600";
 500         case CHIP_RV610: return "AMD RV610";
 501         case CHIP_RV630: return "AMD RV630";
 502         case CHIP_RV670: return "AMD RV670";
 503         case CHIP_RV620: return "AMD RV620";
 504         case CHIP_RV635: return "AMD RV635";
 505         case CHIP_RS780: return "AMD RS780";
 506         case CHIP_RS880: return "AMD RS880";
 507         case CHIP_RV770: return "AMD RV770";
 508         case CHIP_RV730: return "AMD RV730";
 509         case CHIP_RV710: return "AMD RV710";
 510         case CHIP_RV740: return "AMD RV740";
 511         case CHIP_CEDAR: return "AMD CEDAR";
 512         case CHIP_REDWOOD: return "AMD REDWOOD";
 513         case CHIP_JUNIPER: return "AMD JUNIPER";
 514         case CHIP_CYPRESS: return "AMD CYPRESS";
 515         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 516         case CHIP_PALM: return "AMD PALM";
 517         case CHIP_SUMO: return "AMD SUMO";
 518         case CHIP_SUMO2: return "AMD SUMO2";
 519         case CHIP_BARTS: return "AMD BARTS";
 520         case CHIP_TURKS: return "AMD TURKS";
 521         case CHIP_CAICOS: return "AMD CAICOS";
 522         case CHIP_CAYMAN: return "AMD CAYMAN";
 523         case CHIP_ARUBA: return "AMD ARUBA";
 524         default: return "AMD unknown";
 525         }
 526 }
 527
 528 static const char* r600_get_name(struct pipe_screen* pscreen)
 529 {
 530         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 531
 532         return r600_get_family_name(rscreen->family);
 533 }
 534
 535 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 536 {
 537         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 538         enum radeon_family family = rscreen->family;
 539
 540         switch (param) {
 541         /* Supported features (boolean caps). */
 542         case PIPE_CAP_NPOT_TEXTURES:
 543         case PIPE_CAP_TWO_SIDED_STENCIL:
 544         case PIPE_CAP_ANISOTROPIC_FILTER:
 545         case PIPE_CAP_POINT_SPRITE:
 546         case PIPE_CAP_OCCLUSION_QUERY:
 547         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 548         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 549         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 550         case PIPE_CAP_TEXTURE_SWIZZLE:
 551         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 552         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 553         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 554         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 555         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 556         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 557         case PIPE_CAP_SM3:
 558         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 559         case PIPE_CAP_PRIMITIVE_RESTART:
 560         case PIPE_CAP_CONDITIONAL_RENDER:
 561         case PIPE_CAP_TEXTURE_BARRIER:
 562         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 563         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 564         case PIPE_CAP_TGSI_INSTANCEID:
 565         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 566         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 567         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 568         case PIPE_CAP_USER_INDEX_BUFFERS:
 569         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 570         case PIPE_CAP_COMPUTE:
 571         case PIPE_CAP_START_INSTANCE:
 572         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 573         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 574         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 575         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 576                 return 1;
 577         case PIPE_CAP_TGSI_TEXCOORD:
 578                 return 0;
 579
 580         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 581                 return R600_MAP_BUFFER_ALIGNMENT;
 582
 583         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 584                 return 256;
 585
 586         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 587                 return 1;
 588
 589         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 590                 return 140;
 591
 592         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 593                 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
 594
 595         /* Supported except the original R600. */
 596         case PIPE_CAP_INDEP_BLEND_ENABLE:
 597         case PIPE_CAP_INDEP_BLEND_FUNC:
 598                 /* R600 doesn't support per-MRT blends */
 599                 return family == CHIP_R600 ? 0 : 1;
 600
 601         /* Supported on Evergreen. */
 602         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 603         case PIPE_CAP_CUBE_MAP_ARRAY:
 604                 return family >= CHIP_CEDAR ? 1 : 0;
 605
 606         /* Unsupported features. */
 607         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 608         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 609         case PIPE_CAP_SCALED_RESOLVE:
 610         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 611         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 612         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 613         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 614         case PIPE_CAP_USER_VERTEX_BUFFERS:
 615                 return 0;
 616
 617         /* Stream output. */
 618         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 619                 return rscreen->has_streamout ? 4 : 0;
 620         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 621                 return rscreen->has_streamout ? 1 : 0;
 622         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 623         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 624                 return 32*4;
 625
 626         /* Texturing. */
 627         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 628         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 629         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 630                 if (family >= CHIP_CEDAR)
 631                         return 15;
 632                 else
 633                         return 14;
 634         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 635                 return rscreen->info.drm_minor >= 9 ?
 636                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 637         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 638                 return 32;
 639
 640         /* Render targets. */
 641         case PIPE_CAP_MAX_RENDER_TARGETS:
 642                 /* XXX some r6xx are buggy and can only do 4 */
 643                 return 8;
 644
 645         /* Timer queries, present when the clock frequency is non zero. */
 646         case PIPE_CAP_QUERY_TIME_ELAPSED:
 647                 return rscreen->info.r600_clock_crystal_freq != 0;
 648         case PIPE_CAP_QUERY_TIMESTAMP:
 649                 return rscreen->info.drm_minor >= 20 &&
 650                        rscreen->info.r600_clock_crystal_freq != 0;
 651
 652         case PIPE_CAP_MIN_TEXEL_OFFSET:
 653                 return -8;
 654
 655         case PIPE_CAP_MAX_TEXEL_OFFSET:
 656                 return 7;
 657
 658         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 659                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 660         }
 661         return 0;
 662 }
 663
 664 static float r600_get_paramf(struct pipe_screen* pscreen,
 665                              enum pipe_capf param)
 666 {
 667         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 668         enum radeon_family family = rscreen->family;
 669
 670         switch (param) {
 671         case PIPE_CAPF_MAX_LINE_WIDTH:
 672         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 673         case PIPE_CAPF_MAX_POINT_WIDTH:
 674         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 675                 if (family >= CHIP_CEDAR)
 676                         return 16384.0f;
 677                 else
 678                         return 8192.0f;
 679         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 680                 return 16.0f;
 681         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 682                 return 16.0f;
 683         case PIPE_CAPF_GUARD_BAND_LEFT:
 684         case PIPE_CAPF_GUARD_BAND_TOP:
 685         case PIPE_CAPF_GUARD_BAND_RIGHT:
 686         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 687                 return 0.0f;
 688         }
 689         return 0.0f;
 690 }
 691
 692 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 693 {
 694         switch(shader)
 695         {
 696         case PIPE_SHADER_FRAGMENT:
 697         case PIPE_SHADER_VERTEX:
 698         case PIPE_SHADER_COMPUTE:
 699                 break;
 700         case PIPE_SHADER_GEOMETRY:
 701                 /* XXX: support and enable geometry programs */
 702                 return 0;
 703         default:
 704                 /* XXX: support tessellation on Evergreen */
 705                 return 0;
 706         }
 707
 708         switch (param) {
 709         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 710         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 711         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 712         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 713                 return 16384;
 714         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 715                 return 32;
 716         case PIPE_SHADER_CAP_MAX_INPUTS:
 717                 return 32;
 718         case PIPE_SHADER_CAP_MAX_TEMPS:
 719                 return 256; /* Max native temporaries. */
 720         case PIPE_SHADER_CAP_MAX_ADDRS:
 721                 /* XXX Isn't this equal to TEMPS? */
 722                 return 1; /* Max native address registers */
 723         case PIPE_SHADER_CAP_MAX_CONSTS:
 724                 return R600_MAX_CONST_BUFFER_SIZE;
 725         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 726                 return R600_MAX_USER_CONST_BUFFERS;
 727         case PIPE_SHADER_CAP_MAX_PREDS:
 728                 return 0; /* nothing uses this */
 729         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 730                 return 1;
 731         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 732                 return 0;
 733         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 734         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 735         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 736         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 737                 return 1;
 738         case PIPE_SHADER_CAP_SUBROUTINES:
 739                 return 0;
 740         case PIPE_SHADER_CAP_INTEGERS:
 741                 return 1;
 742         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 743                 return 16;
 744         case PIPE_SHADER_CAP_PREFERRED_IR:
 745                 if (shader == PIPE_SHADER_COMPUTE) {
 746                         return PIPE_SHADER_IR_LLVM;
 747                 } else {
 748                         return PIPE_SHADER_IR_TGSI;
 749                 }
 750         }
 751         return 0;
 752 }
 753
 754 static int r600_get_video_param(struct pipe_screen *screen,
 755                                 enum pipe_video_profile profile,
 756                                 enum pipe_video_cap param)
 757 {
 758         switch (param) {
 759         case PIPE_VIDEO_CAP_SUPPORTED:
 760                 return vl_profile_supported(screen, profile);
 761         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 762                 return 1;
 763         case PIPE_VIDEO_CAP_MAX_WIDTH:
 764         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 765                 return vl_video_buffer_max_size(screen);
 766         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 767                 return PIPE_FORMAT_NV12;
 768         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 769                 return false;
 770         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 771                 return false;
 772         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 773                 return true;
 774         default:
 775                 return 0;
 776         }
 777 }
 778
 779 const char * r600_llvm_gpu_string(enum radeon_family family)
 780 {
 781         const char * gpu_family;
 782
 783         switch (family) {
 784         case CHIP_R600:
 785         case CHIP_RV610:
 786         case CHIP_RV630:
 787         case CHIP_RV620:
 788         case CHIP_RV635:
 789         case CHIP_RV670:
 790         case CHIP_RS780:
 791         case CHIP_RS880:
 792                 gpu_family = "r600";
 793                 break;
 794         case CHIP_RV710:
 795                 gpu_family = "rv710";
 796                 break;
 797         case CHIP_RV730:
 798                 gpu_family = "rv730";
 799                 break;
 800         case CHIP_RV740:
 801         case CHIP_RV770:
 802                 gpu_family = "rv770";
 803                 break;
 804         case CHIP_PALM:
 805         case CHIP_CEDAR:
 806                 gpu_family = "cedar";
 807                 break;
 808         case CHIP_SUMO:
 809         case CHIP_SUMO2:
 810         case CHIP_REDWOOD:
 811                 gpu_family = "redwood";
 812                 break;
 813         case CHIP_JUNIPER:
 814                 gpu_family = "juniper";
 815                 break;
 816         case CHIP_HEMLOCK:
 817         case CHIP_CYPRESS:
 818                 gpu_family = "cypress";
 819                 break;
 820         case CHIP_BARTS:
 821                 gpu_family = "barts";
 822                 break;
 823         case CHIP_TURKS:
 824                 gpu_family = "turks";
 825                 break;
 826         case CHIP_CAICOS:
 827                 gpu_family = "caicos";
 828                 break;
 829         case CHIP_CAYMAN:
 830         case CHIP_ARUBA:
 831                 gpu_family = "cayman";
 832                 break;
 833         default:
 834                 gpu_family = "";
 835                 fprintf(stderr, "Chip not supported by r600 llvm "
 836                         "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
 837                 break;
 838         }
 839         return gpu_family;
 840 }
 841
 842
 843 static int r600_get_compute_param(struct pipe_screen *screen,
 844         enum pipe_compute_cap param,
 845         void *ret)
 846 {
 847         struct r600_screen *rscreen = (struct r600_screen *)screen;
 848         //TODO: select these params by asic
 849         switch (param) {
 850         case PIPE_COMPUTE_CAP_IR_TARGET: {
 851                 const char *gpu = r600_llvm_gpu_string(rscreen->family);
 852                 if (ret) {
 853                         sprintf(ret, "%s-r600--", gpu);
 854                 }
 855                 return (8 + strlen(gpu)) * sizeof(char);
 856         }
 857         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 858                 if (ret) {
 859                         uint64_t * grid_dimension = ret;
 860                         grid_dimension[0] = 3;
 861                 }
 862                 return 1 * sizeof(uint64_t);
 863
 864         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 865                 if (ret) {
 866                         uint64_t * grid_size = ret;
 867                         grid_size[0] = 65535;
 868                         grid_size[1] = 65535;
 869                         grid_size[2] = 1;
 870                 }
 871                 return 3 * sizeof(uint64_t) ;
 872
 873         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 874                 if (ret) {
 875                         uint64_t * block_size = ret;
 876                         block_size[0] = 256;
 877                         block_size[1] = 256;
 878                         block_size[2] = 256;
 879                 }
 880                 return 3 * sizeof(uint64_t);
 881
 882         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 883                 if (ret) {
 884                         uint64_t * max_threads_per_block = ret;
 885                         *max_threads_per_block = 256;
 886                 }
 887                 return sizeof(uint64_t);
 888
 889         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 890                 if (ret) {
 891                         uint64_t * max_global_size = ret;
 892                         /* XXX: This is what the proprietary driver reports, we
 893                          * may want to use a different value. */
 894                         *max_global_size = 201326592;
 895                 }
 896                 return sizeof(uint64_t);
 897
 898         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 899                 if (ret) {
 900                         uint64_t * max_input_size = ret;
 901                         *max_input_size = 1024;
 902                 }
 903                 return sizeof(uint64_t);
 904
 905         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 906                 if (ret) {
 907                         uint64_t * max_local_size = ret;
 908                         /* XXX: This is what the proprietary driver reports, we
 909                          * may want to use a different value. */
 910                         *max_local_size = 32768;
 911                 }
 912                 return sizeof(uint64_t);
 913
 914         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 915                 if (ret) {
 916                         uint64_t max_global_size;
 917                         uint64_t * max_mem_alloc_size = ret;
 918                         r600_get_compute_param(screen,
 919                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 920                                         &max_global_size);
 921                         /* OpenCL requres this value be at least
 922                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 923                          * I'm really not sure what value to report here, but
 924                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 925                          */
 926                         *max_mem_alloc_size = max_global_size / 4;
 927                 }
 928                 return sizeof(uint64_t);
 929
 930         default:
 931                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 932                 return 0;
 933         }
 934 }
 935
 936 static void r600_destroy_screen(struct pipe_screen* pscreen)
 937 {
 938         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 939
 940         if (rscreen == NULL)
 941                 return;
 942
 943         if (rscreen->global_pool) {
 944                 compute_memory_pool_delete(rscreen->global_pool);
 945         }
 946
 947         if (rscreen->fences.bo) {
 948                 struct r600_fence_block *entry, *tmp;
 949
 950                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 951                         LIST_DEL(&entry->head);
 952                         FREE(entry);
 953                 }
 954
 955                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 956                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 957         }
 958 #if R600_TRACE_CS
 959         if (rscreen->trace_bo) {
 960                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 961                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 962         }
 963 #endif
 964         pipe_mutex_destroy(rscreen->fences.mutex);
 965
 966         rscreen->ws->destroy(rscreen->ws);
 967         FREE(rscreen);
 968 }
 969
 970 static void r600_fence_reference(struct pipe_screen *pscreen,
 971                                  struct pipe_fence_handle **ptr,
 972                                  struct pipe_fence_handle *fence)
 973 {
 974         struct r600_fence **oldf = (struct r600_fence**)ptr;
 975         struct r600_fence *newf = (struct r600_fence*)fence;
 976
 977         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 978                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 979                 pipe_mutex_lock(rscreen->fences.mutex);
 980                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 981                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 982                 pipe_mutex_unlock(rscreen->fences.mutex);
 983         }
 984
 985         *ptr = fence;
 986 }
 987
 988 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 989                                     struct pipe_fence_handle *fence)
 990 {
 991         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 992         struct r600_fence *rfence = (struct r600_fence*)fence;
 993
 994         return rscreen->fences.data[rfence->index] != 0;
 995 }
 996
 997 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 998                                  struct pipe_fence_handle *fence,
 999                                  uint64_t timeout)
1000 {
1001         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1002         struct r600_fence *rfence = (struct r600_fence*)fence;
1003         int64_t start_time = 0;
1004         unsigned spins = 0;
1005
1006         if (timeout != PIPE_TIMEOUT_INFINITE) {
1007                 start_time = os_time_get();
1008
1009                 /* Convert to microseconds. */
1010                 timeout /= 1000;
1011         }
1012
1013         while (rscreen->fences.data[rfence->index] == 0) {
1014                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
1015                 if (timeout == PIPE_TIMEOUT_INFINITE) {
1016                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
1017                         break;
1018                 }
1019
1020                 /* The dummy BO will be busy until the CS including the fence has completed, or
1021                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
1022                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
1023                         break;
1024
1025                 if (++spins % 256)
1026                         continue;
1027 #ifdef PIPE_OS_UNIX
1028                 sched_yield();
1029 #else
1030                 os_time_sleep(10);
1031 #endif
1032                 if (timeout != PIPE_TIMEOUT_INFINITE &&
1033                     os_time_get() - start_time >= timeout) {
1034                         break;
1035                 }
1036         }
1037
1038         return rscreen->fences.data[rfence->index] != 0;
1039 }
1040
1041 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1042 {
1043         switch ((tiling_config & 0xe) >> 1) {
1044         case 0:
1045                 rscreen->tiling_info.num_channels = 1;
1046                 break;
1047         case 1:
1048                 rscreen->tiling_info.num_channels = 2;
1049                 break;
1050         case 2:
1051                 rscreen->tiling_info.num_channels = 4;
1052                 break;
1053         case 3:
1054                 rscreen->tiling_info.num_channels = 8;
1055                 break;
1056         default:
1057                 return -EINVAL;
1058         }
1059
1060         switch ((tiling_config & 0x30) >> 4) {
1061         case 0:
1062                 rscreen->tiling_info.num_banks = 4;
1063                 break;
1064         case 1:
1065                 rscreen->tiling_info.num_banks = 8;
1066                 break;
1067         default:
1068                 return -EINVAL;
1069
1070         }
1071         switch ((tiling_config & 0xc0) >> 6) {
1072         case 0:
1073                 rscreen->tiling_info.group_bytes = 256;
1074                 break;
1075         case 1:
1076                 rscreen->tiling_info.group_bytes = 512;
1077                 break;
1078         default:
1079                 return -EINVAL;
1080         }
1081         return 0;
1082 }
1083
1084 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1085 {
1086         switch (tiling_config & 0xf) {
1087         case 0:
1088                 rscreen->tiling_info.num_channels = 1;
1089                 break;
1090         case 1:
1091                 rscreen->tiling_info.num_channels = 2;
1092                 break;
1093         case 2:
1094                 rscreen->tiling_info.num_channels = 4;
1095                 break;
1096         case 3:
1097                 rscreen->tiling_info.num_channels = 8;
1098                 break;
1099         default:
1100                 return -EINVAL;
1101         }
1102
1103         switch ((tiling_config & 0xf0) >> 4) {
1104         case 0:
1105                 rscreen->tiling_info.num_banks = 4;
1106                 break;
1107         case 1:
1108                 rscreen->tiling_info.num_banks = 8;
1109                 break;
1110         case 2:
1111                 rscreen->tiling_info.num_banks = 16;
1112                 break;
1113         default:
1114                 return -EINVAL;
1115         }
1116
1117         switch ((tiling_config & 0xf00) >> 8) {
1118         case 0:
1119                 rscreen->tiling_info.group_bytes = 256;
1120                 break;
1121         case 1:
1122                 rscreen->tiling_info.group_bytes = 512;
1123                 break;
1124         default:
1125                 return -EINVAL;
1126         }
1127         return 0;
1128 }
1129
1130 static int r600_init_tiling(struct r600_screen *rscreen)
1131 {
1132         uint32_t tiling_config = rscreen->info.r600_tiling_config;
1133
1134         /* set default group bytes, overridden by tiling info ioctl */
1135         if (rscreen->chip_class <= R700) {
1136                 rscreen->tiling_info.group_bytes = 256;
1137         } else {
1138                 rscreen->tiling_info.group_bytes = 512;
1139         }
1140
1141         if (!tiling_config)
1142                 return 0;
1143
1144         if (rscreen->chip_class <= R700) {
1145                 return r600_interpret_tiling(rscreen, tiling_config);
1146         } else {
1147                 return evergreen_interpret_tiling(rscreen, tiling_config);
1148         }
1149 }
1150
1151 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1152 {
1153         struct r600_screen *rscreen = (struct r600_screen*)screen;
1154
1155         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1156                         rscreen->info.r600_clock_crystal_freq;
1157 }
1158
1159 static int r600_get_driver_query_info(struct pipe_screen *screen,
1160                                       unsigned index,
1161                                       struct pipe_driver_query_info *info)
1162 {
1163         struct r600_screen *rscreen = (struct r600_screen*)screen;
1164         struct pipe_driver_query_info list[] = {
1165                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
1166                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
1167                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
1168                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
1169         };
1170
1171         if (!info)
1172                 return Elements(list);
1173
1174         if (index >= Elements(list))
1175                 return 0;
1176
1177         *info = list[index];
1178         return 1;
1179 }
1180
1181 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1182 {
1183         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1184
1185         if (rscreen == NULL) {
1186                 return NULL;
1187         }
1188
1189         rscreen->ws = ws;
1190         ws->query_info(ws, &rscreen->info);
1191
1192         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1193         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
1194                 rscreen->debug_flags |= DBG_COMPUTE;
1195         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
1196                 rscreen->debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1197         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
1198                 rscreen->debug_flags |= DBG_NO_HYPERZ;
1199         if (!debug_get_bool_option("R600_LLVM", TRUE))
1200                 rscreen->debug_flags |= DBG_NO_LLVM;
1201         if (debug_get_bool_option("R600_PRINT_TEXDEPTH", FALSE))
1202                 rscreen->debug_flags |= DBG_TEX_DEPTH;
1203         rscreen->family = rscreen->info.family;
1204         rscreen->chip_class = rscreen->info.chip_class;
1205
1206         if (rscreen->family == CHIP_UNKNOWN) {
1207                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1208                 FREE(rscreen);
1209                 return NULL;
1210         }
1211
1212         /* Figure out streamout kernel support. */
1213         switch (rscreen->chip_class) {
1214         case R600:
1215                 if (rscreen->family < CHIP_RS780) {
1216                         rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1217                 } else {
1218                         rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1219                 }
1220                 break;
1221         case R700:
1222                 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1223                 break;
1224         case EVERGREEN:
1225         case CAYMAN:
1226                 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1227                 break;
1228         default:
1229                 rscreen->has_streamout = FALSE;
1230                 break;
1231         }
1232
1233         /* MSAA support. */
1234         switch (rscreen->chip_class) {
1235         case R600:
1236         case R700:
1237                 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1238                 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
1239                 break;
1240         case EVERGREEN:
1241                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1242                 rscreen->msaa_texture_support =
1243                         rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
1244                                                         MSAA_TEXTURE_DECOMPRESSED;
1245                 break;
1246         case CAYMAN:
1247                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1248                 /* We should be able to read compressed MSAA textures, but it doesn't work. */
1249                 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
1250                 break;
1251         default:
1252                 rscreen->has_msaa = FALSE;
1253                 rscreen->msaa_texture_support = 0;
1254                 break;
1255         }
1256
1257         rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1258                               !(rscreen->debug_flags & DBG_NO_CP_DMA);
1259
1260         if (r600_init_tiling(rscreen)) {
1261                 FREE(rscreen);
1262                 return NULL;
1263         }
1264
1265         rscreen->screen.destroy = r600_destroy_screen;
1266         rscreen->screen.get_name = r600_get_name;
1267         rscreen->screen.get_vendor = r600_get_vendor;
1268         rscreen->screen.get_param = r600_get_param;
1269         rscreen->screen.get_shader_param = r600_get_shader_param;
1270         rscreen->screen.get_paramf = r600_get_paramf;
1271         rscreen->screen.get_compute_param = r600_get_compute_param;
1272         rscreen->screen.get_timestamp = r600_get_timestamp;
1273
1274         if (rscreen->chip_class >= EVERGREEN) {
1275                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1276                 rscreen->dma_blit = &evergreen_dma_blit;
1277         } else {
1278                 rscreen->screen.is_format_supported = r600_is_format_supported;
1279                 rscreen->dma_blit = &r600_dma_blit;
1280         }
1281         rscreen->screen.context_create = r600_create_context;
1282         rscreen->screen.fence_reference = r600_fence_reference;
1283         rscreen->screen.fence_signalled = r600_fence_signalled;
1284         rscreen->screen.fence_finish = r600_fence_finish;
1285         rscreen->screen.get_driver_query_info = r600_get_driver_query_info;
1286
1287         if (rscreen->info.has_uvd) {
1288                 rscreen->screen.get_video_param = ruvd_get_video_param;
1289                 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
1290         } else {
1291                 rscreen->screen.get_video_param = r600_get_video_param;
1292                 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1293         }
1294
1295         r600_init_screen_resource_functions(&rscreen->screen);
1296
1297         util_format_s3tc_init();
1298
1299         rscreen->fences.bo = NULL;
1300         rscreen->fences.data = NULL;
1301         rscreen->fences.next_index = 0;
1302         LIST_INITHEAD(&rscreen->fences.pool);
1303         LIST_INITHEAD(&rscreen->fences.blocks);
1304         pipe_mutex_init(rscreen->fences.mutex);
1305
1306         rscreen->global_pool = compute_memory_pool_new(rscreen);
1307
1308 #if R600_TRACE_CS
1309         rscreen->cs_count = 0;
1310         if (rscreen->info.drm_minor >= 28) {
1311                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1312                                                                                 PIPE_BIND_CUSTOM,
1313                                                                                 PIPE_USAGE_STAGING,
1314                                                                                 4096);
1315                 if (rscreen->trace_bo) {
1316                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1317                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
1318                 }
1319         }
1320 #endif
1321
1322         return &rscreen->screen;
1323 }