2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
26 #include "evergreen_compute.h"
29 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "vl/vl_decoder.h"
39 #include "vl/vl_video_buffer.h"
40 #include "radeon/radeon_video.h"
41 #include "radeon/radeon_uvd.h"
42 #include "os/os_time.h"
44 static const struct debug_named_value r600_debug_options[] = {
46 #if defined(R600_USE_LLVM)
47 { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
49 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
52 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
53 { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
54 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
55 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
56 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
57 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
58 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
59 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
61 DEBUG_NAMED_VALUE_END /* must be last */
68 static void r600_destroy_context(struct pipe_context *context)
70 struct r600_context *rctx = (struct r600_context *)context;
72 r600_isa_destroy(rctx->isa);
74 r600_sb_context_destroy(rctx->sb_context);
76 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
77 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
79 if (rctx->dummy_pixel_shader) {
80 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
82 if (rctx->custom_dsa_flush) {
83 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
85 if (rctx->custom_blend_resolve) {
86 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
88 if (rctx->custom_blend_decompress) {
89 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
91 if (rctx->custom_blend_fastclear) {
92 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
94 util_unreference_framebuffer_state(&rctx->framebuffer.state);
97 util_blitter_destroy(rctx->blitter);
99 if (rctx->allocator_fetch_shader) {
100 u_suballocator_destroy(rctx->allocator_fetch_shader);
103 r600_release_command_buffer(&rctx->start_cs_cmd);
105 FREE(rctx->start_compute_cs_cmd.buf);
107 r600_common_context_cleanup(&rctx->b);
111 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
113 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
114 struct r600_screen* rscreen = (struct r600_screen *)screen;
115 struct radeon_winsys *ws = rscreen->b.ws;
120 rctx->b.b.screen = screen;
121 rctx->b.b.priv = priv;
122 rctx->b.b.destroy = r600_destroy_context;
124 if (!r600_common_context_init(&rctx->b, &rscreen->b))
127 rctx->screen = rscreen;
128 rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
130 r600_init_blit_functions(rctx);
132 if (rscreen->b.info.has_uvd) {
133 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
134 rctx->b.b.create_video_buffer = r600_video_buffer_create;
136 rctx->b.b.create_video_codec = vl_create_decoder;
137 rctx->b.b.create_video_buffer = vl_video_buffer_create;
140 r600_init_common_state_functions(rctx);
142 switch (rctx->b.chip_class) {
145 r600_init_state_functions(rctx);
146 r600_init_atom_start_cs(rctx);
147 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
148 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
149 : r600_create_resolve_blend(rctx);
150 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
151 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
152 rctx->b.family == CHIP_RV620 ||
153 rctx->b.family == CHIP_RS780 ||
154 rctx->b.family == CHIP_RS880 ||
155 rctx->b.family == CHIP_RV710);
159 evergreen_init_state_functions(rctx);
160 evergreen_init_atom_start_cs(rctx);
161 evergreen_init_atom_start_compute_cs(rctx);
162 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
163 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
164 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
165 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
166 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
167 rctx->b.family == CHIP_PALM ||
168 rctx->b.family == CHIP_SUMO ||
169 rctx->b.family == CHIP_SUMO2 ||
170 rctx->b.family == CHIP_CAICOS ||
171 rctx->b.family == CHIP_CAYMAN ||
172 rctx->b.family == CHIP_ARUBA);
175 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
179 rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
180 r600_context_gfx_flush, rctx,
181 rscreen->b.trace_bo ?
182 rscreen->b.trace_bo->cs_buf : NULL);
183 rctx->b.rings.gfx.flush = r600_context_gfx_flush;
185 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
186 0, PIPE_USAGE_DEFAULT, FALSE);
187 if (!rctx->allocator_fetch_shader)
190 rctx->isa = calloc(1, sizeof(struct r600_isa));
191 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
194 rctx->blitter = util_blitter_create(&rctx->b.b);
195 if (rctx->blitter == NULL)
197 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
198 rctx->blitter->draw_rectangle = r600_draw_rectangle;
200 r600_begin_new_cs(rctx);
201 r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
203 rctx->dummy_pixel_shader =
204 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
205 TGSI_SEMANTIC_GENERIC,
206 TGSI_INTERPOLATE_CONSTANT);
207 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
212 r600_destroy_context(&rctx->b.b);
220 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
222 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
223 enum radeon_family family = rscreen->b.family;
226 /* Supported features (boolean caps). */
227 case PIPE_CAP_NPOT_TEXTURES:
228 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
229 case PIPE_CAP_TWO_SIDED_STENCIL:
230 case PIPE_CAP_ANISOTROPIC_FILTER:
231 case PIPE_CAP_POINT_SPRITE:
232 case PIPE_CAP_OCCLUSION_QUERY:
233 case PIPE_CAP_TEXTURE_SHADOW_MAP:
234 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
235 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
236 case PIPE_CAP_TEXTURE_SWIZZLE:
237 case PIPE_CAP_DEPTH_CLIP_DISABLE:
238 case PIPE_CAP_SHADER_STENCIL_EXPORT:
239 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
240 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
241 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
242 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
244 case PIPE_CAP_SEAMLESS_CUBE_MAP:
245 case PIPE_CAP_PRIMITIVE_RESTART:
246 case PIPE_CAP_CONDITIONAL_RENDER:
247 case PIPE_CAP_TEXTURE_BARRIER:
248 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
249 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
250 case PIPE_CAP_TGSI_INSTANCEID:
251 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
252 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
253 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
254 case PIPE_CAP_USER_INDEX_BUFFERS:
255 case PIPE_CAP_USER_CONSTANT_BUFFERS:
256 case PIPE_CAP_START_INSTANCE:
257 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
258 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
259 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
260 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
261 case PIPE_CAP_TEXTURE_MULTISAMPLE:
262 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
263 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
266 case PIPE_CAP_COMPUTE:
267 return rscreen->b.chip_class > R700;
269 case PIPE_CAP_TGSI_TEXCOORD:
272 case PIPE_CAP_FAKE_SW_MSAA:
275 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
276 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
278 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
279 return R600_MAP_BUFFER_ALIGNMENT;
281 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
284 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
287 case PIPE_CAP_GLSL_FEATURE_LEVEL:
288 if (family >= CHIP_CEDAR)
290 /* pre-evergreen geom shaders need newer kernel */
291 if (rscreen->b.info.drm_minor >= 37)
295 /* Supported except the original R600. */
296 case PIPE_CAP_INDEP_BLEND_ENABLE:
297 case PIPE_CAP_INDEP_BLEND_FUNC:
298 /* R600 doesn't support per-MRT blends */
299 return family == CHIP_R600 ? 0 : 1;
301 /* Supported on Evergreen. */
302 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
303 case PIPE_CAP_CUBE_MAP_ARRAY:
304 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
305 case PIPE_CAP_TEXTURE_GATHER_SM5:
306 case PIPE_CAP_TEXTURE_QUERY_LOD:
307 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
308 return family >= CHIP_CEDAR ? 1 : 0;
309 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
310 return family >= CHIP_CEDAR ? 4 : 0;
312 /* Unsupported features. */
313 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
314 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
315 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
316 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
317 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
318 case PIPE_CAP_USER_VERTEX_BUFFERS:
319 case PIPE_CAP_SAMPLE_SHADING:
320 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
321 case PIPE_CAP_DRAW_INDIRECT:
322 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
326 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
327 return rscreen->b.has_streamout ? 4 : 0;
328 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
329 return rscreen->b.has_streamout ? 1 : 0;
330 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
331 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
334 /* Geometry shader output. */
335 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
337 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
339 case PIPE_CAP_MAX_VERTEX_STREAMS:
342 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
346 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
347 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
348 if (family >= CHIP_CEDAR)
352 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
353 /* textures support 8192, but layered rendering supports 2048 */
355 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
356 /* textures support 8192, but layered rendering supports 2048 */
357 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
359 /* Render targets. */
360 case PIPE_CAP_MAX_RENDER_TARGETS:
361 /* XXX some r6xx are buggy and can only do 4 */
364 case PIPE_CAP_MAX_VIEWPORTS:
367 /* Timer queries, present when the clock frequency is non zero. */
368 case PIPE_CAP_QUERY_TIME_ELAPSED:
369 return rscreen->b.info.r600_clock_crystal_freq != 0;
370 case PIPE_CAP_QUERY_TIMESTAMP:
371 return rscreen->b.info.drm_minor >= 20 &&
372 rscreen->b.info.r600_clock_crystal_freq != 0;
374 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
375 case PIPE_CAP_MIN_TEXEL_OFFSET:
378 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
379 case PIPE_CAP_MAX_TEXEL_OFFSET:
382 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
383 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
384 case PIPE_CAP_ENDIANNESS:
385 return PIPE_ENDIAN_LITTLE;
387 case PIPE_CAP_VENDOR_ID:
389 case PIPE_CAP_DEVICE_ID:
390 return rscreen->b.info.pci_id;
391 case PIPE_CAP_ACCELERATED:
393 case PIPE_CAP_VIDEO_MEMORY:
394 return rscreen->b.info.vram_size >> 20;
401 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
403 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
407 case PIPE_SHADER_FRAGMENT:
408 case PIPE_SHADER_VERTEX:
409 case PIPE_SHADER_COMPUTE:
411 case PIPE_SHADER_GEOMETRY:
412 if (rscreen->b.family >= CHIP_CEDAR)
414 /* pre-evergreen geom shaders need newer kernel */
415 if (rscreen->b.info.drm_minor >= 37)
419 /* XXX: support tessellation on Evergreen */
424 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
425 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
426 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
427 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
429 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
431 case PIPE_SHADER_CAP_MAX_INPUTS:
432 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
433 case PIPE_SHADER_CAP_MAX_TEMPS:
434 return 256; /* Max native temporaries. */
435 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
436 if (shader == PIPE_SHADER_COMPUTE) {
437 uint64_t max_const_buffer_size;
438 pscreen->get_compute_param(pscreen,
439 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
440 &max_const_buffer_size);
441 return max_const_buffer_size;
444 return R600_MAX_CONST_BUFFER_SIZE;
446 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
447 return R600_MAX_USER_CONST_BUFFERS;
448 case PIPE_SHADER_CAP_MAX_PREDS:
449 return 0; /* nothing uses this */
450 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
452 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
454 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
455 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
456 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
457 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
459 case PIPE_SHADER_CAP_SUBROUTINES:
461 case PIPE_SHADER_CAP_INTEGERS:
463 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
464 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
466 case PIPE_SHADER_CAP_PREFERRED_IR:
467 if (shader == PIPE_SHADER_COMPUTE) {
468 return PIPE_SHADER_IR_LLVM;
470 return PIPE_SHADER_IR_TGSI;
472 case PIPE_SHADER_CAP_DOUBLES:
478 static void r600_destroy_screen(struct pipe_screen* pscreen)
480 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
485 if (!rscreen->b.ws->unref(rscreen->b.ws))
488 if (rscreen->global_pool) {
489 compute_memory_pool_delete(rscreen->global_pool);
492 r600_destroy_common_screen(&rscreen->b);
495 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
496 const struct pipe_resource *templ)
498 if (templ->target == PIPE_BUFFER &&
499 (templ->bind & PIPE_BIND_GLOBAL))
500 return r600_compute_global_buffer_create(screen, templ);
502 return r600_resource_create_common(screen, templ);
505 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
507 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
509 if (rscreen == NULL) {
513 /* Set functions first. */
514 rscreen->b.b.context_create = r600_create_context;
515 rscreen->b.b.destroy = r600_destroy_screen;
516 rscreen->b.b.get_param = r600_get_param;
517 rscreen->b.b.get_shader_param = r600_get_shader_param;
518 rscreen->b.b.resource_create = r600_resource_create;
520 if (!r600_common_screen_init(&rscreen->b, ws)) {
525 if (rscreen->b.info.chip_class >= EVERGREEN) {
526 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
528 rscreen->b.b.is_format_supported = r600_is_format_supported;
531 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
532 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
533 rscreen->b.debug_flags |= DBG_COMPUTE;
534 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
535 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
536 if (debug_get_bool_option("R600_HYPERZ", FALSE))
537 rscreen->b.debug_flags |= DBG_HYPERZ;
538 if (debug_get_bool_option("R600_LLVM", FALSE))
539 rscreen->b.debug_flags |= DBG_LLVM;
541 if (rscreen->b.family == CHIP_UNKNOWN) {
542 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
547 /* Figure out streamout kernel support. */
548 switch (rscreen->b.chip_class) {
550 if (rscreen->b.family < CHIP_RS780) {
551 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
553 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
557 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
561 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
564 rscreen->b.has_streamout = FALSE;
569 switch (rscreen->b.chip_class) {
572 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
573 rscreen->has_compressed_msaa_texturing = false;
576 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
577 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
580 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
581 rscreen->has_compressed_msaa_texturing = true;
584 rscreen->has_msaa = FALSE;
585 rscreen->has_compressed_msaa_texturing = false;
588 rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
589 !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
591 rscreen->global_pool = compute_memory_pool_new(rscreen);
593 /* Create the auxiliary context. This must be done last. */
594 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
596 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
597 struct pipe_resource templ = {};
600 templ.height0 = 2048;
602 templ.array_size = 1;
603 templ.target = PIPE_TEXTURE_2D;
604 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
605 templ.usage = PIPE_USAGE_DEFAULT;
607 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
608 unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
612 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
613 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
614 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
615 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
616 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
618 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
621 for (i = 0; i < 256; i++) {
622 printf("%02X", map[i]);
628 return &rscreen->b.b;