src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include <errno.h>
  30 #include "pipe/p_shader_tokens.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_debug.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_uvd.h"
  41 #include "os/os_time.h"
  42
  43 static const struct debug_named_value debug_options[] = {
  44         /* logging */
  45         { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
  46         { "compute", DBG_COMPUTE, "Print compute info" },
  47         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
  48         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
  49
  50         /* shaders */
  51         { "fs", DBG_FS, "Print fetch shaders" },
  52         { "vs", DBG_VS, "Print vertex shaders" },
  53         { "gs", DBG_GS, "Print geometry shaders" },
  54         { "ps", DBG_PS, "Print pixel shaders" },
  55         { "cs", DBG_CS, "Print compute shaders" },
  56
  57         /* features */
  58         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
  59 #if defined(R600_USE_LLVM)
  60         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  61 #endif
  62         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  63         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  64         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
  65         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
  66
  67         DEBUG_NAMED_VALUE_END /* must be last */
  68 };
  69
  70 /*
  71  * pipe_context
  72  */
  73 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  74 {
  75         struct r600_screen *rscreen = rctx->screen;
  76         struct r600_fence *fence = NULL;
  77
  78         pipe_mutex_lock(rscreen->fences.mutex);
  79
  80         if (!rscreen->fences.bo) {
  81                 /* Create the shared buffer object */
  82                 rscreen->fences.bo = (struct r600_resource*)
  83                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  84                                            PIPE_USAGE_STAGING, 4096);
  85                 if (!rscreen->fences.bo) {
  86                         R600_ERR("r600: failed to create bo for fence objects\n");
  87                         goto out;
  88                 }
  89                 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
  90         }
  91
  92         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  93                 struct r600_fence *entry;
  94
  95                 /* Try to find a freed fence that has been signalled */
  96                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  97                         if (rscreen->fences.data[entry->index] != 0) {
  98                                 LIST_DELINIT(&entry->head);
  99                                 fence = entry;
 100                                 break;
 101                         }
 102                 }
 103         }
 104
 105         if (!fence) {
 106                 /* Allocate a new fence */
 107                 struct r600_fence_block *block;
 108                 unsigned index;
 109
 110                 if ((rscreen->fences.next_index + 1) >= 1024) {
 111                         R600_ERR("r600: too many concurrent fences\n");
 112                         goto out;
 113                 }
 114
 115                 index = rscreen->fences.next_index++;
 116
 117                 if (!(index % FENCE_BLOCK_SIZE)) {
 118                         /* Allocate a new block */
 119                         block = CALLOC_STRUCT(r600_fence_block);
 120                         if (block == NULL)
 121                                 goto out;
 122
 123                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 124                 } else {
 125                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 126                 }
 127
 128                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 129                 fence->index = index;
 130         }
 131
 132         pipe_reference_init(&fence->reference, 1);
 133
 134         rscreen->fences.data[fence->index] = 0;
 135         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 136
 137         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 138         fence->sleep_bo = (struct r600_resource*)
 139                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 140                                            PIPE_USAGE_STAGING, 1);
 141         /* Add the fence as a dummy relocation. */
 142         r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 143
 144 out:
 145         pipe_mutex_unlock(rscreen->fences.mutex);
 146         return fence;
 147 }
 148
 149 static void r600_flush(struct pipe_context *ctx, unsigned flags)
 150 {
 151         struct r600_context *rctx = (struct r600_context *)ctx;
 152         struct pipe_query *render_cond = NULL;
 153         unsigned render_cond_mode = 0;
 154
 155         rctx->rings.gfx.flushing = true;
 156         /* Disable render condition. */
 157         if (rctx->current_render_cond) {
 158                 render_cond = rctx->current_render_cond;
 159                 render_cond_mode = rctx->current_render_cond_mode;
 160                 ctx->render_condition(ctx, NULL, 0);
 161         }
 162
 163         r600_context_flush(rctx, flags);
 164         rctx->rings.gfx.flushing = false;
 165         r600_begin_new_cs(rctx);
 166
 167         /* Re-enable render condition. */
 168         if (render_cond) {
 169                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 170         }
 171 }
 172
 173 static void r600_flush_from_st(struct pipe_context *ctx,
 174                                struct pipe_fence_handle **fence,
 175                                enum pipe_flush_flags flags)
 176 {
 177         struct r600_context *rctx = (struct r600_context *)ctx;
 178         struct r600_fence **rfence = (struct r600_fence**)fence;
 179         unsigned fflags;
 180
 181         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 182         if (rfence) {
 183                 *rfence = r600_create_fence(rctx);
 184         }
 185         /* flush gfx & dma ring, order does not matter as only one can be live */
 186         if (rctx->rings.dma.cs) {
 187                 rctx->rings.dma.flush(rctx, fflags);
 188         }
 189         rctx->rings.gfx.flush(rctx, fflags);
 190 }
 191
 192 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 193 {
 194         r600_flush((struct pipe_context*)ctx, flags);
 195 }
 196
 197 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 198 {
 199         struct r600_context *rctx = (struct r600_context *)ctx;
 200         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 201         unsigned padding_dw, i;
 202
 203         if (!cs->cdw) {
 204                 return;
 205         }
 206
 207         /* Pad the DMA CS to a multiple of 8 dwords. */
 208         padding_dw = 8 - cs->cdw % 8;
 209         if (padding_dw < 8) {
 210                 for (i = 0; i < padding_dw; i++) {
 211                         cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
 212                 }
 213         }
 214
 215         rctx->rings.dma.flushing = true;
 216         rctx->ws->cs_flush(cs, flags, 0);
 217         rctx->rings.dma.flushing = false;
 218 }
 219
 220 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
 221                                         struct radeon_winsys_cs_handle *buf,
 222                                         enum radeon_bo_usage usage)
 223 {
 224         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
 225                 return TRUE;
 226         }
 227         if (ctx->rings.dma.cs) {
 228                 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
 229                         return TRUE;
 230                 }
 231         }
 232         return FALSE;
 233 }
 234
 235 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
 236                                         struct r600_resource *resource,
 237                                         unsigned usage)
 238 {
 239         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
 240         unsigned flags = 0;
 241         bool sync_flush = TRUE;
 242
 243         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 244                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 245         }
 246
 247         if (!(usage & PIPE_TRANSFER_WRITE)) {
 248                 /* have to wait for pending read */
 249                 rusage = RADEON_USAGE_WRITE;
 250         }
 251         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 252                 flags |= RADEON_FLUSH_ASYNC;
 253         }
 254
 255         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
 256                 ctx->rings.gfx.flush(ctx, flags);
 257                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
 258                         return NULL;
 259                 }
 260         }
 261         if (ctx->rings.dma.cs) {
 262                 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
 263                         ctx->rings.dma.flush(ctx, flags);
 264                         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 265                                 return NULL;
 266                         }
 267                 }
 268         }
 269
 270         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 271                 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
 272                         return NULL;
 273                 }
 274         }
 275         if (sync_flush) {
 276                 /* Try to avoid busy-waiting in radeon_bo_wait. */
 277                 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
 278                 if (ctx->rings.dma.cs) {
 279                         ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
 280                 }
 281         }
 282         ctx->ws->buffer_wait(resource->buf, rusage);
 283
 284         /* at this point everything is synchronized */
 285         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage | PIPE_TRANSFER_UNSYNCHRONIZED);
 286 }
 287
 288 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 289 {
 290         struct r600_context *rctx = (struct r600_context *)ctx;
 291
 292         rctx->rings.gfx.flush(rctx, flags);
 293 }
 294
 295 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 296 {
 297         struct r600_context *rctx = (struct r600_context *)ctx;
 298
 299         rctx->rings.dma.flush(rctx, flags);
 300 }
 301
 302 static void r600_destroy_context(struct pipe_context *context)
 303 {
 304         struct r600_context *rctx = (struct r600_context *)context;
 305
 306         r600_isa_destroy(rctx->isa);
 307
 308         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 309         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 310
 311         if (rctx->dummy_pixel_shader) {
 312                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 313         }
 314         if (rctx->custom_dsa_flush) {
 315                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 316         }
 317         if (rctx->custom_blend_resolve) {
 318                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
 319         }
 320         if (rctx->custom_blend_decompress) {
 321                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
 322         }
 323         if (rctx->custom_blend_fmask_decompress) {
 324                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
 325         }
 326         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 327
 328         if (rctx->blitter) {
 329                 util_blitter_destroy(rctx->blitter);
 330         }
 331         if (rctx->uploader) {
 332                 u_upload_destroy(rctx->uploader);
 333         }
 334         if (rctx->allocator_so_filled_size) {
 335                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 336         }
 337         if (rctx->allocator_fetch_shader) {
 338                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 339         }
 340         util_slab_destroy(&rctx->pool_transfers);
 341
 342         r600_release_command_buffer(&rctx->start_cs_cmd);
 343
 344         if (rctx->rings.gfx.cs) {
 345                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 346         }
 347         if (rctx->rings.dma.cs) {
 348                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 349         }
 350
 351         FREE(rctx);
 352 }
 353
 354 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 355 {
 356         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 357         struct r600_screen* rscreen = (struct r600_screen *)screen;
 358
 359         if (rctx == NULL)
 360                 return NULL;
 361
 362         util_slab_create(&rctx->pool_transfers,
 363                          sizeof(struct r600_transfer), 64,
 364                          UTIL_SLAB_SINGLETHREADED);
 365
 366         rctx->context.screen = screen;
 367         rctx->context.priv = priv;
 368         rctx->context.destroy = r600_destroy_context;
 369         rctx->context.flush = r600_flush_from_st;
 370
 371         /* Easy accessing of screen/winsys. */
 372         rctx->screen = rscreen;
 373         rctx->ws = rscreen->ws;
 374         rctx->family = rscreen->family;
 375         rctx->chip_class = rscreen->chip_class;
 376         rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
 377
 378         LIST_INITHEAD(&rctx->active_nontimer_queries);
 379
 380         r600_init_blit_functions(rctx);
 381         r600_init_query_functions(rctx);
 382         r600_init_context_resource_functions(rctx);
 383         r600_init_surface_functions(rctx);
 384
 385         if (rscreen->info.has_uvd) {
 386                 rctx->context.create_video_decoder = r600_uvd_create_decoder;
 387                 rctx->context.create_video_buffer = r600_video_buffer_create;
 388         } else {
 389                 rctx->context.create_video_decoder = vl_create_decoder;
 390                 rctx->context.create_video_buffer = vl_video_buffer_create;
 391         }
 392
 393         r600_init_common_state_functions(rctx);
 394
 395         switch (rctx->chip_class) {
 396         case R600:
 397         case R700:
 398                 r600_init_state_functions(rctx);
 399                 r600_init_atom_start_cs(rctx);
 400                 rctx->max_db = 4;
 401                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 402                 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
 403                                                                       : r600_create_resolve_blend(rctx);
 404                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 405                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 406                                            rctx->family == CHIP_RV620 ||
 407                                            rctx->family == CHIP_RS780 ||
 408                                            rctx->family == CHIP_RS880 ||
 409                                            rctx->family == CHIP_RV710);
 410                 break;
 411         case EVERGREEN:
 412         case CAYMAN:
 413                 evergreen_init_state_functions(rctx);
 414                 evergreen_init_atom_start_cs(rctx);
 415                 evergreen_init_atom_start_compute_cs(rctx);
 416                 rctx->max_db = 8;
 417                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 418                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 419                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 420                 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
 421                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 422                                            rctx->family == CHIP_PALM ||
 423                                            rctx->family == CHIP_SUMO ||
 424                                            rctx->family == CHIP_SUMO2 ||
 425                                            rctx->family == CHIP_CAICOS ||
 426                                            rctx->family == CHIP_CAYMAN ||
 427                                            rctx->family == CHIP_ARUBA);
 428                 break;
 429         default:
 430                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 431                 goto fail;
 432         }
 433
 434         if (rscreen->trace_bo) {
 435                 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX, rscreen->trace_bo->cs_buf);
 436         } else {
 437                 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
 438         }
 439         rctx->rings.gfx.flush = r600_flush_gfx_ring;
 440         rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
 441         rctx->rings.gfx.flushing = false;
 442
 443         rctx->rings.dma.cs = NULL;
 444         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 445                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA, NULL);
 446                 rctx->rings.dma.flush = r600_flush_dma_ring;
 447                 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 448                 rctx->rings.dma.flushing = false;
 449         }
 450
 451         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 452                                         PIPE_BIND_INDEX_BUFFER |
 453                                         PIPE_BIND_CONSTANT_BUFFER);
 454         if (!rctx->uploader)
 455                 goto fail;
 456
 457         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
 458                                                              0, PIPE_USAGE_STATIC, FALSE);
 459         if (!rctx->allocator_fetch_shader)
 460                 goto fail;
 461
 462         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
 463                                                                 0, PIPE_USAGE_STATIC, TRUE);
 464         if (!rctx->allocator_so_filled_size)
 465                 goto fail;
 466
 467         rctx->isa = calloc(1, sizeof(struct r600_isa));
 468         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 469                 goto fail;
 470
 471         rctx->blitter = util_blitter_create(&rctx->context);
 472         if (rctx->blitter == NULL)
 473                 goto fail;
 474         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 475         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 476
 477         r600_begin_new_cs(rctx);
 478         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 479
 480         rctx->dummy_pixel_shader =
 481                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 482                                                      TGSI_SEMANTIC_GENERIC,
 483                                                      TGSI_INTERPOLATE_CONSTANT);
 484         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 485
 486         return &rctx->context;
 487
 488 fail:
 489         r600_destroy_context(&rctx->context);
 490         return NULL;
 491 }
 492
 493 /*
 494  * pipe_screen
 495  */
 496 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 497 {
 498         return "X.Org";
 499 }
 500
 501 static const char *r600_get_family_name(enum radeon_family family)
 502 {
 503         switch(family) {
 504         case CHIP_R600: return "AMD R600";
 505         case CHIP_RV610: return "AMD RV610";
 506         case CHIP_RV630: return "AMD RV630";
 507         case CHIP_RV670: return "AMD RV670";
 508         case CHIP_RV620: return "AMD RV620";
 509         case CHIP_RV635: return "AMD RV635";
 510         case CHIP_RS780: return "AMD RS780";
 511         case CHIP_RS880: return "AMD RS880";
 512         case CHIP_RV770: return "AMD RV770";
 513         case CHIP_RV730: return "AMD RV730";
 514         case CHIP_RV710: return "AMD RV710";
 515         case CHIP_RV740: return "AMD RV740";
 516         case CHIP_CEDAR: return "AMD CEDAR";
 517         case CHIP_REDWOOD: return "AMD REDWOOD";
 518         case CHIP_JUNIPER: return "AMD JUNIPER";
 519         case CHIP_CYPRESS: return "AMD CYPRESS";
 520         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 521         case CHIP_PALM: return "AMD PALM";
 522         case CHIP_SUMO: return "AMD SUMO";
 523         case CHIP_SUMO2: return "AMD SUMO2";
 524         case CHIP_BARTS: return "AMD BARTS";
 525         case CHIP_TURKS: return "AMD TURKS";
 526         case CHIP_CAICOS: return "AMD CAICOS";
 527         case CHIP_CAYMAN: return "AMD CAYMAN";
 528         case CHIP_ARUBA: return "AMD ARUBA";
 529         default: return "AMD unknown";
 530         }
 531 }
 532
 533 static const char* r600_get_name(struct pipe_screen* pscreen)
 534 {
 535         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 536
 537         return r600_get_family_name(rscreen->family);
 538 }
 539
 540 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 541 {
 542         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 543         enum radeon_family family = rscreen->family;
 544
 545         switch (param) {
 546         /* Supported features (boolean caps). */
 547         case PIPE_CAP_NPOT_TEXTURES:
 548         case PIPE_CAP_TWO_SIDED_STENCIL:
 549         case PIPE_CAP_ANISOTROPIC_FILTER:
 550         case PIPE_CAP_POINT_SPRITE:
 551         case PIPE_CAP_OCCLUSION_QUERY:
 552         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 553         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 554         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 555         case PIPE_CAP_TEXTURE_SWIZZLE:
 556         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 557         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 558         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 559         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 560         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 561         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 562         case PIPE_CAP_SM3:
 563         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 564         case PIPE_CAP_PRIMITIVE_RESTART:
 565         case PIPE_CAP_CONDITIONAL_RENDER:
 566         case PIPE_CAP_TEXTURE_BARRIER:
 567         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 568         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 569         case PIPE_CAP_TGSI_INSTANCEID:
 570         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 571         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 572         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 573         case PIPE_CAP_USER_INDEX_BUFFERS:
 574         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 575         case PIPE_CAP_COMPUTE:
 576         case PIPE_CAP_START_INSTANCE:
 577         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 578         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 579         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 580         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 581                 return 1;
 582         case PIPE_CAP_TGSI_TEXCOORD:
 583                 return 0;
 584
 585         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 586                 return R600_MAP_BUFFER_ALIGNMENT;
 587
 588         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 589                 return 256;
 590
 591         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 592                 return 1;
 593
 594         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 595                 return 140;
 596
 597         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 598                 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
 599
 600         /* Supported except the original R600. */
 601         case PIPE_CAP_INDEP_BLEND_ENABLE:
 602         case PIPE_CAP_INDEP_BLEND_FUNC:
 603                 /* R600 doesn't support per-MRT blends */
 604                 return family == CHIP_R600 ? 0 : 1;
 605
 606         /* Supported on Evergreen. */
 607         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 608         case PIPE_CAP_CUBE_MAP_ARRAY:
 609                 return family >= CHIP_CEDAR ? 1 : 0;
 610
 611         /* Unsupported features. */
 612         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 613         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 614         case PIPE_CAP_SCALED_RESOLVE:
 615         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 616         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 617         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 618         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 619         case PIPE_CAP_USER_VERTEX_BUFFERS:
 620                 return 0;
 621
 622         /* Stream output. */
 623         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 624                 return rscreen->has_streamout ? 4 : 0;
 625         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 626                 return rscreen->has_streamout ? 1 : 0;
 627         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 628         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 629                 return 32*4;
 630
 631         /* Texturing. */
 632         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 633         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 634         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 635                 if (family >= CHIP_CEDAR)
 636                         return 15;
 637                 else
 638                         return 14;
 639         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 640                 return rscreen->info.drm_minor >= 9 ?
 641                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 642         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 643                 return 32;
 644
 645         /* Render targets. */
 646         case PIPE_CAP_MAX_RENDER_TARGETS:
 647                 /* XXX some r6xx are buggy and can only do 4 */
 648                 return 8;
 649
 650         /* Timer queries, present when the clock frequency is non zero. */
 651         case PIPE_CAP_QUERY_TIME_ELAPSED:
 652                 return rscreen->info.r600_clock_crystal_freq != 0;
 653         case PIPE_CAP_QUERY_TIMESTAMP:
 654                 return rscreen->info.drm_minor >= 20 &&
 655                        rscreen->info.r600_clock_crystal_freq != 0;
 656
 657         case PIPE_CAP_MIN_TEXEL_OFFSET:
 658                 return -8;
 659
 660         case PIPE_CAP_MAX_TEXEL_OFFSET:
 661                 return 7;
 662
 663         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 664                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 665         }
 666         return 0;
 667 }
 668
 669 static float r600_get_paramf(struct pipe_screen* pscreen,
 670                              enum pipe_capf param)
 671 {
 672         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 673         enum radeon_family family = rscreen->family;
 674
 675         switch (param) {
 676         case PIPE_CAPF_MAX_LINE_WIDTH:
 677         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 678         case PIPE_CAPF_MAX_POINT_WIDTH:
 679         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 680                 if (family >= CHIP_CEDAR)
 681                         return 16384.0f;
 682                 else
 683                         return 8192.0f;
 684         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 685                 return 16.0f;
 686         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 687                 return 16.0f;
 688         case PIPE_CAPF_GUARD_BAND_LEFT:
 689         case PIPE_CAPF_GUARD_BAND_TOP:
 690         case PIPE_CAPF_GUARD_BAND_RIGHT:
 691         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 692                 return 0.0f;
 693         }
 694         return 0.0f;
 695 }
 696
 697 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 698 {
 699         switch(shader)
 700         {
 701         case PIPE_SHADER_FRAGMENT:
 702         case PIPE_SHADER_VERTEX:
 703         case PIPE_SHADER_COMPUTE:
 704                 break;
 705         case PIPE_SHADER_GEOMETRY:
 706                 /* XXX: support and enable geometry programs */
 707                 return 0;
 708         default:
 709                 /* XXX: support tessellation on Evergreen */
 710                 return 0;
 711         }
 712
 713         switch (param) {
 714         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 715         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 716         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 717         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 718                 return 16384;
 719         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 720                 return 32;
 721         case PIPE_SHADER_CAP_MAX_INPUTS:
 722                 return 32;
 723         case PIPE_SHADER_CAP_MAX_TEMPS:
 724                 return 256; /* Max native temporaries. */
 725         case PIPE_SHADER_CAP_MAX_ADDRS:
 726                 /* XXX Isn't this equal to TEMPS? */
 727                 return 1; /* Max native address registers */
 728         case PIPE_SHADER_CAP_MAX_CONSTS:
 729                 return R600_MAX_CONST_BUFFER_SIZE;
 730         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 731                 return R600_MAX_USER_CONST_BUFFERS;
 732         case PIPE_SHADER_CAP_MAX_PREDS:
 733                 return 0; /* nothing uses this */
 734         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 735                 return 1;
 736         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 737                 return 0;
 738         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 739         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 740         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 741         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 742                 return 1;
 743         case PIPE_SHADER_CAP_SUBROUTINES:
 744                 return 0;
 745         case PIPE_SHADER_CAP_INTEGERS:
 746                 return 1;
 747         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 748                 return 16;
 749         case PIPE_SHADER_CAP_PREFERRED_IR:
 750                 if (shader == PIPE_SHADER_COMPUTE) {
 751                         return PIPE_SHADER_IR_LLVM;
 752                 } else {
 753                         return PIPE_SHADER_IR_TGSI;
 754                 }
 755         }
 756         return 0;
 757 }
 758
 759 static int r600_get_video_param(struct pipe_screen *screen,
 760                                 enum pipe_video_profile profile,
 761                                 enum pipe_video_cap param)
 762 {
 763         switch (param) {
 764         case PIPE_VIDEO_CAP_SUPPORTED:
 765                 return vl_profile_supported(screen, profile);
 766         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 767                 return 1;
 768         case PIPE_VIDEO_CAP_MAX_WIDTH:
 769         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 770                 return vl_video_buffer_max_size(screen);
 771         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 772                 return PIPE_FORMAT_NV12;
 773         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 774                 return false;
 775         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 776                 return false;
 777         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 778                 return true;
 779         default:
 780                 return 0;
 781         }
 782 }
 783
 784 const char * r600_llvm_gpu_string(enum radeon_family family)
 785 {
 786         const char * gpu_family;
 787
 788         switch (family) {
 789         case CHIP_R600:
 790         case CHIP_RV610:
 791         case CHIP_RV630:
 792         case CHIP_RV620:
 793         case CHIP_RV635:
 794         case CHIP_RV670:
 795         case CHIP_RS780:
 796         case CHIP_RS880:
 797                 gpu_family = "r600";
 798                 break;
 799         case CHIP_RV710:
 800                 gpu_family = "rv710";
 801                 break;
 802         case CHIP_RV730:
 803                 gpu_family = "rv730";
 804                 break;
 805         case CHIP_RV740:
 806         case CHIP_RV770:
 807                 gpu_family = "rv770";
 808                 break;
 809         case CHIP_PALM:
 810         case CHIP_CEDAR:
 811                 gpu_family = "cedar";
 812                 break;
 813         case CHIP_SUMO:
 814         case CHIP_SUMO2:
 815         case CHIP_REDWOOD:
 816                 gpu_family = "redwood";
 817                 break;
 818         case CHIP_JUNIPER:
 819                 gpu_family = "juniper";
 820                 break;
 821         case CHIP_HEMLOCK:
 822         case CHIP_CYPRESS:
 823                 gpu_family = "cypress";
 824                 break;
 825         case CHIP_BARTS:
 826                 gpu_family = "barts";
 827                 break;
 828         case CHIP_TURKS:
 829                 gpu_family = "turks";
 830                 break;
 831         case CHIP_CAICOS:
 832                 gpu_family = "caicos";
 833                 break;
 834         case CHIP_CAYMAN:
 835         case CHIP_ARUBA:
 836                 gpu_family = "cayman";
 837                 break;
 838         default:
 839                 gpu_family = "";
 840                 fprintf(stderr, "Chip not supported by r600 llvm "
 841                         "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
 842                 break;
 843         }
 844         return gpu_family;
 845 }
 846
 847
 848 static int r600_get_compute_param(struct pipe_screen *screen,
 849         enum pipe_compute_cap param,
 850         void *ret)
 851 {
 852         struct r600_screen *rscreen = (struct r600_screen *)screen;
 853         //TODO: select these params by asic
 854         switch (param) {
 855         case PIPE_COMPUTE_CAP_IR_TARGET: {
 856                 const char *gpu = r600_llvm_gpu_string(rscreen->family);
 857                 if (ret) {
 858                         sprintf(ret, "%s-r600--", gpu);
 859                 }
 860                 return (8 + strlen(gpu)) * sizeof(char);
 861         }
 862         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 863                 if (ret) {
 864                         uint64_t * grid_dimension = ret;
 865                         grid_dimension[0] = 3;
 866                 }
 867                 return 1 * sizeof(uint64_t);
 868
 869         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 870                 if (ret) {
 871                         uint64_t * grid_size = ret;
 872                         grid_size[0] = 65535;
 873                         grid_size[1] = 65535;
 874                         grid_size[2] = 1;
 875                 }
 876                 return 3 * sizeof(uint64_t) ;
 877
 878         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 879                 if (ret) {
 880                         uint64_t * block_size = ret;
 881                         block_size[0] = 256;
 882                         block_size[1] = 256;
 883                         block_size[2] = 256;
 884                 }
 885                 return 3 * sizeof(uint64_t);
 886
 887         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 888                 if (ret) {
 889                         uint64_t * max_threads_per_block = ret;
 890                         *max_threads_per_block = 256;
 891                 }
 892                 return sizeof(uint64_t);
 893
 894         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 895                 if (ret) {
 896                         uint64_t * max_global_size = ret;
 897                         /* XXX: This is what the proprietary driver reports, we
 898                          * may want to use a different value. */
 899                         *max_global_size = 201326592;
 900                 }
 901                 return sizeof(uint64_t);
 902
 903         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 904                 if (ret) {
 905                         uint64_t * max_input_size = ret;
 906                         *max_input_size = 1024;
 907                 }
 908                 return sizeof(uint64_t);
 909
 910         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 911                 if (ret) {
 912                         uint64_t * max_local_size = ret;
 913                         /* XXX: This is what the proprietary driver reports, we
 914                          * may want to use a different value. */
 915                         *max_local_size = 32768;
 916                 }
 917                 return sizeof(uint64_t);
 918
 919         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 920                 if (ret) {
 921                         uint64_t max_global_size;
 922                         uint64_t * max_mem_alloc_size = ret;
 923                         r600_get_compute_param(screen,
 924                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 925                                         &max_global_size);
 926                         /* OpenCL requres this value be at least
 927                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 928                          * I'm really not sure what value to report here, but
 929                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 930                          */
 931                         *max_mem_alloc_size = max_global_size / 4;
 932                 }
 933                 return sizeof(uint64_t);
 934
 935         default:
 936                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 937                 return 0;
 938         }
 939 }
 940
 941 static void r600_destroy_screen(struct pipe_screen* pscreen)
 942 {
 943         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 944
 945         if (rscreen == NULL)
 946                 return;
 947
 948         pipe_mutex_destroy(rscreen->aux_context_lock);
 949         rscreen->aux_context->destroy(rscreen->aux_context);
 950
 951         if (rscreen->global_pool) {
 952                 compute_memory_pool_delete(rscreen->global_pool);
 953         }
 954
 955         if (rscreen->fences.bo) {
 956                 struct r600_fence_block *entry, *tmp;
 957
 958                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 959                         LIST_DEL(&entry->head);
 960                         FREE(entry);
 961                 }
 962
 963                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 964                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 965         }
 966         if (rscreen->trace_bo) {
 967                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 968                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 969         }
 970         pipe_mutex_destroy(rscreen->fences.mutex);
 971
 972         rscreen->ws->destroy(rscreen->ws);
 973         FREE(rscreen);
 974 }
 975
 976 static void r600_fence_reference(struct pipe_screen *pscreen,
 977                                  struct pipe_fence_handle **ptr,
 978                                  struct pipe_fence_handle *fence)
 979 {
 980         struct r600_fence **oldf = (struct r600_fence**)ptr;
 981         struct r600_fence *newf = (struct r600_fence*)fence;
 982
 983         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 984                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 985                 pipe_mutex_lock(rscreen->fences.mutex);
 986                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 987                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 988                 pipe_mutex_unlock(rscreen->fences.mutex);
 989         }
 990
 991         *ptr = fence;
 992 }
 993
 994 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 995                                     struct pipe_fence_handle *fence)
 996 {
 997         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 998         struct r600_fence *rfence = (struct r600_fence*)fence;
 999
1000         return rscreen->fences.data[rfence->index] != 0;
1001 }
1002
1003 static boolean r600_fence_finish(struct pipe_screen *pscreen,
1004                                  struct pipe_fence_handle *fence,
1005                                  uint64_t timeout)
1006 {
1007         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1008         struct r600_fence *rfence = (struct r600_fence*)fence;
1009         int64_t start_time = 0;
1010         unsigned spins = 0;
1011
1012         if (timeout != PIPE_TIMEOUT_INFINITE) {
1013                 start_time = os_time_get();
1014
1015                 /* Convert to microseconds. */
1016                 timeout /= 1000;
1017         }
1018
1019         while (rscreen->fences.data[rfence->index] == 0) {
1020                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
1021                 if (timeout == PIPE_TIMEOUT_INFINITE) {
1022                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
1023                         break;
1024                 }
1025
1026                 /* The dummy BO will be busy until the CS including the fence has completed, or
1027                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
1028                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
1029                         break;
1030
1031                 if (++spins % 256)
1032                         continue;
1033 #ifdef PIPE_OS_UNIX
1034                 sched_yield();
1035 #else
1036                 os_time_sleep(10);
1037 #endif
1038                 if (timeout != PIPE_TIMEOUT_INFINITE &&
1039                     os_time_get() - start_time >= timeout) {
1040                         break;
1041                 }
1042         }
1043
1044         return rscreen->fences.data[rfence->index] != 0;
1045 }
1046
1047 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1048 {
1049         switch ((tiling_config & 0xe) >> 1) {
1050         case 0:
1051                 rscreen->tiling_info.num_channels = 1;
1052                 break;
1053         case 1:
1054                 rscreen->tiling_info.num_channels = 2;
1055                 break;
1056         case 2:
1057                 rscreen->tiling_info.num_channels = 4;
1058                 break;
1059         case 3:
1060                 rscreen->tiling_info.num_channels = 8;
1061                 break;
1062         default:
1063                 return -EINVAL;
1064         }
1065
1066         switch ((tiling_config & 0x30) >> 4) {
1067         case 0:
1068                 rscreen->tiling_info.num_banks = 4;
1069                 break;
1070         case 1:
1071                 rscreen->tiling_info.num_banks = 8;
1072                 break;
1073         default:
1074                 return -EINVAL;
1075
1076         }
1077         switch ((tiling_config & 0xc0) >> 6) {
1078         case 0:
1079                 rscreen->tiling_info.group_bytes = 256;
1080                 break;
1081         case 1:
1082                 rscreen->tiling_info.group_bytes = 512;
1083                 break;
1084         default:
1085                 return -EINVAL;
1086         }
1087         return 0;
1088 }
1089
1090 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1091 {
1092         switch (tiling_config & 0xf) {
1093         case 0:
1094                 rscreen->tiling_info.num_channels = 1;
1095                 break;
1096         case 1:
1097                 rscreen->tiling_info.num_channels = 2;
1098                 break;
1099         case 2:
1100                 rscreen->tiling_info.num_channels = 4;
1101                 break;
1102         case 3:
1103                 rscreen->tiling_info.num_channels = 8;
1104                 break;
1105         default:
1106                 return -EINVAL;
1107         }
1108
1109         switch ((tiling_config & 0xf0) >> 4) {
1110         case 0:
1111                 rscreen->tiling_info.num_banks = 4;
1112                 break;
1113         case 1:
1114                 rscreen->tiling_info.num_banks = 8;
1115                 break;
1116         case 2:
1117                 rscreen->tiling_info.num_banks = 16;
1118                 break;
1119         default:
1120                 return -EINVAL;
1121         }
1122
1123         switch ((tiling_config & 0xf00) >> 8) {
1124         case 0:
1125                 rscreen->tiling_info.group_bytes = 256;
1126                 break;
1127         case 1:
1128                 rscreen->tiling_info.group_bytes = 512;
1129                 break;
1130         default:
1131                 return -EINVAL;
1132         }
1133         return 0;
1134 }
1135
1136 static int r600_init_tiling(struct r600_screen *rscreen)
1137 {
1138         uint32_t tiling_config = rscreen->info.r600_tiling_config;
1139
1140         /* set default group bytes, overridden by tiling info ioctl */
1141         if (rscreen->chip_class <= R700) {
1142                 rscreen->tiling_info.group_bytes = 256;
1143         } else {
1144                 rscreen->tiling_info.group_bytes = 512;
1145         }
1146
1147         if (!tiling_config)
1148                 return 0;
1149
1150         if (rscreen->chip_class <= R700) {
1151                 return r600_interpret_tiling(rscreen, tiling_config);
1152         } else {
1153                 return evergreen_interpret_tiling(rscreen, tiling_config);
1154         }
1155 }
1156
1157 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1158 {
1159         struct r600_screen *rscreen = (struct r600_screen*)screen;
1160
1161         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1162                         rscreen->info.r600_clock_crystal_freq;
1163 }
1164
1165 static int r600_get_driver_query_info(struct pipe_screen *screen,
1166                                       unsigned index,
1167                                       struct pipe_driver_query_info *info)
1168 {
1169         struct r600_screen *rscreen = (struct r600_screen*)screen;
1170         struct pipe_driver_query_info list[] = {
1171                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
1172                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
1173                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
1174                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
1175         };
1176
1177         if (!info)
1178                 return Elements(list);
1179
1180         if (index >= Elements(list))
1181                 return 0;
1182
1183         *info = list[index];
1184         return 1;
1185 }
1186
1187 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1188 {
1189         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1190
1191         if (rscreen == NULL) {
1192                 return NULL;
1193         }
1194
1195         rscreen->ws = ws;
1196         ws->query_info(ws, &rscreen->info);
1197
1198         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1199         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
1200                 rscreen->debug_flags |= DBG_COMPUTE;
1201         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
1202                 rscreen->debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1203         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
1204                 rscreen->debug_flags |= DBG_NO_HYPERZ;
1205         if (!debug_get_bool_option("R600_LLVM", TRUE))
1206                 rscreen->debug_flags |= DBG_NO_LLVM;
1207         if (debug_get_bool_option("R600_PRINT_TEXDEPTH", FALSE))
1208                 rscreen->debug_flags |= DBG_TEX_DEPTH;
1209         rscreen->family = rscreen->info.family;
1210         rscreen->chip_class = rscreen->info.chip_class;
1211
1212         if (rscreen->family == CHIP_UNKNOWN) {
1213                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1214                 FREE(rscreen);
1215                 return NULL;
1216         }
1217
1218         /* Figure out streamout kernel support. */
1219         switch (rscreen->chip_class) {
1220         case R600:
1221                 if (rscreen->family < CHIP_RS780) {
1222                         rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1223                 } else {
1224                         rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1225                 }
1226                 break;
1227         case R700:
1228                 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1229                 break;
1230         case EVERGREEN:
1231         case CAYMAN:
1232                 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1233                 break;
1234         default:
1235                 rscreen->has_streamout = FALSE;
1236                 break;
1237         }
1238
1239         /* MSAA support. */
1240         switch (rscreen->chip_class) {
1241         case R600:
1242         case R700:
1243                 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1244                 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
1245                 break;
1246         case EVERGREEN:
1247                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1248                 rscreen->msaa_texture_support =
1249                         rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
1250                                                         MSAA_TEXTURE_DECOMPRESSED;
1251                 break;
1252         case CAYMAN:
1253                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1254                 /* We should be able to read compressed MSAA textures, but it doesn't work. */
1255                 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
1256                 break;
1257         default:
1258                 rscreen->has_msaa = FALSE;
1259                 rscreen->msaa_texture_support = 0;
1260                 break;
1261         }
1262
1263         rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1264                               !(rscreen->debug_flags & DBG_NO_CP_DMA);
1265
1266         if (r600_init_tiling(rscreen)) {
1267                 FREE(rscreen);
1268                 return NULL;
1269         }
1270
1271         rscreen->screen.destroy = r600_destroy_screen;
1272         rscreen->screen.get_name = r600_get_name;
1273         rscreen->screen.get_vendor = r600_get_vendor;
1274         rscreen->screen.get_param = r600_get_param;
1275         rscreen->screen.get_shader_param = r600_get_shader_param;
1276         rscreen->screen.get_paramf = r600_get_paramf;
1277         rscreen->screen.get_compute_param = r600_get_compute_param;
1278         rscreen->screen.get_timestamp = r600_get_timestamp;
1279
1280         if (rscreen->chip_class >= EVERGREEN) {
1281                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1282                 rscreen->dma_blit = &evergreen_dma_blit;
1283         } else {
1284                 rscreen->screen.is_format_supported = r600_is_format_supported;
1285                 rscreen->dma_blit = &r600_dma_blit;
1286         }
1287         rscreen->screen.context_create = r600_create_context;
1288         rscreen->screen.fence_reference = r600_fence_reference;
1289         rscreen->screen.fence_signalled = r600_fence_signalled;
1290         rscreen->screen.fence_finish = r600_fence_finish;
1291         rscreen->screen.get_driver_query_info = r600_get_driver_query_info;
1292
1293         if (rscreen->info.has_uvd) {
1294                 rscreen->screen.get_video_param = ruvd_get_video_param;
1295                 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
1296         } else {
1297                 rscreen->screen.get_video_param = r600_get_video_param;
1298                 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1299         }
1300
1301         r600_init_screen_resource_functions(&rscreen->screen);
1302
1303         util_format_s3tc_init();
1304
1305         rscreen->fences.bo = NULL;
1306         rscreen->fences.data = NULL;
1307         rscreen->fences.next_index = 0;
1308         LIST_INITHEAD(&rscreen->fences.pool);
1309         LIST_INITHEAD(&rscreen->fences.blocks);
1310         pipe_mutex_init(rscreen->fences.mutex);
1311
1312         rscreen->global_pool = compute_memory_pool_new(rscreen);
1313
1314         rscreen->cs_count = 0;
1315         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
1316                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1317                                                                                 PIPE_BIND_CUSTOM,
1318                                                                                 PIPE_USAGE_STAGING,
1319                                                                                 4096);
1320                 if (rscreen->trace_bo) {
1321                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1322                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
1323                 }
1324         }
1325
1326         /* Create the auxiliary context. */
1327         pipe_mutex_init(rscreen->aux_context_lock);
1328         rscreen->aux_context = rscreen->screen.context_create(&rscreen->screen, NULL);
1329
1330 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
1331         struct pipe_resource templ = {};
1332
1333         templ.width0 = 4;
1334         templ.height0 = 2048;
1335         templ.depth0 = 1;
1336         templ.array_size = 1;
1337         templ.target = PIPE_TEXTURE_2D;
1338         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1339         templ.usage = PIPE_USAGE_STATIC;
1340
1341         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
1342         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
1343
1344         memset(map, 0, 256);
1345
1346         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
1347         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
1348         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
1349         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
1350         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
1351
1352         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
1353
1354         int i;
1355         for (i = 0; i < 256; i++) {
1356                 printf("%02X", map[i]);
1357                 if (i % 16 == 15)
1358                         printf("\n");
1359         }
1360 #endif
1361
1362         return &rscreen->screen;
1363 }