src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "../radeon/r600_pipe_common.h"
  30 #include "../radeon/r600_cs.h"
  31
  32 #include "r600_llvm.h"
  33 #include "r600_public.h"
  34 #include "r600_resource.h"
  35
  36 #include "util/u_blitter.h"
  37 #include "util/u_slab.h"
  38 #include "util/u_suballoc.h"
  39 #include "util/u_double_list.h"
  40 #include "util/u_transfer.h"
  41
  42 #define R600_NUM_ATOMS 41
  43
  44 /* the number of CS dwords for flushing and drawing */
  45 #define R600_MAX_FLUSH_CS_DWORDS        16
  46 #define R600_MAX_DRAW_CS_DWORDS         34
  47 #define R600_TRACE_CS_DWORDS            7
  48
  49 #define R600_MAX_USER_CONST_BUFFERS 13
  50 #define R600_MAX_DRIVER_CONST_BUFFERS 3
  51 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
  52
  53 /* start driver buffers after user buffers */
  54 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
  55 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
  56 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
  57
  58 #define R600_MAX_CONST_BUFFER_SIZE 4096
  59
  60 #ifdef PIPE_ARCH_BIG_ENDIAN
  61 #define R600_BIG_ENDIAN 1
  62 #else
  63 #define R600_BIG_ENDIAN 0
  64 #endif
  65
  66 #define R600_MAP_BUFFER_ALIGNMENT 64
  67
  68 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  69 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  70 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  71 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  72
  73 struct r600_context;
  74 struct r600_bytecode;
  75 struct r600_shader_key;
  76
  77 /* This is an atom containing GPU commands that never change.
  78  * This is supposed to be copied directly into the CS. */
  79 struct r600_command_buffer {
  80         uint32_t *buf;
  81         unsigned num_dw;
  82         unsigned max_num_dw;
  83         unsigned pkt_flags;
  84 };
  85
  86 struct r600_db_state {
  87         struct r600_atom                atom;
  88         struct r600_surface             *rsurf;
  89 };
  90
  91 struct r600_db_misc_state {
  92         struct r600_atom                atom;
  93         bool                            occlusion_query_enabled;
  94         bool                            flush_depthstencil_through_cb;
  95         bool                            flush_depthstencil_in_place;
  96         bool                            copy_depth, copy_stencil;
  97         unsigned                        copy_sample;
  98         unsigned                        log_samples;
  99         unsigned                        db_shader_control;
 100         bool                            htile_clear;
 101 };
 102
 103 struct r600_cb_misc_state {
 104         struct r600_atom atom;
 105         unsigned cb_color_control; /* this comes from blend state */
 106         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
 107         unsigned nr_cbufs;
 108         unsigned nr_ps_color_outputs;
 109         bool multiwrite;
 110         bool dual_src_blend;
 111 };
 112
 113 struct r600_clip_misc_state {
 114         struct r600_atom atom;
 115         unsigned pa_cl_clip_cntl;   /* from rasterizer    */
 116         unsigned pa_cl_vs_out_cntl; /* from vertex shader */
 117         unsigned clip_plane_enable; /* from rasterizer    */
 118         unsigned clip_dist_write;   /* from vertex shader */
 119 };
 120
 121 struct r600_alphatest_state {
 122         struct r600_atom atom;
 123         unsigned sx_alpha_test_control; /* this comes from dsa state */
 124         unsigned sx_alpha_ref; /* this comes from dsa state */
 125         bool bypass;
 126         bool cb0_export_16bpc; /* from set_framebuffer_state */
 127 };
 128
 129 struct r600_vgt_state {
 130         struct r600_atom atom;
 131         uint32_t vgt_multi_prim_ib_reset_en;
 132         uint32_t vgt_multi_prim_ib_reset_indx;
 133         uint32_t vgt_indx_offset;
 134 };
 135
 136 struct r600_blend_color {
 137         struct r600_atom atom;
 138         struct pipe_blend_color state;
 139 };
 140
 141 struct r600_clip_state {
 142         struct r600_atom atom;
 143         struct pipe_clip_state state;
 144 };
 145
 146 struct r600_cs_shader_state {
 147         struct r600_atom atom;
 148         unsigned kernel_index;
 149         struct r600_pipe_compute *shader;
 150 };
 151
 152 struct r600_framebuffer {
 153         struct r600_atom atom;
 154         struct pipe_framebuffer_state state;
 155         unsigned compressed_cb_mask;
 156         unsigned nr_samples;
 157         bool export_16bpc;
 158         bool cb0_is_integer;
 159         bool is_msaa_resolve;
 160 };
 161
 162 struct r600_sample_mask {
 163         struct r600_atom atom;
 164         uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
 165 };
 166
 167 struct r600_config_state {
 168         struct r600_atom atom;
 169         unsigned sq_gpr_resource_mgmt_1;
 170 };
 171
 172 struct r600_stencil_ref
 173 {
 174         ubyte ref_value[2];
 175         ubyte valuemask[2];
 176         ubyte writemask[2];
 177 };
 178
 179 struct r600_stencil_ref_state {
 180         struct r600_atom atom;
 181         struct r600_stencil_ref state;
 182         struct pipe_stencil_ref pipe_state;
 183 };
 184
 185 struct r600_viewport_state {
 186         struct r600_atom atom;
 187         struct pipe_viewport_state state;
 188 };
 189
 190 struct r600_pipe_fences {
 191         struct r600_resource            *bo;
 192         unsigned                        *data;
 193         unsigned                        next_index;
 194         /* linked list of preallocated blocks */
 195         struct list_head                blocks;
 196         /* linked list of freed fences */
 197         struct list_head                pool;
 198         pipe_mutex                      mutex;
 199 };
 200
 201 /* This must start from 16. */
 202 /* features */
 203 #define DBG_NO_LLVM             (1 << 17)
 204 #define DBG_NO_CP_DMA           (1 << 18)
 205 #define DBG_NO_ASYNC_DMA        (1 << 19)
 206 #define DBG_NO_DISCARD_RANGE    (1 << 20)
 207 /* shader backend */
 208 #define DBG_NO_SB               (1 << 21)
 209 #define DBG_SB_CS               (1 << 22)
 210 #define DBG_SB_DRY_RUN  (1 << 23)
 211 #define DBG_SB_STAT             (1 << 24)
 212 #define DBG_SB_DUMP             (1 << 25)
 213 #define DBG_SB_NO_FALLBACK      (1 << 26)
 214 #define DBG_SB_DISASM   (1 << 27)
 215 #define DBG_SB_SAFEMATH (1 << 28)
 216
 217 struct r600_screen {
 218         struct r600_common_screen       b;
 219         bool                            has_streamout;
 220         bool                            has_msaa;
 221         bool                            has_cp_dma;
 222         bool                            has_compressed_msaa_texturing;
 223         struct r600_pipe_fences         fences;
 224
 225         /*for compute global memory binding, we allocate stuff here, instead of
 226          * buffers.
 227          * XXX: Not sure if this is the best place for global_pool.  Also,
 228          * it's not thread safe, so it won't work with multiple contexts. */
 229         struct compute_memory_pool *global_pool;
 230         struct r600_resource            *trace_bo;
 231         uint32_t                        *trace_ptr;
 232         unsigned                        cs_count;
 233 };
 234
 235 struct r600_pipe_sampler_view {
 236         struct pipe_sampler_view        base;
 237         struct r600_resource            *tex_resource;
 238         uint32_t                        tex_resource_words[8];
 239         bool                            skip_mip_address_reloc;
 240 };
 241
 242 struct r600_rasterizer_state {
 243         struct r600_command_buffer      buffer;
 244         boolean                         flatshade;
 245         boolean                         two_side;
 246         unsigned                        sprite_coord_enable;
 247         unsigned                        clip_plane_enable;
 248         unsigned                        pa_sc_line_stipple;
 249         unsigned                        pa_cl_clip_cntl;
 250         float                           offset_units;
 251         float                           offset_scale;
 252         bool                            offset_enable;
 253         bool                            scissor_enable;
 254         bool                            multisample_enable;
 255 };
 256
 257 struct r600_poly_offset_state {
 258         struct r600_atom                atom;
 259         enum pipe_format                zs_format;
 260         float                           offset_units;
 261         float                           offset_scale;
 262 };
 263
 264 struct r600_blend_state {
 265         struct r600_command_buffer      buffer;
 266         struct r600_command_buffer      buffer_no_blend;
 267         unsigned                        cb_target_mask;
 268         unsigned                        cb_color_control;
 269         unsigned                        cb_color_control_no_blend;
 270         bool                            dual_src_blend;
 271         bool                            alpha_to_one;
 272 };
 273
 274 struct r600_dsa_state {
 275         struct r600_command_buffer      buffer;
 276         unsigned                        alpha_ref;
 277         ubyte                           valuemask[2];
 278         ubyte                           writemask[2];
 279         unsigned                        zwritemask;
 280         unsigned                        sx_alpha_test_control;
 281 };
 282
 283 struct r600_pipe_shader;
 284
 285 struct r600_pipe_shader_selector {
 286         struct r600_pipe_shader *current;
 287
 288         struct tgsi_token       *tokens;
 289         struct pipe_stream_output_info  so;
 290
 291         unsigned        num_shaders;
 292
 293         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 294         unsigned        type;
 295
 296         unsigned        nr_ps_max_color_exports;
 297 };
 298
 299 struct r600_pipe_sampler_state {
 300         uint32_t                        tex_sampler_words[3];
 301         union pipe_color_union          border_color;
 302         bool                            border_color_use;
 303         bool                            seamless_cube_map;
 304 };
 305
 306 /* needed for blitter save */
 307 #define NUM_TEX_UNITS 16
 308
 309 struct r600_seamless_cube_map {
 310         struct r600_atom                atom;
 311         bool                            enabled;
 312 };
 313
 314 struct r600_samplerview_state {
 315         struct r600_atom                atom;
 316         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 317         uint32_t                        enabled_mask;
 318         uint32_t                        dirty_mask;
 319         uint32_t                        compressed_depthtex_mask; /* which textures are depth */
 320         uint32_t                        compressed_colortex_mask;
 321         boolean                         dirty_txq_constants;
 322         boolean                         dirty_buffer_constants;
 323 };
 324
 325 struct r600_sampler_states {
 326         struct r600_atom                atom;
 327         struct r600_pipe_sampler_state  *states[NUM_TEX_UNITS];
 328         uint32_t                        enabled_mask;
 329         uint32_t                        dirty_mask;
 330         uint32_t                        has_bordercolor_mask; /* which states contain the border color */
 331 };
 332
 333 struct r600_textures_info {
 334         struct r600_samplerview_state   views;
 335         struct r600_sampler_states      states;
 336         bool                            is_array_sampler[NUM_TEX_UNITS];
 337
 338         /* cube array txq workaround */
 339         uint32_t                        *txq_constants;
 340         /* buffer related workarounds */
 341         uint32_t                        *buffer_constants;
 342 };
 343
 344 struct r600_fence {
 345         struct pipe_reference           reference;
 346         unsigned                        index; /* in the shared bo */
 347         struct r600_resource            *sleep_bo;
 348         struct list_head                head;
 349 };
 350
 351 #define FENCE_BLOCK_SIZE 16
 352
 353 struct r600_fence_block {
 354         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 355         struct list_head                head;
 356 };
 357
 358 struct r600_constbuf_state
 359 {
 360         struct r600_atom                atom;
 361         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 362         uint32_t                        enabled_mask;
 363         uint32_t                        dirty_mask;
 364 };
 365
 366 struct r600_vertexbuf_state
 367 {
 368         struct r600_atom                atom;
 369         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
 370         uint32_t                        enabled_mask; /* non-NULL buffers */
 371         uint32_t                        dirty_mask;
 372 };
 373
 374 /* CSO (constant state object, in other words, immutable state). */
 375 struct r600_cso_state
 376 {
 377         struct r600_atom atom;
 378         void *cso; /* e.g. r600_blend_state */
 379         struct r600_command_buffer *cb;
 380 };
 381
 382 struct r600_scissor_state
 383 {
 384         struct r600_atom                atom;
 385         struct pipe_scissor_state       scissor;
 386         bool                            enable; /* r6xx only */
 387 };
 388
 389 struct r600_fetch_shader {
 390         struct r600_resource            *buffer;
 391         unsigned                        offset;
 392 };
 393
 394 struct r600_shader_state {
 395         struct r600_atom                atom;
 396         struct r600_pipe_shader_selector *shader;
 397 };
 398
 399 struct r600_query_buffer {
 400         /* The buffer where query results are stored. */
 401         struct r600_resource                    *buf;
 402         /* Offset of the next free result after current query data */
 403         unsigned                                results_end;
 404         /* If a query buffer is full, a new buffer is created and the old one
 405          * is put in here. When we calculate the result, we sum up the samples
 406          * from all buffers. */
 407         struct r600_query_buffer                *previous;
 408 };
 409
 410 struct r600_query {
 411         /* The query buffer and how many results are in it. */
 412         struct r600_query_buffer                buffer;
 413         /* The type of query */
 414         unsigned                                type;
 415         /* Size of the result in memory for both begin_query and end_query,
 416          * this can be one or two numbers, or it could even be a size of a structure. */
 417         unsigned                                result_size;
 418         /* The number of dwords for begin_query or end_query. */
 419         unsigned                                num_cs_dw;
 420         /* linked list of queries */
 421         struct list_head                        list;
 422         /* for custom non-GPU queries */
 423         uint64_t begin_result;
 424         uint64_t end_result;
 425 };
 426
 427 struct r600_context {
 428         struct r600_common_context      b;
 429         struct r600_screen              *screen;
 430         struct blitter_context          *blitter;
 431         struct u_upload_mgr             *uploader;
 432         struct u_suballocator           *allocator_fetch_shader;
 433         struct util_slab_mempool        pool_transfers;
 434         unsigned                        initial_gfx_cs_size;
 435
 436         /* Hardware info. */
 437         boolean                         has_vertex_cache;
 438         boolean                         keep_tiling_flags;
 439         unsigned                        default_ps_gprs, default_vs_gprs;
 440         unsigned                        r6xx_num_clause_temp_gprs;
 441         unsigned                        backend_mask;
 442         unsigned                        max_db; /* for OQ */
 443
 444         /* Miscellaneous state objects. */
 445         void                            *custom_dsa_flush;
 446         void                            *custom_blend_resolve;
 447         void                            *custom_blend_decompress;
 448         void                            *custom_blend_fastclear;
 449         /* With rasterizer discard, there doesn't have to be a pixel shader.
 450          * In that case, we bind this one: */
 451         void                            *dummy_pixel_shader;
 452         /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
 453          * bug where valid CMASK and FMASK are required to be present to avoid
 454          * a hardlock in certain operations but aren't actually used
 455          * for anything useful. */
 456         struct r600_resource            *dummy_fmask;
 457         struct r600_resource            *dummy_cmask;
 458
 459         /* State binding slots are here. */
 460         struct r600_atom                *atoms[R600_NUM_ATOMS];
 461         /* States for CS initialization. */
 462         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 463         /** Compute specific registers initializations.  The start_cs_cmd atom
 464          *  must be emitted before start_compute_cs_cmd. */
 465         struct r600_command_buffer      start_compute_cs_cmd;
 466         /* Register states. */
 467         struct r600_alphatest_state     alphatest_state;
 468         struct r600_cso_state           blend_state;
 469         struct r600_blend_color         blend_color;
 470         struct r600_cb_misc_state       cb_misc_state;
 471         struct r600_clip_misc_state     clip_misc_state;
 472         struct r600_clip_state          clip_state;
 473         struct r600_db_misc_state       db_misc_state;
 474         struct r600_db_state            db_state;
 475         struct r600_cso_state           dsa_state;
 476         struct r600_framebuffer         framebuffer;
 477         struct r600_poly_offset_state   poly_offset_state;
 478         struct r600_cso_state           rasterizer_state;
 479         struct r600_sample_mask         sample_mask;
 480         struct r600_scissor_state       scissor;
 481         struct r600_seamless_cube_map   seamless_cube_map;
 482         struct r600_config_state        config_state;
 483         struct r600_stencil_ref_state   stencil_ref;
 484         struct r600_vgt_state           vgt_state;
 485         struct r600_viewport_state      viewport;
 486         /* Shaders and shader resources. */
 487         struct r600_cso_state           vertex_fetch_shader;
 488         struct r600_shader_state        vertex_shader;
 489         struct r600_shader_state        pixel_shader;
 490         struct r600_cs_shader_state     cs_shader_state;
 491         struct r600_constbuf_state      constbuf_state[PIPE_SHADER_TYPES];
 492         struct r600_textures_info       samplers[PIPE_SHADER_TYPES];
 493         /** Vertex buffers for fetch shaders */
 494         struct r600_vertexbuf_state     vertex_buffer_state;
 495         /** Vertex buffers for compute shaders */
 496         struct r600_vertexbuf_state     cs_vertex_buffer_state;
 497
 498         /* Additional context states. */
 499         unsigned                        compute_cb_target_mask;
 500         struct r600_pipe_shader_selector *ps_shader;
 501         struct r600_pipe_shader_selector *vs_shader;
 502         struct r600_rasterizer_state    *rasterizer;
 503         bool                            alpha_to_one;
 504         bool                            force_blend_disable;
 505         boolean                         dual_src_blend;
 506         unsigned                        zwritemask;
 507
 508         /* Index buffer. */
 509         struct pipe_index_buffer        index_buffer;
 510
 511         /* Last draw state (-1 = unset). */
 512         int                             last_primitive_type; /* Last primitive type used in draw_vbo. */
 513         int                             last_start_instance;
 514
 515         /* Queries. */
 516         /* The list of active queries. Only one query of each type can be active. */
 517         int                             num_occlusion_queries;
 518         int                             num_pipelinestat_queries;
 519         /* Keep track of non-timer queries, because they should be suspended
 520          * during context flushing.
 521          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 522         struct list_head                active_nontimer_queries;
 523         unsigned                        num_cs_dw_nontimer_queries_suspend;
 524         /* If queries have been suspended. */
 525         bool                            nontimer_queries_suspended;
 526         unsigned                        num_draw_calls;
 527
 528         /* Render condition. */
 529         struct pipe_query               *current_render_cond;
 530         unsigned                        current_render_cond_mode;
 531         boolean                         current_render_cond_cond;
 532         boolean                         predicate_drawing;
 533
 534         void                            *sb_context;
 535         struct r600_isa         *isa;
 536 };
 537
 538 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
 539                                             struct r600_command_buffer *cb)
 540 {
 541         assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
 542         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
 543         cs->cdw += cb->num_dw;
 544 }
 545
 546 void r600_trace_emit(struct r600_context *rctx);
 547
 548 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 549 {
 550         atom->emit(&rctx->b, atom);
 551         atom->dirty = false;
 552         if (rctx->screen->trace_bo) {
 553                 r600_trace_emit(rctx);
 554         }
 555 }
 556
 557 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
 558 {
 559         state->cso = cso;
 560         state->atom.dirty = cso != NULL;
 561 }
 562
 563 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
 564                                               struct r600_command_buffer *cb)
 565 {
 566         state->cb = cb;
 567         state->atom.num_dw = cb->num_dw;
 568         r600_set_cso_state(state, cso);
 569 }
 570
 571 /* compute_memory_pool.c */
 572 struct compute_memory_pool;
 573 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 574 struct compute_memory_pool* compute_memory_pool_new(
 575         struct r600_screen *rscreen);
 576
 577 /* evergreen_compute.c */
 578 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
 579                                    unsigned start_slot, unsigned count,
 580                                    struct pipe_sampler_view **views);
 581
 582 /* evergreen_state.c */
 583 struct pipe_sampler_view *
 584 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 585                                      struct pipe_resource *texture,
 586                                      const struct pipe_sampler_view *state,
 587                                      unsigned width0, unsigned height0);
 588 void evergreen_init_common_regs(struct r600_command_buffer *cb,
 589                                 enum chip_class ctx_chip_class,
 590                                 enum radeon_family ctx_family,
 591                                 int ctx_drm_minor);
 592 void cayman_init_common_regs(struct r600_command_buffer *cb,
 593                              enum chip_class ctx_chip_class,
 594                              enum radeon_family ctx_family,
 595                              int ctx_drm_minor);
 596
 597 void evergreen_init_state_functions(struct r600_context *rctx);
 598 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 599 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 600 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 601 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 602 void *evergreen_create_resolve_blend(struct r600_context *rctx);
 603 void *evergreen_create_decompress_blend(struct r600_context *rctx);
 604 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
 605 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 606                                       enum pipe_format format,
 607                                       enum pipe_texture_target target,
 608                                       unsigned sample_count,
 609                                       unsigned usage);
 610 void evergreen_init_color_surface(struct r600_context *rctx,
 611                                   struct r600_surface *surf);
 612 void evergreen_init_color_surface_rat(struct r600_context *rctx,
 613                                         struct r600_surface *surf);
 614 void evergreen_update_db_shader_control(struct r600_context * rctx);
 615
 616 /* r600_blit.c */
 617 void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
 618                       struct pipe_resource *src, const struct pipe_box *src_box);
 619 void r600_init_blit_functions(struct r600_context *rctx);
 620 void r600_decompress_depth_textures(struct r600_context *rctx,
 621                                     struct r600_samplerview_state *textures);
 622 void r600_decompress_color_textures(struct r600_context *rctx,
 623                                     struct r600_samplerview_state *textures);
 624
 625 /* r600_buffer.c */
 626 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 627                                          const struct pipe_resource *templ,
 628                                          unsigned alignment);
 629
 630 /* r600_pipe.c */
 631 const char * r600_llvm_gpu_string(enum radeon_family family);
 632
 633
 634 /* r600_query.c */
 635 void r600_init_query_functions(struct r600_context *rctx);
 636 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 637 void r600_resume_nontimer_queries(struct r600_context *ctx);
 638
 639 /* r600_resource.c */
 640 void r600_init_context_resource_functions(struct r600_context *r600);
 641
 642 /* r600_shader.c */
 643 int r600_pipe_shader_create(struct pipe_context *ctx,
 644                             struct r600_pipe_shader *shader,
 645                             struct r600_shader_key key);
 646
 647 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 648
 649 /* r600_state.c */
 650 struct pipe_sampler_view *
 651 r600_create_sampler_view_custom(struct pipe_context *ctx,
 652                                 struct pipe_resource *texture,
 653                                 const struct pipe_sampler_view *state,
 654                                 unsigned width_first_level, unsigned height_first_level);
 655 void r600_init_state_functions(struct r600_context *rctx);
 656 void r600_init_atom_start_cs(struct r600_context *rctx);
 657 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 658 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 659 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 660 void *r600_create_resolve_blend(struct r600_context *rctx);
 661 void *r700_create_resolve_blend(struct r600_context *rctx);
 662 void *r600_create_decompress_blend(struct r600_context *rctx);
 663 bool r600_adjust_gprs(struct r600_context *rctx);
 664 boolean r600_is_format_supported(struct pipe_screen *screen,
 665                                  enum pipe_format format,
 666                                  enum pipe_texture_target target,
 667                                  unsigned sample_count,
 668                                  unsigned usage);
 669 void r600_update_db_shader_control(struct r600_context * rctx);
 670
 671 /* r600_hw_context.c */
 672 void r600_get_backend_mask(struct r600_context *ctx);
 673 void r600_context_flush(struct r600_context *ctx, unsigned flags);
 674 void r600_begin_new_cs(struct r600_context *ctx);
 675 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
 676                              unsigned offset, unsigned value);
 677 void r600_flush_emit(struct r600_context *ctx);
 678 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
 679 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
 680 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 681                              struct pipe_resource *dst, uint64_t dst_offset,
 682                              struct pipe_resource *src, uint64_t src_offset,
 683                              unsigned size);
 684 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
 685                                    struct pipe_resource *dst, uint64_t offset,
 686                                    unsigned size, uint32_t clear_value);
 687 void r600_dma_copy(struct r600_context *rctx,
 688                 struct pipe_resource *dst,
 689                 struct pipe_resource *src,
 690                 uint64_t dst_offset,
 691                 uint64_t src_offset,
 692                 uint64_t size);
 693
 694 /*
 695  * evergreen_hw_context.c
 696  */
 697 void evergreen_dma_copy(struct r600_context *rctx,
 698                 struct pipe_resource *dst,
 699                 struct pipe_resource *src,
 700                 uint64_t dst_offset,
 701                 uint64_t src_offset,
 702                 uint64_t size);
 703
 704 /* r600_state_common.c */
 705 void r600_init_common_state_functions(struct r600_context *rctx);
 706 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
 707 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
 708 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
 709 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
 710 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
 711 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
 712 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
 713 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
 714 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
 715                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 716                     unsigned num_dw);
 717 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 718 void r600_sampler_views_dirty(struct r600_context *rctx,
 719                               struct r600_samplerview_state *state);
 720 void r600_sampler_states_dirty(struct r600_context *rctx,
 721                                struct r600_sampler_states *state);
 722 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 723 void r600_draw_rectangle(struct blitter_context *blitter,
 724                          int x1, int y1, int x2, int y2, float depth,
 725                          enum blitter_attrib_type type, const union pipe_color_union *attrib);
 726 uint32_t r600_translate_stencil_op(int s_op);
 727 uint32_t r600_translate_fill(uint32_t func);
 728 unsigned r600_tex_wrap(unsigned wrap);
 729 unsigned r600_tex_filter(unsigned filter);
 730 unsigned r600_tex_mipfilter(unsigned filter);
 731 unsigned r600_tex_compare(unsigned compare);
 732 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
 733 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 734                                                 struct pipe_resource *texture,
 735                                                 const struct pipe_surface *templ,
 736                                                 unsigned width, unsigned height);
 737 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 738                                    const unsigned char *swizzle_view,
 739                                    boolean vtx);
 740 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 741                                   const unsigned char *swizzle_view,
 742                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 743
 744 /* r600_uvd.c */
 745 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
 746                                                    const struct pipe_video_codec *decoder);
 747
 748 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
 749                                                    const struct pipe_video_buffer *tmpl);
 750
 751 /*
 752  * Helpers for building command buffers
 753  */
 754
 755 #define PKT3_SET_CONFIG_REG     0x68
 756 #define PKT3_SET_CONTEXT_REG    0x69
 757 #define PKT3_SET_CTL_CONST      0x6F
 758 #define PKT3_SET_LOOP_CONST                    0x6C
 759
 760 #define R600_CONFIG_REG_OFFSET  0x08000
 761 #define R600_CONTEXT_REG_OFFSET 0x28000
 762 #define R600_CTL_CONST_OFFSET   0x3CFF0
 763 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 764 #define EG_LOOP_CONST_OFFSET               0x0003A200
 765
 766 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 767 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 768 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 769 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 770 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 771
 772 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
 773
 774 /*Evergreen Compute packet3*/
 775 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
 776
 777 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 778 {
 779         cb->buf[cb->num_dw++] = value;
 780 }
 781
 782 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
 783 {
 784         assert(cb->num_dw+num <= cb->max_num_dw);
 785         memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
 786         cb->num_dw += num;
 787 }
 788
 789 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 790 {
 791         assert(reg < R600_CONTEXT_REG_OFFSET);
 792         assert(cb->num_dw+2+num <= cb->max_num_dw);
 793         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 794         cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 795 }
 796
 797 /**
 798  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 799  * shaders.
 800  */
 801 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 802 {
 803         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 804         assert(cb->num_dw+2+num <= cb->max_num_dw);
 805         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 806         cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 807 }
 808
 809 /**
 810  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 811  * shaders.
 812  */
 813 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 814 {
 815         assert(reg >= R600_CTL_CONST_OFFSET);
 816         assert(cb->num_dw+2+num <= cb->max_num_dw);
 817         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 818         cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 819 }
 820
 821 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 822 {
 823         assert(reg >= R600_LOOP_CONST_OFFSET);
 824         assert(cb->num_dw+2+num <= cb->max_num_dw);
 825         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 826         cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 827 }
 828
 829 /**
 830  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 831  * shaders.
 832  */
 833 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 834 {
 835         assert(reg >= EG_LOOP_CONST_OFFSET);
 836         assert(cb->num_dw+2+num <= cb->max_num_dw);
 837         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 838         cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 839 }
 840
 841 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 842 {
 843         r600_store_config_reg_seq(cb, reg, 1);
 844         r600_store_value(cb, value);
 845 }
 846
 847 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 848 {
 849         r600_store_context_reg_seq(cb, reg, 1);
 850         r600_store_value(cb, value);
 851 }
 852
 853 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 854 {
 855         r600_store_ctl_const_seq(cb, reg, 1);
 856         r600_store_value(cb, value);
 857 }
 858
 859 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 860 {
 861         r600_store_loop_const_seq(cb, reg, 1);
 862         r600_store_value(cb, value);
 863 }
 864
 865 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 866 {
 867         eg_store_loop_const_seq(cb, reg, 1);
 868         r600_store_value(cb, value);
 869 }
 870
 871 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
 872 void r600_release_command_buffer(struct r600_command_buffer *cb);
 873
 874 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 875 {
 876         r600_write_context_reg_seq(cs, reg, num);
 877         /* Set the compute bit on the packet header */
 878         cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
 879 }
 880
 881 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 882 {
 883         assert(reg >= R600_CTL_CONST_OFFSET);
 884         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 885         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 886         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 887 }
 888
 889 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 890 {
 891         r600_write_compute_context_reg_seq(cs, reg, 1);
 892         radeon_emit(cs, value);
 893 }
 894
 895 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
 896 {
 897         if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
 898                 r600_write_compute_context_reg(cs, reg, value);
 899         } else {
 900                 r600_write_context_reg(cs, reg, value);
 901         }
 902 }
 903
 904 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 905 {
 906         r600_write_ctl_const_seq(cs, reg, 1);
 907         radeon_emit(cs, value);
 908 }
 909
 910 /*
 911  * common helpers
 912  */
 913 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 914 {
 915         return value * (1 << frac_bits);
 916 }
 917 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 918
 919 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 920 {
 921         if (filter <= 1)   return 0;
 922         if (filter <= 2)   return 1;
 923         if (filter <= 4)   return 2;
 924         if (filter <= 8)   return 3;
 925          /* else */        return 4;
 926 }
 927
 928 /* 12.4 fixed-point */
 929 static INLINE unsigned r600_pack_float_12p4(float x)
 930 {
 931         return x <= 0    ? 0 :
 932                x >= 4096 ? 0xffff : x * 16;
 933 }
 934
 935 #endif