src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_formats.h"
  24 #include "r600_shader.h"
  25 #include "r600d.h"
  26
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_framebuffer.h"
  31 #include "util/u_dual_blend.h"
  32
  33 static uint32_t r600_translate_blend_function(int blend_func)
  34 {
  35         switch (blend_func) {
  36         case PIPE_BLEND_ADD:
  37                 return V_028804_COMB_DST_PLUS_SRC;
  38         case PIPE_BLEND_SUBTRACT:
  39                 return V_028804_COMB_SRC_MINUS_DST;
  40         case PIPE_BLEND_REVERSE_SUBTRACT:
  41                 return V_028804_COMB_DST_MINUS_SRC;
  42         case PIPE_BLEND_MIN:
  43                 return V_028804_COMB_MIN_DST_SRC;
  44         case PIPE_BLEND_MAX:
  45                 return V_028804_COMB_MAX_DST_SRC;
  46         default:
  47                 R600_ERR("Unknown blend function %d\n", blend_func);
  48                 assert(0);
  49                 break;
  50         }
  51         return 0;
  52 }
  53
  54 static uint32_t r600_translate_blend_factor(int blend_fact)
  55 {
  56         switch (blend_fact) {
  57         case PIPE_BLENDFACTOR_ONE:
  58                 return V_028804_BLEND_ONE;
  59         case PIPE_BLENDFACTOR_SRC_COLOR:
  60                 return V_028804_BLEND_SRC_COLOR;
  61         case PIPE_BLENDFACTOR_SRC_ALPHA:
  62                 return V_028804_BLEND_SRC_ALPHA;
  63         case PIPE_BLENDFACTOR_DST_ALPHA:
  64                 return V_028804_BLEND_DST_ALPHA;
  65         case PIPE_BLENDFACTOR_DST_COLOR:
  66                 return V_028804_BLEND_DST_COLOR;
  67         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  68                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  69         case PIPE_BLENDFACTOR_CONST_COLOR:
  70                 return V_028804_BLEND_CONST_COLOR;
  71         case PIPE_BLENDFACTOR_CONST_ALPHA:
  72                 return V_028804_BLEND_CONST_ALPHA;
  73         case PIPE_BLENDFACTOR_ZERO:
  74                 return V_028804_BLEND_ZERO;
  75         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  76                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  77         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  78                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  79         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  80                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  81         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  82                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  83         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
  84                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
  85         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
  86                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
  87         case PIPE_BLENDFACTOR_SRC1_COLOR:
  88                 return V_028804_BLEND_SRC1_COLOR;
  89         case PIPE_BLENDFACTOR_SRC1_ALPHA:
  90                 return V_028804_BLEND_SRC1_ALPHA;
  91         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
  92                 return V_028804_BLEND_INV_SRC1_COLOR;
  93         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
  94                 return V_028804_BLEND_INV_SRC1_ALPHA;
  95         default:
  96                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
  97                 assert(0);
  98                 break;
  99         }
 100         return 0;
 101 }
 102
 103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
 104 {
 105         switch (dim) {
 106         default:
 107         case PIPE_TEXTURE_1D:
 108                 return V_038000_SQ_TEX_DIM_1D;
 109         case PIPE_TEXTURE_1D_ARRAY:
 110                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 111         case PIPE_TEXTURE_2D:
 112         case PIPE_TEXTURE_RECT:
 113                 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
 114                                         V_038000_SQ_TEX_DIM_2D;
 115         case PIPE_TEXTURE_2D_ARRAY:
 116                 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
 117                                         V_038000_SQ_TEX_DIM_2D_ARRAY;
 118         case PIPE_TEXTURE_3D:
 119                 return V_038000_SQ_TEX_DIM_3D;
 120         case PIPE_TEXTURE_CUBE:
 121         case PIPE_TEXTURE_CUBE_ARRAY:
 122                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 123         }
 124 }
 125
 126 static uint32_t r600_translate_dbformat(enum pipe_format format)
 127 {
 128         switch (format) {
 129         case PIPE_FORMAT_Z16_UNORM:
 130                 return V_028010_DEPTH_16;
 131         case PIPE_FORMAT_Z24X8_UNORM:
 132                 return V_028010_DEPTH_X8_24;
 133         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 134                 return V_028010_DEPTH_8_24;
 135         case PIPE_FORMAT_Z32_FLOAT:
 136                 return V_028010_DEPTH_32_FLOAT;
 137         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 138                 return V_028010_DEPTH_X24_8_32_FLOAT;
 139         default:
 140                 return ~0U;
 141         }
 142 }
 143
 144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 145 {
 146         return r600_translate_texformat(screen, format, NULL, NULL, NULL,
 147                                    FALSE) != ~0U;
 148 }
 149
 150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
 151 {
 152         return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
 153                r600_translate_colorswap(format, FALSE) != ~0U;
 154 }
 155
 156 static bool r600_is_zs_format_supported(enum pipe_format format)
 157 {
 158         return r600_translate_dbformat(format) != ~0U;
 159 }
 160
 161 boolean r600_is_format_supported(struct pipe_screen *screen,
 162                                  enum pipe_format format,
 163                                  enum pipe_texture_target target,
 164                                  unsigned sample_count,
 165                                  unsigned usage)
 166 {
 167         struct r600_screen *rscreen = (struct r600_screen*)screen;
 168         unsigned retval = 0;
 169
 170         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 171                 R600_ERR("r600: unsupported texture type %d\n", target);
 172                 return FALSE;
 173         }
 174
 175         if (!util_format_is_supported(format, usage))
 176                 return FALSE;
 177
 178         if (sample_count > 1) {
 179                 if (!rscreen->has_msaa)
 180                         return FALSE;
 181
 182                 /* R11G11B10 is broken on R6xx. */
 183                 if (rscreen->b.chip_class == R600 &&
 184                     format == PIPE_FORMAT_R11G11B10_FLOAT)
 185                         return FALSE;
 186
 187                 /* MSAA integer colorbuffers hang. */
 188                 if (util_format_is_pure_integer(format) &&
 189                     !util_format_is_depth_or_stencil(format))
 190                         return FALSE;
 191
 192                 switch (sample_count) {
 193                 case 2:
 194                 case 4:
 195                 case 8:
 196                         break;
 197                 default:
 198                         return FALSE;
 199                 }
 200         }
 201
 202         if (usage & PIPE_BIND_SAMPLER_VIEW) {
 203                 if (target == PIPE_BUFFER) {
 204                         if (r600_is_vertex_format_supported(format))
 205                                 retval |= PIPE_BIND_SAMPLER_VIEW;
 206                 } else {
 207                         if (r600_is_sampler_format_supported(screen, format))
 208                                 retval |= PIPE_BIND_SAMPLER_VIEW;
 209                 }
 210         }
 211
 212         if ((usage & (PIPE_BIND_RENDER_TARGET |
 213                       PIPE_BIND_DISPLAY_TARGET |
 214                       PIPE_BIND_SCANOUT |
 215                       PIPE_BIND_SHARED |
 216                       PIPE_BIND_BLENDABLE)) &&
 217             r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
 218                 retval |= usage &
 219                           (PIPE_BIND_RENDER_TARGET |
 220                            PIPE_BIND_DISPLAY_TARGET |
 221                            PIPE_BIND_SCANOUT |
 222                            PIPE_BIND_SHARED);
 223                 if (!util_format_is_pure_integer(format) &&
 224                     !util_format_is_depth_or_stencil(format))
 225                         retval |= usage & PIPE_BIND_BLENDABLE;
 226         }
 227
 228         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 229             r600_is_zs_format_supported(format)) {
 230                 retval |= PIPE_BIND_DEPTH_STENCIL;
 231         }
 232
 233         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 234             r600_is_vertex_format_supported(format)) {
 235                 retval |= PIPE_BIND_VERTEX_BUFFER;
 236         }
 237
 238         if (usage & PIPE_BIND_TRANSFER_READ)
 239                 retval |= PIPE_BIND_TRANSFER_READ;
 240         if (usage & PIPE_BIND_TRANSFER_WRITE)
 241                 retval |= PIPE_BIND_TRANSFER_WRITE;
 242
 243         if ((usage & PIPE_BIND_LINEAR) &&
 244             !util_format_is_compressed(format) &&
 245             !(usage & PIPE_BIND_DEPTH_STENCIL))
 246                 retval |= PIPE_BIND_LINEAR;
 247
 248         return retval == usage;
 249 }
 250
 251 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
 252 {
 253         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 254         struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
 255         float offset_units = state->offset_units;
 256         float offset_scale = state->offset_scale;
 257
 258         switch (state->zs_format) {
 259         case PIPE_FORMAT_Z24X8_UNORM:
 260         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 261                 offset_units *= 2.0f;
 262                 break;
 263         case PIPE_FORMAT_Z16_UNORM:
 264                 offset_units *= 4.0f;
 265                 break;
 266         default:;
 267         }
 268
 269         radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
 270         radeon_emit(cs, fui(offset_scale));
 271         radeon_emit(cs, fui(offset_units));
 272         radeon_emit(cs, fui(offset_scale));
 273         radeon_emit(cs, fui(offset_units));
 274 }
 275
 276 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
 277 {
 278         int j = state->independent_blend_enable ? i : 0;
 279
 280         unsigned eqRGB = state->rt[j].rgb_func;
 281         unsigned srcRGB = state->rt[j].rgb_src_factor;
 282         unsigned dstRGB = state->rt[j].rgb_dst_factor;
 283
 284         unsigned eqA = state->rt[j].alpha_func;
 285         unsigned srcA = state->rt[j].alpha_src_factor;
 286         unsigned dstA = state->rt[j].alpha_dst_factor;
 287         uint32_t bc = 0;
 288
 289         if (!state->rt[j].blend_enable)
 290                 return 0;
 291
 292         bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 293         bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 294         bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 295
 296         if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 297                 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 298                 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 299                 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 300                 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 301         }
 302         return bc;
 303 }
 304
 305 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
 306                                           const struct pipe_blend_state *state,
 307                                           int mode)
 308 {
 309         struct r600_context *rctx = (struct r600_context *)ctx;
 310         uint32_t color_control = 0, target_mask = 0;
 311         struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
 312
 313         if (!blend) {
 314                 return NULL;
 315         }
 316
 317         r600_init_command_buffer(&blend->buffer, 20);
 318         r600_init_command_buffer(&blend->buffer_no_blend, 20);
 319
 320         /* R600 does not support per-MRT blends */
 321         if (rctx->b.family > CHIP_R600)
 322                 color_control |= S_028808_PER_MRT_BLEND(1);
 323
 324         if (state->logicop_enable) {
 325                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 326         } else {
 327                 color_control |= (0xcc << 16);
 328         }
 329         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 330         if (state->independent_blend_enable) {
 331                 for (int i = 0; i < 8; i++) {
 332                         if (state->rt[i].blend_enable) {
 333                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 334                         }
 335                         target_mask |= (state->rt[i].colormask << (4 * i));
 336                 }
 337         } else {
 338                 for (int i = 0; i < 8; i++) {
 339                         if (state->rt[0].blend_enable) {
 340                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 341                         }
 342                         target_mask |= (state->rt[0].colormask << (4 * i));
 343                 }
 344         }
 345
 346         if (target_mask)
 347                 color_control |= S_028808_SPECIAL_OP(mode);
 348         else
 349                 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
 350
 351         /* only MRT0 has dual src blend */
 352         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 353         blend->cb_target_mask = target_mask;
 354         blend->cb_color_control = color_control;
 355         blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
 356         blend->alpha_to_one = state->alpha_to_one;
 357
 358         r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
 359                                S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 360                                S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
 361                                S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
 362                                S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
 363                                S_028D44_ALPHA_TO_MASK_OFFSET3(2));
 364
 365         /* Copy over the registers set so far into buffer_no_blend. */
 366         memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
 367         blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
 368
 369         /* Only add blend registers if blending is enabled. */
 370         if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
 371                 return blend;
 372         }
 373
 374         /* The first R600 does not support per-MRT blends */
 375         r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
 376                                r600_get_blend_control(state, 0));
 377
 378         if (rctx->b.family > CHIP_R600) {
 379                 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
 380                 for (int i = 0; i < 8; i++) {
 381                         r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
 382                 }
 383         }
 384         return blend;
 385 }
 386
 387 static void *r600_create_blend_state(struct pipe_context *ctx,
 388                                      const struct pipe_blend_state *state)
 389 {
 390         return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
 391 }
 392
 393 static void *r600_create_dsa_state(struct pipe_context *ctx,
 394                                    const struct pipe_depth_stencil_alpha_state *state)
 395 {
 396         unsigned db_depth_control, alpha_test_control, alpha_ref;
 397         struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
 398
 399         if (!dsa) {
 400                 return NULL;
 401         }
 402
 403         r600_init_command_buffer(&dsa->buffer, 3);
 404
 405         dsa->valuemask[0] = state->stencil[0].valuemask;
 406         dsa->valuemask[1] = state->stencil[1].valuemask;
 407         dsa->writemask[0] = state->stencil[0].writemask;
 408         dsa->writemask[1] = state->stencil[1].writemask;
 409         dsa->zwritemask = state->depth.writemask;
 410
 411         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 412                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 413                 S_028800_ZFUNC(state->depth.func);
 414
 415         /* stencil */
 416         if (state->stencil[0].enabled) {
 417                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 418                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 419                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 420                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 421                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 422
 423                 if (state->stencil[1].enabled) {
 424                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 425                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 426                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 427                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 428                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 429                 }
 430         }
 431
 432         /* alpha */
 433         alpha_test_control = 0;
 434         alpha_ref = 0;
 435         if (state->alpha.enabled) {
 436                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 437                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 438                 alpha_ref = fui(state->alpha.ref_value);
 439         }
 440         dsa->sx_alpha_test_control = alpha_test_control & 0xff;
 441         dsa->alpha_ref = alpha_ref;
 442
 443         r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 444         return dsa;
 445 }
 446
 447 static void *r600_create_rs_state(struct pipe_context *ctx,
 448                                   const struct pipe_rasterizer_state *state)
 449 {
 450         struct r600_context *rctx = (struct r600_context *)ctx;
 451         unsigned tmp, sc_mode_cntl, spi_interp;
 452         float psize_min, psize_max;
 453         struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
 454
 455         if (!rs) {
 456                 return NULL;
 457         }
 458
 459         r600_init_command_buffer(&rs->buffer, 30);
 460
 461         rs->scissor_enable = state->scissor;
 462         rs->flatshade = state->flatshade;
 463         rs->sprite_coord_enable = state->sprite_coord_enable;
 464         rs->two_side = state->light_twoside;
 465         rs->clip_plane_enable = state->clip_plane_enable;
 466         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 467                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 468                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 469         rs->pa_cl_clip_cntl =
 470                 S_028810_PS_UCP_MODE(3) |
 471                 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
 472                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 473                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 474                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 475         if (rctx->b.chip_class == R700) {
 476                 rs->pa_cl_clip_cntl |=
 477                         S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
 478         }
 479         rs->multisample_enable = state->multisample;
 480
 481         /* offset */
 482         rs->offset_units = state->offset_units;
 483         rs->offset_scale = state->offset_scale * 16.0f;
 484         rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
 485
 486         if (state->point_size_per_vertex) {
 487                 psize_min = util_get_min_point_size(state);
 488                 psize_max = 8192;
 489         } else {
 490                 /* Force the point size to be as if the vertex output was disabled. */
 491                 psize_min = state->point_size;
 492                 psize_max = state->point_size;
 493         }
 494
 495         sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
 496                        S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
 497                        S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
 498                        S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
 499         if (rctx->b.family == CHIP_RV770) {
 500                 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
 501                 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
 502         }
 503         if (rctx->b.chip_class >= R700) {
 504                 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
 505                                 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
 506                                 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
 507         } else {
 508                 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
 509         }
 510
 511         spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
 512         if (state->sprite_coord_enable) {
 513                 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
 514                               S_0286D4_PNT_SPRITE_OVRD_X(2) |
 515                               S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 516                               S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 517                               S_0286D4_PNT_SPRITE_OVRD_W(1);
 518                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 519                         spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 520                 }
 521         }
 522
 523         r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
 524         /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
 525         tmp = r600_pack_float_12p4(state->point_size/2);
 526         r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
 527                          S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 528         r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
 529                          S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 530                          S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
 531         r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
 532                          S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
 533
 534         r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
 535         r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
 536         r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
 537                                S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
 538                                S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 539         r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 540
 541         rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 542                                  S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
 543                                  S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
 544                                  S_028814_FACE(!state->front_ccw) |
 545                                  S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
 546                                  S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
 547                                  S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
 548                                  S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
 549                                                                          state->fill_back != PIPE_POLYGON_MODE_FILL) |
 550                                  S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 551                                  S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
 552         if (rctx->b.chip_class == R700) {
 553                 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
 554         }
 555         if (rctx->b.chip_class == R600) {
 556                 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
 557                                        S_028350_MULTIPASS(state->rasterizer_discard));
 558         }
 559         return rs;
 560 }
 561
 562 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
 563 {
 564         if (filter == PIPE_TEX_FILTER_LINEAR)
 565                 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
 566                                      : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 567         else
 568                 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
 569                                      : V_03C000_SQ_TEX_XY_FILTER_POINT;
 570 }
 571
 572 static void *r600_create_sampler_state(struct pipe_context *ctx,
 573                                         const struct pipe_sampler_state *state)
 574 {
 575         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 576         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 577         unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
 578                                                        : state->max_anisotropy;
 579         unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
 580
 581         if (!ss) {
 582                 return NULL;
 583         }
 584
 585         ss->seamless_cube_map = state->seamless_cube_map;
 586         ss->border_color_use = sampler_state_needs_border_color(state);
 587
 588         /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
 589         ss->tex_sampler_words[0] =
 590                 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 591                 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 592                 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 593                 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
 594                 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
 595                 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 596                 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
 597                 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 598                 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
 599         /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
 600         ss->tex_sampler_words[1] =
 601                 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 602                 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 603                 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 604         /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
 605         ss->tex_sampler_words[2] = S_03C008_TYPE(1);
 606
 607         if (ss->border_color_use) {
 608                 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
 609         }
 610         return ss;
 611 }
 612
 613 static struct pipe_sampler_view *
 614 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
 615                             unsigned width0, unsigned height0)
 616
 617 {
 618         struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
 619         int stride = util_format_get_blocksize(view->base.format);
 620         unsigned format, num_format, format_comp, endian;
 621         uint64_t offset = view->base.u.buf.first_element * stride;
 622         unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
 623
 624         r600_vertex_data_type(view->base.format,
 625                               &format, &num_format, &format_comp,
 626                               &endian);
 627
 628         view->tex_resource = &tmp->resource;
 629         view->skip_mip_address_reloc = true;
 630
 631         view->tex_resource_words[0] = offset;
 632         view->tex_resource_words[1] = size - 1;
 633         view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
 634                 S_038008_STRIDE(stride) |
 635                 S_038008_DATA_FORMAT(format) |
 636                 S_038008_NUM_FORMAT_ALL(num_format) |
 637                 S_038008_FORMAT_COMP_ALL(format_comp) |
 638                 S_038008_ENDIAN_SWAP(endian);
 639         view->tex_resource_words[3] = 0;
 640         /*
 641          * in theory dword 4 is for number of elements, for use with resinfo,
 642          * but it seems to utterly fail to work, the amd gpu shader analyser
 643          * uses a const buffer to store the element sizes for buffer txq
 644          */
 645         view->tex_resource_words[4] = 0;
 646         view->tex_resource_words[5] = 0;
 647         view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
 648         return &view->base;
 649 }
 650
 651 struct pipe_sampler_view *
 652 r600_create_sampler_view_custom(struct pipe_context *ctx,
 653                                 struct pipe_resource *texture,
 654                                 const struct pipe_sampler_view *state,
 655                                 unsigned width_first_level, unsigned height_first_level)
 656 {
 657         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
 658         struct r600_texture *tmp = (struct r600_texture*)texture;
 659         unsigned format, endian;
 660         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 661         unsigned char swizzle[4], array_mode = 0;
 662         unsigned width, height, depth, offset_level, last_level;
 663         bool do_endian_swap = FALSE;
 664
 665         if (!view)
 666                 return NULL;
 667
 668         /* initialize base object */
 669         view->base = *state;
 670         view->base.texture = NULL;
 671         pipe_reference(NULL, &texture->reference);
 672         view->base.texture = texture;
 673         view->base.reference.count = 1;
 674         view->base.context = ctx;
 675
 676         if (texture->target == PIPE_BUFFER)
 677                 return texture_buffer_sampler_view(view, texture->width0, 1);
 678
 679         swizzle[0] = state->swizzle_r;
 680         swizzle[1] = state->swizzle_g;
 681         swizzle[2] = state->swizzle_b;
 682         swizzle[3] = state->swizzle_a;
 683
 684         if (R600_BIG_ENDIAN)
 685                 do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
 686
 687         format = r600_translate_texformat(ctx->screen, state->format,
 688                                           swizzle,
 689                                           &word4, &yuv_format, do_endian_swap);
 690         assert(format != ~0);
 691         if (format == ~0) {
 692                 FREE(view);
 693                 return NULL;
 694         }
 695
 696         if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
 697                 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
 698                         FREE(view);
 699                         return NULL;
 700                 }
 701                 tmp = tmp->flushed_depth_texture;
 702         }
 703
 704         endian = r600_colorformat_endian_swap(format, do_endian_swap);
 705
 706         offset_level = state->u.tex.first_level;
 707         last_level = state->u.tex.last_level - offset_level;
 708         width = width_first_level;
 709         height = height_first_level;
 710         depth = u_minify(texture->depth0, offset_level);
 711         pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
 712
 713         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
 714                 height = 1;
 715                 depth = texture->array_size;
 716         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
 717                 depth = texture->array_size;
 718         } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
 719                 depth = texture->array_size / 6;
 720
 721         switch (tmp->surface.level[offset_level].mode) {
 722         default:
 723         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 724                 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
 725                 break;
 726         case RADEON_SURF_MODE_1D:
 727                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 728                 break;
 729         case RADEON_SURF_MODE_2D:
 730                 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 731                 break;
 732         }
 733
 734         if (state->format == PIPE_FORMAT_X24S8_UINT ||
 735             state->format == PIPE_FORMAT_S8X24_UINT ||
 736             state->format == PIPE_FORMAT_X32_S8X24_UINT ||
 737             state->format == PIPE_FORMAT_S8_UINT)
 738                 view->is_stencil_sampler = true;
 739
 740         view->tex_resource = &tmp->resource;
 741         view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
 742                                        S_038000_TILE_MODE(array_mode) |
 743                                        S_038000_TILE_TYPE(tmp->non_disp_tiling) |
 744                                        S_038000_PITCH((pitch / 8) - 1) |
 745                                        S_038000_TEX_WIDTH(width - 1));
 746         view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
 747                                        S_038004_TEX_DEPTH(depth - 1) |
 748                                        S_038004_DATA_FORMAT(format));
 749         view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
 750         if (offset_level >= tmp->surface.last_level) {
 751                 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
 752         } else {
 753                 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
 754         }
 755         view->tex_resource_words[4] = (word4 |
 756                                        S_038010_REQUEST_SIZE(1) |
 757                                        S_038010_ENDIAN_SWAP(endian) |
 758                                        S_038010_BASE_LEVEL(0));
 759         view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
 760                                        S_038014_LAST_ARRAY(state->u.tex.last_layer));
 761         if (texture->nr_samples > 1) {
 762                 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
 763                 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
 764         } else {
 765                 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
 766         }
 767         view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
 768                                        S_038018_MAX_ANISO(4 /* max 16 samples */));
 769         return &view->base;
 770 }
 771
 772 static struct pipe_sampler_view *
 773 r600_create_sampler_view(struct pipe_context *ctx,
 774                          struct pipe_resource *tex,
 775                          const struct pipe_sampler_view *state)
 776 {
 777         return r600_create_sampler_view_custom(ctx, tex, state,
 778                                                u_minify(tex->width0, state->u.tex.first_level),
 779                                                u_minify(tex->height0, state->u.tex.first_level));
 780 }
 781
 782 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
 783 {
 784         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
 785         struct pipe_clip_state *state = &rctx->clip_state.state;
 786
 787         radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
 788         radeon_emit_array(cs, (unsigned*)state, 6*4);
 789 }
 790
 791 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 792                                          const struct pipe_poly_stipple *state)
 793 {
 794 }
 795
 796 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
 797                                                        unsigned size, unsigned alignment)
 798 {
 799         struct pipe_resource buffer;
 800
 801         memset(&buffer, 0, sizeof buffer);
 802         buffer.target = PIPE_BUFFER;
 803         buffer.format = PIPE_FORMAT_R8_UNORM;
 804         buffer.bind = PIPE_BIND_CUSTOM;
 805         buffer.usage = PIPE_USAGE_DEFAULT;
 806         buffer.flags = 0;
 807         buffer.width0 = size;
 808         buffer.height0 = 1;
 809         buffer.depth0 = 1;
 810         buffer.array_size = 1;
 811
 812         return (struct r600_resource*)
 813                 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
 814 }
 815
 816 static void r600_init_color_surface(struct r600_context *rctx,
 817                                     struct r600_surface *surf,
 818                                     bool force_cmask_fmask)
 819 {
 820         struct r600_screen *rscreen = rctx->screen;
 821         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
 822         unsigned level = surf->base.u.tex.level;
 823         unsigned pitch, slice;
 824         unsigned color_info;
 825         unsigned color_view;
 826         unsigned format, swap, ntype, endian;
 827         unsigned offset;
 828         const struct util_format_description *desc;
 829         int i;
 830         bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
 831
 832         if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
 833                 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
 834                 rtex = rtex->flushed_depth_texture;
 835                 assert(rtex);
 836         }
 837
 838         offset = rtex->surface.level[level].offset;
 839         color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
 840                      S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
 841
 842         pitch = rtex->surface.level[level].nblk_x / 8 - 1;
 843         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
 844         if (slice) {
 845                 slice = slice - 1;
 846         }
 847         color_info = 0;
 848         switch (rtex->surface.level[level].mode) {
 849         default:
 850         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 851                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
 852                 break;
 853         case RADEON_SURF_MODE_1D:
 854                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
 855                 break;
 856         case RADEON_SURF_MODE_2D:
 857                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
 858                 break;
 859         }
 860
 861         desc = util_format_description(surf->base.format);
 862
 863         for (i = 0; i < 4; i++) {
 864                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 865                         break;
 866                 }
 867         }
 868
 869         ntype = V_0280A0_NUMBER_UNORM;
 870         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 871                 ntype = V_0280A0_NUMBER_SRGB;
 872         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 873                 if (desc->channel[i].normalized)
 874                         ntype = V_0280A0_NUMBER_SNORM;
 875                 else if (desc->channel[i].pure_integer)
 876                         ntype = V_0280A0_NUMBER_SINT;
 877         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
 878                 if (desc->channel[i].normalized)
 879                         ntype = V_0280A0_NUMBER_UNORM;
 880                 else if (desc->channel[i].pure_integer)
 881                         ntype = V_0280A0_NUMBER_UINT;
 882         }
 883
 884         if (R600_BIG_ENDIAN)
 885                 do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
 886
 887         format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
 888                                                       do_endian_swap);
 889         assert(format != ~0);
 890
 891         swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
 892         assert(swap != ~0);
 893
 894         endian = r600_colorformat_endian_swap(format, do_endian_swap);
 895
 896         /* set blend bypass according to docs if SINT/UINT or
 897            8/24 COLOR variants */
 898         if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
 899             format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
 900             format == V_0280A0_COLOR_X24_8_32_FLOAT) {
 901                 blend_clamp = 0;
 902                 blend_bypass = 1;
 903         }
 904
 905         surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
 906
 907         color_info |= S_0280A0_FORMAT(format) |
 908                 S_0280A0_COMP_SWAP(swap) |
 909                 S_0280A0_BLEND_BYPASS(blend_bypass) |
 910                 S_0280A0_BLEND_CLAMP(blend_clamp) |
 911                 S_0280A0_NUMBER_TYPE(ntype) |
 912                 S_0280A0_ENDIAN(endian);
 913
 914         /* EXPORT_NORM is an optimzation that can be enabled for better
 915          * performance in certain cases
 916          */
 917         if (rctx->b.chip_class == R600) {
 918                 /* EXPORT_NORM can be enabled if:
 919                  * - 11-bit or smaller UNORM/SNORM/SRGB
 920                  * - BLEND_CLAMP is enabled
 921                  * - BLEND_FLOAT32 is disabled
 922                  */
 923                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
 924                     (desc->channel[i].size < 12 &&
 925                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
 926                      ntype != V_0280A0_NUMBER_UINT &&
 927                      ntype != V_0280A0_NUMBER_SINT) &&
 928                     G_0280A0_BLEND_CLAMP(color_info) &&
 929                     !G_0280A0_BLEND_FLOAT32(color_info)) {
 930                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
 931                         surf->export_16bpc = true;
 932                 }
 933         } else {
 934                 /* EXPORT_NORM can be enabled if:
 935                  * - 11-bit or smaller UNORM/SNORM/SRGB
 936                  * - 16-bit or smaller FLOAT
 937                  */
 938                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
 939                     ((desc->channel[i].size < 12 &&
 940                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
 941                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
 942                     (desc->channel[i].size < 17 &&
 943                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
 944                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
 945                         surf->export_16bpc = true;
 946                 }
 947         }
 948
 949         /* These might not always be initialized to zero. */
 950         surf->cb_color_base = offset >> 8;
 951         surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
 952                               S_028060_SLICE_TILE_MAX(slice);
 953         surf->cb_color_fmask = surf->cb_color_base;
 954         surf->cb_color_cmask = surf->cb_color_base;
 955         surf->cb_color_mask = 0;
 956
 957         pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
 958                                 &rtex->resource.b.b);
 959         pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
 960                                 &rtex->resource.b.b);
 961
 962         if (rtex->cmask.size) {
 963                 surf->cb_color_cmask = rtex->cmask.offset >> 8;
 964                 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
 965
 966                 if (rtex->fmask.size) {
 967                         color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
 968                         surf->cb_color_fmask = rtex->fmask.offset >> 8;
 969                         surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
 970                 } else { /* cmask only */
 971                         color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
 972                 }
 973         } else if (force_cmask_fmask) {
 974                 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
 975                  *
 976                  * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
 977                  * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
 978                  * because it's not an MSAA buffer.
 979                  */
 980                 struct r600_cmask_info cmask;
 981                 struct r600_fmask_info fmask;
 982
 983                 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
 984                 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
 985
 986                 /* CMASK. */
 987                 if (!rctx->dummy_cmask ||
 988                     rctx->dummy_cmask->b.b.width0 < cmask.size ||
 989                     rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
 990                         struct pipe_transfer *transfer;
 991                         void *ptr;
 992
 993                         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 994                         rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
 995
 996                         /* Set the contents to 0xCC. */
 997                         ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
 998                         memset(ptr, 0xCC, cmask.size);
 999                         pipe_buffer_unmap(&rctx->b.b, transfer);
1000                 }
1001                 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1002                                         &rctx->dummy_cmask->b.b);
1003
1004                 /* FMASK. */
1005                 if (!rctx->dummy_fmask ||
1006                     rctx->dummy_fmask->b.b.width0 < fmask.size ||
1007                     rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1008                         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1009                         rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1010
1011                 }
1012                 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1013                                         &rctx->dummy_fmask->b.b);
1014
1015                 /* Init the registers. */
1016                 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1017                 surf->cb_color_cmask = 0;
1018                 surf->cb_color_fmask = 0;
1019                 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1020                                       S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1021         }
1022
1023         surf->cb_color_info = color_info;
1024         surf->cb_color_view = color_view;
1025         surf->color_initialized = true;
1026 }
1027
1028 static void r600_init_depth_surface(struct r600_context *rctx,
1029                                     struct r600_surface *surf)
1030 {
1031         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1032         unsigned level, pitch, slice, format, offset, array_mode;
1033
1034         level = surf->base.u.tex.level;
1035         offset = rtex->surface.level[level].offset;
1036         pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1037         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1038         if (slice) {
1039                 slice = slice - 1;
1040         }
1041         switch (rtex->surface.level[level].mode) {
1042         case RADEON_SURF_MODE_2D:
1043                 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1044                 break;
1045         case RADEON_SURF_MODE_1D:
1046         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1047         default:
1048                 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1049                 break;
1050         }
1051
1052         format = r600_translate_dbformat(surf->base.format);
1053         assert(format != ~0);
1054
1055         surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1056         surf->db_depth_base = offset >> 8;
1057         surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1058                               S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1059         surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1060         surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1061
1062         switch (surf->base.format) {
1063         case PIPE_FORMAT_Z24X8_UNORM:
1064         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1065                 surf->pa_su_poly_offset_db_fmt_cntl =
1066                         S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1067                 break;
1068         case PIPE_FORMAT_Z32_FLOAT:
1069         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1070                 surf->pa_su_poly_offset_db_fmt_cntl =
1071                         S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1072                         S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1073                 break;
1074         case PIPE_FORMAT_Z16_UNORM:
1075                 surf->pa_su_poly_offset_db_fmt_cntl =
1076                         S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1077                 break;
1078         default:;
1079         }
1080
1081         /* use htile only for first level */
1082         if (rtex->htile_buffer && !level) {
1083                 surf->db_htile_data_base = 0;
1084                 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1085                                          S_028D24_HTILE_HEIGHT(1) |
1086                                          S_028D24_FULL_CACHE(1);
1087                 /* preload is not working properly on r6xx/r7xx */
1088                 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1089         }
1090
1091         surf->depth_initialized = true;
1092 }
1093
1094 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1095                                         const struct pipe_framebuffer_state *state)
1096 {
1097         struct r600_context *rctx = (struct r600_context *)ctx;
1098         struct r600_surface *surf;
1099         struct r600_texture *rtex;
1100         unsigned i;
1101
1102         if (rctx->framebuffer.state.nr_cbufs) {
1103                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1104                 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1105                                  R600_CONTEXT_FLUSH_AND_INV_CB_META;
1106         }
1107         if (rctx->framebuffer.state.zsbuf) {
1108                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1109                 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1110
1111                 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1112                 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1113                         rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1114                 }
1115         }
1116
1117         /* Set the new state. */
1118         util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1119
1120         rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1121         rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1122                                util_format_is_pure_integer(state->cbufs[0]->format);
1123         rctx->framebuffer.compressed_cb_mask = 0;
1124         rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1125                                             state->cbufs[0] && state->cbufs[1] &&
1126                                             state->cbufs[0]->texture->nr_samples > 1 &&
1127                                             state->cbufs[1]->texture->nr_samples <= 1;
1128         rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1129
1130         /* Colorbuffers. */
1131         for (i = 0; i < state->nr_cbufs; i++) {
1132                 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1133                 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1134                                          rctx->framebuffer.is_msaa_resolve &&
1135                                          i == 1;
1136
1137                 surf = (struct r600_surface*)state->cbufs[i];
1138                 if (!surf)
1139                         continue;
1140
1141                 rtex = (struct r600_texture*)surf->base.texture;
1142                 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1143
1144                 if (!surf->color_initialized || force_cmask_fmask) {
1145                         r600_init_color_surface(rctx, surf, force_cmask_fmask);
1146                         if (force_cmask_fmask) {
1147                                 /* re-initialize later without compression */
1148                                 surf->color_initialized = false;
1149                         }
1150                 }
1151
1152                 if (!surf->export_16bpc) {
1153                         rctx->framebuffer.export_16bpc = false;
1154                 }
1155
1156                 if (rtex->fmask.size && rtex->cmask.size) {
1157                         rctx->framebuffer.compressed_cb_mask |= 1 << i;
1158                 }
1159         }
1160
1161         /* Update alpha-test state dependencies.
1162          * Alpha-test is done on the first colorbuffer only. */
1163         if (state->nr_cbufs) {
1164                 bool alphatest_bypass = false;
1165
1166                 surf = (struct r600_surface*)state->cbufs[0];
1167                 if (surf) {
1168                         alphatest_bypass = surf->alphatest_bypass;
1169                 }
1170
1171                 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1172                         rctx->alphatest_state.bypass = alphatest_bypass;
1173                         r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1174                 }
1175         }
1176
1177         /* ZS buffer. */
1178         if (state->zsbuf) {
1179                 surf = (struct r600_surface*)state->zsbuf;
1180
1181                 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1182
1183                 if (!surf->depth_initialized) {
1184                         r600_init_depth_surface(rctx, surf);
1185                 }
1186
1187                 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1188                         rctx->poly_offset_state.zs_format = state->zsbuf->format;
1189                         r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1190                 }
1191
1192                 if (rctx->db_state.rsurf != surf) {
1193                         rctx->db_state.rsurf = surf;
1194                         r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1195                         r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1196                 }
1197         } else if (rctx->db_state.rsurf) {
1198                 rctx->db_state.rsurf = NULL;
1199                 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1200                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1201         }
1202
1203         if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1204                 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1205                 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1206         }
1207
1208         if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1209                 rctx->alphatest_state.bypass = false;
1210                 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1211         }
1212
1213         /* Calculate the CS size. */
1214         rctx->framebuffer.atom.num_dw =
1215                 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1216
1217         if (rctx->framebuffer.state.nr_cbufs) {
1218                 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1219                 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1220         }
1221         if (rctx->framebuffer.state.zsbuf) {
1222                 rctx->framebuffer.atom.num_dw += 16;
1223         } else if (rctx->screen->b.info.drm_minor >= 18) {
1224                 rctx->framebuffer.atom.num_dw += 3;
1225         }
1226         if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1227                 rctx->framebuffer.atom.num_dw += 2;
1228         }
1229
1230         r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1231
1232         r600_set_sample_locations_constant_buffer(rctx);
1233 }
1234
1235 static uint32_t sample_locs_2x[] = {
1236         FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1237         FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1238 };
1239 static unsigned max_dist_2x = 4;
1240
1241 static uint32_t sample_locs_4x[] = {
1242         FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1243         FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1244 };
1245 static unsigned max_dist_4x = 6;
1246 static uint32_t sample_locs_8x[] = {
1247         FILL_SREG(-1,  1,  1,  5,  3, -5,  5,  3),
1248         FILL_SREG(-7, -1, -3, -7,  7, -3, -5,  7),
1249 };
1250 static unsigned max_dist_8x = 7;
1251
1252 static void r600_get_sample_position(struct pipe_context *ctx,
1253                                      unsigned sample_count,
1254                                      unsigned sample_index,
1255                                      float *out_value)
1256 {
1257         int offset, index;
1258         struct {
1259                 int idx:4;
1260         } val;
1261         switch (sample_count) {
1262         case 1:
1263         default:
1264                 out_value[0] = out_value[1] = 0.5;
1265                 break;
1266         case 2:
1267                 offset = 4 * (sample_index * 2);
1268                 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1269                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1270                 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1271                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1272                 break;
1273         case 4:
1274                 offset = 4 * (sample_index * 2);
1275                 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1276                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1277                 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1278                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1279                 break;
1280         case 8:
1281                 offset = 4 * (sample_index % 4 * 2);
1282                 index = (sample_index / 4);
1283                 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1284                 out_value[0] = (float)(val.idx + 8) / 16.0f;
1285                 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1286                 out_value[1] = (float)(val.idx + 8) / 16.0f;
1287                 break;
1288         }
1289 }
1290
1291 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1292 {
1293         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1294         unsigned max_dist = 0;
1295
1296         if (rctx->b.family == CHIP_R600) {
1297                 switch (nr_samples) {
1298                 default:
1299                         nr_samples = 0;
1300                         break;
1301                 case 2:
1302                         radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1303                         max_dist = max_dist_2x;
1304                         break;
1305                 case 4:
1306                         radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1307                         max_dist = max_dist_4x;
1308                         break;
1309                 case 8:
1310                         radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1311                         radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1312                         radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1313                         max_dist = max_dist_8x;
1314                         break;
1315                 }
1316         } else {
1317                 switch (nr_samples) {
1318                 default:
1319                         radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1320                         radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1321                         radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1322                         nr_samples = 0;
1323                         break;
1324                 case 2:
1325                         radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1326                         radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1327                         radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1328                         max_dist = max_dist_2x;
1329                         break;
1330                 case 4:
1331                         radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1332                         radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1333                         radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1334                         max_dist = max_dist_4x;
1335                         break;
1336                 case 8:
1337                         radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1338                         radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1339                         radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1340                         max_dist = max_dist_8x;
1341                         break;
1342                 }
1343         }
1344
1345         if (nr_samples > 1) {
1346                 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1347                 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1348                                      S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1349                 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1350                                      S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1351         } else {
1352                 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1353                 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1354                 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1355         }
1356 }
1357
1358 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1359 {
1360         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1361         struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1362         unsigned nr_cbufs = state->nr_cbufs;
1363         struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1364         unsigned i, sbu = 0;
1365
1366         /* Colorbuffers. */
1367         radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1368         for (i = 0; i < nr_cbufs; i++) {
1369                 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1370         }
1371         /* set CB_COLOR1_INFO for possible dual-src blending */
1372         if (i == 1 && cb[0]) {
1373                 radeon_emit(cs, cb[0]->cb_color_info);
1374                 i++;
1375         }
1376         for (; i < 8; i++) {
1377                 radeon_emit(cs, 0);
1378         }
1379
1380         if (nr_cbufs) {
1381                 for (i = 0; i < nr_cbufs; i++) {
1382                         unsigned reloc;
1383
1384                         if (!cb[i])
1385                                 continue;
1386
1387                         /* COLOR_BASE */
1388                         radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1389
1390                         reloc = radeon_add_to_buffer_list(&rctx->b,
1391                                                       &rctx->b.gfx,
1392                                                       (struct r600_resource*)cb[i]->base.texture,
1393                                                       RADEON_USAGE_READWRITE,
1394                                                       cb[i]->base.texture->nr_samples > 1 ?
1395                                                               RADEON_PRIO_COLOR_BUFFER_MSAA :
1396                                                               RADEON_PRIO_COLOR_BUFFER);
1397                         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1398                         radeon_emit(cs, reloc);
1399
1400                         /* FMASK */
1401                         radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1402
1403                         reloc = radeon_add_to_buffer_list(&rctx->b,
1404                                                       &rctx->b.gfx,
1405                                                       cb[i]->cb_buffer_fmask,
1406                                                       RADEON_USAGE_READWRITE,
1407                                                       cb[i]->base.texture->nr_samples > 1 ?
1408                                                               RADEON_PRIO_COLOR_BUFFER_MSAA :
1409                                                               RADEON_PRIO_COLOR_BUFFER);
1410                         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1411                         radeon_emit(cs, reloc);
1412
1413                         /* CMASK */
1414                         radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1415
1416                         reloc = radeon_add_to_buffer_list(&rctx->b,
1417                                                       &rctx->b.gfx,
1418                                                       cb[i]->cb_buffer_cmask,
1419                                                       RADEON_USAGE_READWRITE,
1420                                                       cb[i]->base.texture->nr_samples > 1 ?
1421                                                               RADEON_PRIO_COLOR_BUFFER_MSAA :
1422                                                               RADEON_PRIO_COLOR_BUFFER);
1423                         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1424                         radeon_emit(cs, reloc);
1425                 }
1426
1427                 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1428                 for (i = 0; i < nr_cbufs; i++) {
1429                         radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1430                 }
1431
1432                 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1433                 for (i = 0; i < nr_cbufs; i++) {
1434                         radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1435                 }
1436
1437                 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1438                 for (i = 0; i < nr_cbufs; i++) {
1439                         radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1440                 }
1441
1442                 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1443         }
1444
1445         /* SURFACE_BASE_UPDATE */
1446         if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1447                 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1448                 radeon_emit(cs, sbu);
1449                 sbu = 0;
1450         }
1451
1452         /* Zbuffer. */
1453         if (state->zsbuf) {
1454                 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1455                 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1456                                                        &rctx->b.gfx,
1457                                                        (struct r600_resource*)state->zsbuf->texture,
1458                                                        RADEON_USAGE_READWRITE,
1459                                                        surf->base.texture->nr_samples > 1 ?
1460                                                                RADEON_PRIO_DEPTH_BUFFER_MSAA :
1461                                                                RADEON_PRIO_DEPTH_BUFFER);
1462
1463                 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1464                                        surf->pa_su_poly_offset_db_fmt_cntl);
1465
1466                 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1467                 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1468                 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1469                 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1470                 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1471                 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1472
1473                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1474                 radeon_emit(cs, reloc);
1475
1476                 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1477
1478                 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1479         } else if (rctx->screen->b.info.drm_minor >= 18) {
1480                 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1481                  * Older kernels are out of luck. */
1482                 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1483         }
1484
1485         /* SURFACE_BASE_UPDATE */
1486         if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1487                 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1488                 radeon_emit(cs, sbu);
1489                 sbu = 0;
1490         }
1491
1492         /* Framebuffer dimensions. */
1493         radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1494         radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1495                              S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1496         radeon_emit(cs, S_028244_BR_X(state->width) |
1497                              S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1498
1499         if (rctx->framebuffer.is_msaa_resolve) {
1500                 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1501         } else {
1502                 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1503                  * will assure that the alpha-test will work even if there is
1504                  * no colorbuffer bound. */
1505                 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1506                                        (1ull << MAX2(nr_cbufs, 1)) - 1);
1507         }
1508
1509         r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1510 }
1511
1512 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1513 {
1514         struct r600_context *rctx = (struct r600_context *)ctx;
1515
1516         if (rctx->ps_iter_samples == min_samples)
1517                 return;
1518
1519         rctx->ps_iter_samples = min_samples;
1520         if (rctx->framebuffer.nr_samples > 1) {
1521                 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1522                 if (rctx->b.chip_class == R600)
1523                         r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1524         }
1525 }
1526
1527 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1528 {
1529         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1530         struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1531
1532         if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1533                 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1534                 if (rctx->b.chip_class == R600) {
1535                         radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1536                         radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1537                 } else {
1538                         radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1539                         radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1540                 }
1541                 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1542         } else {
1543                 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1544                 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1545                 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1546
1547                 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1548                 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1549                 /* Always enable the first color output to make sure alpha-test works even without one. */
1550                 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1551                 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1552                                        a->cb_color_control |
1553                                        S_028808_MULTIWRITE_ENABLE(multiwrite));
1554         }
1555 }
1556
1557 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1558 {
1559         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1560         struct r600_db_state *a = (struct r600_db_state*)atom;
1561
1562         if (a->rsurf && a->rsurf->db_htile_surface) {
1563                 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1564                 unsigned reloc_idx;
1565
1566                 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1567                 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1568                 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1569                 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1570                                                   RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1571                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1572                 cs->buf[cs->cdw++] = reloc_idx;
1573         } else {
1574                 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1575         }
1576 }
1577
1578 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1579 {
1580         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1581         struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1582         unsigned db_render_control = 0;
1583         unsigned db_render_override =
1584                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1585                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1586
1587         if (rctx->b.chip_class >= R700) {
1588                 switch (a->ps_conservative_z) {
1589                 default: /* fall through */
1590                 case TGSI_FS_DEPTH_LAYOUT_ANY:
1591                         db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1592                         break;
1593                 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1594                         db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1595                         break;
1596                 case TGSI_FS_DEPTH_LAYOUT_LESS:
1597                         db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1598                         break;
1599                 }
1600         }
1601
1602         if (rctx->b.num_occlusion_queries > 0 &&
1603             !a->occlusion_queries_disabled) {
1604                 if (rctx->b.chip_class >= R700) {
1605                         db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1606                 }
1607                 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1608         } else {
1609                 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1610         }
1611
1612         if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1613                 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1614                 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1615                 /* This is to fix a lockup when hyperz and alpha test are enabled at
1616                  * the same time somehow GPU get confuse on which order to pick for
1617                  * z test
1618                  */
1619                 if (rctx->alphatest_state.sx_alpha_test_control) {
1620                         db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1621                 }
1622         } else {
1623                 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1624         }
1625         if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1626                 /* sample shading and hyperz causes lockups on R6xx chips */
1627                 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1628         }
1629         if (a->flush_depthstencil_through_cb) {
1630                 assert(a->copy_depth || a->copy_stencil);
1631
1632                 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1633                                      S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1634                                      S_028D0C_COPY_CENTROID(1) |
1635                                      S_028D0C_COPY_SAMPLE(a->copy_sample);
1636
1637                 if (rctx->b.chip_class == R600)
1638                         db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1639
1640                 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1641                     rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1642                         db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1643         } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1644                 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1645                                      S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1646                 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1647         }
1648         if (a->htile_clear) {
1649                 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1650         }
1651
1652         /* RV770 workaround for a hang with 8x MSAA. */
1653         if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1654                 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1655         }
1656
1657         radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1658         radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1659         radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1660         radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1661 }
1662
1663 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1664 {
1665         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1666         struct r600_config_state *a = (struct r600_config_state*)atom;
1667
1668         radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1669         radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1670 }
1671
1672 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1673 {
1674         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1675         uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1676
1677         while (dirty_mask) {
1678                 struct pipe_vertex_buffer *vb;
1679                 struct r600_resource *rbuffer;
1680                 unsigned offset;
1681                 unsigned buffer_index = u_bit_scan(&dirty_mask);
1682
1683                 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1684                 rbuffer = (struct r600_resource*)vb->buffer;
1685                 assert(rbuffer);
1686
1687                 offset = vb->buffer_offset;
1688
1689                 /* fetch resources start at index 320 (OFFSET_FS) */
1690                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1691                 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1692                 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1693                 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1694                 radeon_emit(cs, /* RESOURCEi_WORD2 */
1695                                  S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1696                                  S_038008_STRIDE(vb->stride));
1697                 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1698                 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1699                 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1700                 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1701
1702                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1703                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1704                                                       RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1705         }
1706 }
1707
1708 static void r600_emit_constant_buffers(struct r600_context *rctx,
1709                                        struct r600_constbuf_state *state,
1710                                        unsigned buffer_id_base,
1711                                        unsigned reg_alu_constbuf_size,
1712                                        unsigned reg_alu_const_cache)
1713 {
1714         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1715         uint32_t dirty_mask = state->dirty_mask;
1716
1717         while (dirty_mask) {
1718                 struct pipe_constant_buffer *cb;
1719                 struct r600_resource *rbuffer;
1720                 unsigned offset;
1721                 unsigned buffer_index = ffs(dirty_mask) - 1;
1722                 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1723                 cb = &state->cb[buffer_index];
1724                 rbuffer = (struct r600_resource*)cb->buffer;
1725                 assert(rbuffer);
1726
1727                 offset = cb->buffer_offset;
1728
1729                 if (!gs_ring_buffer) {
1730                         radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1731                                                DIV_ROUND_UP(cb->buffer_size, 256));
1732                         radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1733                 }
1734
1735                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1736                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1737                                                       RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1738
1739                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1740                 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1741                 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1742                 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1743                 radeon_emit(cs, /* RESOURCEi_WORD2 */
1744                             S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1745                             S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1746                 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1747                 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1748                 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1749                 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1750
1751                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1752                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1753                                                       RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1754
1755                 dirty_mask &= ~(1 << buffer_index);
1756         }
1757         state->dirty_mask = 0;
1758 }
1759
1760 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1761 {
1762         r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1763                                    R600_FETCH_CONSTANTS_OFFSET_VS,
1764                                    R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1765                                    R_028980_ALU_CONST_CACHE_VS_0);
1766 }
1767
1768 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1769 {
1770         r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1771                                    R600_FETCH_CONSTANTS_OFFSET_GS,
1772                                    R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1773                                    R_0289C0_ALU_CONST_CACHE_GS_0);
1774 }
1775
1776 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1777 {
1778         r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1779                                    R600_FETCH_CONSTANTS_OFFSET_PS,
1780                                    R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1781                                    R_028940_ALU_CONST_CACHE_PS_0);
1782 }
1783
1784 static void r600_emit_sampler_views(struct r600_context *rctx,
1785                                     struct r600_samplerview_state *state,
1786                                     unsigned resource_id_base)
1787 {
1788         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1789         uint32_t dirty_mask = state->dirty_mask;
1790
1791         while (dirty_mask) {
1792                 struct r600_pipe_sampler_view *rview;
1793                 unsigned resource_index = u_bit_scan(&dirty_mask);
1794                 unsigned reloc;
1795
1796                 rview = state->views[resource_index];
1797                 assert(rview);
1798
1799                 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1800                 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1801                 radeon_emit_array(cs, rview->tex_resource_words, 7);
1802
1803                 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1804                                               RADEON_USAGE_READ,
1805                                               r600_get_sampler_view_priority(rview->tex_resource));
1806                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1807                 radeon_emit(cs, reloc);
1808                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1809                 radeon_emit(cs, reloc);
1810         }
1811         state->dirty_mask = 0;
1812 }
1813
1814
1815 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1816 {
1817         r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1818 }
1819
1820 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1821 {
1822         r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1823 }
1824
1825 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1826 {
1827         r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1828 }
1829
1830 static void r600_emit_sampler_states(struct r600_context *rctx,
1831                                 struct r600_textures_info *texinfo,
1832                                 unsigned resource_id_base,
1833                                 unsigned border_color_reg)
1834 {
1835         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1836         uint32_t dirty_mask = texinfo->states.dirty_mask;
1837
1838         while (dirty_mask) {
1839                 struct r600_pipe_sampler_state *rstate;
1840                 struct r600_pipe_sampler_view *rview;
1841                 unsigned i = u_bit_scan(&dirty_mask);
1842
1843                 rstate = texinfo->states.states[i];
1844                 assert(rstate);
1845                 rview = texinfo->views.views[i];
1846
1847                 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1848                  * filtering between layers.
1849                  * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1850                  */
1851                 if (rview) {
1852                         enum pipe_texture_target target = rview->base.texture->target;
1853                         if (target == PIPE_TEXTURE_1D_ARRAY ||
1854                             target == PIPE_TEXTURE_2D_ARRAY) {
1855                                 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1856                                 texinfo->is_array_sampler[i] = true;
1857                         } else {
1858                                 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1859                                 texinfo->is_array_sampler[i] = false;
1860                         }
1861                 }
1862
1863                 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1864                 radeon_emit(cs, (resource_id_base + i) * 3);
1865                 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1866
1867                 if (rstate->border_color_use) {
1868                         unsigned offset;
1869
1870                         offset = border_color_reg;
1871                         offset += i * 16;
1872                         radeon_set_config_reg_seq(cs, offset, 4);
1873                         radeon_emit_array(cs, rstate->border_color.ui, 4);
1874                 }
1875         }
1876         texinfo->states.dirty_mask = 0;
1877 }
1878
1879 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1880 {
1881         r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1882 }
1883
1884 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1885 {
1886         r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1887 }
1888
1889 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1890 {
1891         r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1892 }
1893
1894 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1895 {
1896         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1897         unsigned tmp;
1898
1899         tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1900                 S_009508_SYNC_GRADIENT(1) |
1901                 S_009508_SYNC_WALKER(1) |
1902                 S_009508_SYNC_ALIGNER(1);
1903         if (!rctx->seamless_cube_map.enabled) {
1904                 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1905         }
1906         radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1907 }
1908
1909 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1910 {
1911         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1912         uint8_t mask = s->sample_mask;
1913
1914         radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1915                                mask | (mask << 8) | (mask << 16) | (mask << 24));
1916 }
1917
1918 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1919 {
1920         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1921         struct r600_cso_state *state = (struct r600_cso_state*)a;
1922         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1923
1924         radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1925         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1926         radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1927                                                   RADEON_USAGE_READ,
1928                                                   RADEON_PRIO_INTERNAL_SHADER));
1929 }
1930
1931 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1932 {
1933         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1934         struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1935
1936         uint32_t v2 = 0, primid = 0;
1937
1938         if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1939                 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1940                 primid = 1;
1941         }
1942
1943         if (state->geom_enable) {
1944                 uint32_t cut_val;
1945
1946                 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1947                         cut_val = V_028A40_GS_CUT_128;
1948                 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1949                         cut_val = V_028A40_GS_CUT_256;
1950                 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1951                         cut_val = V_028A40_GS_CUT_512;
1952                 else
1953                         cut_val = V_028A40_GS_CUT_1024;
1954
1955                 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1956                         S_028A40_CUT_MODE(cut_val);
1957
1958                 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1959                         primid = 1;
1960         }
1961
1962         radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1963         radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1964 }
1965
1966 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1967 {
1968         struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1969         struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1970         struct r600_resource *rbuffer;
1971
1972         radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1973         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1974         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1975
1976         if (state->enable) {
1977                 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1978                 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1979                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1980                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1981                                                       RADEON_USAGE_READWRITE,
1982                                                       RADEON_PRIO_RINGS_STREAMOUT));
1983                 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1984                                 state->esgs_ring.buffer_size >> 8);
1985
1986                 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1987                 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1988                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1989                 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1990                                                       RADEON_USAGE_READWRITE,
1991                                                       RADEON_PRIO_RINGS_STREAMOUT));
1992                 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1993                                 state->gsvs_ring.buffer_size >> 8);
1994         } else {
1995                 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1996                 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1997         }
1998
1999         radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2000         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2001         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2002 }
2003
2004 /* Adjust GPR allocation on R6xx/R7xx */
2005 bool r600_adjust_gprs(struct r600_context *rctx)
2006 {
2007         unsigned num_gprs[R600_NUM_HW_STAGES];
2008         unsigned new_gprs[R600_NUM_HW_STAGES];
2009         unsigned cur_gprs[R600_NUM_HW_STAGES];
2010         unsigned def_gprs[R600_NUM_HW_STAGES];
2011         unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2012         unsigned max_gprs;
2013         unsigned tmp, tmp2;
2014         unsigned i;
2015         bool need_recalc = false, use_default = true;
2016
2017         /* hardware will reserve twice num_clause_temp_gprs */
2018         max_gprs = def_num_clause_temp_gprs * 2;
2019         for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2020                 def_gprs[i] = rctx->default_gprs[i];
2021                 max_gprs += def_gprs[i];
2022         }
2023
2024         cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2025         cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2026         cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2027         cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2028
2029         num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2030         if (rctx->gs_shader) {
2031                 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2032                 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2033                 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2034         } else {
2035                 num_gprs[R600_HW_STAGE_ES] = 0;
2036                 num_gprs[R600_HW_STAGE_GS] = 0;
2037                 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2038         }
2039
2040         for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2041                 new_gprs[i] = num_gprs[i];
2042                 if (new_gprs[i] > cur_gprs[i])
2043                         need_recalc = true;
2044                 if (new_gprs[i] > def_gprs[i])
2045                         use_default = false;
2046         }
2047
2048         /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2049         if (!need_recalc)
2050                 return true;
2051
2052         /* try to use switch back to default */
2053         if (!use_default) {
2054                 /* always privilege vs stage so that at worst we have the
2055                  * pixel stage producing wrong output (not the vertex
2056                  * stage) */
2057                 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2058                 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2059                         new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2060         } else {
2061                 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2062                         new_gprs[i] = def_gprs[i];
2063         }
2064
2065         /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2066          * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2067          * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2068          * it will lockup. So in this case just discard the draw command
2069          * and don't change the current gprs repartitions.
2070          */
2071         for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2072                 if (num_gprs[i] > new_gprs[i]) {
2073                         R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2074                                  "for a combined maximum of %d\n",
2075                                  num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2076                         return false;
2077                 }
2078         }
2079
2080         /* in some case we endup recomputing the current value */
2081         tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2082                 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2083                 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2084
2085         tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2086                 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2087         if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2088                 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2089                 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2090                 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2091                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2092         }
2093         return true;
2094 }
2095
2096 void r600_init_atom_start_cs(struct r600_context *rctx)
2097 {
2098         int ps_prio;
2099         int vs_prio;
2100         int gs_prio;
2101         int es_prio;
2102         int num_ps_gprs;
2103         int num_vs_gprs;
2104         int num_gs_gprs;
2105         int num_es_gprs;
2106         int num_temp_gprs;
2107         int num_ps_threads;
2108         int num_vs_threads;
2109         int num_gs_threads;
2110         int num_es_threads;
2111         int num_ps_stack_entries;
2112         int num_vs_stack_entries;
2113         int num_gs_stack_entries;
2114         int num_es_stack_entries;
2115         enum radeon_family family;
2116         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2117         uint32_t tmp, i;
2118
2119         r600_init_command_buffer(cb, 256);
2120
2121         /* R6xx requires this packet at the start of each command buffer */
2122         if (rctx->b.chip_class == R600) {
2123                 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2124                 r600_store_value(cb, 0);
2125         }
2126         /* All asics require this one */
2127         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2128         r600_store_value(cb, 0x80000000);
2129         r600_store_value(cb, 0x80000000);
2130
2131         /* We're setting config registers here. */
2132         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2133         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2134
2135         /* This enables pipeline stat & streamout queries.
2136          * They are only disabled by blits.
2137          */
2138         r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2139         r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2140
2141         family = rctx->b.family;
2142         ps_prio = 0;
2143         vs_prio = 1;
2144         gs_prio = 2;
2145         es_prio = 3;
2146         switch (family) {
2147         case CHIP_R600:
2148                 num_ps_gprs = 192;
2149                 num_vs_gprs = 56;
2150                 num_temp_gprs = 4;
2151                 num_gs_gprs = 0;
2152                 num_es_gprs = 0;
2153                 num_ps_threads = 136;
2154                 num_vs_threads = 48;
2155                 num_gs_threads = 4;
2156                 num_es_threads = 4;
2157                 num_ps_stack_entries = 128;
2158                 num_vs_stack_entries = 128;
2159                 num_gs_stack_entries = 0;
2160                 num_es_stack_entries = 0;
2161                 break;
2162         case CHIP_RV630:
2163         case CHIP_RV635:
2164                 num_ps_gprs = 84;
2165                 num_vs_gprs = 36;
2166                 num_temp_gprs = 4;
2167                 num_gs_gprs = 0;
2168                 num_es_gprs = 0;
2169                 num_ps_threads = 144;
2170                 num_vs_threads = 40;
2171                 num_gs_threads = 4;
2172                 num_es_threads = 4;
2173                 num_ps_stack_entries = 40;
2174                 num_vs_stack_entries = 40;
2175                 num_gs_stack_entries = 32;
2176                 num_es_stack_entries = 16;
2177                 break;
2178         case CHIP_RV610:
2179         case CHIP_RV620:
2180         case CHIP_RS780:
2181         case CHIP_RS880:
2182         default:
2183                 num_ps_gprs = 84;
2184                 num_vs_gprs = 36;
2185                 num_temp_gprs = 4;
2186                 num_gs_gprs = 0;
2187                 num_es_gprs = 0;
2188                 /* use limits 40 VS and at least 16 ES/GS */
2189                 num_ps_threads = 120;
2190                 num_vs_threads = 40;
2191                 num_gs_threads = 16;
2192                 num_es_threads = 16;
2193                 num_ps_stack_entries = 40;
2194                 num_vs_stack_entries = 40;
2195                 num_gs_stack_entries = 32;
2196                 num_es_stack_entries = 16;
2197                 break;
2198         case CHIP_RV670:
2199                 num_ps_gprs = 144;
2200                 num_vs_gprs = 40;
2201                 num_temp_gprs = 4;
2202                 num_gs_gprs = 0;
2203                 num_es_gprs = 0;
2204                 num_ps_threads = 136;
2205                 num_vs_threads = 48;
2206                 num_gs_threads = 4;
2207                 num_es_threads = 4;
2208                 num_ps_stack_entries = 40;
2209                 num_vs_stack_entries = 40;
2210                 num_gs_stack_entries = 32;
2211                 num_es_stack_entries = 16;
2212                 break;
2213         case CHIP_RV770:
2214                 num_ps_gprs = 130;
2215                 num_vs_gprs = 56;
2216                 num_temp_gprs = 4;
2217                 num_gs_gprs = 31;
2218                 num_es_gprs = 31;
2219                 num_ps_threads = 180;
2220                 num_vs_threads = 60;
2221                 num_gs_threads = 4;
2222                 num_es_threads = 4;
2223                 num_ps_stack_entries = 128;
2224                 num_vs_stack_entries = 128;
2225                 num_gs_stack_entries = 128;
2226                 num_es_stack_entries = 128;
2227                 break;
2228         case CHIP_RV730:
2229         case CHIP_RV740:
2230                 num_ps_gprs = 84;
2231                 num_vs_gprs = 36;
2232                 num_temp_gprs = 4;
2233                 num_gs_gprs = 0;
2234                 num_es_gprs = 0;
2235                 num_ps_threads = 180;
2236                 num_vs_threads = 60;
2237                 num_gs_threads = 4;
2238                 num_es_threads = 4;
2239                 num_ps_stack_entries = 128;
2240                 num_vs_stack_entries = 128;
2241                 num_gs_stack_entries = 0;
2242                 num_es_stack_entries = 0;
2243                 break;
2244         case CHIP_RV710:
2245                 num_ps_gprs = 192;
2246                 num_vs_gprs = 56;
2247                 num_temp_gprs = 4;
2248                 num_gs_gprs = 0;
2249                 num_es_gprs = 0;
2250                 num_ps_threads = 136;
2251                 num_vs_threads = 48;
2252                 num_gs_threads = 4;
2253                 num_es_threads = 4;
2254                 num_ps_stack_entries = 128;
2255                 num_vs_stack_entries = 128;
2256                 num_gs_stack_entries = 0;
2257                 num_es_stack_entries = 0;
2258                 break;
2259         }
2260
2261         rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2262         rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2263         rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2264         rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2265
2266         rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2267
2268         /* SQ_CONFIG */
2269         tmp = 0;
2270         switch (family) {
2271         case CHIP_RV610:
2272         case CHIP_RV620:
2273         case CHIP_RS780:
2274         case CHIP_RS880:
2275         case CHIP_RV710:
2276                 break;
2277         default:
2278                 tmp |= S_008C00_VC_ENABLE(1);
2279                 break;
2280         }
2281         tmp |= S_008C00_DX9_CONSTS(0);
2282         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2283         tmp |= S_008C00_PS_PRIO(ps_prio);
2284         tmp |= S_008C00_VS_PRIO(vs_prio);
2285         tmp |= S_008C00_GS_PRIO(gs_prio);
2286         tmp |= S_008C00_ES_PRIO(es_prio);
2287         r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2288
2289         /* SQ_GPR_RESOURCE_MGMT_2 */
2290         tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2291         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2292         r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2293         r600_store_value(cb, tmp);
2294
2295         /* SQ_THREAD_RESOURCE_MGMT */
2296         tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2297         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2298         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2299         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2300         r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2301
2302         /* SQ_STACK_RESOURCE_MGMT_1 */
2303         tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2304         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2305         r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2306
2307         /* SQ_STACK_RESOURCE_MGMT_2 */
2308         tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2309         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2310         r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2311
2312         r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2313
2314         if (rctx->b.chip_class >= R700) {
2315                 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2316                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2317                 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2318                 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2319                 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2320         } else {
2321                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2322                 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2323                 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2324                 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2325         }
2326         r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2327         r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2328         r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2329         r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2330         r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2331         r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2332         r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2333         r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2334         r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2335         r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2336
2337         /* to avoid GPU doing any preloading of constant from random address */
2338         r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2339         for (i = 0; i < 16; i++)
2340                 r600_store_value(cb, 0);
2341
2342         r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2343         for (i = 0; i < 16; i++)
2344                 r600_store_value(cb, 0);
2345
2346         r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2347         for (i = 0; i < 16; i++)
2348                 r600_store_value(cb, 0);
2349
2350         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2351         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2352         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2353         r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2354         r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2355         r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2356         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2357         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2358         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2359         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2360         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2361         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2362         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2363         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2364
2365         r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2366         r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2367         r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2368
2369         r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2370         r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2371         r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2372
2373         r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2374
2375         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2376
2377         r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2378
2379         r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2380         r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2381         r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2382         r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2383
2384         r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2385         r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2386         r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2387         r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2388
2389         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2390         r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2391
2392         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2393         for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2394                 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2395                 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2396         }
2397
2398         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2399         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2400
2401         if (rctx->b.chip_class >= R700) {
2402                 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2403         }
2404
2405         r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2406         r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2407         r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2408         r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2409         r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2410
2411         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2412         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2413         r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2414
2415         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2416         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2417         r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2418
2419         r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2420         r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2421         r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2422         r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2423         r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2424         r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2425
2426         r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2427
2428         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2429         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2430         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2431
2432         r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2433
2434         if (rctx->b.chip_class == R700)
2435                 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2436         if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2437                 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2438
2439         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2440         if (rctx->screen->b.has_streamout) {
2441                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2442         }
2443
2444         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2445         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2446         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2447 }
2448
2449 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2450 {
2451         struct r600_context *rctx = (struct r600_context *)ctx;
2452         struct r600_command_buffer *cb = &shader->command_buffer;
2453         struct r600_shader *rshader = &shader->shader;
2454         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2455         int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2456         unsigned tmp, sid, ufi = 0;
2457         int need_linear = 0;
2458         unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2459         unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2460
2461         if (!cb->buf) {
2462                 r600_init_command_buffer(cb, 64);
2463         } else {
2464                 cb->num_dw = 0;
2465         }
2466
2467         r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2468         for (i = 0; i < rshader->ninput; i++) {
2469                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2470                         pos_index = i;
2471                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2472                         face_index = i;
2473                 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2474                         fixed_pt_position_index = i;
2475
2476                 sid = rshader->input[i].spi_sid;
2477
2478                 tmp = S_028644_SEMANTIC(sid);
2479
2480                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2481                         rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2482                         (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2483                                 rctx->rasterizer && rctx->rasterizer->flatshade))
2484                         tmp |= S_028644_FLAT_SHADE(1);
2485
2486                 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2487                     sprite_coord_enable & (1 << rshader->input[i].sid)) {
2488                         tmp |= S_028644_PT_SPRITE_TEX(1);
2489                 }
2490
2491                 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2492                         tmp |= S_028644_SEL_CENTROID(1);
2493
2494                 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2495                         tmp |= S_028644_SEL_SAMPLE(1);
2496
2497                 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2498                         need_linear = 1;
2499                         tmp |= S_028644_SEL_LINEAR(1);
2500                 }
2501
2502                 r600_store_value(cb, tmp);
2503         }
2504
2505         db_shader_control = 0;
2506         for (i = 0; i < rshader->noutput; i++) {
2507                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2508                         z_export = 1;
2509                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2510                         stencil_export = 1;
2511                 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2512                         rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2513                         mask_export = 1;
2514         }
2515         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2516         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2517         db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2518         if (rshader->uses_kill)
2519                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2520
2521         exports_ps = 0;
2522         for (i = 0; i < rshader->noutput; i++) {
2523                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2524                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2525                     rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2526                         exports_ps |= 1;
2527                 }
2528         }
2529         num_cout = rshader->nr_ps_color_exports;
2530         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2531         if (!exports_ps) {
2532                 /* always at least export 1 component per pixel */
2533                 exports_ps = 2;
2534         }
2535
2536         shader->nr_ps_color_outputs = num_cout;
2537
2538         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2539                                 S_0286CC_PERSP_GRADIENT_ENA(1)|
2540                                 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2541         spi_input_z = 0;
2542         if (pos_index != -1) {
2543                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2544                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2545                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2546                                         S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2547                                         S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2548                 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2549         }
2550
2551         spi_ps_in_control_1 = 0;
2552         if (face_index != -1) {
2553                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2554                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2555         }
2556         if (fixed_pt_position_index != -1) {
2557                 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2558                         S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2559         }
2560
2561         /* HW bug in original R600 */
2562         if (rctx->b.family == CHIP_R600)
2563                 ufi = 1;
2564
2565         r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2566         r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2567         r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2568
2569         r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2570
2571         r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2572         r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2573                          S_028850_NUM_GPRS(rshader->bc.ngpr) |
2574                          S_028850_STACK_SIZE(rshader->bc.nstack) |
2575                          S_028850_UNCACHED_FIRST_INST(ufi));
2576         r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2577
2578         r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2579         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2580
2581         /* only set some bits here, the other bits are set in the dsa state */
2582         shader->db_shader_control = db_shader_control;
2583         shader->ps_depth_export = z_export | stencil_export | mask_export;
2584
2585         shader->sprite_coord_enable = sprite_coord_enable;
2586         if (rctx->rasterizer)
2587                 shader->flatshade = rctx->rasterizer->flatshade;
2588 }
2589
2590 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2591 {
2592         struct r600_command_buffer *cb = &shader->command_buffer;
2593         struct r600_shader *rshader = &shader->shader;
2594         unsigned spi_vs_out_id[10] = {};
2595         unsigned i, tmp, nparams = 0;
2596
2597         for (i = 0; i < rshader->noutput; i++) {
2598                 if (rshader->output[i].spi_sid) {
2599                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2600                         spi_vs_out_id[nparams / 4] |= tmp;
2601                         nparams++;
2602                 }
2603         }
2604
2605         r600_init_command_buffer(cb, 32);
2606
2607         r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2608         for (i = 0; i < 10; i++) {
2609                 r600_store_value(cb, spi_vs_out_id[i]);
2610         }
2611
2612         /* Certain attributes (position, psize, etc.) don't count as params.
2613          * VS is required to export at least one param and r600_shader_from_tgsi()
2614          * takes care of adding a dummy export.
2615          */
2616         if (nparams < 1)
2617                 nparams = 1;
2618
2619         r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2620                                S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2621         r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2622                                S_028868_NUM_GPRS(rshader->bc.ngpr) |
2623                                S_028868_STACK_SIZE(rshader->bc.nstack));
2624         if (rshader->vs_position_window_space) {
2625                 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2626                         S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2627         } else {
2628                 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2629                         S_028818_VTX_W0_FMT(1) |
2630                         S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2631                         S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2632                         S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2633
2634         }
2635         r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2636         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2637
2638         shader->pa_cl_vs_out_cntl =
2639                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2640                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2641                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2642                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2643                 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2644                 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2645                 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2646 }
2647
2648 #define RV610_GSVS_ALIGN 32
2649 #define R600_GSVS_ALIGN 16
2650
2651 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2652 {
2653         struct r600_context *rctx = (struct r600_context *)ctx;
2654         struct r600_command_buffer *cb = &shader->command_buffer;
2655         struct r600_shader *rshader = &shader->shader;
2656         struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2657         unsigned gsvs_itemsize =
2658                         (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2659
2660         /* some r600s needs gsvs itemsize aligned to cacheline size
2661            this was fixed in rs780 and above. */
2662         switch (rctx->b.family) {
2663         case CHIP_RV610:
2664                 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2665                 break;
2666         case CHIP_R600:
2667         case CHIP_RV630:
2668         case CHIP_RV670:
2669         case CHIP_RV620:
2670         case CHIP_RV635:
2671                 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2672                 break;
2673         default:
2674                 break;
2675         }
2676
2677         r600_init_command_buffer(cb, 64);
2678
2679         /* VGT_GS_MODE is written by r600_emit_shader_stages */
2680         r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2681
2682         if (rctx->b.chip_class >= R700) {
2683                 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2684                                        S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2685         }
2686         r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2687                                r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2688
2689         r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2690                                cp_shader->ring_item_sizes[0] >> 2);
2691
2692         r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2693                                (rshader->ring_item_sizes[0]) >> 2);
2694
2695         r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2696                                gsvs_itemsize);
2697
2698         /* FIXME calculate these values somehow ??? */
2699         r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2700         r600_store_value(cb, 0x80); /* GS_PER_ES */
2701         r600_store_value(cb, 0x100); /* ES_PER_GS */
2702         r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2703         r600_store_value(cb, 0x2); /* GS_PER_VS */
2704
2705         r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2706                                S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2707                                S_02887C_STACK_SIZE(rshader->bc.nstack));
2708         r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2709         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2710 }
2711
2712 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2713 {
2714         struct r600_command_buffer *cb = &shader->command_buffer;
2715         struct r600_shader *rshader = &shader->shader;
2716
2717         r600_init_command_buffer(cb, 32);
2718
2719         r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2720                                S_028890_NUM_GPRS(rshader->bc.ngpr) |
2721                                S_028890_STACK_SIZE(rshader->bc.nstack));
2722         r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2723         /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2724 }
2725
2726
2727 void *r600_create_resolve_blend(struct r600_context *rctx)
2728 {
2729         struct pipe_blend_state blend;
2730         unsigned i;
2731
2732         memset(&blend, 0, sizeof(blend));
2733         blend.independent_blend_enable = true;
2734         for (i = 0; i < 2; i++) {
2735                 blend.rt[i].colormask = 0xf;
2736                 blend.rt[i].blend_enable = 1;
2737                 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2738                 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2739                 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2740                 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2741                 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2742                 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2743         }
2744         return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2745 }
2746
2747 void *r700_create_resolve_blend(struct r600_context *rctx)
2748 {
2749         struct pipe_blend_state blend;
2750
2751         memset(&blend, 0, sizeof(blend));
2752         blend.independent_blend_enable = true;
2753         blend.rt[0].colormask = 0xf;
2754         return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2755 }
2756
2757 void *r600_create_decompress_blend(struct r600_context *rctx)
2758 {
2759         struct pipe_blend_state blend;
2760
2761         memset(&blend, 0, sizeof(blend));
2762         blend.independent_blend_enable = true;
2763         blend.rt[0].colormask = 0xf;
2764         return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2765 }
2766
2767 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2768 {
2769         struct pipe_depth_stencil_alpha_state dsa;
2770         boolean quirk = false;
2771
2772         if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2773                 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2774                 quirk = true;
2775
2776         memset(&dsa, 0, sizeof(dsa));
2777
2778         if (quirk) {
2779                 dsa.depth.enabled = 1;
2780                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2781                 dsa.stencil[0].enabled = 1;
2782                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2783                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2784                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2785                 dsa.stencil[0].writemask = 0xff;
2786         }
2787
2788         return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2789 }
2790
2791 void r600_update_db_shader_control(struct r600_context * rctx)
2792 {
2793         bool dual_export;
2794         unsigned db_shader_control;
2795         uint8_t ps_conservative_z;
2796
2797         if (!rctx->ps_shader) {
2798                 return;
2799         }
2800
2801         dual_export = rctx->framebuffer.export_16bpc &&
2802                       !rctx->ps_shader->current->ps_depth_export;
2803
2804         db_shader_control = rctx->ps_shader->current->db_shader_control |
2805                             S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2806
2807         ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2808
2809         /* When alpha test is enabled we can't trust the hw to make the proper
2810          * decision on the order in which ztest should be run related to fragment
2811          * shader execution.
2812          *
2813          * If alpha test is enabled perform z test after fragment. RE_Z (early
2814          * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2815          */
2816         if (rctx->alphatest_state.sx_alpha_test_control) {
2817                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2818         } else {
2819                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2820         }
2821
2822         if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2823                 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2824                 rctx->db_misc_state.db_shader_control = db_shader_control;
2825                 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2826                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2827         }
2828 }
2829
2830 static inline unsigned r600_array_mode(unsigned mode)
2831 {
2832         switch (mode) {
2833         default:
2834         case RADEON_SURF_MODE_LINEAR_ALIGNED:   return V_0280A0_ARRAY_LINEAR_ALIGNED;
2835                 break;
2836         case RADEON_SURF_MODE_1D:               return V_0280A0_ARRAY_1D_TILED_THIN1;
2837                 break;
2838         case RADEON_SURF_MODE_2D:               return V_0280A0_ARRAY_2D_TILED_THIN1;
2839         }
2840 }
2841
2842 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2843                                 struct pipe_resource *dst,
2844                                 unsigned dst_level,
2845                                 unsigned dst_x,
2846                                 unsigned dst_y,
2847                                 unsigned dst_z,
2848                                 struct pipe_resource *src,
2849                                 unsigned src_level,
2850                                 unsigned src_x,
2851                                 unsigned src_y,
2852                                 unsigned src_z,
2853                                 unsigned copy_height,
2854                                 unsigned pitch,
2855                                 unsigned bpp)
2856 {
2857         struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2858         struct r600_texture *rsrc = (struct r600_texture*)src;
2859         struct r600_texture *rdst = (struct r600_texture*)dst;
2860         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2861         unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2862         uint64_t base, addr;
2863
2864         dst_mode = rdst->surface.level[dst_level].mode;
2865         src_mode = rsrc->surface.level[src_level].mode;
2866         assert(dst_mode != src_mode);
2867
2868         y = 0;
2869         lbpp = util_logbase2(bpp);
2870         pitch_tile_max = ((pitch / bpp) / 8) - 1;
2871
2872         if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2873                 /* T2L */
2874                 array_mode = r600_array_mode(src_mode);
2875                 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2876                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2877                 /* linear height must be the same as the slice tile max height, it's ok even
2878                  * if the linear destination/source have smaller heigh as the size of the
2879                  * dma packet will be using the copy_height which is always smaller or equal
2880                  * to the linear height
2881                  */
2882                 height = rsrc->surface.level[src_level].npix_y;
2883                 detile = 1;
2884                 x = src_x;
2885                 y = src_y;
2886                 z = src_z;
2887                 base = rsrc->surface.level[src_level].offset;
2888                 addr = rdst->surface.level[dst_level].offset;
2889                 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2890                 addr += dst_y * pitch + dst_x * bpp;
2891         } else {
2892                 /* L2T */
2893                 array_mode = r600_array_mode(dst_mode);
2894                 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2895                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2896                 /* linear height must be the same as the slice tile max height, it's ok even
2897                  * if the linear destination/source have smaller heigh as the size of the
2898                  * dma packet will be using the copy_height which is always smaller or equal
2899                  * to the linear height
2900                  */
2901                 height = rdst->surface.level[dst_level].npix_y;
2902                 detile = 0;
2903                 x = dst_x;
2904                 y = dst_y;
2905                 z = dst_z;
2906                 base = rdst->surface.level[dst_level].offset;
2907                 addr = rsrc->surface.level[src_level].offset;
2908                 addr += rsrc->surface.level[src_level].slice_size * src_z;
2909                 addr += src_y * pitch + src_x * bpp;
2910         }
2911         /* check that we are in dw/base alignment constraint */
2912         if (addr % 4 || base % 256) {
2913                 return FALSE;
2914         }
2915
2916         /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2917          * line in the blit. Compute max 8 line we can copy in the size limit
2918          */
2919         cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2920         ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2921         r600_need_dma_space(&rctx->b, ncopy * 7);
2922
2923         for (i = 0; i < ncopy; i++) {
2924                 cheight = cheight > copy_height ? copy_height : cheight;
2925                 size = (cheight * pitch) / 4;
2926                 /* emit reloc before writing cs so that cs is always in consistent state */
2927                 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2928                                       RADEON_PRIO_SDMA_TEXTURE);
2929                 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2930                                       RADEON_PRIO_SDMA_TEXTURE);
2931                 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2932                 cs->buf[cs->cdw++] = base >> 8;
2933                 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2934                                         (lbpp << 24) | ((height - 1) << 10) |
2935                                         pitch_tile_max;
2936                 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2937                 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2938                 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2939                 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2940                 copy_height -= cheight;
2941                 addr += cheight * pitch;
2942                 y += cheight;
2943         }
2944         return TRUE;
2945 }
2946
2947 static void r600_dma_copy(struct pipe_context *ctx,
2948                           struct pipe_resource *dst,
2949                           unsigned dst_level,
2950                           unsigned dstx, unsigned dsty, unsigned dstz,
2951                           struct pipe_resource *src,
2952                           unsigned src_level,
2953                           const struct pipe_box *src_box)
2954 {
2955         struct r600_context *rctx = (struct r600_context *)ctx;
2956         struct r600_texture *rsrc = (struct r600_texture*)src;
2957         struct r600_texture *rdst = (struct r600_texture*)dst;
2958         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2959         unsigned src_w, dst_w;
2960         unsigned src_x, src_y;
2961         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2962
2963         if (rctx->b.dma.cs == NULL) {
2964                 goto fallback;
2965         }
2966
2967         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2968                 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2969                         goto fallback;
2970
2971                 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2972                 return;
2973         }
2974
2975         if (src_box->depth > 1 ||
2976             !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2977                                         dstz, rsrc, src_level, src_box))
2978                 goto fallback;
2979
2980         src_x = util_format_get_nblocksx(src->format, src_box->x);
2981         dst_x = util_format_get_nblocksx(src->format, dst_x);
2982         src_y = util_format_get_nblocksy(src->format, src_box->y);
2983         dst_y = util_format_get_nblocksy(src->format, dst_y);
2984
2985         bpp = rdst->surface.bpe;
2986         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2987         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2988         src_w = rsrc->surface.level[src_level].npix_x;
2989         dst_w = rdst->surface.level[dst_level].npix_x;
2990         copy_height = src_box->height / rsrc->surface.blk_h;
2991
2992         dst_mode = rdst->surface.level[dst_level].mode;
2993         src_mode = rsrc->surface.level[src_level].mode;
2994
2995         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2996                 /* strict requirement on r6xx/r7xx */
2997                 goto fallback;
2998         }
2999         /* lot of constraint on alignment this should capture them all */
3000         if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3001                 goto fallback;
3002         }
3003
3004         if (src_mode == dst_mode) {
3005                 uint64_t dst_offset, src_offset, size;
3006
3007                 /* simple dma blit would do NOTE code here assume :
3008                  *   src_box.x/y == 0
3009                  *   dst_x/y == 0
3010                  *   dst_pitch == src_pitch
3011                  */
3012                 src_offset= rsrc->surface.level[src_level].offset;
3013                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3014                 src_offset += src_y * src_pitch + src_x * bpp;
3015                 dst_offset = rdst->surface.level[dst_level].offset;
3016                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3017                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3018                 size = src_box->height * src_pitch;
3019                 /* must be dw aligned */
3020                 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3021                         goto fallback;
3022                 }
3023                 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3024         } else {
3025                 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3026                                         src, src_level, src_x, src_y, src_box->z,
3027                                         copy_height, dst_pitch, bpp)) {
3028                         goto fallback;
3029                 }
3030         }
3031         return;
3032
3033 fallback:
3034         r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3035                                   src, src_level, src_box);
3036 }
3037
3038 void r600_init_state_functions(struct r600_context *rctx)
3039 {
3040         unsigned id = 1;
3041         unsigned i;
3042         /* !!!
3043          *  To avoid GPU lockup registers must be emited in a specific order
3044          * (no kidding ...). The order below is important and have been
3045          * partialy infered from analyzing fglrx command stream.
3046          *
3047          * Don't reorder atom without carefully checking the effect (GPU lockup
3048          * or piglit regression).
3049          * !!!
3050          */
3051
3052         r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3053
3054         /* shader const */
3055         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3056         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3057         r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3058
3059         /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3060          * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3061          */
3062         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3063         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3064         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3065         /* resource */
3066         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3067         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3068         r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3069         r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3070
3071         r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3072
3073         r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3074         r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3075         rctx->sample_mask.sample_mask = ~0;
3076
3077         r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3078         r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3079         r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3080         r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3081         r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3082         r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3083         r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3084         r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3085         r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3086         r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3087         r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3088         r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3089         r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3090         r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3091         r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3092         r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3093         r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3094         r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3095         r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3096         for (i = 0; i < R600_NUM_HW_STAGES; i++)
3097                 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3098         r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3099         r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3100
3101         rctx->b.b.create_blend_state = r600_create_blend_state;
3102         rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3103         rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3104         rctx->b.b.create_sampler_state = r600_create_sampler_state;
3105         rctx->b.b.create_sampler_view = r600_create_sampler_view;
3106         rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3107         rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3108         rctx->b.b.set_min_samples = r600_set_min_samples;
3109         rctx->b.b.get_sample_position = r600_get_sample_position;
3110         rctx->b.dma_copy = r600_dma_copy;
3111 }
3112 /* this function must be last */