src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include "pipe/p_defines.h"
  30 #include "pipe/p_state.h"
  31 #include "pipe/p_context.h"
  32 #include "tgsi/tgsi_scan.h"
  33 #include "tgsi/tgsi_parse.h"
  34 #include "tgsi/tgsi_util.h"
  35 #include "util/u_double_list.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_framebuffer.h"
  40 #include "util/u_transfer.h"
  41 #include "pipebuffer/pb_buffer.h"
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "r600_resource.h"
  45 #include "r600_shader.h"
  46 #include "r600_pipe.h"
  47 #include "r600_formats.h"
  48
  49 static uint32_t r600_translate_blend_function(int blend_func)
  50 {
  51         switch (blend_func) {
  52         case PIPE_BLEND_ADD:
  53                 return V_028804_COMB_DST_PLUS_SRC;
  54         case PIPE_BLEND_SUBTRACT:
  55                 return V_028804_COMB_SRC_MINUS_DST;
  56         case PIPE_BLEND_REVERSE_SUBTRACT:
  57                 return V_028804_COMB_DST_MINUS_SRC;
  58         case PIPE_BLEND_MIN:
  59                 return V_028804_COMB_MIN_DST_SRC;
  60         case PIPE_BLEND_MAX:
  61                 return V_028804_COMB_MAX_DST_SRC;
  62         default:
  63                 R600_ERR("Unknown blend function %d\n", blend_func);
  64                 assert(0);
  65                 break;
  66         }
  67         return 0;
  68 }
  69
  70 static uint32_t r600_translate_blend_factor(int blend_fact)
  71 {
  72         switch (blend_fact) {
  73         case PIPE_BLENDFACTOR_ONE:
  74                 return V_028804_BLEND_ONE;
  75         case PIPE_BLENDFACTOR_SRC_COLOR:
  76                 return V_028804_BLEND_SRC_COLOR;
  77         case PIPE_BLENDFACTOR_SRC_ALPHA:
  78                 return V_028804_BLEND_SRC_ALPHA;
  79         case PIPE_BLENDFACTOR_DST_ALPHA:
  80                 return V_028804_BLEND_DST_ALPHA;
  81         case PIPE_BLENDFACTOR_DST_COLOR:
  82                 return V_028804_BLEND_DST_COLOR;
  83         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  84                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  85         case PIPE_BLENDFACTOR_CONST_COLOR:
  86                 return V_028804_BLEND_CONST_COLOR;
  87         case PIPE_BLENDFACTOR_CONST_ALPHA:
  88                 return V_028804_BLEND_CONST_ALPHA;
  89         case PIPE_BLENDFACTOR_ZERO:
  90                 return V_028804_BLEND_ZERO;
  91         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  92                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  93         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  94                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  95         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  96                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  97         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  98                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  99         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 100                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
 101         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 102                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
 103         case PIPE_BLENDFACTOR_SRC1_COLOR:
 104                 return V_028804_BLEND_SRC1_COLOR;
 105         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 106                 return V_028804_BLEND_SRC1_ALPHA;
 107         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 108                 return V_028804_BLEND_INV_SRC1_COLOR;
 109         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 110                 return V_028804_BLEND_INV_SRC1_ALPHA;
 111         default:
 112                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 113                 assert(0);
 114                 break;
 115         }
 116         return 0;
 117 }
 118
 119 static uint32_t r600_translate_stencil_op(int s_op)
 120 {
 121         switch (s_op) {
 122         case PIPE_STENCIL_OP_KEEP:
 123                 return V_028800_STENCIL_KEEP;
 124         case PIPE_STENCIL_OP_ZERO:
 125                 return V_028800_STENCIL_ZERO;
 126         case PIPE_STENCIL_OP_REPLACE:
 127                 return V_028800_STENCIL_REPLACE;
 128         case PIPE_STENCIL_OP_INCR:
 129                 return V_028800_STENCIL_INCR;
 130         case PIPE_STENCIL_OP_DECR:
 131                 return V_028800_STENCIL_DECR;
 132         case PIPE_STENCIL_OP_INCR_WRAP:
 133                 return V_028800_STENCIL_INCR_WRAP;
 134         case PIPE_STENCIL_OP_DECR_WRAP:
 135                 return V_028800_STENCIL_DECR_WRAP;
 136         case PIPE_STENCIL_OP_INVERT:
 137                 return V_028800_STENCIL_INVERT;
 138         default:
 139                 R600_ERR("Unknown stencil op %d", s_op);
 140                 assert(0);
 141                 break;
 142         }
 143         return 0;
 144 }
 145
 146 static uint32_t r600_translate_fill(uint32_t func)
 147 {
 148         switch(func) {
 149         case PIPE_POLYGON_MODE_FILL:
 150                 return 2;
 151         case PIPE_POLYGON_MODE_LINE:
 152                 return 1;
 153         case PIPE_POLYGON_MODE_POINT:
 154                 return 0;
 155         default:
 156                 assert(0);
 157                 return 0;
 158         }
 159 }
 160
 161 /* translates straight */
 162 static uint32_t r600_translate_ds_func(int func)
 163 {
 164         return func;
 165 }
 166
 167 static unsigned r600_tex_wrap(unsigned wrap)
 168 {
 169         switch (wrap) {
 170         default:
 171         case PIPE_TEX_WRAP_REPEAT:
 172                 return V_03C000_SQ_TEX_WRAP;
 173         case PIPE_TEX_WRAP_CLAMP:
 174                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 175         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 176                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 177         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 178                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 179         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 180                 return V_03C000_SQ_TEX_MIRROR;
 181         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 182                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 183         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 184                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 185         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 186                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 187         }
 188 }
 189
 190 static unsigned r600_tex_filter(unsigned filter)
 191 {
 192         switch (filter) {
 193         default:
 194         case PIPE_TEX_FILTER_NEAREST:
 195                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 196         case PIPE_TEX_FILTER_LINEAR:
 197                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 198         }
 199 }
 200
 201 static unsigned r600_tex_mipfilter(unsigned filter)
 202 {
 203         switch (filter) {
 204         case PIPE_TEX_MIPFILTER_NEAREST:
 205                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 206         case PIPE_TEX_MIPFILTER_LINEAR:
 207                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 208         default:
 209         case PIPE_TEX_MIPFILTER_NONE:
 210                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 211         }
 212 }
 213
 214 static unsigned r600_tex_compare(unsigned compare)
 215 {
 216         switch (compare) {
 217         default:
 218         case PIPE_FUNC_NEVER:
 219                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 220         case PIPE_FUNC_LESS:
 221                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 222         case PIPE_FUNC_EQUAL:
 223                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 224         case PIPE_FUNC_LEQUAL:
 225                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 226         case PIPE_FUNC_GREATER:
 227                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 228         case PIPE_FUNC_NOTEQUAL:
 229                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 230         case PIPE_FUNC_GEQUAL:
 231                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 232         case PIPE_FUNC_ALWAYS:
 233                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 234         }
 235 }
 236
 237 static unsigned r600_tex_dim(unsigned dim)
 238 {
 239         switch (dim) {
 240         default:
 241         case PIPE_TEXTURE_1D:
 242                 return V_038000_SQ_TEX_DIM_1D;
 243         case PIPE_TEXTURE_1D_ARRAY:
 244                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 245         case PIPE_TEXTURE_2D:
 246         case PIPE_TEXTURE_RECT:
 247                 return V_038000_SQ_TEX_DIM_2D;
 248         case PIPE_TEXTURE_2D_ARRAY:
 249                 return V_038000_SQ_TEX_DIM_2D_ARRAY;
 250         case PIPE_TEXTURE_3D:
 251                 return V_038000_SQ_TEX_DIM_3D;
 252         case PIPE_TEXTURE_CUBE:
 253                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 254         }
 255 }
 256
 257 static uint32_t r600_translate_dbformat(enum pipe_format format)
 258 {
 259         switch (format) {
 260         case PIPE_FORMAT_Z16_UNORM:
 261                 return V_028010_DEPTH_16;
 262         case PIPE_FORMAT_Z24X8_UNORM:
 263                 return V_028010_DEPTH_X8_24;
 264         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 265                 return V_028010_DEPTH_8_24;
 266         case PIPE_FORMAT_Z32_FLOAT:
 267                 return V_028010_DEPTH_32_FLOAT;
 268         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 269                 return V_028010_DEPTH_X24_8_32_FLOAT;
 270         default:
 271                 return ~0U;
 272         }
 273 }
 274
 275 static uint32_t r600_translate_colorswap(enum pipe_format format)
 276 {
 277         switch (format) {
 278         /* 8-bit buffers. */
 279         case PIPE_FORMAT_A8_UNORM:
 280         case PIPE_FORMAT_A8_UINT:
 281         case PIPE_FORMAT_A8_SINT:
 282         case PIPE_FORMAT_R4A4_UNORM:
 283                 return V_0280A0_SWAP_ALT_REV;
 284         case PIPE_FORMAT_I8_UNORM:
 285         case PIPE_FORMAT_L8_UNORM:
 286         case PIPE_FORMAT_I8_UINT:
 287         case PIPE_FORMAT_I8_SINT:
 288         case PIPE_FORMAT_L8_UINT:
 289         case PIPE_FORMAT_L8_SINT:
 290         case PIPE_FORMAT_L8_SRGB:
 291         case PIPE_FORMAT_R8_UNORM:
 292         case PIPE_FORMAT_R8_SNORM:
 293         case PIPE_FORMAT_R8_UINT:
 294         case PIPE_FORMAT_R8_SINT:
 295                 return V_0280A0_SWAP_STD;
 296
 297         case PIPE_FORMAT_L4A4_UNORM:
 298         case PIPE_FORMAT_A4R4_UNORM:
 299                 return V_0280A0_SWAP_ALT;
 300
 301         /* 16-bit buffers. */
 302         case PIPE_FORMAT_B5G6R5_UNORM:
 303                 return V_0280A0_SWAP_STD_REV;
 304
 305         case PIPE_FORMAT_B5G5R5A1_UNORM:
 306         case PIPE_FORMAT_B5G5R5X1_UNORM:
 307                 return V_0280A0_SWAP_ALT;
 308
 309         case PIPE_FORMAT_B4G4R4A4_UNORM:
 310         case PIPE_FORMAT_B4G4R4X4_UNORM:
 311                 return V_0280A0_SWAP_ALT;
 312
 313         case PIPE_FORMAT_Z16_UNORM:
 314                 return V_0280A0_SWAP_STD;
 315
 316         case PIPE_FORMAT_L8A8_UNORM:
 317         case PIPE_FORMAT_L8A8_UINT:
 318         case PIPE_FORMAT_L8A8_SINT:
 319         case PIPE_FORMAT_L8A8_SRGB:
 320                 return V_0280A0_SWAP_ALT;
 321         case PIPE_FORMAT_R8G8_UNORM:
 322         case PIPE_FORMAT_R8G8_UINT:
 323         case PIPE_FORMAT_R8G8_SINT:
 324                 return V_0280A0_SWAP_STD;
 325
 326         case PIPE_FORMAT_R16_UNORM:
 327         case PIPE_FORMAT_R16_UINT:
 328         case PIPE_FORMAT_R16_SINT:
 329         case PIPE_FORMAT_R16_FLOAT:
 330                 return V_0280A0_SWAP_STD;
 331
 332         /* 32-bit buffers. */
 333
 334         case PIPE_FORMAT_A8B8G8R8_SRGB:
 335                 return V_0280A0_SWAP_STD_REV;
 336         case PIPE_FORMAT_B8G8R8A8_SRGB:
 337                 return V_0280A0_SWAP_ALT;
 338
 339         case PIPE_FORMAT_B8G8R8A8_UNORM:
 340         case PIPE_FORMAT_B8G8R8X8_UNORM:
 341                 return V_0280A0_SWAP_ALT;
 342
 343         case PIPE_FORMAT_A8R8G8B8_UNORM:
 344         case PIPE_FORMAT_X8R8G8B8_UNORM:
 345                 return V_0280A0_SWAP_ALT_REV;
 346         case PIPE_FORMAT_R8G8B8A8_SNORM:
 347         case PIPE_FORMAT_R8G8B8A8_UNORM:
 348         case PIPE_FORMAT_R8G8B8X8_UNORM:
 349         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 350         case PIPE_FORMAT_R8G8B8A8_USCALED:
 351         case PIPE_FORMAT_R8G8B8A8_SINT:
 352         case PIPE_FORMAT_R8G8B8A8_UINT:
 353                 return V_0280A0_SWAP_STD;
 354
 355         case PIPE_FORMAT_A8B8G8R8_UNORM:
 356         case PIPE_FORMAT_X8B8G8R8_UNORM:
 357         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 358                 return V_0280A0_SWAP_STD_REV;
 359
 360         case PIPE_FORMAT_Z24X8_UNORM:
 361         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 362                 return V_0280A0_SWAP_STD;
 363
 364         case PIPE_FORMAT_X8Z24_UNORM:
 365         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 366                 return V_0280A0_SWAP_STD;
 367
 368         case PIPE_FORMAT_R10G10B10A2_UNORM:
 369         case PIPE_FORMAT_R10G10B10X2_SNORM:
 370         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 371                 return V_0280A0_SWAP_STD;
 372
 373         case PIPE_FORMAT_B10G10R10A2_UNORM:
 374         case PIPE_FORMAT_B10G10R10A2_UINT:
 375                 return V_0280A0_SWAP_ALT;
 376
 377         case PIPE_FORMAT_R11G11B10_FLOAT:
 378         case PIPE_FORMAT_R16G16_UNORM:
 379         case PIPE_FORMAT_R16G16_FLOAT:
 380         case PIPE_FORMAT_R16G16_UINT:
 381         case PIPE_FORMAT_R16G16_SINT:
 382         case PIPE_FORMAT_R32_UINT:
 383         case PIPE_FORMAT_R32_SINT:
 384         case PIPE_FORMAT_R32_FLOAT:
 385         case PIPE_FORMAT_Z32_FLOAT:
 386                 return V_0280A0_SWAP_STD;
 387
 388         /* 64-bit buffers. */
 389         case PIPE_FORMAT_R32G32_FLOAT:
 390         case PIPE_FORMAT_R32G32_UINT:
 391         case PIPE_FORMAT_R32G32_SINT:
 392         case PIPE_FORMAT_R16G16B16A16_UNORM:
 393         case PIPE_FORMAT_R16G16B16A16_SNORM:
 394         case PIPE_FORMAT_R16G16B16A16_USCALED:
 395         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 396         case PIPE_FORMAT_R16G16B16A16_UINT:
 397         case PIPE_FORMAT_R16G16B16A16_SINT:
 398         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 399         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 400
 401         /* 128-bit buffers. */
 402         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 403         case PIPE_FORMAT_R32G32B32A32_SNORM:
 404         case PIPE_FORMAT_R32G32B32A32_UNORM:
 405         case PIPE_FORMAT_R32G32B32A32_USCALED:
 406         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 407         case PIPE_FORMAT_R32G32B32A32_SINT:
 408         case PIPE_FORMAT_R32G32B32A32_UINT:
 409                 return V_0280A0_SWAP_STD;
 410         default:
 411                 R600_ERR("unsupported colorswap format %d\n", format);
 412                 return ~0U;
 413         }
 414         return ~0U;
 415 }
 416
 417 static uint32_t r600_translate_colorformat(enum pipe_format format)
 418 {
 419         switch (format) {
 420         case PIPE_FORMAT_L4A4_UNORM:
 421         case PIPE_FORMAT_R4A4_UNORM:
 422         case PIPE_FORMAT_A4R4_UNORM:
 423                 return V_0280A0_COLOR_4_4;
 424
 425         /* 8-bit buffers. */
 426         case PIPE_FORMAT_A8_UNORM:
 427         case PIPE_FORMAT_A8_UINT:
 428         case PIPE_FORMAT_A8_SINT:
 429         case PIPE_FORMAT_I8_UNORM:
 430         case PIPE_FORMAT_I8_UINT:
 431         case PIPE_FORMAT_I8_SINT:
 432         case PIPE_FORMAT_L8_UNORM:
 433         case PIPE_FORMAT_L8_UINT:
 434         case PIPE_FORMAT_L8_SINT:
 435         case PIPE_FORMAT_L8_SRGB:
 436         case PIPE_FORMAT_R8_UNORM:
 437         case PIPE_FORMAT_R8_SNORM:
 438         case PIPE_FORMAT_R8_UINT:
 439         case PIPE_FORMAT_R8_SINT:
 440                 return V_0280A0_COLOR_8;
 441
 442         /* 16-bit buffers. */
 443         case PIPE_FORMAT_B5G6R5_UNORM:
 444                 return V_0280A0_COLOR_5_6_5;
 445
 446         case PIPE_FORMAT_B5G5R5A1_UNORM:
 447         case PIPE_FORMAT_B5G5R5X1_UNORM:
 448                 return V_0280A0_COLOR_1_5_5_5;
 449
 450         case PIPE_FORMAT_B4G4R4A4_UNORM:
 451         case PIPE_FORMAT_B4G4R4X4_UNORM:
 452                 return V_0280A0_COLOR_4_4_4_4;
 453
 454         case PIPE_FORMAT_Z16_UNORM:
 455                 return V_0280A0_COLOR_16;
 456
 457         case PIPE_FORMAT_L8A8_UNORM:
 458         case PIPE_FORMAT_L8A8_UINT:
 459         case PIPE_FORMAT_L8A8_SINT:
 460         case PIPE_FORMAT_L8A8_SRGB:
 461         case PIPE_FORMAT_R8G8_UNORM:
 462         case PIPE_FORMAT_R8G8_UINT:
 463         case PIPE_FORMAT_R8G8_SINT:
 464                 return V_0280A0_COLOR_8_8;
 465
 466         case PIPE_FORMAT_R16_UNORM:
 467         case PIPE_FORMAT_R16_UINT:
 468         case PIPE_FORMAT_R16_SINT:
 469                 return V_0280A0_COLOR_16;
 470
 471         case PIPE_FORMAT_R16_FLOAT:
 472                 return V_0280A0_COLOR_16_FLOAT;
 473
 474         /* 32-bit buffers. */
 475         case PIPE_FORMAT_A8B8G8R8_SRGB:
 476         case PIPE_FORMAT_A8B8G8R8_UNORM:
 477         case PIPE_FORMAT_A8R8G8B8_UNORM:
 478         case PIPE_FORMAT_B8G8R8A8_SRGB:
 479         case PIPE_FORMAT_B8G8R8A8_UNORM:
 480         case PIPE_FORMAT_B8G8R8X8_UNORM:
 481         case PIPE_FORMAT_R8G8B8A8_SNORM:
 482         case PIPE_FORMAT_R8G8B8A8_UNORM:
 483         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 484         case PIPE_FORMAT_R8G8B8A8_USCALED:
 485         case PIPE_FORMAT_R8G8B8X8_UNORM:
 486         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 487         case PIPE_FORMAT_X8B8G8R8_UNORM:
 488         case PIPE_FORMAT_X8R8G8B8_UNORM:
 489         case PIPE_FORMAT_R8G8B8_UNORM:
 490         case PIPE_FORMAT_R8G8B8A8_SINT:
 491         case PIPE_FORMAT_R8G8B8A8_UINT:
 492                 return V_0280A0_COLOR_8_8_8_8;
 493
 494         case PIPE_FORMAT_R10G10B10A2_UNORM:
 495         case PIPE_FORMAT_R10G10B10X2_SNORM:
 496         case PIPE_FORMAT_B10G10R10A2_UNORM:
 497         case PIPE_FORMAT_B10G10R10A2_UINT:
 498         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 499                 return V_0280A0_COLOR_2_10_10_10;
 500
 501         case PIPE_FORMAT_Z24X8_UNORM:
 502         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 503                 return V_0280A0_COLOR_8_24;
 504
 505         case PIPE_FORMAT_X8Z24_UNORM:
 506         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 507                 return V_0280A0_COLOR_24_8;
 508
 509         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 510                 return V_0280A0_COLOR_X24_8_32_FLOAT;
 511
 512         case PIPE_FORMAT_R32_UINT:
 513         case PIPE_FORMAT_R32_SINT:
 514                 return V_0280A0_COLOR_32;
 515
 516         case PIPE_FORMAT_R32_FLOAT:
 517         case PIPE_FORMAT_Z32_FLOAT:
 518                 return V_0280A0_COLOR_32_FLOAT;
 519
 520         case PIPE_FORMAT_R16G16_FLOAT:
 521                 return V_0280A0_COLOR_16_16_FLOAT;
 522
 523         case PIPE_FORMAT_R16G16_SSCALED:
 524         case PIPE_FORMAT_R16G16_UNORM:
 525         case PIPE_FORMAT_R16G16_UINT:
 526         case PIPE_FORMAT_R16G16_SINT:
 527                 return V_0280A0_COLOR_16_16;
 528
 529         case PIPE_FORMAT_R11G11B10_FLOAT:
 530                 return V_0280A0_COLOR_10_11_11_FLOAT;
 531
 532         /* 64-bit buffers. */
 533         case PIPE_FORMAT_R16G16B16_USCALED:
 534         case PIPE_FORMAT_R16G16B16A16_USCALED:
 535         case PIPE_FORMAT_R16G16B16_SSCALED:
 536         case PIPE_FORMAT_R16G16B16A16_UINT:
 537         case PIPE_FORMAT_R16G16B16A16_SINT:
 538         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 539         case PIPE_FORMAT_R16G16B16A16_UNORM:
 540         case PIPE_FORMAT_R16G16B16A16_SNORM:
 541                 return V_0280A0_COLOR_16_16_16_16;
 542
 543         case PIPE_FORMAT_R16G16B16_FLOAT:
 544         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 545                 return V_0280A0_COLOR_16_16_16_16_FLOAT;
 546
 547         case PIPE_FORMAT_R32G32_FLOAT:
 548                 return V_0280A0_COLOR_32_32_FLOAT;
 549
 550         case PIPE_FORMAT_R32G32_USCALED:
 551         case PIPE_FORMAT_R32G32_SSCALED:
 552         case PIPE_FORMAT_R32G32_SINT:
 553         case PIPE_FORMAT_R32G32_UINT:
 554                 return V_0280A0_COLOR_32_32;
 555
 556         /* 96-bit buffers. */
 557         case PIPE_FORMAT_R32G32B32_FLOAT:
 558                 return V_0280A0_COLOR_32_32_32_FLOAT;
 559
 560         /* 128-bit buffers. */
 561         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 562                 return V_0280A0_COLOR_32_32_32_32_FLOAT;
 563         case PIPE_FORMAT_R32G32B32A32_SNORM:
 564         case PIPE_FORMAT_R32G32B32A32_UNORM:
 565         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 566         case PIPE_FORMAT_R32G32B32A32_USCALED:
 567         case PIPE_FORMAT_R32G32B32A32_SINT:
 568         case PIPE_FORMAT_R32G32B32A32_UINT:
 569                 return V_0280A0_COLOR_32_32_32_32;
 570
 571         /* YUV buffers. */
 572         case PIPE_FORMAT_UYVY:
 573         case PIPE_FORMAT_YUYV:
 574         default:
 575                 return ~0U; /* Unsupported. */
 576         }
 577 }
 578
 579 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 580 {
 581         if (R600_BIG_ENDIAN) {
 582                 switch(colorformat) {
 583                 case V_0280A0_COLOR_4_4:
 584                         return ENDIAN_NONE;
 585
 586                 /* 8-bit buffers. */
 587                 case V_0280A0_COLOR_8:
 588                         return ENDIAN_NONE;
 589
 590                 /* 16-bit buffers. */
 591                 case V_0280A0_COLOR_5_6_5:
 592                 case V_0280A0_COLOR_1_5_5_5:
 593                 case V_0280A0_COLOR_4_4_4_4:
 594                 case V_0280A0_COLOR_16:
 595                 case V_0280A0_COLOR_8_8:
 596                         return ENDIAN_8IN16;
 597
 598                 /* 32-bit buffers. */
 599                 case V_0280A0_COLOR_8_8_8_8:
 600                 case V_0280A0_COLOR_2_10_10_10:
 601                 case V_0280A0_COLOR_8_24:
 602                 case V_0280A0_COLOR_24_8:
 603                 case V_0280A0_COLOR_32_FLOAT:
 604                 case V_0280A0_COLOR_16_16_FLOAT:
 605                 case V_0280A0_COLOR_16_16:
 606                         return ENDIAN_8IN32;
 607
 608                 /* 64-bit buffers. */
 609                 case V_0280A0_COLOR_16_16_16_16:
 610                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
 611                         return ENDIAN_8IN16;
 612
 613                 case V_0280A0_COLOR_32_32_FLOAT:
 614                 case V_0280A0_COLOR_32_32:
 615                 case V_0280A0_COLOR_X24_8_32_FLOAT:
 616                         return ENDIAN_8IN32;
 617
 618                 /* 128-bit buffers. */
 619                 case V_0280A0_COLOR_32_32_32_FLOAT:
 620                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
 621                 case V_0280A0_COLOR_32_32_32_32:
 622                         return ENDIAN_8IN32;
 623                 default:
 624                         return ENDIAN_NONE; /* Unsupported. */
 625                 }
 626         } else {
 627                 return ENDIAN_NONE;
 628         }
 629 }
 630
 631 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 632 {
 633         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 634 }
 635
 636 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 637 {
 638         return r600_translate_colorformat(format) != ~0U &&
 639                r600_translate_colorswap(format) != ~0U;
 640 }
 641
 642 static bool r600_is_zs_format_supported(enum pipe_format format)
 643 {
 644         return r600_translate_dbformat(format) != ~0U;
 645 }
 646
 647 boolean r600_is_format_supported(struct pipe_screen *screen,
 648                                  enum pipe_format format,
 649                                  enum pipe_texture_target target,
 650                                  unsigned sample_count,
 651                                  unsigned usage)
 652 {
 653         unsigned retval = 0;
 654
 655         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 656                 R600_ERR("r600: unsupported texture type %d\n", target);
 657                 return FALSE;
 658         }
 659
 660         if (!util_format_is_supported(format, usage))
 661                 return FALSE;
 662
 663         /* Multisample */
 664         if (sample_count > 1)
 665                 return FALSE;
 666
 667         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 668             r600_is_sampler_format_supported(screen, format)) {
 669                 retval |= PIPE_BIND_SAMPLER_VIEW;
 670         }
 671
 672         if ((usage & (PIPE_BIND_RENDER_TARGET |
 673                       PIPE_BIND_DISPLAY_TARGET |
 674                       PIPE_BIND_SCANOUT |
 675                       PIPE_BIND_SHARED)) &&
 676             r600_is_colorbuffer_format_supported(format)) {
 677                 retval |= usage &
 678                           (PIPE_BIND_RENDER_TARGET |
 679                            PIPE_BIND_DISPLAY_TARGET |
 680                            PIPE_BIND_SCANOUT |
 681                            PIPE_BIND_SHARED);
 682         }
 683
 684         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 685             r600_is_zs_format_supported(format)) {
 686                 retval |= PIPE_BIND_DEPTH_STENCIL;
 687         }
 688
 689         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 690             r600_is_vertex_format_supported(format)) {
 691                 retval |= PIPE_BIND_VERTEX_BUFFER;
 692         }
 693
 694         if (usage & PIPE_BIND_TRANSFER_READ)
 695                 retval |= PIPE_BIND_TRANSFER_READ;
 696         if (usage & PIPE_BIND_TRANSFER_WRITE)
 697                 retval |= PIPE_BIND_TRANSFER_WRITE;
 698
 699         return retval == usage;
 700 }
 701
 702 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
 703 {
 704         struct r600_pipe_state state;
 705
 706         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
 707         state.nregs = 0;
 708         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 709                 float offset_units = rctx->rasterizer->offset_units;
 710                 unsigned offset_db_fmt_cntl = 0, depth;
 711
 712                 switch (rctx->framebuffer.zsbuf->texture->format) {
 713                 case PIPE_FORMAT_Z24X8_UNORM:
 714                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 715                         depth = -24;
 716                         offset_units *= 2.0f;
 717                         break;
 718                 case PIPE_FORMAT_Z32_FLOAT:
 719                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 720                         depth = -23;
 721                         offset_units *= 1.0f;
 722                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 723                         break;
 724                 case PIPE_FORMAT_Z16_UNORM:
 725                         depth = -16;
 726                         offset_units *= 4.0f;
 727                         break;
 728                 default:
 729                         return;
 730                 }
 731                 /* FIXME some of those reg can be computed with cso */
 732                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 733                 r600_pipe_state_add_reg(&state,
 734                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 735                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
 736                 r600_pipe_state_add_reg(&state,
 737                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 738                                 fui(offset_units), 0xFFFFFFFF, NULL, 0);
 739                 r600_pipe_state_add_reg(&state,
 740                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 741                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
 742                 r600_pipe_state_add_reg(&state,
 743                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 744                                 fui(offset_units), 0xFFFFFFFF, NULL, 0);
 745                 r600_pipe_state_add_reg(&state,
 746                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 747                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
 748                 r600_context_pipe_state_set(&rctx->ctx, &state);
 749         }
 750 }
 751
 752 static void r600_set_blend_color(struct pipe_context *ctx,
 753                                         const struct pipe_blend_color *state)
 754 {
 755         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 756         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 757
 758         if (rstate == NULL)
 759                 return;
 760
 761         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 762         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
 763         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
 764         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
 765         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
 766         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 767         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 768         r600_context_pipe_state_set(&rctx->ctx, rstate);
 769 }
 770
 771 static void *r600_create_blend_state(struct pipe_context *ctx,
 772                                         const struct pipe_blend_state *state)
 773 {
 774         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 775         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 776         struct r600_pipe_state *rstate;
 777         u32 color_control = 0, target_mask;
 778
 779         if (blend == NULL) {
 780                 return NULL;
 781         }
 782         rstate = &blend->rstate;
 783
 784         rstate->id = R600_PIPE_STATE_BLEND;
 785
 786         target_mask = 0;
 787
 788         /* R600 does not support per-MRT blends */
 789         if (rctx->family > CHIP_R600)
 790                 color_control |= S_028808_PER_MRT_BLEND(1);
 791         if (state->logicop_enable) {
 792                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 793         } else {
 794                 color_control |= (0xcc << 16);
 795         }
 796         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 797         if (state->independent_blend_enable) {
 798                 for (int i = 0; i < 8; i++) {
 799                         if (state->rt[i].blend_enable) {
 800                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 801                         }
 802                         target_mask |= (state->rt[i].colormask << (4 * i));
 803                 }
 804         } else {
 805                 for (int i = 0; i < 8; i++) {
 806                         if (state->rt[0].blend_enable) {
 807                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 808                         }
 809                         target_mask |= (state->rt[0].colormask << (4 * i));
 810                 }
 811         }
 812         blend->cb_target_mask = target_mask;
 813         /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
 814         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 815                                 color_control, 0xFFFFFFFD, NULL, 0);
 816
 817         for (int i = 0; i < 8; i++) {
 818                 /* state->rt entries > 0 only written if independent blending */
 819                 const int j = state->independent_blend_enable ? i : 0;
 820
 821                 unsigned eqRGB = state->rt[j].rgb_func;
 822                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 823                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 824
 825                 unsigned eqA = state->rt[j].alpha_func;
 826                 unsigned srcA = state->rt[j].alpha_src_factor;
 827                 unsigned dstA = state->rt[j].alpha_dst_factor;
 828                 uint32_t bc = 0;
 829
 830                 if (!state->rt[j].blend_enable)
 831                         continue;
 832
 833                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 834                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 835                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 836
 837                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 838                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 839                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 840                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 841                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 842                 }
 843
 844                 /* R600 does not support per-MRT blends */
 845                 if (rctx->family > CHIP_R600)
 846                         r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL, 0);
 847                 if (i == 0)
 848                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL, 0);
 849         }
 850         return rstate;
 851 }
 852
 853 static void *r600_create_dsa_state(struct pipe_context *ctx,
 854                                    const struct pipe_depth_stencil_alpha_state *state)
 855 {
 856         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 857         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 858         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 859         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 860         struct r600_pipe_state *rstate;
 861
 862         if (dsa == NULL) {
 863                 return NULL;
 864         }
 865
 866         rstate = &dsa->rstate;
 867
 868         rstate->id = R600_PIPE_STATE_DSA;
 869         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 870         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 871         stencil_ref_mask = 0;
 872         stencil_ref_mask_bf = 0;
 873         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 874                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 875                 S_028800_ZFUNC(state->depth.func);
 876
 877         /* stencil */
 878         if (state->stencil[0].enabled) {
 879                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 880                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 881                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 882                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 883                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 884
 885
 886                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 887                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 888                 if (state->stencil[1].enabled) {
 889                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 890                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 891                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 892                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 893                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 894                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 895                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 896                 }
 897         }
 898
 899         /* alpha */
 900         alpha_test_control = 0;
 901         alpha_ref = 0;
 902         if (state->alpha.enabled) {
 903                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 904                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 905                 alpha_ref = fui(state->alpha.ref_value);
 906         }
 907         dsa->alpha_ref = alpha_ref;
 908
 909         /* misc */
 910         db_render_control = 0;
 911         db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 912                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 913                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
 914         /* TODO db_render_override depends on query */
 915         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
 916         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
 917         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
 918         r600_pipe_state_add_reg(rstate,
 919                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 920                                 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
 921         r600_pipe_state_add_reg(rstate,
 922                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 923                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
 924         r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
 925         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
 926         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
 927         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
 928         /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
 929          * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
 930          * r600_pipe_shader_ps().*/
 931         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
 932         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
 933         r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
 934         r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL, 0);
 935         r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL, 0);
 936         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
 937
 938         return rstate;
 939 }
 940
 941 static void *r600_create_rs_state(struct pipe_context *ctx,
 942                                   const struct pipe_rasterizer_state *state)
 943 {
 944         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 945         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 946         struct r600_pipe_state *rstate;
 947         unsigned tmp;
 948         unsigned prov_vtx = 1, polygon_dual_mode;
 949         unsigned clip_rule;
 950         unsigned sc_mode_cntl;
 951
 952         if (rs == NULL) {
 953                 return NULL;
 954         }
 955
 956         rstate = &rs->rstate;
 957         rs->clamp_vertex_color = state->clamp_vertex_color;
 958         rs->clamp_fragment_color = state->clamp_fragment_color;
 959         rs->flatshade = state->flatshade;
 960         rs->sprite_coord_enable = state->sprite_coord_enable;
 961         rs->two_side = state->light_twoside;
 962         rs->clip_plane_enable = state->clip_plane_enable;
 963
 964         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 965         /* offset */
 966         rs->offset_units = state->offset_units;
 967         rs->offset_scale = state->offset_scale * 12.0f;
 968
 969         rstate->id = R600_PIPE_STATE_RASTERIZER;
 970         if (state->flatshade_first)
 971                 prov_vtx = 0;
 972         tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
 973         if (state->sprite_coord_enable) {
 974                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 975                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 976                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 977                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 978                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 979                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 980                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 981                 }
 982         }
 983         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
 984
 985         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 986                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 987         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 988                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 989                 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 990                 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 991                 S_028814_FACE(!state->front_ccw) |
 992                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 993                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 994                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 995                 S_028814_POLY_MODE(polygon_dual_mode) |
 996                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 997                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
 998         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 999                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex),
1000                         S_02881C_USE_VTX_POINT_SIZE(1), NULL, 0);
1001         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1002         /* point size 12.4 fixed point */
1003         tmp = (unsigned)(state->point_size * 8.0);
1004         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
1005         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
1006
1007         tmp = (unsigned)state->line_width * 8;
1008         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
1009
1010         if (state->line_stipple_enable) {
1011                 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
1012                                         S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1013                                         S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
1014                                         0x9FFFFFFF, NULL, 0);
1015         }
1016
1017         if (rctx->chip_class >= R700)
1018                 sc_mode_cntl = 0x514002;
1019         else
1020                 sc_mode_cntl = 0x4102;
1021         sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
1022
1023         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
1024                                 0xFFFFFFFF, NULL, 0);
1025         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1026         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
1027
1028         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
1029                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1030                                 0xFFFFFFFF, NULL, 0);
1031
1032         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1033         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1034         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1035         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1036         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
1037         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
1038         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1039                         S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1040                         S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip),
1041                         S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(1) |
1042                         S_028810_ZCLIP_FAR_DISABLE(1), NULL, 0);
1043         return rstate;
1044 }
1045
1046 static void *r600_create_sampler_state(struct pipe_context *ctx,
1047                                         const struct pipe_sampler_state *state)
1048 {
1049         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1050         struct r600_pipe_state *rstate;
1051         union util_color uc;
1052         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
1053
1054         if (ss == NULL) {
1055                 return NULL;
1056         }
1057
1058         ss->seamless_cube_map = state->seamless_cube_map;
1059         rstate = &ss->rstate;
1060         rstate->id = R600_PIPE_STATE_SAMPLER;
1061         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1062         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1063                                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1064                                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1065                                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1066                                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1067                                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1068                                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1069                                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1070                                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1071                                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1072         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1073                                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1074                                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1075                                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0);
1076         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0);
1077         if (uc.ui) {
1078                 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1079                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1080                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1081                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1082         }
1083         return rstate;
1084 }
1085
1086 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1087                                                         struct pipe_resource *texture,
1088                                                         const struct pipe_sampler_view *state)
1089 {
1090         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1091         struct r600_pipe_resource_state *rstate;
1092         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1093         unsigned format, endian;
1094         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1095         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1096         unsigned width, height, depth, offset_level, last_level;
1097
1098         if (view == NULL)
1099                 return NULL;
1100         rstate = &view->state;
1101
1102         /* initialize base object */
1103         view->base = *state;
1104         view->base.texture = NULL;
1105         pipe_reference(NULL, &texture->reference);
1106         view->base.texture = texture;
1107         view->base.reference.count = 1;
1108         view->base.context = ctx;
1109
1110         swizzle[0] = state->swizzle_r;
1111         swizzle[1] = state->swizzle_g;
1112         swizzle[2] = state->swizzle_b;
1113         swizzle[3] = state->swizzle_a;
1114
1115         format = r600_translate_texformat(ctx->screen, state->format,
1116                                           swizzle,
1117                                           &word4, &yuv_format);
1118         if (format == ~0) {
1119                 format = 0;
1120         }
1121
1122         if (tmp->depth && !tmp->is_flushing_texture) {
1123                 r600_texture_depth_flush(ctx, texture, TRUE);
1124                 tmp = tmp->flushed_depth_texture;
1125         }
1126
1127         endian = r600_colorformat_endian_swap(format);
1128
1129         offset_level = state->u.tex.first_level;
1130         last_level = state->u.tex.last_level - offset_level;
1131         width = u_minify(texture->width0, offset_level);
1132         height = u_minify(texture->height0, offset_level);
1133         depth = u_minify(texture->depth0, offset_level);
1134
1135         pitch = align(tmp->pitch_in_blocks[offset_level] *
1136                       util_format_get_blockwidth(state->format), 8);
1137         array_mode = tmp->array_mode[offset_level];
1138         tile_type = tmp->tile_type;
1139
1140         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1141                 height = 1;
1142                 depth = texture->array_size;
1143         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1144                 depth = texture->array_size;
1145         }
1146
1147         rstate->bo[0] = &tmp->resource;
1148         rstate->bo[1] = &tmp->resource;
1149         rstate->bo_usage[0] = RADEON_USAGE_READ;
1150         rstate->bo_usage[1] = RADEON_USAGE_READ;
1151
1152         rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1153                           S_038000_TILE_MODE(array_mode) |
1154                           S_038000_TILE_TYPE(tile_type) |
1155                           S_038000_PITCH((pitch / 8) - 1) |
1156                           S_038000_TEX_WIDTH(width - 1));
1157         rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1158                           S_038004_TEX_DEPTH(depth - 1) |
1159                           S_038004_DATA_FORMAT(format));
1160         rstate->val[2] = tmp->offset[offset_level] >> 8;
1161         rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1162         rstate->val[4] = (word4 |
1163                           S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1164                           S_038010_REQUEST_SIZE(1) |
1165                           S_038010_ENDIAN_SWAP(endian) |
1166                           S_038010_BASE_LEVEL(0));
1167         rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1168                           S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1169                           S_038014_LAST_ARRAY(state->u.tex.last_layer));
1170         rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1171                           S_038018_MAX_ANISO(4 /* max 16 samples */));
1172
1173         return &view->base;
1174 }
1175
1176 static void r600_set_sampler_views(struct r600_pipe_context *rctx,
1177                                    struct r600_textures_info *dst,
1178                                    unsigned count,
1179                                    struct pipe_sampler_view **views,
1180                                    void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1181 {
1182         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1183         unsigned i;
1184
1185         for (i = 0; i < count; i++) {
1186                 if (rviews[i]) {
1187                         if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1188                                 rctx->have_depth_texture = true;
1189
1190                         /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1191                         if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1192                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1193                                 dst->samplers_dirty = true;
1194
1195                         set_resource(&rctx->ctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1196                 } else {
1197                         set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1198                 }
1199
1200                 pipe_sampler_view_reference(
1201                         (struct pipe_sampler_view **)&dst->views[i],
1202                         views[i]);
1203         }
1204
1205         for (i = count; i < dst->n_views; i++) {
1206                 if (dst->views[i]) {
1207                         set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1208                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1209                 }
1210         }
1211
1212         dst->n_views = count;
1213 }
1214
1215 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1216                                       struct pipe_sampler_view **views)
1217 {
1218         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1219         r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1220                                r600_context_pipe_state_set_vs_resource);
1221 }
1222
1223 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1224                                       struct pipe_sampler_view **views)
1225 {
1226         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1227         r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1228                                r600_context_pipe_state_set_ps_resource);
1229 }
1230
1231 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1232 {
1233         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1234         if (rstate == NULL)
1235                 return;
1236
1237         rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1238         r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1239                                 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1240                                 1, NULL, 0);
1241
1242         free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1243         rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1244         r600_context_pipe_state_set(&rctx->ctx, rstate);
1245 }
1246
1247 static void r600_bind_samplers(struct r600_pipe_context *rctx,
1248                                struct r600_textures_info *dst,
1249                                unsigned count, void **states)
1250 {
1251         memcpy(dst->samplers, states, sizeof(void*) * count);
1252         dst->n_samplers = count;
1253         dst->samplers_dirty = true;
1254 }
1255
1256 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1257 {
1258         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1259         r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1260 }
1261
1262 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1263 {
1264         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1265         r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1266 }
1267
1268 static void r600_update_samplers(struct r600_pipe_context *rctx,
1269                                  struct r600_textures_info *tex,
1270                                  void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1271 {
1272         unsigned i;
1273
1274         if (tex->samplers_dirty) {
1275                 int seamless = -1;
1276                 for (i = 0; i < tex->n_samplers; i++) {
1277                         if (!tex->samplers[i])
1278                                 continue;
1279
1280                         /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1281                          * filtering between layers.
1282                          * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1283                         if (tex->views[i]) {
1284                                 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1285                                     tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1286                                         tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1287                                         tex->is_array_sampler[i] = true;
1288                                 } else {
1289                                         tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1290                                         tex->is_array_sampler[i] = false;
1291                                 }
1292                         }
1293
1294                         set_sampler(&rctx->ctx, &tex->samplers[i]->rstate, i);
1295
1296                         if (tex->samplers[i])
1297                                 seamless = tex->samplers[i]->seamless_cube_map;
1298                 }
1299
1300                 if (seamless != -1)
1301                         r600_set_seamless_cubemap(rctx, seamless);
1302
1303                 tex->samplers_dirty = false;
1304         }
1305 }
1306
1307 void r600_update_sampler_states(struct r600_pipe_context *rctx)
1308 {
1309         r600_update_samplers(rctx, &rctx->vs_samplers,
1310                              r600_context_pipe_state_set_vs_sampler);
1311         r600_update_samplers(rctx, &rctx->ps_samplers,
1312                              r600_context_pipe_state_set_ps_sampler);
1313 }
1314
1315 static void r600_set_clip_state(struct pipe_context *ctx,
1316                                 const struct pipe_clip_state *state)
1317 {
1318         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1319         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1320
1321         if (rstate == NULL)
1322                 return;
1323
1324         rctx->clip = *state;
1325         rstate->id = R600_PIPE_STATE_CLIP;
1326         for (int i = 0; i < 6; i++) {
1327                 r600_pipe_state_add_reg(rstate,
1328                                         R_028E20_PA_CL_UCP0_X + i * 16,
1329                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1330                 r600_pipe_state_add_reg(rstate,
1331                                         R_028E24_PA_CL_UCP0_Y + i * 16,
1332                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1333                 r600_pipe_state_add_reg(rstate,
1334                                         R_028E28_PA_CL_UCP0_Z + i * 16,
1335                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1336                 r600_pipe_state_add_reg(rstate,
1337                                         R_028E2C_PA_CL_UCP0_W + i * 16,
1338                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1339         }
1340
1341         free(rctx->states[R600_PIPE_STATE_CLIP]);
1342         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1343         r600_context_pipe_state_set(&rctx->ctx, rstate);
1344 }
1345
1346 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1347                                          const struct pipe_poly_stipple *state)
1348 {
1349 }
1350
1351 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1352 {
1353 }
1354
1355 static void r600_set_scissor_state(struct pipe_context *ctx,
1356                                         const struct pipe_scissor_state *state)
1357 {
1358         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1359         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1360         u32 tl, br;
1361
1362         if (rstate == NULL)
1363                 return;
1364
1365         rstate->id = R600_PIPE_STATE_SCISSOR;
1366         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1367         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1368         r600_pipe_state_add_reg(rstate,
1369                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1370                                 0xFFFFFFFF, NULL, 0);
1371         r600_pipe_state_add_reg(rstate,
1372                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1373                                 0xFFFFFFFF, NULL, 0);
1374         r600_pipe_state_add_reg(rstate,
1375                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1376                                 0xFFFFFFFF, NULL, 0);
1377         r600_pipe_state_add_reg(rstate,
1378                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1379                                 0xFFFFFFFF, NULL, 0);
1380         r600_pipe_state_add_reg(rstate,
1381                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1382                                 0xFFFFFFFF, NULL, 0);
1383         r600_pipe_state_add_reg(rstate,
1384                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1385                                 0xFFFFFFFF, NULL, 0);
1386         r600_pipe_state_add_reg(rstate,
1387                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1388                                 0xFFFFFFFF, NULL, 0);
1389         r600_pipe_state_add_reg(rstate,
1390                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1391                                 0xFFFFFFFF, NULL, 0);
1392
1393         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1394         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1395         r600_context_pipe_state_set(&rctx->ctx, rstate);
1396 }
1397
1398 static void r600_set_stencil_ref(struct pipe_context *ctx,
1399                                 const struct pipe_stencil_ref *state)
1400 {
1401         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1402         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1403         u32 tmp;
1404
1405         if (rstate == NULL)
1406                 return;
1407
1408         rctx->stencil_ref = *state;
1409         rstate->id = R600_PIPE_STATE_STENCIL_REF;
1410         tmp = S_028430_STENCILREF(state->ref_value[0]);
1411         r600_pipe_state_add_reg(rstate,
1412                                 R_028430_DB_STENCILREFMASK, tmp,
1413                                 ~C_028430_STENCILREF, NULL, 0);
1414         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1415         r600_pipe_state_add_reg(rstate,
1416                                 R_028434_DB_STENCILREFMASK_BF, tmp,
1417                                 ~C_028434_STENCILREF_BF, NULL, 0);
1418
1419         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1420         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1421         r600_context_pipe_state_set(&rctx->ctx, rstate);
1422 }
1423
1424 static void r600_set_viewport_state(struct pipe_context *ctx,
1425                                         const struct pipe_viewport_state *state)
1426 {
1427         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1428         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1429
1430         if (rstate == NULL)
1431                 return;
1432
1433         rctx->viewport = *state;
1434         rstate->id = R600_PIPE_STATE_VIEWPORT;
1435         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1436         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1437         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1438         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1439         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1440         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1441         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1442         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1443         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1444
1445         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1446         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1447         r600_context_pipe_state_set(&rctx->ctx, rstate);
1448 }
1449
1450 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1451                         const struct pipe_framebuffer_state *state, int cb)
1452 {
1453         struct r600_resource_texture *rtex;
1454         struct r600_surface *surf;
1455         unsigned level = state->cbufs[cb]->u.tex.level;
1456         unsigned pitch, slice;
1457         unsigned color_info;
1458         unsigned format, swap, ntype, endian;
1459         unsigned offset;
1460         const struct util_format_description *desc;
1461         int i;
1462
1463         surf = (struct r600_surface *)state->cbufs[cb];
1464         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1465
1466         if (rtex->depth)
1467                 rctx->have_depth_fb = TRUE;
1468
1469         if (rtex->depth && !rtex->is_flushing_texture) {
1470                 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1471                 rtex = rtex->flushed_depth_texture;
1472         }
1473
1474         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1475         offset = r600_texture_get_offset(rtex,
1476                                          level, state->cbufs[cb]->u.tex.first_layer);
1477         pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1478         slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1479         desc = util_format_description(surf->base.format);
1480
1481         for (i = 0; i < 4; i++) {
1482                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1483                         break;
1484                 }
1485         }
1486
1487         ntype = V_0280A0_NUMBER_UNORM;
1488         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1489                 ntype = V_0280A0_NUMBER_SRGB;
1490         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1491                 if (desc->channel[i].normalized)
1492                         ntype = V_0280A0_NUMBER_SNORM;
1493                 else if (desc->channel[i].pure_integer)
1494                         ntype = V_0280A0_NUMBER_SINT;
1495         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1496                 if (desc->channel[i].normalized)
1497                         ntype = V_0280A0_NUMBER_UNORM;
1498                 else if (desc->channel[i].pure_integer)
1499                         ntype = V_0280A0_NUMBER_UINT;
1500         }
1501
1502         format = r600_translate_colorformat(surf->base.format);
1503         swap = r600_translate_colorswap(surf->base.format);
1504         if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1505                 endian = ENDIAN_NONE;
1506         } else {
1507                 endian = r600_colorformat_endian_swap(format);
1508         }
1509
1510         color_info = S_0280A0_FORMAT(format) |
1511                 S_0280A0_COMP_SWAP(swap) |
1512                 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1513                 S_0280A0_BLEND_CLAMP(1) |
1514                 S_0280A0_NUMBER_TYPE(ntype) |
1515                 S_0280A0_ENDIAN(endian);
1516
1517         /* EXPORT_NORM is an optimzation that can be enabled for better
1518          * performance in certain cases
1519          */
1520         if (rctx->chip_class == R600) {
1521                 /* EXPORT_NORM can be enabled if:
1522                  * - 11-bit or smaller UNORM/SNORM/SRGB
1523                  * - BLEND_CLAMP is enabled
1524                  * - BLEND_FLOAT32 is disabled
1525                  */
1526                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1527                     (desc->channel[i].size < 12 &&
1528                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1529                      ntype != V_0280A0_NUMBER_UINT &&
1530                      ntype != V_0280A0_NUMBER_SINT) &&
1531                     G_0280A0_BLEND_CLAMP(color_info) &&
1532                     !G_0280A0_BLEND_FLOAT32(color_info))
1533                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1534         } else {
1535                 /* EXPORT_NORM can be enabled if:
1536                  * - 11-bit or smaller UNORM/SNORM/SRGB
1537                  * - 16-bit or smaller FLOAT
1538                  */
1539                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1540                     ((desc->channel[i].size < 12 &&
1541                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1542                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1543                     (desc->channel[i].size < 17 &&
1544                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1545                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1546         }
1547
1548         r600_pipe_state_add_reg(rstate,
1549                                 R_028040_CB_COLOR0_BASE + cb * 4,
1550                                 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1551         r600_pipe_state_add_reg(rstate,
1552                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
1553                                 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1554         r600_pipe_state_add_reg(rstate,
1555                                 R_028060_CB_COLOR0_SIZE + cb * 4,
1556                                 S_028060_PITCH_TILE_MAX(pitch) |
1557                                 S_028060_SLICE_TILE_MAX(slice),
1558                                 0xFFFFFFFF, NULL, 0);
1559         r600_pipe_state_add_reg(rstate,
1560                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1561                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1562         r600_pipe_state_add_reg(rstate,
1563                                 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1564                                 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1565         r600_pipe_state_add_reg(rstate,
1566                                 R_0280C0_CB_COLOR0_TILE + cb * 4,
1567                                 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1568         r600_pipe_state_add_reg(rstate,
1569                                 R_028100_CB_COLOR0_MASK + cb * 4,
1570                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1571 }
1572
1573 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1574                         const struct pipe_framebuffer_state *state)
1575 {
1576         struct r600_resource_texture *rtex;
1577         struct r600_surface *surf;
1578         unsigned level, pitch, slice, format, offset, array_mode;
1579
1580         if (state->zsbuf == NULL)
1581                 return;
1582
1583         level = state->zsbuf->u.tex.level;
1584
1585         surf = (struct r600_surface *)state->zsbuf;
1586         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1587
1588         /* XXX remove this once tiling is properly supported */
1589         array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1590                                                V_0280A0_ARRAY_1D_TILED_THIN1;
1591
1592         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1593         offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1594                                          level, state->zsbuf->u.tex.first_layer);
1595         pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1596         slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1597         format = r600_translate_dbformat(state->zsbuf->texture->format);
1598
1599         r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1600                                 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1601         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1602                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1603                                 0xFFFFFFFF, NULL, 0);
1604         r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1605         r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1606                                 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1607                                 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1608         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1609                                 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);
1610 }
1611
1612 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1613                                         const struct pipe_framebuffer_state *state)
1614 {
1615         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1616         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1617         u32 shader_mask, tl, br, shader_control, target_mask;
1618
1619         if (rstate == NULL)
1620                 return;
1621
1622         r600_context_flush_dest_caches(&rctx->ctx);
1623         rctx->ctx.num_dest_buffers = state->nr_cbufs;
1624
1625         /* unreference old buffer and reference new one */
1626         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1627
1628         util_copy_framebuffer_state(&rctx->framebuffer, state);
1629
1630         /* build states */
1631         rctx->have_depth_fb = 0;
1632         for (int i = 0; i < state->nr_cbufs; i++) {
1633                 r600_cb(rctx, rstate, state, i);
1634         }
1635         if (state->zsbuf) {
1636                 r600_db(rctx, rstate, state);
1637                 rctx->ctx.num_dest_buffers++;
1638         }
1639
1640         target_mask = 0x00000000;
1641         target_mask = 0xFFFFFFFF;
1642         shader_mask = 0;
1643         shader_control = 0;
1644         for (int i = 0; i < state->nr_cbufs; i++) {
1645                 target_mask ^= 0xf << (i * 4);
1646                 shader_mask |= 0xf << (i * 4);
1647                 shader_control |= 1 << i;
1648         }
1649         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1650         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1651
1652         r600_pipe_state_add_reg(rstate,
1653                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1654                                 0xFFFFFFFF, NULL, 0);
1655         r600_pipe_state_add_reg(rstate,
1656                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1657                                 0xFFFFFFFF, NULL, 0);
1658         r600_pipe_state_add_reg(rstate,
1659                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1660                                 0xFFFFFFFF, NULL, 0);
1661         r600_pipe_state_add_reg(rstate,
1662                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1663                                 0xFFFFFFFF, NULL, 0);
1664         r600_pipe_state_add_reg(rstate,
1665                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1666                                 0xFFFFFFFF, NULL, 0);
1667         r600_pipe_state_add_reg(rstate,
1668                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1669                                 0xFFFFFFFF, NULL, 0);
1670         r600_pipe_state_add_reg(rstate,
1671                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1672                                 0xFFFFFFFF, NULL, 0);
1673         r600_pipe_state_add_reg(rstate,
1674                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1675                                 0xFFFFFFFF, NULL, 0);
1676         r600_pipe_state_add_reg(rstate,
1677                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1678                                 0xFFFFFFFF, NULL, 0);
1679         if (rctx->chip_class >= R700) {
1680                 r600_pipe_state_add_reg(rstate,
1681                                         R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1682                                         0xFFFFFFFF, NULL, 0);
1683         }
1684
1685         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1686                                 shader_control, 0xFFFFFFFF, NULL, 0);
1687         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1688                                 0x00000000, target_mask, NULL, 0);
1689         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1690                                 shader_mask, 0xFFFFFFFF, NULL, 0);
1691         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1692                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1693         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1694                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1695         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1696                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1697         r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1698                                 0x01000000, 0xFFFFFFFF, NULL, 0);
1699         r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1700                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1701         r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1702                                 0x000000FF, 0xFFFFFFFF, NULL, 0);
1703         r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1704                                 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1705         r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1706                                 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1707
1708         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1709         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1710         r600_context_pipe_state_set(&rctx->ctx, rstate);
1711
1712         if (state->zsbuf) {
1713                 r600_polygon_offset_update(rctx);
1714         }
1715 }
1716
1717 static void r600_texture_barrier(struct pipe_context *ctx)
1718 {
1719         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1720
1721         r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1722                         S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1723                         S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1724                         S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1725                         S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1726 }
1727
1728 void r600_init_state_functions(struct r600_pipe_context *rctx)
1729 {
1730         rctx->context.create_blend_state = r600_create_blend_state;
1731         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1732         rctx->context.create_fs_state = r600_create_shader_state;
1733         rctx->context.create_rasterizer_state = r600_create_rs_state;
1734         rctx->context.create_sampler_state = r600_create_sampler_state;
1735         rctx->context.create_sampler_view = r600_create_sampler_view;
1736         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1737         rctx->context.create_vs_state = r600_create_shader_state;
1738         rctx->context.bind_blend_state = r600_bind_blend_state;
1739         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1740         rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1741         rctx->context.bind_fs_state = r600_bind_ps_shader;
1742         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1743         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1744         rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1745         rctx->context.bind_vs_state = r600_bind_vs_shader;
1746         rctx->context.delete_blend_state = r600_delete_state;
1747         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1748         rctx->context.delete_fs_state = r600_delete_ps_shader;
1749         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1750         rctx->context.delete_sampler_state = r600_delete_state;
1751         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1752         rctx->context.delete_vs_state = r600_delete_vs_shader;
1753         rctx->context.set_blend_color = r600_set_blend_color;
1754         rctx->context.set_clip_state = r600_set_clip_state;
1755         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1756         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1757         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1758         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1759         rctx->context.set_sample_mask = r600_set_sample_mask;
1760         rctx->context.set_scissor_state = r600_set_scissor_state;
1761         rctx->context.set_stencil_ref = r600_set_stencil_ref;
1762         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1763         rctx->context.set_index_buffer = r600_set_index_buffer;
1764         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1765         rctx->context.set_viewport_state = r600_set_viewport_state;
1766         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1767         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1768         rctx->context.texture_barrier = r600_texture_barrier;
1769         rctx->context.create_stream_output_target = r600_create_so_target;
1770         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1771         rctx->context.set_stream_output_targets = r600_set_so_targets;
1772 }
1773
1774 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1775 {
1776         struct r600_pipe_state rstate;
1777         unsigned num_ps_gprs = rctx->default_ps_gprs;
1778         unsigned num_vs_gprs = rctx->default_vs_gprs;
1779         unsigned tmp;
1780         int diff;
1781
1782         if (rctx->chip_class >= EVERGREEN)
1783                 return;
1784
1785         if (!rctx->ps_shader || !rctx->vs_shader)
1786                 return;
1787
1788         if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1789         {
1790                 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1791                 num_vs_gprs -= diff;
1792                 num_ps_gprs += diff;
1793         }
1794
1795         if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1796         {
1797                 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1798                 num_ps_gprs -= diff;
1799                 num_vs_gprs += diff;
1800         }
1801
1802         tmp = 0;
1803         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1804         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1805         rstate.nregs = 0;
1806         r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL, 0);
1807
1808         r600_context_pipe_state_set(&rctx->ctx, &rstate);
1809 }
1810
1811 void r600_init_config(struct r600_pipe_context *rctx)
1812 {
1813         int ps_prio;
1814         int vs_prio;
1815         int gs_prio;
1816         int es_prio;
1817         int num_ps_gprs;
1818         int num_vs_gprs;
1819         int num_gs_gprs;
1820         int num_es_gprs;
1821         int num_temp_gprs;
1822         int num_ps_threads;
1823         int num_vs_threads;
1824         int num_gs_threads;
1825         int num_es_threads;
1826         int num_ps_stack_entries;
1827         int num_vs_stack_entries;
1828         int num_gs_stack_entries;
1829         int num_es_stack_entries;
1830         enum radeon_family family;
1831         struct r600_pipe_state *rstate = &rctx->config;
1832         u32 tmp;
1833
1834         family = rctx->family;
1835         ps_prio = 0;
1836         vs_prio = 1;
1837         gs_prio = 2;
1838         es_prio = 3;
1839         switch (family) {
1840         case CHIP_R600:
1841                 num_ps_gprs = 192;
1842                 num_vs_gprs = 56;
1843                 num_temp_gprs = 4;
1844                 num_gs_gprs = 0;
1845                 num_es_gprs = 0;
1846                 num_ps_threads = 136;
1847                 num_vs_threads = 48;
1848                 num_gs_threads = 4;
1849                 num_es_threads = 4;
1850                 num_ps_stack_entries = 128;
1851                 num_vs_stack_entries = 128;
1852                 num_gs_stack_entries = 0;
1853                 num_es_stack_entries = 0;
1854                 break;
1855         case CHIP_RV630:
1856         case CHIP_RV635:
1857                 num_ps_gprs = 84;
1858                 num_vs_gprs = 36;
1859                 num_temp_gprs = 4;
1860                 num_gs_gprs = 0;
1861                 num_es_gprs = 0;
1862                 num_ps_threads = 144;
1863                 num_vs_threads = 40;
1864                 num_gs_threads = 4;
1865                 num_es_threads = 4;
1866                 num_ps_stack_entries = 40;
1867                 num_vs_stack_entries = 40;
1868                 num_gs_stack_entries = 32;
1869                 num_es_stack_entries = 16;
1870                 break;
1871         case CHIP_RV610:
1872         case CHIP_RV620:
1873         case CHIP_RS780:
1874         case CHIP_RS880:
1875         default:
1876                 num_ps_gprs = 84;
1877                 num_vs_gprs = 36;
1878                 num_temp_gprs = 4;
1879                 num_gs_gprs = 0;
1880                 num_es_gprs = 0;
1881                 num_ps_threads = 136;
1882                 num_vs_threads = 48;
1883                 num_gs_threads = 4;
1884                 num_es_threads = 4;
1885                 num_ps_stack_entries = 40;
1886                 num_vs_stack_entries = 40;
1887                 num_gs_stack_entries = 32;
1888                 num_es_stack_entries = 16;
1889                 break;
1890         case CHIP_RV670:
1891                 num_ps_gprs = 144;
1892                 num_vs_gprs = 40;
1893                 num_temp_gprs = 4;
1894                 num_gs_gprs = 0;
1895                 num_es_gprs = 0;
1896                 num_ps_threads = 136;
1897                 num_vs_threads = 48;
1898                 num_gs_threads = 4;
1899                 num_es_threads = 4;
1900                 num_ps_stack_entries = 40;
1901                 num_vs_stack_entries = 40;
1902                 num_gs_stack_entries = 32;
1903                 num_es_stack_entries = 16;
1904                 break;
1905         case CHIP_RV770:
1906                 num_ps_gprs = 192;
1907                 num_vs_gprs = 56;
1908                 num_temp_gprs = 4;
1909                 num_gs_gprs = 0;
1910                 num_es_gprs = 0;
1911                 num_ps_threads = 188;
1912                 num_vs_threads = 60;
1913                 num_gs_threads = 0;
1914                 num_es_threads = 0;
1915                 num_ps_stack_entries = 256;
1916                 num_vs_stack_entries = 256;
1917                 num_gs_stack_entries = 0;
1918                 num_es_stack_entries = 0;
1919                 break;
1920         case CHIP_RV730:
1921         case CHIP_RV740:
1922                 num_ps_gprs = 84;
1923                 num_vs_gprs = 36;
1924                 num_temp_gprs = 4;
1925                 num_gs_gprs = 0;
1926                 num_es_gprs = 0;
1927                 num_ps_threads = 188;
1928                 num_vs_threads = 60;
1929                 num_gs_threads = 0;
1930                 num_es_threads = 0;
1931                 num_ps_stack_entries = 128;
1932                 num_vs_stack_entries = 128;
1933                 num_gs_stack_entries = 0;
1934                 num_es_stack_entries = 0;
1935                 break;
1936         case CHIP_RV710:
1937                 num_ps_gprs = 192;
1938                 num_vs_gprs = 56;
1939                 num_temp_gprs = 4;
1940                 num_gs_gprs = 0;
1941                 num_es_gprs = 0;
1942                 num_ps_threads = 144;
1943                 num_vs_threads = 48;
1944                 num_gs_threads = 0;
1945                 num_es_threads = 0;
1946                 num_ps_stack_entries = 128;
1947                 num_vs_stack_entries = 128;
1948                 num_gs_stack_entries = 0;
1949                 num_es_stack_entries = 0;
1950                 break;
1951         }
1952
1953         rctx->default_ps_gprs = num_ps_gprs;
1954         rctx->default_vs_gprs = num_vs_gprs;
1955
1956         rstate->id = R600_PIPE_STATE_CONFIG;
1957
1958         /* SQ_CONFIG */
1959         tmp = 0;
1960         switch (family) {
1961         case CHIP_RV610:
1962         case CHIP_RV620:
1963         case CHIP_RS780:
1964         case CHIP_RS880:
1965         case CHIP_RV710:
1966                 break;
1967         default:
1968                 tmp |= S_008C00_VC_ENABLE(1);
1969                 break;
1970         }
1971         tmp |= S_008C00_DX9_CONSTS(0);
1972         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1973         tmp |= S_008C00_PS_PRIO(ps_prio);
1974         tmp |= S_008C00_VS_PRIO(vs_prio);
1975         tmp |= S_008C00_GS_PRIO(gs_prio);
1976         tmp |= S_008C00_ES_PRIO(es_prio);
1977         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1978
1979         /* SQ_GPR_RESOURCE_MGMT_1 */
1980         tmp = 0;
1981         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1982         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1983         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1984         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1985
1986         /* SQ_GPR_RESOURCE_MGMT_2 */
1987         tmp = 0;
1988         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1989         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1990         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1991
1992         /* SQ_THREAD_RESOURCE_MGMT */
1993         tmp = 0;
1994         tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1995         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1996         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1997         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1998         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
1999
2000         /* SQ_STACK_RESOURCE_MGMT_1 */
2001         tmp = 0;
2002         tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2003         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2004         r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2005
2006         /* SQ_STACK_RESOURCE_MGMT_2 */
2007         tmp = 0;
2008         tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2009         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2010         r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2011
2012         r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2013         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL, 0);
2014
2015         if (rctx->chip_class >= R700) {
2016                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL, 0);
2017                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2018                                         S_009508_DISABLE_CUBE_ANISO(1) |
2019                                         S_009508_SYNC_GRADIENT(1) |
2020                                         S_009508_SYNC_WALKER(1) |
2021                                         S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2022                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0);
2023                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0);
2024                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0);
2025         } else {
2026                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0);
2027                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2028                                         S_009508_DISABLE_CUBE_ANISO(1) |
2029                                         S_009508_SYNC_GRADIENT(1) |
2030                                         S_009508_SYNC_WALKER(1) |
2031                                         S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2032                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0);
2033                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0);
2034                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0);
2035         }
2036         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2037         r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2038         r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2039         r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2040         r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2041         r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2042         r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2043         r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2044         r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2045         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2046         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2047         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2048         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2049         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL, 0);
2050         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2051         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2052         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2053         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2054         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2055         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2056         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2057         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2058         r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2059         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL, 0);
2060         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2061         r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2062
2063         r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL, 0);
2064         r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2065         r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2066         r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
2067         r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL, 0);
2068         r600_context_pipe_state_set(&rctx->ctx, rstate);
2069 }
2070
2071 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2072 {
2073         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2074         struct r600_pipe_state *rstate = &shader->rstate;
2075         struct r600_shader *rshader = &shader->shader;
2076         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2077         int pos_index = -1, face_index = -1;
2078         unsigned tmp, sid, ufi = 0;
2079
2080         rstate->nregs = 0;
2081
2082         for (i = 0; i < rshader->ninput; i++) {
2083                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2084                         pos_index = i;
2085                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2086                         face_index = i;
2087
2088                 sid = rshader->input[i].spi_sid;
2089
2090                 tmp = S_028644_SEMANTIC(sid);
2091
2092                 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
2093                                 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
2094                                 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
2095                         tmp |= S_028644_FLAT_SHADE(1);
2096                 }
2097
2098                 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2099                                 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2100                         tmp |= S_028644_PT_SPRITE_TEX(1);
2101                 }
2102
2103                 if (rshader->input[i].centroid)
2104                         tmp |= S_028644_SEL_CENTROID(1);
2105
2106                 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2107                         tmp |= S_028644_SEL_LINEAR(1);
2108
2109                 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2110                                 tmp, 0xFFFFFFFF, NULL, 0);
2111         }
2112
2113         db_shader_control = 0;
2114         for (i = 0; i < rshader->noutput; i++) {
2115                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2116                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2117                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2118                         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2119         }
2120         if (rshader->uses_kill)
2121                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2122
2123         exports_ps = 0;
2124         num_cout = 0;
2125         for (i = 0; i < rshader->noutput; i++) {
2126                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2127                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2128                         exports_ps |= 1;
2129                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2130                         num_cout++;
2131                 }
2132         }
2133         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2134         if (!exports_ps) {
2135                 /* always at least export 1 component per pixel */
2136                 exports_ps = 2;
2137         }
2138
2139         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2140                                 S_0286CC_PERSP_GRADIENT_ENA(1);
2141         spi_input_z = 0;
2142         if (pos_index != -1) {
2143                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2144                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2145                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2146                                         S_0286CC_BARYC_SAMPLE_CNTL(1));
2147                 spi_input_z |= 1;
2148         }
2149
2150         spi_ps_in_control_1 = 0;
2151         if (face_index != -1) {
2152                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2153                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2154         }
2155
2156         /* HW bug in original R600 */
2157         if (rctx->family == CHIP_R600)
2158                 ufi = 1;
2159
2160         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2161         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2162         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2163         r600_pipe_state_add_reg(rstate,
2164                                 R_028840_SQ_PGM_START_PS,
2165                                 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2166         r600_pipe_state_add_reg(rstate,
2167                                 R_028850_SQ_PGM_RESOURCES_PS,
2168                                 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2169                                 S_028850_STACK_SIZE(rshader->bc.nstack) |
2170                                 S_028850_UNCACHED_FIRST_INST(ufi),
2171                                 0xFFFFFFFF, NULL, 0);
2172         r600_pipe_state_add_reg(rstate,
2173                                 R_028854_SQ_PGM_EXPORTS_PS,
2174                                 exports_ps, 0xFFFFFFFF, NULL, 0);
2175         r600_pipe_state_add_reg(rstate,
2176                                 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2177                                 0x00000000, 0xFFFFFFFF, NULL, 0);
2178         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2179                                 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2180                                 S_028808_MULTIWRITE_ENABLE(1),
2181                                 NULL, 0);
2182         /* only set some bits here, the other bits are set in the dsa state */
2183         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2184                                 db_shader_control,
2185                                 S_02880C_Z_EXPORT_ENABLE(1) |
2186                                 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2187                                 S_02880C_KILL_ENABLE(1),
2188                                 NULL, 0);
2189
2190         r600_pipe_state_add_reg(rstate,
2191                                 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2192                                 0xFFFFFFFF, NULL, 0);
2193
2194         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2195 }
2196
2197 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2198 {
2199         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2200         struct r600_pipe_state *rstate = &shader->rstate;
2201         struct r600_shader *rshader = &shader->shader;
2202         unsigned spi_vs_out_id[10] = {};
2203         unsigned i, tmp, nparams = 0;
2204
2205         /* clear previous register */
2206         rstate->nregs = 0;
2207
2208         for (i = 0; i < rshader->noutput; i++) {
2209                 if (rshader->output[i].spi_sid) {
2210                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2211                         spi_vs_out_id[nparams / 4] |= tmp;
2212                         nparams++;
2213                 }
2214         }
2215
2216         for (i = 0; i < 10; i++) {
2217                 r600_pipe_state_add_reg(rstate,
2218                                         R_028614_SPI_VS_OUT_ID_0 + i * 4,
2219                                         spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2220         }
2221
2222         /* Certain attributes (position, psize, etc.) don't count as params.
2223          * VS is required to export at least one param and r600_shader_from_tgsi()
2224          * takes care of adding a dummy export.
2225          */
2226         if (nparams < 1)
2227                 nparams = 1;
2228
2229         r600_pipe_state_add_reg(rstate,
2230                         R_0286C4_SPI_VS_OUT_CONFIG,
2231                         S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2232                         0xFFFFFFFF, NULL, 0);
2233         r600_pipe_state_add_reg(rstate,
2234                         R_028868_SQ_PGM_RESOURCES_VS,
2235                         S_028868_NUM_GPRS(rshader->bc.ngpr) |
2236                         S_028868_STACK_SIZE(rshader->bc.nstack),
2237                         0xFFFFFFFF, NULL, 0);
2238         r600_pipe_state_add_reg(rstate,
2239                         R_0288D0_SQ_PGM_CF_OFFSET_VS,
2240                         0x00000000, 0xFFFFFFFF, NULL, 0);
2241         r600_pipe_state_add_reg(rstate,
2242                         R_028858_SQ_PGM_START_VS,
2243                         0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2244
2245         r600_pipe_state_add_reg(rstate,
2246                                 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2247                                 0xFFFFFFFF, NULL, 0);
2248
2249         r600_pipe_state_add_reg(rstate,
2250                                 R_02881C_PA_CL_VS_OUT_CNTL,
2251                                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2252                                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2253                                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write),
2254                                 S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
2255                                 S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
2256                                 S_02881C_VS_OUT_MISC_VEC_ENA(1),
2257                                 NULL, 0);
2258 }
2259
2260 void r600_fetch_shader(struct pipe_context *ctx,
2261                        struct r600_vertex_element *ve)
2262 {
2263         struct r600_pipe_state *rstate;
2264         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2265
2266         rstate = &ve->rstate;
2267         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2268         rstate->nregs = 0;
2269         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2270                                 0x00000000, 0xFFFFFFFF, NULL, 0);
2271         r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2272                                 0x00000000, 0xFFFFFFFF, NULL, 0);
2273         r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2274                                 0,
2275                                 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2276 }
2277
2278 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2279 {
2280         struct pipe_depth_stencil_alpha_state dsa;
2281         struct r600_pipe_state *rstate;
2282         boolean quirk = false;
2283
2284         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2285                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2286                 quirk = true;
2287
2288         memset(&dsa, 0, sizeof(dsa));
2289
2290         if (quirk) {
2291                 dsa.depth.enabled = 1;
2292                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2293                 dsa.stencil[0].enabled = 1;
2294                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2295                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2296                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2297                 dsa.stencil[0].writemask = 0xff;
2298         }
2299
2300         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2301         r600_pipe_state_add_reg(rstate,
2302                                 R_02880C_DB_SHADER_CONTROL,
2303                                 0x0,
2304                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2305         r600_pipe_state_add_reg(rstate,
2306                                 R_028D0C_DB_RENDER_CONTROL,
2307                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2308                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2309                                 S_028D0C_COPY_CENTROID(1),
2310                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2311                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2312                                 S_028D0C_COPY_CENTROID(1), NULL, 0);
2313         return rstate;
2314 }
2315
2316 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2317                                     struct r600_pipe_resource_state *rstate)
2318 {
2319         rstate->id = R600_PIPE_STATE_RESOURCE;
2320
2321         rstate->bo[0] = NULL;
2322         rstate->val[0] = 0;
2323         rstate->val[1] = 0;
2324         rstate->val[2] = 0;
2325         rstate->val[3] = 0;
2326         rstate->val[4] = 0;
2327         rstate->val[5] = 0;
2328         rstate->val[6] = 0xc0000000;
2329 }
2330
2331 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2332                                    struct r600_resource *rbuffer,
2333                                    unsigned offset, unsigned stride,
2334                                    enum radeon_bo_usage usage)
2335 {
2336         rstate->val[0] = offset;
2337         rstate->bo[0] = rbuffer;
2338         rstate->bo_usage[0] = usage;
2339         rstate->val[1] = rbuffer->buf->size - offset - 1;
2340         rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2341                          S_038008_STRIDE(stride);
2342 }