src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include "pipe/p_defines.h"
  30 #include "pipe/p_state.h"
  31 #include "pipe/p_context.h"
  32 #include "tgsi/tgsi_scan.h"
  33 #include "tgsi/tgsi_parse.h"
  34 #include "tgsi/tgsi_util.h"
  35 #include "util/u_double_list.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_framebuffer.h"
  40 #include "util/u_transfer.h"
  41 #include "pipebuffer/pb_buffer.h"
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "r600_resource.h"
  45 #include "r600_shader.h"
  46 #include "r600_pipe.h"
  47 #include "r600_formats.h"
  48
  49 static uint32_t r600_translate_blend_function(int blend_func)
  50 {
  51         switch (blend_func) {
  52         case PIPE_BLEND_ADD:
  53                 return V_028804_COMB_DST_PLUS_SRC;
  54         case PIPE_BLEND_SUBTRACT:
  55                 return V_028804_COMB_SRC_MINUS_DST;
  56         case PIPE_BLEND_REVERSE_SUBTRACT:
  57                 return V_028804_COMB_DST_MINUS_SRC;
  58         case PIPE_BLEND_MIN:
  59                 return V_028804_COMB_MIN_DST_SRC;
  60         case PIPE_BLEND_MAX:
  61                 return V_028804_COMB_MAX_DST_SRC;
  62         default:
  63                 R600_ERR("Unknown blend function %d\n", blend_func);
  64                 assert(0);
  65                 break;
  66         }
  67         return 0;
  68 }
  69
  70 static uint32_t r600_translate_blend_factor(int blend_fact)
  71 {
  72         switch (blend_fact) {
  73         case PIPE_BLENDFACTOR_ONE:
  74                 return V_028804_BLEND_ONE;
  75         case PIPE_BLENDFACTOR_SRC_COLOR:
  76                 return V_028804_BLEND_SRC_COLOR;
  77         case PIPE_BLENDFACTOR_SRC_ALPHA:
  78                 return V_028804_BLEND_SRC_ALPHA;
  79         case PIPE_BLENDFACTOR_DST_ALPHA:
  80                 return V_028804_BLEND_DST_ALPHA;
  81         case PIPE_BLENDFACTOR_DST_COLOR:
  82                 return V_028804_BLEND_DST_COLOR;
  83         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  84                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  85         case PIPE_BLENDFACTOR_CONST_COLOR:
  86                 return V_028804_BLEND_CONST_COLOR;
  87         case PIPE_BLENDFACTOR_CONST_ALPHA:
  88                 return V_028804_BLEND_CONST_ALPHA;
  89         case PIPE_BLENDFACTOR_ZERO:
  90                 return V_028804_BLEND_ZERO;
  91         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  92                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  93         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  94                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  95         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  96                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  97         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  98                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  99         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 100                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
 101         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 102                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
 103         case PIPE_BLENDFACTOR_SRC1_COLOR:
 104                 return V_028804_BLEND_SRC1_COLOR;
 105         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 106                 return V_028804_BLEND_SRC1_ALPHA;
 107         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 108                 return V_028804_BLEND_INV_SRC1_COLOR;
 109         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 110                 return V_028804_BLEND_INV_SRC1_ALPHA;
 111         default:
 112                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 113                 assert(0);
 114                 break;
 115         }
 116         return 0;
 117 }
 118
 119 static uint32_t r600_translate_stencil_op(int s_op)
 120 {
 121         switch (s_op) {
 122         case PIPE_STENCIL_OP_KEEP:
 123                 return V_028800_STENCIL_KEEP;
 124         case PIPE_STENCIL_OP_ZERO:
 125                 return V_028800_STENCIL_ZERO;
 126         case PIPE_STENCIL_OP_REPLACE:
 127                 return V_028800_STENCIL_REPLACE;
 128         case PIPE_STENCIL_OP_INCR:
 129                 return V_028800_STENCIL_INCR;
 130         case PIPE_STENCIL_OP_DECR:
 131                 return V_028800_STENCIL_DECR;
 132         case PIPE_STENCIL_OP_INCR_WRAP:
 133                 return V_028800_STENCIL_INCR_WRAP;
 134         case PIPE_STENCIL_OP_DECR_WRAP:
 135                 return V_028800_STENCIL_DECR_WRAP;
 136         case PIPE_STENCIL_OP_INVERT:
 137                 return V_028800_STENCIL_INVERT;
 138         default:
 139                 R600_ERR("Unknown stencil op %d", s_op);
 140                 assert(0);
 141                 break;
 142         }
 143         return 0;
 144 }
 145
 146 static uint32_t r600_translate_fill(uint32_t func)
 147 {
 148         switch(func) {
 149         case PIPE_POLYGON_MODE_FILL:
 150                 return 2;
 151         case PIPE_POLYGON_MODE_LINE:
 152                 return 1;
 153         case PIPE_POLYGON_MODE_POINT:
 154                 return 0;
 155         default:
 156                 assert(0);
 157                 return 0;
 158         }
 159 }
 160
 161 /* translates straight */
 162 static uint32_t r600_translate_ds_func(int func)
 163 {
 164         return func;
 165 }
 166
 167 static unsigned r600_tex_wrap(unsigned wrap)
 168 {
 169         switch (wrap) {
 170         default:
 171         case PIPE_TEX_WRAP_REPEAT:
 172                 return V_03C000_SQ_TEX_WRAP;
 173         case PIPE_TEX_WRAP_CLAMP:
 174                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 175         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 176                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 177         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 178                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 179         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 180                 return V_03C000_SQ_TEX_MIRROR;
 181         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 182                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 183         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 184                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 185         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 186                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 187         }
 188 }
 189
 190 static unsigned r600_tex_filter(unsigned filter)
 191 {
 192         switch (filter) {
 193         default:
 194         case PIPE_TEX_FILTER_NEAREST:
 195                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 196         case PIPE_TEX_FILTER_LINEAR:
 197                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 198         }
 199 }
 200
 201 static unsigned r600_tex_mipfilter(unsigned filter)
 202 {
 203         switch (filter) {
 204         case PIPE_TEX_MIPFILTER_NEAREST:
 205                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 206         case PIPE_TEX_MIPFILTER_LINEAR:
 207                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 208         default:
 209         case PIPE_TEX_MIPFILTER_NONE:
 210                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 211         }
 212 }
 213
 214 static unsigned r600_tex_compare(unsigned compare)
 215 {
 216         switch (compare) {
 217         default:
 218         case PIPE_FUNC_NEVER:
 219                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 220         case PIPE_FUNC_LESS:
 221                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 222         case PIPE_FUNC_EQUAL:
 223                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 224         case PIPE_FUNC_LEQUAL:
 225                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 226         case PIPE_FUNC_GREATER:
 227                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 228         case PIPE_FUNC_NOTEQUAL:
 229                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 230         case PIPE_FUNC_GEQUAL:
 231                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 232         case PIPE_FUNC_ALWAYS:
 233                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 234         }
 235 }
 236
 237 static unsigned r600_tex_dim(unsigned dim)
 238 {
 239         switch (dim) {
 240         default:
 241         case PIPE_TEXTURE_1D:
 242                 return V_038000_SQ_TEX_DIM_1D;
 243         case PIPE_TEXTURE_1D_ARRAY:
 244                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 245         case PIPE_TEXTURE_2D:
 246         case PIPE_TEXTURE_RECT:
 247                 return V_038000_SQ_TEX_DIM_2D;
 248         case PIPE_TEXTURE_2D_ARRAY:
 249                 return V_038000_SQ_TEX_DIM_2D_ARRAY;
 250         case PIPE_TEXTURE_3D:
 251                 return V_038000_SQ_TEX_DIM_3D;
 252         case PIPE_TEXTURE_CUBE:
 253                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 254         }
 255 }
 256
 257 static uint32_t r600_translate_dbformat(enum pipe_format format)
 258 {
 259         switch (format) {
 260         case PIPE_FORMAT_Z16_UNORM:
 261                 return V_028010_DEPTH_16;
 262         case PIPE_FORMAT_Z24X8_UNORM:
 263                 return V_028010_DEPTH_X8_24;
 264         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 265                 return V_028010_DEPTH_8_24;
 266         case PIPE_FORMAT_Z32_FLOAT:
 267                 return V_028010_DEPTH_32_FLOAT;
 268         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 269                 return V_028010_DEPTH_X24_8_32_FLOAT;
 270         default:
 271                 return ~0U;
 272         }
 273 }
 274
 275 static uint32_t r600_translate_colorswap(enum pipe_format format)
 276 {
 277         switch (format) {
 278         /* 8-bit buffers. */
 279         case PIPE_FORMAT_A8_UNORM:
 280         case PIPE_FORMAT_A8_UINT:
 281         case PIPE_FORMAT_A8_SINT:
 282         case PIPE_FORMAT_R4A4_UNORM:
 283                 return V_0280A0_SWAP_ALT_REV;
 284         case PIPE_FORMAT_I8_UNORM:
 285         case PIPE_FORMAT_L8_UNORM:
 286         case PIPE_FORMAT_I8_UINT:
 287         case PIPE_FORMAT_I8_SINT:
 288         case PIPE_FORMAT_L8_UINT:
 289         case PIPE_FORMAT_L8_SINT:
 290         case PIPE_FORMAT_L8_SRGB:
 291         case PIPE_FORMAT_R8_UNORM:
 292         case PIPE_FORMAT_R8_SNORM:
 293                 return V_0280A0_SWAP_STD;
 294
 295         case PIPE_FORMAT_L4A4_UNORM:
 296         case PIPE_FORMAT_A4R4_UNORM:
 297                 return V_0280A0_SWAP_ALT;
 298
 299         /* 16-bit buffers. */
 300         case PIPE_FORMAT_B5G6R5_UNORM:
 301                 return V_0280A0_SWAP_STD_REV;
 302
 303         case PIPE_FORMAT_B5G5R5A1_UNORM:
 304         case PIPE_FORMAT_B5G5R5X1_UNORM:
 305                 return V_0280A0_SWAP_ALT;
 306
 307         case PIPE_FORMAT_B4G4R4A4_UNORM:
 308         case PIPE_FORMAT_B4G4R4X4_UNORM:
 309                 return V_0280A0_SWAP_ALT;
 310
 311         case PIPE_FORMAT_Z16_UNORM:
 312                 return V_0280A0_SWAP_STD;
 313
 314         case PIPE_FORMAT_L8A8_UNORM:
 315         case PIPE_FORMAT_L8A8_UINT:
 316         case PIPE_FORMAT_L8A8_SINT:
 317         case PIPE_FORMAT_L8A8_SRGB:
 318                 return V_0280A0_SWAP_ALT;
 319         case PIPE_FORMAT_R8G8_UNORM:
 320         case PIPE_FORMAT_R8G8_UINT:
 321         case PIPE_FORMAT_R8G8_SINT:
 322                 return V_0280A0_SWAP_STD;
 323
 324         case PIPE_FORMAT_R16_UNORM:
 325         case PIPE_FORMAT_R16_UINT:
 326         case PIPE_FORMAT_R16_SINT:
 327         case PIPE_FORMAT_R16_FLOAT:
 328                 return V_0280A0_SWAP_STD;
 329
 330         /* 32-bit buffers. */
 331
 332         case PIPE_FORMAT_A8B8G8R8_SRGB:
 333                 return V_0280A0_SWAP_STD_REV;
 334         case PIPE_FORMAT_B8G8R8A8_SRGB:
 335                 return V_0280A0_SWAP_ALT;
 336
 337         case PIPE_FORMAT_B8G8R8A8_UNORM:
 338         case PIPE_FORMAT_B8G8R8X8_UNORM:
 339                 return V_0280A0_SWAP_ALT;
 340
 341         case PIPE_FORMAT_A8R8G8B8_UNORM:
 342         case PIPE_FORMAT_X8R8G8B8_UNORM:
 343                 return V_0280A0_SWAP_ALT_REV;
 344         case PIPE_FORMAT_R8G8B8A8_SNORM:
 345         case PIPE_FORMAT_R8G8B8A8_UNORM:
 346         case PIPE_FORMAT_R8G8B8X8_UNORM:
 347         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 348         case PIPE_FORMAT_R8G8B8A8_USCALED:
 349         case PIPE_FORMAT_R8G8B8A8_SINT:
 350         case PIPE_FORMAT_R8G8B8A8_UINT:
 351                 return V_0280A0_SWAP_STD;
 352
 353         case PIPE_FORMAT_A8B8G8R8_UNORM:
 354         case PIPE_FORMAT_X8B8G8R8_UNORM:
 355         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 356                 return V_0280A0_SWAP_STD_REV;
 357
 358         case PIPE_FORMAT_Z24X8_UNORM:
 359         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 360                 return V_0280A0_SWAP_STD;
 361
 362         case PIPE_FORMAT_X8Z24_UNORM:
 363         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 364                 return V_0280A0_SWAP_STD;
 365
 366         case PIPE_FORMAT_R10G10B10A2_UNORM:
 367         case PIPE_FORMAT_R10G10B10X2_SNORM:
 368         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 369                 return V_0280A0_SWAP_STD;
 370
 371         case PIPE_FORMAT_B10G10R10A2_UNORM:
 372         case PIPE_FORMAT_B10G10R10A2_UINT:
 373                 return V_0280A0_SWAP_ALT;
 374
 375         case PIPE_FORMAT_R11G11B10_FLOAT:
 376         case PIPE_FORMAT_R16G16_UNORM:
 377         case PIPE_FORMAT_R16G16_FLOAT:
 378         case PIPE_FORMAT_R16G16_UINT:
 379         case PIPE_FORMAT_R16G16_SINT:
 380         case PIPE_FORMAT_R32_UINT:
 381         case PIPE_FORMAT_R32_SINT:
 382         case PIPE_FORMAT_R32_FLOAT:
 383         case PIPE_FORMAT_Z32_FLOAT:
 384                 return V_0280A0_SWAP_STD;
 385
 386         /* 64-bit buffers. */
 387         case PIPE_FORMAT_R32G32_FLOAT:
 388         case PIPE_FORMAT_R32G32_UINT:
 389         case PIPE_FORMAT_R32G32_SINT:
 390         case PIPE_FORMAT_R16G16B16A16_UNORM:
 391         case PIPE_FORMAT_R16G16B16A16_SNORM:
 392         case PIPE_FORMAT_R16G16B16A16_USCALED:
 393         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 394         case PIPE_FORMAT_R16G16B16A16_UINT:
 395         case PIPE_FORMAT_R16G16B16A16_SINT:
 396         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 397         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 398
 399         /* 128-bit buffers. */
 400         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 401         case PIPE_FORMAT_R32G32B32A32_SNORM:
 402         case PIPE_FORMAT_R32G32B32A32_UNORM:
 403         case PIPE_FORMAT_R32G32B32A32_USCALED:
 404         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 405         case PIPE_FORMAT_R32G32B32A32_SINT:
 406         case PIPE_FORMAT_R32G32B32A32_UINT:
 407                 return V_0280A0_SWAP_STD;
 408         default:
 409                 R600_ERR("unsupported colorswap format %d\n", format);
 410                 return ~0U;
 411         }
 412         return ~0U;
 413 }
 414
 415 static uint32_t r600_translate_colorformat(enum pipe_format format)
 416 {
 417         switch (format) {
 418         case PIPE_FORMAT_L4A4_UNORM:
 419         case PIPE_FORMAT_R4A4_UNORM:
 420         case PIPE_FORMAT_A4R4_UNORM:
 421                 return V_0280A0_COLOR_4_4;
 422
 423         /* 8-bit buffers. */
 424         case PIPE_FORMAT_A8_UNORM:
 425         case PIPE_FORMAT_A8_UINT:
 426         case PIPE_FORMAT_A8_SINT:
 427         case PIPE_FORMAT_I8_UNORM:
 428         case PIPE_FORMAT_I8_UINT:
 429         case PIPE_FORMAT_I8_SINT:
 430         case PIPE_FORMAT_L8_UNORM:
 431         case PIPE_FORMAT_L8_UINT:
 432         case PIPE_FORMAT_L8_SINT:
 433         case PIPE_FORMAT_L8_SRGB:
 434         case PIPE_FORMAT_R8_UNORM:
 435         case PIPE_FORMAT_R8_SNORM:
 436         case PIPE_FORMAT_R8_UINT:
 437         case PIPE_FORMAT_R8_SINT:
 438                 return V_0280A0_COLOR_8;
 439
 440         /* 16-bit buffers. */
 441         case PIPE_FORMAT_B5G6R5_UNORM:
 442                 return V_0280A0_COLOR_5_6_5;
 443
 444         case PIPE_FORMAT_B5G5R5A1_UNORM:
 445         case PIPE_FORMAT_B5G5R5X1_UNORM:
 446                 return V_0280A0_COLOR_1_5_5_5;
 447
 448         case PIPE_FORMAT_B4G4R4A4_UNORM:
 449         case PIPE_FORMAT_B4G4R4X4_UNORM:
 450                 return V_0280A0_COLOR_4_4_4_4;
 451
 452         case PIPE_FORMAT_Z16_UNORM:
 453                 return V_0280A0_COLOR_16;
 454
 455         case PIPE_FORMAT_L8A8_UNORM:
 456         case PIPE_FORMAT_L8A8_UINT:
 457         case PIPE_FORMAT_L8A8_SINT:
 458         case PIPE_FORMAT_L8A8_SRGB:
 459         case PIPE_FORMAT_R8G8_UNORM:
 460         case PIPE_FORMAT_R8G8_UINT:
 461         case PIPE_FORMAT_R8G8_SINT:
 462                 return V_0280A0_COLOR_8_8;
 463
 464         case PIPE_FORMAT_R16_UNORM:
 465         case PIPE_FORMAT_R16_UINT:
 466         case PIPE_FORMAT_R16_SINT:
 467                 return V_0280A0_COLOR_16;
 468
 469         case PIPE_FORMAT_R16_FLOAT:
 470                 return V_0280A0_COLOR_16_FLOAT;
 471
 472         /* 32-bit buffers. */
 473         case PIPE_FORMAT_A8B8G8R8_SRGB:
 474         case PIPE_FORMAT_A8B8G8R8_UNORM:
 475         case PIPE_FORMAT_A8R8G8B8_UNORM:
 476         case PIPE_FORMAT_B8G8R8A8_SRGB:
 477         case PIPE_FORMAT_B8G8R8A8_UNORM:
 478         case PIPE_FORMAT_B8G8R8X8_UNORM:
 479         case PIPE_FORMAT_R8G8B8A8_SNORM:
 480         case PIPE_FORMAT_R8G8B8A8_UNORM:
 481         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 482         case PIPE_FORMAT_R8G8B8A8_USCALED:
 483         case PIPE_FORMAT_R8G8B8X8_UNORM:
 484         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 485         case PIPE_FORMAT_X8B8G8R8_UNORM:
 486         case PIPE_FORMAT_X8R8G8B8_UNORM:
 487         case PIPE_FORMAT_R8G8B8_UNORM:
 488         case PIPE_FORMAT_R8G8B8A8_SINT:
 489         case PIPE_FORMAT_R8G8B8A8_UINT:
 490                 return V_0280A0_COLOR_8_8_8_8;
 491
 492         case PIPE_FORMAT_R10G10B10A2_UNORM:
 493         case PIPE_FORMAT_R10G10B10X2_SNORM:
 494         case PIPE_FORMAT_B10G10R10A2_UNORM:
 495         case PIPE_FORMAT_B10G10R10A2_UINT:
 496         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 497                 return V_0280A0_COLOR_2_10_10_10;
 498
 499         case PIPE_FORMAT_Z24X8_UNORM:
 500         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 501                 return V_0280A0_COLOR_8_24;
 502
 503         case PIPE_FORMAT_X8Z24_UNORM:
 504         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 505                 return V_0280A0_COLOR_24_8;
 506
 507         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 508                 return V_0280A0_COLOR_X24_8_32_FLOAT;
 509
 510         case PIPE_FORMAT_R32_FLOAT:
 511         case PIPE_FORMAT_Z32_FLOAT:
 512                 return V_0280A0_COLOR_32_FLOAT;
 513
 514         case PIPE_FORMAT_R16G16_FLOAT:
 515                 return V_0280A0_COLOR_16_16_FLOAT;
 516
 517         case PIPE_FORMAT_R16G16_SSCALED:
 518         case PIPE_FORMAT_R16G16_UNORM:
 519         case PIPE_FORMAT_R16G16_UINT:
 520         case PIPE_FORMAT_R16G16_SINT:
 521                 return V_0280A0_COLOR_16_16;
 522
 523         case PIPE_FORMAT_R11G11B10_FLOAT:
 524                 return V_0280A0_COLOR_10_11_11_FLOAT;
 525
 526         /* 64-bit buffers. */
 527         case PIPE_FORMAT_R16G16B16_USCALED:
 528         case PIPE_FORMAT_R16G16B16A16_USCALED:
 529         case PIPE_FORMAT_R16G16B16_SSCALED:
 530         case PIPE_FORMAT_R16G16B16A16_UINT:
 531         case PIPE_FORMAT_R16G16B16A16_SINT:
 532         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 533         case PIPE_FORMAT_R16G16B16A16_UNORM:
 534         case PIPE_FORMAT_R16G16B16A16_SNORM:
 535                 return V_0280A0_COLOR_16_16_16_16;
 536
 537         case PIPE_FORMAT_R16G16B16_FLOAT:
 538         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 539                 return V_0280A0_COLOR_16_16_16_16_FLOAT;
 540
 541         case PIPE_FORMAT_R32G32_FLOAT:
 542                 return V_0280A0_COLOR_32_32_FLOAT;
 543
 544         case PIPE_FORMAT_R32G32_USCALED:
 545         case PIPE_FORMAT_R32G32_SSCALED:
 546         case PIPE_FORMAT_R32G32_SINT:
 547         case PIPE_FORMAT_R32G32_UINT:
 548                 return V_0280A0_COLOR_32_32;
 549
 550         /* 96-bit buffers. */
 551         case PIPE_FORMAT_R32G32B32_FLOAT:
 552                 return V_0280A0_COLOR_32_32_32_FLOAT;
 553
 554         /* 128-bit buffers. */
 555         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 556                 return V_0280A0_COLOR_32_32_32_32_FLOAT;
 557         case PIPE_FORMAT_R32G32B32A32_SNORM:
 558         case PIPE_FORMAT_R32G32B32A32_UNORM:
 559         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 560         case PIPE_FORMAT_R32G32B32A32_USCALED:
 561         case PIPE_FORMAT_R32G32B32A32_SINT:
 562         case PIPE_FORMAT_R32G32B32A32_UINT:
 563                 return V_0280A0_COLOR_32_32_32_32;
 564
 565         /* YUV buffers. */
 566         case PIPE_FORMAT_UYVY:
 567         case PIPE_FORMAT_YUYV:
 568         default:
 569                 return ~0U; /* Unsupported. */
 570         }
 571 }
 572
 573 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 574 {
 575         if (R600_BIG_ENDIAN) {
 576                 switch(colorformat) {
 577                 case V_0280A0_COLOR_4_4:
 578                         return ENDIAN_NONE;
 579
 580                 /* 8-bit buffers. */
 581                 case V_0280A0_COLOR_8:
 582                         return ENDIAN_NONE;
 583
 584                 /* 16-bit buffers. */
 585                 case V_0280A0_COLOR_5_6_5:
 586                 case V_0280A0_COLOR_1_5_5_5:
 587                 case V_0280A0_COLOR_4_4_4_4:
 588                 case V_0280A0_COLOR_16:
 589                 case V_0280A0_COLOR_8_8:
 590                         return ENDIAN_8IN16;
 591
 592                 /* 32-bit buffers. */
 593                 case V_0280A0_COLOR_8_8_8_8:
 594                 case V_0280A0_COLOR_2_10_10_10:
 595                 case V_0280A0_COLOR_8_24:
 596                 case V_0280A0_COLOR_24_8:
 597                 case V_0280A0_COLOR_32_FLOAT:
 598                 case V_0280A0_COLOR_16_16_FLOAT:
 599                 case V_0280A0_COLOR_16_16:
 600                         return ENDIAN_8IN32;
 601
 602                 /* 64-bit buffers. */
 603                 case V_0280A0_COLOR_16_16_16_16:
 604                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
 605                         return ENDIAN_8IN16;
 606
 607                 case V_0280A0_COLOR_32_32_FLOAT:
 608                 case V_0280A0_COLOR_32_32:
 609                 case V_0280A0_COLOR_X24_8_32_FLOAT:
 610                         return ENDIAN_8IN32;
 611
 612                 /* 128-bit buffers. */
 613                 case V_0280A0_COLOR_32_32_32_FLOAT:
 614                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
 615                 case V_0280A0_COLOR_32_32_32_32:
 616                         return ENDIAN_8IN32;
 617                 default:
 618                         return ENDIAN_NONE; /* Unsupported. */
 619                 }
 620         } else {
 621                 return ENDIAN_NONE;
 622         }
 623 }
 624
 625 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 626 {
 627         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 628 }
 629
 630 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 631 {
 632         return r600_translate_colorformat(format) != ~0U &&
 633                r600_translate_colorswap(format) != ~0U;
 634 }
 635
 636 static bool r600_is_zs_format_supported(enum pipe_format format)
 637 {
 638         return r600_translate_dbformat(format) != ~0U;
 639 }
 640
 641 boolean r600_is_format_supported(struct pipe_screen *screen,
 642                                  enum pipe_format format,
 643                                  enum pipe_texture_target target,
 644                                  unsigned sample_count,
 645                                  unsigned usage)
 646 {
 647         unsigned retval = 0;
 648
 649         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 650                 R600_ERR("r600: unsupported texture type %d\n", target);
 651                 return FALSE;
 652         }
 653
 654         if (!util_format_is_supported(format, usage))
 655                 return FALSE;
 656
 657         /* Multisample */
 658         if (sample_count > 1)
 659                 return FALSE;
 660
 661         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 662             r600_is_sampler_format_supported(screen, format)) {
 663                 retval |= PIPE_BIND_SAMPLER_VIEW;
 664         }
 665
 666         if ((usage & (PIPE_BIND_RENDER_TARGET |
 667                       PIPE_BIND_DISPLAY_TARGET |
 668                       PIPE_BIND_SCANOUT |
 669                       PIPE_BIND_SHARED)) &&
 670             r600_is_colorbuffer_format_supported(format)) {
 671                 retval |= usage &
 672                           (PIPE_BIND_RENDER_TARGET |
 673                            PIPE_BIND_DISPLAY_TARGET |
 674                            PIPE_BIND_SCANOUT |
 675                            PIPE_BIND_SHARED);
 676         }
 677
 678         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 679             r600_is_zs_format_supported(format)) {
 680                 retval |= PIPE_BIND_DEPTH_STENCIL;
 681         }
 682
 683         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 684             r600_is_vertex_format_supported(format)) {
 685                 retval |= PIPE_BIND_VERTEX_BUFFER;
 686         }
 687
 688         if (usage & PIPE_BIND_TRANSFER_READ)
 689                 retval |= PIPE_BIND_TRANSFER_READ;
 690         if (usage & PIPE_BIND_TRANSFER_WRITE)
 691                 retval |= PIPE_BIND_TRANSFER_WRITE;
 692
 693         return retval == usage;
 694 }
 695
 696 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
 697 {
 698         struct r600_pipe_state state;
 699
 700         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
 701         state.nregs = 0;
 702         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 703                 float offset_units = rctx->rasterizer->offset_units;
 704                 unsigned offset_db_fmt_cntl = 0, depth;
 705
 706                 switch (rctx->framebuffer.zsbuf->texture->format) {
 707                 case PIPE_FORMAT_Z24X8_UNORM:
 708                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 709                         depth = -24;
 710                         offset_units *= 2.0f;
 711                         break;
 712                 case PIPE_FORMAT_Z32_FLOAT:
 713                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 714                         depth = -23;
 715                         offset_units *= 1.0f;
 716                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 717                         break;
 718                 case PIPE_FORMAT_Z16_UNORM:
 719                         depth = -16;
 720                         offset_units *= 4.0f;
 721                         break;
 722                 default:
 723                         return;
 724                 }
 725                 /* FIXME some of those reg can be computed with cso */
 726                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 727                 r600_pipe_state_add_reg(&state,
 728                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 729                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
 730                 r600_pipe_state_add_reg(&state,
 731                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 732                                 fui(offset_units), 0xFFFFFFFF, NULL, 0);
 733                 r600_pipe_state_add_reg(&state,
 734                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 735                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
 736                 r600_pipe_state_add_reg(&state,
 737                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 738                                 fui(offset_units), 0xFFFFFFFF, NULL, 0);
 739                 r600_pipe_state_add_reg(&state,
 740                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 741                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
 742                 r600_context_pipe_state_set(&rctx->ctx, &state);
 743         }
 744 }
 745
 746 static void r600_set_blend_color(struct pipe_context *ctx,
 747                                         const struct pipe_blend_color *state)
 748 {
 749         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 750         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 751
 752         if (rstate == NULL)
 753                 return;
 754
 755         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 756         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
 757         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
 758         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
 759         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
 760         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 761         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 762         r600_context_pipe_state_set(&rctx->ctx, rstate);
 763 }
 764
 765 static void *r600_create_blend_state(struct pipe_context *ctx,
 766                                         const struct pipe_blend_state *state)
 767 {
 768         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 769         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 770         struct r600_pipe_state *rstate;
 771         u32 color_control = 0, target_mask;
 772
 773         if (blend == NULL) {
 774                 return NULL;
 775         }
 776         rstate = &blend->rstate;
 777
 778         rstate->id = R600_PIPE_STATE_BLEND;
 779
 780         target_mask = 0;
 781
 782         /* R600 does not support per-MRT blends */
 783         if (rctx->family > CHIP_R600)
 784                 color_control |= S_028808_PER_MRT_BLEND(1);
 785         if (state->logicop_enable) {
 786                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 787         } else {
 788                 color_control |= (0xcc << 16);
 789         }
 790         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 791         if (state->independent_blend_enable) {
 792                 for (int i = 0; i < 8; i++) {
 793                         if (state->rt[i].blend_enable) {
 794                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 795                         }
 796                         target_mask |= (state->rt[i].colormask << (4 * i));
 797                 }
 798         } else {
 799                 for (int i = 0; i < 8; i++) {
 800                         if (state->rt[0].blend_enable) {
 801                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 802                         }
 803                         target_mask |= (state->rt[0].colormask << (4 * i));
 804                 }
 805         }
 806         blend->cb_target_mask = target_mask;
 807         /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
 808         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 809                                 color_control, 0xFFFFFFFD, NULL, 0);
 810
 811         for (int i = 0; i < 8; i++) {
 812                 /* state->rt entries > 0 only written if independent blending */
 813                 const int j = state->independent_blend_enable ? i : 0;
 814
 815                 unsigned eqRGB = state->rt[j].rgb_func;
 816                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 817                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 818
 819                 unsigned eqA = state->rt[j].alpha_func;
 820                 unsigned srcA = state->rt[j].alpha_src_factor;
 821                 unsigned dstA = state->rt[j].alpha_dst_factor;
 822                 uint32_t bc = 0;
 823
 824                 if (!state->rt[j].blend_enable)
 825                         continue;
 826
 827                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 828                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 829                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 830
 831                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 832                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 833                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 834                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 835                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 836                 }
 837
 838                 /* R600 does not support per-MRT blends */
 839                 if (rctx->family > CHIP_R600)
 840                         r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL, 0);
 841                 if (i == 0)
 842                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL, 0);
 843         }
 844         return rstate;
 845 }
 846
 847 static void *r600_create_dsa_state(struct pipe_context *ctx,
 848                                    const struct pipe_depth_stencil_alpha_state *state)
 849 {
 850         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 851         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 852         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 853         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 854         struct r600_pipe_state *rstate;
 855
 856         if (dsa == NULL) {
 857                 return NULL;
 858         }
 859
 860         rstate = &dsa->rstate;
 861
 862         rstate->id = R600_PIPE_STATE_DSA;
 863         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 864         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 865         stencil_ref_mask = 0;
 866         stencil_ref_mask_bf = 0;
 867         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 868                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 869                 S_028800_ZFUNC(state->depth.func);
 870
 871         /* stencil */
 872         if (state->stencil[0].enabled) {
 873                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 874                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 875                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 876                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 877                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 878
 879
 880                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 881                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 882                 if (state->stencil[1].enabled) {
 883                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 884                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 885                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 886                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 887                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 888                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 889                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 890                 }
 891         }
 892
 893         /* alpha */
 894         alpha_test_control = 0;
 895         alpha_ref = 0;
 896         if (state->alpha.enabled) {
 897                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 898                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 899                 alpha_ref = fui(state->alpha.ref_value);
 900         }
 901         dsa->alpha_ref = alpha_ref;
 902
 903         /* misc */
 904         db_render_control = 0;
 905         db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 906                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 907                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
 908         /* TODO db_render_override depends on query */
 909         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
 910         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
 911         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
 912         r600_pipe_state_add_reg(rstate,
 913                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 914                                 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
 915         r600_pipe_state_add_reg(rstate,
 916                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 917                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
 918         r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
 919         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
 920         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
 921         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
 922         /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
 923          * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
 924          * r600_pipe_shader_ps().*/
 925         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
 926         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
 927         r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
 928         r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL, 0);
 929         r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL, 0);
 930         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
 931
 932         return rstate;
 933 }
 934
 935 static void *r600_create_rs_state(struct pipe_context *ctx,
 936                                   const struct pipe_rasterizer_state *state)
 937 {
 938         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 939         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 940         struct r600_pipe_state *rstate;
 941         unsigned tmp;
 942         unsigned prov_vtx = 1, polygon_dual_mode;
 943         unsigned clip_rule;
 944         unsigned sc_mode_cntl;
 945
 946         if (rs == NULL) {
 947                 return NULL;
 948         }
 949
 950         rstate = &rs->rstate;
 951         rs->clamp_vertex_color = state->clamp_vertex_color;
 952         rs->clamp_fragment_color = state->clamp_fragment_color;
 953         rs->flatshade = state->flatshade;
 954         rs->sprite_coord_enable = state->sprite_coord_enable;
 955
 956         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 957         /* offset */
 958         rs->offset_units = state->offset_units;
 959         rs->offset_scale = state->offset_scale * 12.0f;
 960
 961         rstate->id = R600_PIPE_STATE_RASTERIZER;
 962         if (state->flatshade_first)
 963                 prov_vtx = 0;
 964         tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
 965         if (state->sprite_coord_enable) {
 966                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 967                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 968                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 969                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 970                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 971                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 972                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 973                 }
 974         }
 975         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
 976
 977         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 978                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 979         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 980                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 981                 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 982                 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 983                 S_028814_FACE(!state->front_ccw) |
 984                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 985                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 986                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 987                 S_028814_POLY_MODE(polygon_dual_mode) |
 988                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 989                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
 990         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 991                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 992                         S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
 993         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
 994         /* point size 12.4 fixed point */
 995         tmp = (unsigned)(state->point_size * 8.0);
 996         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
 997         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
 998
 999         tmp = (unsigned)state->line_width * 8;
1000         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
1001
1002         if (state->line_stipple_enable) {
1003                 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
1004                                         S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1005                                         S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
1006                                         0x9FFFFFFF, NULL, 0);
1007         }
1008
1009         if (rctx->chip_class >= R700)
1010                 sc_mode_cntl = 0x514002;
1011         else
1012                 sc_mode_cntl = 0x4102;
1013         sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
1014
1015         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
1016                                 0xFFFFFFFF, NULL, 0);
1017         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1018         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
1019
1020         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
1021                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1022                                 0xFFFFFFFF, NULL, 0);
1023
1024         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1025         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1026         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1027         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1028         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
1029         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
1030
1031         return rstate;
1032 }
1033
1034 static void *r600_create_sampler_state(struct pipe_context *ctx,
1035                                         const struct pipe_sampler_state *state)
1036 {
1037         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1038         struct r600_pipe_state *rstate;
1039         union util_color uc;
1040         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
1041
1042         if (ss == NULL) {
1043                 return NULL;
1044         }
1045
1046         ss->seamless_cube_map = state->seamless_cube_map;
1047         rstate = &ss->rstate;
1048         rstate->id = R600_PIPE_STATE_SAMPLER;
1049         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1050         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1051                                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1052                                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1053                                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1054                                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1055                                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1056                                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1057                                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1058                                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1059                                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1060         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1061                                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1062                                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1063                                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0);
1064         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0);
1065         if (uc.ui) {
1066                 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1067                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1068                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1069                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1070         }
1071         return rstate;
1072 }
1073
1074 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1075                                                         struct pipe_resource *texture,
1076                                                         const struct pipe_sampler_view *state)
1077 {
1078         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1079         struct r600_pipe_resource_state *rstate;
1080         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1081         unsigned format, endian;
1082         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1083         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1084         unsigned width, height, depth, offset_level, last_level;
1085
1086         if (view == NULL)
1087                 return NULL;
1088         rstate = &view->state;
1089
1090         /* initialize base object */
1091         view->base = *state;
1092         view->base.texture = NULL;
1093         pipe_reference(NULL, &texture->reference);
1094         view->base.texture = texture;
1095         view->base.reference.count = 1;
1096         view->base.context = ctx;
1097
1098         swizzle[0] = state->swizzle_r;
1099         swizzle[1] = state->swizzle_g;
1100         swizzle[2] = state->swizzle_b;
1101         swizzle[3] = state->swizzle_a;
1102
1103         format = r600_translate_texformat(ctx->screen, state->format,
1104                                           swizzle,
1105                                           &word4, &yuv_format);
1106         if (format == ~0) {
1107                 format = 0;
1108         }
1109
1110         if (tmp->depth && !tmp->is_flushing_texture) {
1111                 r600_texture_depth_flush(ctx, texture, TRUE);
1112                 tmp = tmp->flushed_depth_texture;
1113         }
1114
1115         endian = r600_colorformat_endian_swap(format);
1116
1117         offset_level = state->u.tex.first_level;
1118         last_level = state->u.tex.last_level - offset_level;
1119         width = u_minify(texture->width0, offset_level);
1120         height = u_minify(texture->height0, offset_level);
1121         depth = u_minify(texture->depth0, offset_level);
1122
1123         pitch = align(tmp->pitch_in_blocks[offset_level] *
1124                       util_format_get_blockwidth(state->format), 8);
1125         array_mode = tmp->array_mode[offset_level];
1126         tile_type = tmp->tile_type;
1127
1128         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1129                 height = 1;
1130                 depth = texture->array_size;
1131         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1132                 depth = texture->array_size;
1133         }
1134
1135         rstate->bo[0] = &tmp->resource;
1136         rstate->bo[1] = &tmp->resource;
1137         rstate->bo_usage[0] = RADEON_USAGE_READ;
1138         rstate->bo_usage[1] = RADEON_USAGE_READ;
1139
1140         rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1141                           S_038000_TILE_MODE(array_mode) |
1142                           S_038000_TILE_TYPE(tile_type) |
1143                           S_038000_PITCH((pitch / 8) - 1) |
1144                           S_038000_TEX_WIDTH(width - 1));
1145         rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1146                           S_038004_TEX_DEPTH(depth - 1) |
1147                           S_038004_DATA_FORMAT(format));
1148         rstate->val[2] = tmp->offset[offset_level] >> 8;
1149         rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1150         rstate->val[4] = (word4 |
1151                           S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1152                           S_038010_REQUEST_SIZE(1) |
1153                           S_038010_ENDIAN_SWAP(endian) |
1154                           S_038010_BASE_LEVEL(0));
1155         rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1156                           S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1157                           S_038014_LAST_ARRAY(state->u.tex.last_layer));
1158         rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1159                           S_038018_MAX_ANISO(4 /* max 16 samples */));
1160
1161         return &view->base;
1162 }
1163
1164 static void r600_set_sampler_views(struct r600_pipe_context *rctx,
1165                                    struct r600_textures_info *dst,
1166                                    unsigned count,
1167                                    struct pipe_sampler_view **views,
1168                                    void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1169 {
1170         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1171         unsigned i;
1172
1173         for (i = 0; i < count; i++) {
1174                 if (rviews[i]) {
1175                         if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1176                                 rctx->have_depth_texture = true;
1177
1178                         /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1179                         if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1180                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1181                                 dst->samplers_dirty = true;
1182
1183                         set_resource(&rctx->ctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1184                 } else {
1185                         set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1186                 }
1187
1188                 pipe_sampler_view_reference(
1189                         (struct pipe_sampler_view **)&dst->views[i],
1190                         views[i]);
1191         }
1192
1193         for (i = count; i < dst->n_views; i++) {
1194                 if (dst->views[i]) {
1195                         set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1196                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1197                 }
1198         }
1199
1200         dst->n_views = count;
1201 }
1202
1203 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1204                                       struct pipe_sampler_view **views)
1205 {
1206         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1207         r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1208                                r600_context_pipe_state_set_vs_resource);
1209 }
1210
1211 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1212                                       struct pipe_sampler_view **views)
1213 {
1214         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1215         r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1216                                r600_context_pipe_state_set_ps_resource);
1217 }
1218
1219 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1220 {
1221         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1222         if (rstate == NULL)
1223                 return;
1224
1225         rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1226         r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1227                                 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1228                                 1, NULL, 0);
1229
1230         free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1231         rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1232         r600_context_pipe_state_set(&rctx->ctx, rstate);
1233 }
1234
1235 static void r600_bind_samplers(struct r600_pipe_context *rctx,
1236                                struct r600_textures_info *dst,
1237                                unsigned count, void **states)
1238 {
1239         memcpy(dst->samplers, states, sizeof(void*) * count);
1240         dst->n_samplers = count;
1241         dst->samplers_dirty = true;
1242 }
1243
1244 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1245 {
1246         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1247         r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1248 }
1249
1250 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1251 {
1252         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1253         r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1254 }
1255
1256 static void r600_update_samplers(struct r600_pipe_context *rctx,
1257                                  struct r600_textures_info *tex,
1258                                  void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1259 {
1260         unsigned i;
1261
1262         if (tex->samplers_dirty) {
1263                 int seamless = -1;
1264                 for (i = 0; i < tex->n_samplers; i++) {
1265                         if (!tex->samplers[i])
1266                                 continue;
1267
1268                         /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1269                          * filtering between layers.
1270                          * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1271                         if (tex->views[i]) {
1272                                 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1273                                     tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1274                                         tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1275                                         tex->is_array_sampler[i] = true;
1276                                 } else {
1277                                         tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1278                                         tex->is_array_sampler[i] = false;
1279                                 }
1280                         }
1281
1282                         set_sampler(&rctx->ctx, &tex->samplers[i]->rstate, i);
1283
1284                         if (tex->samplers[i])
1285                                 seamless = tex->samplers[i]->seamless_cube_map;
1286                 }
1287
1288                 if (seamless != -1)
1289                         r600_set_seamless_cubemap(rctx, seamless);
1290
1291                 tex->samplers_dirty = false;
1292         }
1293 }
1294
1295 void r600_update_sampler_states(struct r600_pipe_context *rctx)
1296 {
1297         r600_update_samplers(rctx, &rctx->vs_samplers,
1298                              r600_context_pipe_state_set_vs_sampler);
1299         r600_update_samplers(rctx, &rctx->ps_samplers,
1300                              r600_context_pipe_state_set_ps_sampler);
1301 }
1302
1303 static void r600_set_clip_state(struct pipe_context *ctx,
1304                                 const struct pipe_clip_state *state)
1305 {
1306         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1307         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1308
1309         if (rstate == NULL)
1310                 return;
1311
1312         rctx->clip = *state;
1313         rstate->id = R600_PIPE_STATE_CLIP;
1314         for (int i = 0; i < state->nr; i++) {
1315                 r600_pipe_state_add_reg(rstate,
1316                                         R_028E20_PA_CL_UCP0_X + i * 16,
1317                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1318                 r600_pipe_state_add_reg(rstate,
1319                                         R_028E24_PA_CL_UCP0_Y + i * 16,
1320                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1321                 r600_pipe_state_add_reg(rstate,
1322                                         R_028E28_PA_CL_UCP0_Z + i * 16,
1323                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1324                 r600_pipe_state_add_reg(rstate,
1325                                         R_028E2C_PA_CL_UCP0_W + i * 16,
1326                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1327         }
1328         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1329                         S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1330                         S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1331                         S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1332
1333         free(rctx->states[R600_PIPE_STATE_CLIP]);
1334         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1335         r600_context_pipe_state_set(&rctx->ctx, rstate);
1336 }
1337
1338 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1339                                          const struct pipe_poly_stipple *state)
1340 {
1341 }
1342
1343 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1344 {
1345 }
1346
1347 static void r600_set_scissor_state(struct pipe_context *ctx,
1348                                         const struct pipe_scissor_state *state)
1349 {
1350         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1351         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1352         u32 tl, br;
1353
1354         if (rstate == NULL)
1355                 return;
1356
1357         rstate->id = R600_PIPE_STATE_SCISSOR;
1358         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1359         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1360         r600_pipe_state_add_reg(rstate,
1361                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1362                                 0xFFFFFFFF, NULL, 0);
1363         r600_pipe_state_add_reg(rstate,
1364                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1365                                 0xFFFFFFFF, NULL, 0);
1366         r600_pipe_state_add_reg(rstate,
1367                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1368                                 0xFFFFFFFF, NULL, 0);
1369         r600_pipe_state_add_reg(rstate,
1370                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1371                                 0xFFFFFFFF, NULL, 0);
1372         r600_pipe_state_add_reg(rstate,
1373                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1374                                 0xFFFFFFFF, NULL, 0);
1375         r600_pipe_state_add_reg(rstate,
1376                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1377                                 0xFFFFFFFF, NULL, 0);
1378         r600_pipe_state_add_reg(rstate,
1379                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1380                                 0xFFFFFFFF, NULL, 0);
1381         r600_pipe_state_add_reg(rstate,
1382                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1383                                 0xFFFFFFFF, NULL, 0);
1384
1385         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1386         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1387         r600_context_pipe_state_set(&rctx->ctx, rstate);
1388 }
1389
1390 static void r600_set_stencil_ref(struct pipe_context *ctx,
1391                                 const struct pipe_stencil_ref *state)
1392 {
1393         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1394         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1395         u32 tmp;
1396
1397         if (rstate == NULL)
1398                 return;
1399
1400         rctx->stencil_ref = *state;
1401         rstate->id = R600_PIPE_STATE_STENCIL_REF;
1402         tmp = S_028430_STENCILREF(state->ref_value[0]);
1403         r600_pipe_state_add_reg(rstate,
1404                                 R_028430_DB_STENCILREFMASK, tmp,
1405                                 ~C_028430_STENCILREF, NULL, 0);
1406         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1407         r600_pipe_state_add_reg(rstate,
1408                                 R_028434_DB_STENCILREFMASK_BF, tmp,
1409                                 ~C_028434_STENCILREF_BF, NULL, 0);
1410
1411         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1412         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1413         r600_context_pipe_state_set(&rctx->ctx, rstate);
1414 }
1415
1416 static void r600_set_viewport_state(struct pipe_context *ctx,
1417                                         const struct pipe_viewport_state *state)
1418 {
1419         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1420         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1421
1422         if (rstate == NULL)
1423                 return;
1424
1425         rctx->viewport = *state;
1426         rstate->id = R600_PIPE_STATE_VIEWPORT;
1427         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1428         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1429         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1430         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1431         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1432         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1433         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1434         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1435         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1436
1437         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1438         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1439         r600_context_pipe_state_set(&rctx->ctx, rstate);
1440 }
1441
1442 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1443                         const struct pipe_framebuffer_state *state, int cb)
1444 {
1445         struct r600_resource_texture *rtex;
1446         struct r600_surface *surf;
1447         unsigned level = state->cbufs[cb]->u.tex.level;
1448         unsigned pitch, slice;
1449         unsigned color_info;
1450         unsigned format, swap, ntype, endian;
1451         unsigned offset;
1452         const struct util_format_description *desc;
1453         int i;
1454
1455         surf = (struct r600_surface *)state->cbufs[cb];
1456         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1457
1458         if (rtex->depth)
1459                 rctx->have_depth_fb = TRUE;
1460
1461         if (rtex->depth && !rtex->is_flushing_texture) {
1462                 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1463                 rtex = rtex->flushed_depth_texture;
1464         }
1465
1466         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1467         offset = r600_texture_get_offset(rtex,
1468                                          level, state->cbufs[cb]->u.tex.first_layer);
1469         pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1470         slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1471         desc = util_format_description(surf->base.format);
1472
1473         for (i = 0; i < 4; i++) {
1474                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1475                         break;
1476                 }
1477         }
1478
1479         ntype = V_0280A0_NUMBER_UNORM;
1480         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1481                 ntype = V_0280A0_NUMBER_SRGB;
1482         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1483                 if (desc->channel[i].normalized)
1484                         ntype = V_0280A0_NUMBER_SNORM;
1485                 else if (desc->channel[i].pure_integer)
1486                         ntype = V_0280A0_NUMBER_SINT;
1487         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1488                 if (desc->channel[i].normalized)
1489                         ntype = V_0280A0_NUMBER_UNORM;
1490                 else if (desc->channel[i].pure_integer)
1491                         ntype = V_0280A0_NUMBER_UINT;
1492         }
1493
1494         format = r600_translate_colorformat(surf->base.format);
1495         swap = r600_translate_colorswap(surf->base.format);
1496         if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1497                 endian = ENDIAN_NONE;
1498         } else {
1499                 endian = r600_colorformat_endian_swap(format);
1500         }
1501
1502         color_info = S_0280A0_FORMAT(format) |
1503                 S_0280A0_COMP_SWAP(swap) |
1504                 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1505                 S_0280A0_BLEND_CLAMP(1) |
1506                 S_0280A0_NUMBER_TYPE(ntype) |
1507                 S_0280A0_ENDIAN(endian);
1508
1509         /* EXPORT_NORM is an optimzation that can be enabled for better
1510          * performance in certain cases
1511          */
1512         if (rctx->chip_class == R600) {
1513                 /* EXPORT_NORM can be enabled if:
1514                  * - 11-bit or smaller UNORM/SNORM/SRGB
1515                  * - BLEND_CLAMP is enabled
1516                  * - BLEND_FLOAT32 is disabled
1517                  */
1518                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1519                     (desc->channel[i].size < 12 &&
1520                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1521                      ntype != V_0280A0_NUMBER_UINT &&
1522                      ntype != V_0280A0_NUMBER_SINT) &&
1523                     G_0280A0_BLEND_CLAMP(color_info) &&
1524                     !G_0280A0_BLEND_FLOAT32(color_info))
1525                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1526         } else {
1527                 /* EXPORT_NORM can be enabled if:
1528                  * - 11-bit or smaller UNORM/SNORM/SRGB
1529                  * - 16-bit or smaller FLOAT
1530                  */
1531                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1532                     ((desc->channel[i].size < 12 &&
1533                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1534                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1535                     (desc->channel[i].size < 17 &&
1536                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1537                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1538         }
1539
1540         r600_pipe_state_add_reg(rstate,
1541                                 R_028040_CB_COLOR0_BASE + cb * 4,
1542                                 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1543         r600_pipe_state_add_reg(rstate,
1544                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
1545                                 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1546         r600_pipe_state_add_reg(rstate,
1547                                 R_028060_CB_COLOR0_SIZE + cb * 4,
1548                                 S_028060_PITCH_TILE_MAX(pitch) |
1549                                 S_028060_SLICE_TILE_MAX(slice),
1550                                 0xFFFFFFFF, NULL, 0);
1551         r600_pipe_state_add_reg(rstate,
1552                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1553                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1554         r600_pipe_state_add_reg(rstate,
1555                                 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1556                                 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1557         r600_pipe_state_add_reg(rstate,
1558                                 R_0280C0_CB_COLOR0_TILE + cb * 4,
1559                                 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1560         r600_pipe_state_add_reg(rstate,
1561                                 R_028100_CB_COLOR0_MASK + cb * 4,
1562                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1563 }
1564
1565 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1566                         const struct pipe_framebuffer_state *state)
1567 {
1568         struct r600_resource_texture *rtex;
1569         struct r600_surface *surf;
1570         unsigned level, pitch, slice, format, offset, array_mode;
1571
1572         if (state->zsbuf == NULL)
1573                 return;
1574
1575         level = state->zsbuf->u.tex.level;
1576
1577         surf = (struct r600_surface *)state->zsbuf;
1578         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1579
1580         /* XXX remove this once tiling is properly supported */
1581         array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1582                                                V_0280A0_ARRAY_1D_TILED_THIN1;
1583
1584         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1585         offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1586                                          level, state->zsbuf->u.tex.first_layer);
1587         pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1588         slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1589         format = r600_translate_dbformat(state->zsbuf->texture->format);
1590
1591         r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1592                                 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1593         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1594                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1595                                 0xFFFFFFFF, NULL, 0);
1596         r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1597         r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1598                                 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1599                                 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1600         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1601                                 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);
1602 }
1603
1604 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1605                                         const struct pipe_framebuffer_state *state)
1606 {
1607         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1608         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1609         u32 shader_mask, tl, br, shader_control, target_mask;
1610
1611         if (rstate == NULL)
1612                 return;
1613
1614         r600_context_flush_dest_caches(&rctx->ctx);
1615         rctx->ctx.num_dest_buffers = state->nr_cbufs;
1616
1617         /* unreference old buffer and reference new one */
1618         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1619
1620         util_copy_framebuffer_state(&rctx->framebuffer, state);
1621
1622         /* build states */
1623         rctx->have_depth_fb = 0;
1624         for (int i = 0; i < state->nr_cbufs; i++) {
1625                 r600_cb(rctx, rstate, state, i);
1626         }
1627         if (state->zsbuf) {
1628                 r600_db(rctx, rstate, state);
1629                 rctx->ctx.num_dest_buffers++;
1630         }
1631
1632         target_mask = 0x00000000;
1633         target_mask = 0xFFFFFFFF;
1634         shader_mask = 0;
1635         shader_control = 0;
1636         for (int i = 0; i < state->nr_cbufs; i++) {
1637                 target_mask ^= 0xf << (i * 4);
1638                 shader_mask |= 0xf << (i * 4);
1639                 shader_control |= 1 << i;
1640         }
1641         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1642         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1643
1644         r600_pipe_state_add_reg(rstate,
1645                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1646                                 0xFFFFFFFF, NULL, 0);
1647         r600_pipe_state_add_reg(rstate,
1648                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1649                                 0xFFFFFFFF, NULL, 0);
1650         r600_pipe_state_add_reg(rstate,
1651                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1652                                 0xFFFFFFFF, NULL, 0);
1653         r600_pipe_state_add_reg(rstate,
1654                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1655                                 0xFFFFFFFF, NULL, 0);
1656         r600_pipe_state_add_reg(rstate,
1657                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1658                                 0xFFFFFFFF, NULL, 0);
1659         r600_pipe_state_add_reg(rstate,
1660                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1661                                 0xFFFFFFFF, NULL, 0);
1662         r600_pipe_state_add_reg(rstate,
1663                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1664                                 0xFFFFFFFF, NULL, 0);
1665         r600_pipe_state_add_reg(rstate,
1666                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1667                                 0xFFFFFFFF, NULL, 0);
1668         r600_pipe_state_add_reg(rstate,
1669                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1670                                 0xFFFFFFFF, NULL, 0);
1671         if (rctx->chip_class >= R700) {
1672                 r600_pipe_state_add_reg(rstate,
1673                                         R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1674                                         0xFFFFFFFF, NULL, 0);
1675         }
1676
1677         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1678                                 shader_control, 0xFFFFFFFF, NULL, 0);
1679         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1680                                 0x00000000, target_mask, NULL, 0);
1681         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1682                                 shader_mask, 0xFFFFFFFF, NULL, 0);
1683         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1684                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1685         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1686                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1687         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1688                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1689         r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1690                                 0x01000000, 0xFFFFFFFF, NULL, 0);
1691         r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1692                                 0x00000000, 0xFFFFFFFF, NULL, 0);
1693         r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1694                                 0x000000FF, 0xFFFFFFFF, NULL, 0);
1695         r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1696                                 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1697         r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1698                                 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1699
1700         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1701         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1702         r600_context_pipe_state_set(&rctx->ctx, rstate);
1703
1704         if (state->zsbuf) {
1705                 r600_polygon_offset_update(rctx);
1706         }
1707 }
1708
1709 static void r600_texture_barrier(struct pipe_context *ctx)
1710 {
1711         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1712
1713         r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1714                         S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1715                         S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1716                         S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1717                         S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1718 }
1719
1720 void r600_init_state_functions(struct r600_pipe_context *rctx)
1721 {
1722         rctx->context.create_blend_state = r600_create_blend_state;
1723         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1724         rctx->context.create_fs_state = r600_create_shader_state;
1725         rctx->context.create_rasterizer_state = r600_create_rs_state;
1726         rctx->context.create_sampler_state = r600_create_sampler_state;
1727         rctx->context.create_sampler_view = r600_create_sampler_view;
1728         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1729         rctx->context.create_vs_state = r600_create_shader_state;
1730         rctx->context.bind_blend_state = r600_bind_blend_state;
1731         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1732         rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1733         rctx->context.bind_fs_state = r600_bind_ps_shader;
1734         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1735         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1736         rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1737         rctx->context.bind_vs_state = r600_bind_vs_shader;
1738         rctx->context.delete_blend_state = r600_delete_state;
1739         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1740         rctx->context.delete_fs_state = r600_delete_ps_shader;
1741         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1742         rctx->context.delete_sampler_state = r600_delete_state;
1743         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1744         rctx->context.delete_vs_state = r600_delete_vs_shader;
1745         rctx->context.set_blend_color = r600_set_blend_color;
1746         rctx->context.set_clip_state = r600_set_clip_state;
1747         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1748         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1749         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1750         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1751         rctx->context.set_sample_mask = r600_set_sample_mask;
1752         rctx->context.set_scissor_state = r600_set_scissor_state;
1753         rctx->context.set_stencil_ref = r600_set_stencil_ref;
1754         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1755         rctx->context.set_index_buffer = r600_set_index_buffer;
1756         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1757         rctx->context.set_viewport_state = r600_set_viewport_state;
1758         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1759         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1760         rctx->context.texture_barrier = r600_texture_barrier;
1761         rctx->context.create_stream_output_target = r600_create_so_target;
1762         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1763         rctx->context.set_stream_output_targets = r600_set_so_targets;
1764 }
1765
1766 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1767 {
1768         struct r600_pipe_state rstate;
1769         unsigned num_ps_gprs = rctx->default_ps_gprs;
1770         unsigned num_vs_gprs = rctx->default_vs_gprs;
1771         unsigned tmp;
1772         int diff;
1773
1774         if (rctx->chip_class >= EVERGREEN)
1775                 return;
1776
1777         if (!rctx->ps_shader || !rctx->vs_shader)
1778                 return;
1779
1780         if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1781         {
1782                 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1783                 num_vs_gprs -= diff;
1784                 num_ps_gprs += diff;
1785         }
1786
1787         if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1788         {
1789                 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1790                 num_ps_gprs -= diff;
1791                 num_vs_gprs += diff;
1792         }
1793
1794         tmp = 0;
1795         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1796         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1797         rstate.nregs = 0;
1798         r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL, 0);
1799
1800         r600_context_pipe_state_set(&rctx->ctx, &rstate);
1801 }
1802
1803 void r600_init_config(struct r600_pipe_context *rctx)
1804 {
1805         int ps_prio;
1806         int vs_prio;
1807         int gs_prio;
1808         int es_prio;
1809         int num_ps_gprs;
1810         int num_vs_gprs;
1811         int num_gs_gprs;
1812         int num_es_gprs;
1813         int num_temp_gprs;
1814         int num_ps_threads;
1815         int num_vs_threads;
1816         int num_gs_threads;
1817         int num_es_threads;
1818         int num_ps_stack_entries;
1819         int num_vs_stack_entries;
1820         int num_gs_stack_entries;
1821         int num_es_stack_entries;
1822         enum radeon_family family;
1823         struct r600_pipe_state *rstate = &rctx->config;
1824         u32 tmp;
1825
1826         family = rctx->family;
1827         ps_prio = 0;
1828         vs_prio = 1;
1829         gs_prio = 2;
1830         es_prio = 3;
1831         switch (family) {
1832         case CHIP_R600:
1833                 num_ps_gprs = 192;
1834                 num_vs_gprs = 56;
1835                 num_temp_gprs = 4;
1836                 num_gs_gprs = 0;
1837                 num_es_gprs = 0;
1838                 num_ps_threads = 136;
1839                 num_vs_threads = 48;
1840                 num_gs_threads = 4;
1841                 num_es_threads = 4;
1842                 num_ps_stack_entries = 128;
1843                 num_vs_stack_entries = 128;
1844                 num_gs_stack_entries = 0;
1845                 num_es_stack_entries = 0;
1846                 break;
1847         case CHIP_RV630:
1848         case CHIP_RV635:
1849                 num_ps_gprs = 84;
1850                 num_vs_gprs = 36;
1851                 num_temp_gprs = 4;
1852                 num_gs_gprs = 0;
1853                 num_es_gprs = 0;
1854                 num_ps_threads = 144;
1855                 num_vs_threads = 40;
1856                 num_gs_threads = 4;
1857                 num_es_threads = 4;
1858                 num_ps_stack_entries = 40;
1859                 num_vs_stack_entries = 40;
1860                 num_gs_stack_entries = 32;
1861                 num_es_stack_entries = 16;
1862                 break;
1863         case CHIP_RV610:
1864         case CHIP_RV620:
1865         case CHIP_RS780:
1866         case CHIP_RS880:
1867         default:
1868                 num_ps_gprs = 84;
1869                 num_vs_gprs = 36;
1870                 num_temp_gprs = 4;
1871                 num_gs_gprs = 0;
1872                 num_es_gprs = 0;
1873                 num_ps_threads = 136;
1874                 num_vs_threads = 48;
1875                 num_gs_threads = 4;
1876                 num_es_threads = 4;
1877                 num_ps_stack_entries = 40;
1878                 num_vs_stack_entries = 40;
1879                 num_gs_stack_entries = 32;
1880                 num_es_stack_entries = 16;
1881                 break;
1882         case CHIP_RV670:
1883                 num_ps_gprs = 144;
1884                 num_vs_gprs = 40;
1885                 num_temp_gprs = 4;
1886                 num_gs_gprs = 0;
1887                 num_es_gprs = 0;
1888                 num_ps_threads = 136;
1889                 num_vs_threads = 48;
1890                 num_gs_threads = 4;
1891                 num_es_threads = 4;
1892                 num_ps_stack_entries = 40;
1893                 num_vs_stack_entries = 40;
1894                 num_gs_stack_entries = 32;
1895                 num_es_stack_entries = 16;
1896                 break;
1897         case CHIP_RV770:
1898                 num_ps_gprs = 192;
1899                 num_vs_gprs = 56;
1900                 num_temp_gprs = 4;
1901                 num_gs_gprs = 0;
1902                 num_es_gprs = 0;
1903                 num_ps_threads = 188;
1904                 num_vs_threads = 60;
1905                 num_gs_threads = 0;
1906                 num_es_threads = 0;
1907                 num_ps_stack_entries = 256;
1908                 num_vs_stack_entries = 256;
1909                 num_gs_stack_entries = 0;
1910                 num_es_stack_entries = 0;
1911                 break;
1912         case CHIP_RV730:
1913         case CHIP_RV740:
1914                 num_ps_gprs = 84;
1915                 num_vs_gprs = 36;
1916                 num_temp_gprs = 4;
1917                 num_gs_gprs = 0;
1918                 num_es_gprs = 0;
1919                 num_ps_threads = 188;
1920                 num_vs_threads = 60;
1921                 num_gs_threads = 0;
1922                 num_es_threads = 0;
1923                 num_ps_stack_entries = 128;
1924                 num_vs_stack_entries = 128;
1925                 num_gs_stack_entries = 0;
1926                 num_es_stack_entries = 0;
1927                 break;
1928         case CHIP_RV710:
1929                 num_ps_gprs = 192;
1930                 num_vs_gprs = 56;
1931                 num_temp_gprs = 4;
1932                 num_gs_gprs = 0;
1933                 num_es_gprs = 0;
1934                 num_ps_threads = 144;
1935                 num_vs_threads = 48;
1936                 num_gs_threads = 0;
1937                 num_es_threads = 0;
1938                 num_ps_stack_entries = 128;
1939                 num_vs_stack_entries = 128;
1940                 num_gs_stack_entries = 0;
1941                 num_es_stack_entries = 0;
1942                 break;
1943         }
1944
1945         rctx->default_ps_gprs = num_ps_gprs;
1946         rctx->default_vs_gprs = num_vs_gprs;
1947
1948         rstate->id = R600_PIPE_STATE_CONFIG;
1949
1950         /* SQ_CONFIG */
1951         tmp = 0;
1952         switch (family) {
1953         case CHIP_RV610:
1954         case CHIP_RV620:
1955         case CHIP_RS780:
1956         case CHIP_RS880:
1957         case CHIP_RV710:
1958                 break;
1959         default:
1960                 tmp |= S_008C00_VC_ENABLE(1);
1961                 break;
1962         }
1963         tmp |= S_008C00_DX9_CONSTS(0);
1964         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1965         tmp |= S_008C00_PS_PRIO(ps_prio);
1966         tmp |= S_008C00_VS_PRIO(vs_prio);
1967         tmp |= S_008C00_GS_PRIO(gs_prio);
1968         tmp |= S_008C00_ES_PRIO(es_prio);
1969         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1970
1971         /* SQ_GPR_RESOURCE_MGMT_1 */
1972         tmp = 0;
1973         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1974         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1975         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1976         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1977
1978         /* SQ_GPR_RESOURCE_MGMT_2 */
1979         tmp = 0;
1980         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1981         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1982         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1983
1984         /* SQ_THREAD_RESOURCE_MGMT */
1985         tmp = 0;
1986         tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1987         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1988         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1989         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1990         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
1991
1992         /* SQ_STACK_RESOURCE_MGMT_1 */
1993         tmp = 0;
1994         tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1995         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1996         r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1997
1998         /* SQ_STACK_RESOURCE_MGMT_2 */
1999         tmp = 0;
2000         tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2001         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2002         r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2003
2004         r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2005         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL, 0);
2006
2007         if (rctx->chip_class >= R700) {
2008                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL, 0);
2009                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2010                                         S_009508_DISABLE_CUBE_ANISO(1) |
2011                                         S_009508_SYNC_GRADIENT(1) |
2012                                         S_009508_SYNC_WALKER(1) |
2013                                         S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2014                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0);
2015                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0);
2016                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0);
2017         } else {
2018                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0);
2019                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2020                                         S_009508_DISABLE_CUBE_ANISO(1) |
2021                                         S_009508_SYNC_GRADIENT(1) |
2022                                         S_009508_SYNC_WALKER(1) |
2023                                         S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2024                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0);
2025                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0);
2026                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0);
2027         }
2028         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2029         r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2030         r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2031         r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2032         r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2033         r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2034         r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2035         r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2036         r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2037         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2038         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2039         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2040         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2041         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL, 0);
2042         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2043         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2044         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2045         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2046         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2047         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2048         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2049         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2050         r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2051         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL, 0);
2052         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2053         r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2054
2055         r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL, 0);
2056         r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2057         r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2058         r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
2059         r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL, 0);
2060         r600_context_pipe_state_set(&rctx->ctx, rstate);
2061 }
2062
2063 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2064 {
2065         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2066         struct r600_pipe_state *rstate = &shader->rstate;
2067         struct r600_shader *rshader = &shader->shader;
2068         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2069         int pos_index = -1, face_index = -1;
2070         unsigned tmp, sid;
2071
2072         rstate->nregs = 0;
2073
2074         for (i = 0; i < rshader->ninput; i++) {
2075                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2076                         pos_index = i;
2077                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2078                         face_index = i;
2079
2080                 sid = rshader->input[i].spi_sid;
2081
2082                 tmp = S_028644_SEMANTIC(sid);
2083
2084                 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
2085                                 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
2086                                 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
2087                         tmp |= S_028644_FLAT_SHADE(1);
2088                 }
2089
2090                 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2091                                 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2092                         tmp |= S_028644_PT_SPRITE_TEX(1);
2093                 }
2094
2095                 if (rshader->input[i].centroid)
2096                         tmp |= S_028644_SEL_CENTROID(1);
2097
2098                 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2099                         tmp |= S_028644_SEL_LINEAR(1);
2100
2101                 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2102                                 tmp, 0xFFFFFFFF, NULL, 0);
2103         }
2104
2105         db_shader_control = 0;
2106         for (i = 0; i < rshader->noutput; i++) {
2107                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2108                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2109                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2110                         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2111         }
2112         if (rshader->uses_kill)
2113                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2114
2115         exports_ps = 0;
2116         num_cout = 0;
2117         for (i = 0; i < rshader->noutput; i++) {
2118                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2119                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2120                         exports_ps |= 1;
2121                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2122                         num_cout++;
2123                 }
2124         }
2125         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2126         if (!exports_ps) {
2127                 /* always at least export 1 component per pixel */
2128                 exports_ps = 2;
2129         }
2130
2131         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2132                                 S_0286CC_PERSP_GRADIENT_ENA(1);
2133         spi_input_z = 0;
2134         if (pos_index != -1) {
2135                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2136                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2137                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2138                                         S_0286CC_BARYC_SAMPLE_CNTL(1));
2139                 spi_input_z |= 1;
2140         }
2141
2142         spi_ps_in_control_1 = 0;
2143         if (face_index != -1) {
2144                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2145                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2146         }
2147
2148         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2149         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2150         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2151         r600_pipe_state_add_reg(rstate,
2152                                 R_028840_SQ_PGM_START_PS,
2153                                 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2154         r600_pipe_state_add_reg(rstate,
2155                                 R_028850_SQ_PGM_RESOURCES_PS,
2156                                 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2157                                 S_028850_STACK_SIZE(rshader->bc.nstack),
2158                                 0xFFFFFFFF, NULL, 0);
2159         r600_pipe_state_add_reg(rstate,
2160                                 R_028854_SQ_PGM_EXPORTS_PS,
2161                                 exports_ps, 0xFFFFFFFF, NULL, 0);
2162         r600_pipe_state_add_reg(rstate,
2163                                 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2164                                 0x00000000, 0xFFFFFFFF, NULL, 0);
2165         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2166                                 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2167                                 S_028808_MULTIWRITE_ENABLE(1),
2168                                 NULL, 0);
2169         /* only set some bits here, the other bits are set in the dsa state */
2170         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2171                                 db_shader_control,
2172                                 S_02880C_Z_EXPORT_ENABLE(1) |
2173                                 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2174                                 S_02880C_KILL_ENABLE(1),
2175                                 NULL, 0);
2176
2177         r600_pipe_state_add_reg(rstate,
2178                                 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2179                                 0xFFFFFFFF, NULL, 0);
2180
2181         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2182 }
2183
2184 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2185 {
2186         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2187         struct r600_pipe_state *rstate = &shader->rstate;
2188         struct r600_shader *rshader = &shader->shader;
2189         unsigned spi_vs_out_id[10] = {};
2190         unsigned i, tmp, nparams = 0;
2191
2192         /* clear previous register */
2193         rstate->nregs = 0;
2194
2195         for (i = 0; i < rshader->noutput; i++) {
2196                 if (rshader->output[i].spi_sid) {
2197                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2198                         spi_vs_out_id[nparams / 4] |= tmp;
2199                         nparams++;
2200                 }
2201         }
2202
2203         for (i = 0; i < 10; i++) {
2204                 r600_pipe_state_add_reg(rstate,
2205                                         R_028614_SPI_VS_OUT_ID_0 + i * 4,
2206                                         spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2207         }
2208
2209         /* Certain attributes (position, psize, etc.) don't count as params.
2210          * VS is required to export at least one param and r600_shader_from_tgsi()
2211          * takes care of adding a dummy export.
2212          */
2213         if (nparams < 1)
2214                 nparams = 1;
2215
2216         r600_pipe_state_add_reg(rstate,
2217                         R_0286C4_SPI_VS_OUT_CONFIG,
2218                         S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2219                         0xFFFFFFFF, NULL, 0);
2220         r600_pipe_state_add_reg(rstate,
2221                         R_028868_SQ_PGM_RESOURCES_VS,
2222                         S_028868_NUM_GPRS(rshader->bc.ngpr) |
2223                         S_028868_STACK_SIZE(rshader->bc.nstack),
2224                         0xFFFFFFFF, NULL, 0);
2225         r600_pipe_state_add_reg(rstate,
2226                         R_0288D0_SQ_PGM_CF_OFFSET_VS,
2227                         0x00000000, 0xFFFFFFFF, NULL, 0);
2228         r600_pipe_state_add_reg(rstate,
2229                         R_028858_SQ_PGM_START_VS,
2230                         0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2231
2232         r600_pipe_state_add_reg(rstate,
2233                                 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2234                                 0xFFFFFFFF, NULL, 0);
2235 }
2236
2237 void r600_fetch_shader(struct pipe_context *ctx,
2238                        struct r600_vertex_element *ve)
2239 {
2240         struct r600_pipe_state *rstate;
2241         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2242
2243         rstate = &ve->rstate;
2244         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2245         rstate->nregs = 0;
2246         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2247                                 0x00000000, 0xFFFFFFFF, NULL, 0);
2248         r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2249                                 0x00000000, 0xFFFFFFFF, NULL, 0);
2250         r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2251                                 0,
2252                                 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2253 }
2254
2255 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2256 {
2257         struct pipe_depth_stencil_alpha_state dsa;
2258         struct r600_pipe_state *rstate;
2259         boolean quirk = false;
2260
2261         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2262                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2263                 quirk = true;
2264
2265         memset(&dsa, 0, sizeof(dsa));
2266
2267         if (quirk) {
2268                 dsa.depth.enabled = 1;
2269                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2270                 dsa.stencil[0].enabled = 1;
2271                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2272                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2273                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2274                 dsa.stencil[0].writemask = 0xff;
2275         }
2276
2277         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2278         r600_pipe_state_add_reg(rstate,
2279                                 R_02880C_DB_SHADER_CONTROL,
2280                                 0x0,
2281                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2282         r600_pipe_state_add_reg(rstate,
2283                                 R_028D0C_DB_RENDER_CONTROL,
2284                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2285                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2286                                 S_028D0C_COPY_CENTROID(1),
2287                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2288                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2289                                 S_028D0C_COPY_CENTROID(1), NULL, 0);
2290         return rstate;
2291 }
2292
2293 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2294                                     struct r600_pipe_resource_state *rstate)
2295 {
2296         rstate->id = R600_PIPE_STATE_RESOURCE;
2297
2298         rstate->bo[0] = NULL;
2299         rstate->val[0] = 0;
2300         rstate->val[1] = 0;
2301         rstate->val[2] = 0;
2302         rstate->val[3] = 0;
2303         rstate->val[4] = 0;
2304         rstate->val[5] = 0;
2305         rstate->val[6] = 0xc0000000;
2306 }
2307
2308 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2309                                    struct r600_resource *rbuffer,
2310                                    unsigned offset, unsigned stride,
2311                                    enum radeon_bo_usage usage)
2312 {
2313         rstate->val[0] = offset;
2314         rstate->bo[0] = rbuffer;
2315         rstate->bo_usage[0] = usage;
2316         rstate->val[1] = rbuffer->buf->size - offset - 1;
2317         rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2318                          S_038008_STRIDE(stride);
2319 }