src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600_shader.h"
  29 #include "r600d.h"
  30
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_index_modify.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "util/u_math.h"
  36 #include "tgsi/tgsi_parse.h"
  37
  38 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
  39 {
  40         assert(!cb->buf);
  41         cb->buf = CALLOC(1, 4 * num_dw);
  42         cb->max_num_dw = num_dw;
  43 }
  44
  45 void r600_release_command_buffer(struct r600_command_buffer *cb)
  46 {
  47         FREE(cb->buf);
  48 }
  49
  50 void r600_add_atom(struct r600_context *rctx,
  51                    struct r600_atom *atom,
  52                    unsigned id)
  53 {
  54         assert(id < R600_NUM_ATOMS);
  55         assert(rctx->atoms[id] == NULL);
  56         rctx->atoms[id] = atom;
  57         atom->dirty = false;
  58 }
  59
  60 void r600_init_atom(struct r600_context *rctx,
  61                     struct r600_atom *atom,
  62                     unsigned id,
  63                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  64                     unsigned num_dw)
  65 {
  66         atom->emit = (void*)emit;
  67         atom->num_dw = num_dw;
  68         r600_add_atom(rctx, atom, id);
  69 }
  70
  71 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
  72 {
  73         r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
  74 }
  75
  76 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
  77 {
  78         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
  79         struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
  80         unsigned alpha_ref = a->sx_alpha_ref;
  81
  82         if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
  83                 alpha_ref &= ~0x1FFF;
  84         }
  85
  86         r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
  87                                a->sx_alpha_test_control |
  88                                S_028410_ALPHA_TEST_BYPASS(a->bypass));
  89         r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
  90 }
  91
  92 static void r600_texture_barrier(struct pipe_context *ctx)
  93 {
  94         struct r600_context *rctx = (struct r600_context *)ctx;
  95
  96         rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
  97                        R600_CONTEXT_FLUSH_AND_INV_CB |
  98                        R600_CONTEXT_FLUSH_AND_INV |
  99                        R600_CONTEXT_WAIT_3D_IDLE;
 100 }
 101
 102 static unsigned r600_conv_pipe_prim(unsigned prim)
 103 {
 104         static const unsigned prim_conv[] = {
 105                 [PIPE_PRIM_POINTS]                      = V_008958_DI_PT_POINTLIST,
 106                 [PIPE_PRIM_LINES]                       = V_008958_DI_PT_LINELIST,
 107                 [PIPE_PRIM_LINE_LOOP]                   = V_008958_DI_PT_LINELOOP,
 108                 [PIPE_PRIM_LINE_STRIP]                  = V_008958_DI_PT_LINESTRIP,
 109                 [PIPE_PRIM_TRIANGLES]                   = V_008958_DI_PT_TRILIST,
 110                 [PIPE_PRIM_TRIANGLE_STRIP]              = V_008958_DI_PT_TRISTRIP,
 111                 [PIPE_PRIM_TRIANGLE_FAN]                = V_008958_DI_PT_TRIFAN,
 112                 [PIPE_PRIM_QUADS]                       = V_008958_DI_PT_QUADLIST,
 113                 [PIPE_PRIM_QUAD_STRIP]                  = V_008958_DI_PT_QUADSTRIP,
 114                 [PIPE_PRIM_POLYGON]                     = V_008958_DI_PT_POLYGON,
 115                 [PIPE_PRIM_LINES_ADJACENCY]             = V_008958_DI_PT_LINELIST_ADJ,
 116                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = V_008958_DI_PT_LINESTRIP_ADJ,
 117                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = V_008958_DI_PT_TRILIST_ADJ,
 118                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = V_008958_DI_PT_TRISTRIP_ADJ,
 119                 [R600_PRIM_RECTANGLE_LIST]              = V_008958_DI_PT_RECTLIST
 120         };
 121         assert(prim < Elements(prim_conv));
 122         return prim_conv[prim];
 123 }
 124
 125 /* common state between evergreen and r600 */
 126
 127 static void r600_bind_blend_state_internal(struct r600_context *rctx,
 128                 struct r600_blend_state *blend, bool blend_disable)
 129 {
 130         unsigned color_control;
 131         bool update_cb = false;
 132
 133         rctx->alpha_to_one = blend->alpha_to_one;
 134         rctx->dual_src_blend = blend->dual_src_blend;
 135
 136         if (!blend_disable) {
 137                 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
 138                 color_control = blend->cb_color_control;
 139         } else {
 140                 /* Blending is disabled. */
 141                 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
 142                 color_control = blend->cb_color_control_no_blend;
 143         }
 144
 145         /* Update derived states. */
 146         if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 147                 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 148                 update_cb = true;
 149         }
 150         if (rctx->b.chip_class <= R700 &&
 151             rctx->cb_misc_state.cb_color_control != color_control) {
 152                 rctx->cb_misc_state.cb_color_control = color_control;
 153                 update_cb = true;
 154         }
 155         if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
 156                 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
 157                 update_cb = true;
 158         }
 159         if (update_cb) {
 160                 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 161         }
 162 }
 163
 164 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 165 {
 166         struct r600_context *rctx = (struct r600_context *)ctx;
 167         struct r600_blend_state *blend = (struct r600_blend_state *)state;
 168
 169         if (blend == NULL) {
 170                 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
 171                 return;
 172         }
 173
 174         r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
 175 }
 176
 177 static void r600_set_blend_color(struct pipe_context *ctx,
 178                                  const struct pipe_blend_color *state)
 179 {
 180         struct r600_context *rctx = (struct r600_context *)ctx;
 181
 182         rctx->blend_color.state = *state;
 183         r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
 184 }
 185
 186 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
 187 {
 188         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 189         struct pipe_blend_color *state = &rctx->blend_color.state;
 190
 191         r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 192         radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
 193         radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
 194         radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
 195         radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 196 }
 197
 198 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
 199 {
 200         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 201         struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
 202
 203         r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
 204         r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
 205         radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
 206         radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
 207         if (a->last_draw_was_indirect) {
 208                 a->last_draw_was_indirect = false;
 209                 r600_write_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
 210         }
 211 }
 212
 213 static void r600_set_clip_state(struct pipe_context *ctx,
 214                                 const struct pipe_clip_state *state)
 215 {
 216         struct r600_context *rctx = (struct r600_context *)ctx;
 217         struct pipe_constant_buffer cb;
 218
 219         rctx->clip_state.state = *state;
 220         r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
 221
 222         cb.buffer = NULL;
 223         cb.user_buffer = state->ucp;
 224         cb.buffer_offset = 0;
 225         cb.buffer_size = 4*4*8;
 226         ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
 227         pipe_resource_reference(&cb.buffer, NULL);
 228 }
 229
 230 static void r600_set_stencil_ref(struct pipe_context *ctx,
 231                                  const struct r600_stencil_ref *state)
 232 {
 233         struct r600_context *rctx = (struct r600_context *)ctx;
 234
 235         rctx->stencil_ref.state = *state;
 236         r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
 237 }
 238
 239 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
 240 {
 241         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 242         struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
 243
 244         r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 245         radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
 246                          S_028430_STENCILREF(a->state.ref_value[0]) |
 247                          S_028430_STENCILMASK(a->state.valuemask[0]) |
 248                          S_028430_STENCILWRITEMASK(a->state.writemask[0]));
 249         radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
 250                          S_028434_STENCILREF_BF(a->state.ref_value[1]) |
 251                          S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
 252                          S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
 253 }
 254
 255 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 256                                       const struct pipe_stencil_ref *state)
 257 {
 258         struct r600_context *rctx = (struct r600_context *)ctx;
 259         struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
 260         struct r600_stencil_ref ref;
 261
 262         rctx->stencil_ref.pipe_state = *state;
 263
 264         if (!dsa)
 265                 return;
 266
 267         ref.ref_value[0] = state->ref_value[0];
 268         ref.ref_value[1] = state->ref_value[1];
 269         ref.valuemask[0] = dsa->valuemask[0];
 270         ref.valuemask[1] = dsa->valuemask[1];
 271         ref.writemask[0] = dsa->writemask[0];
 272         ref.writemask[1] = dsa->writemask[1];
 273
 274         r600_set_stencil_ref(ctx, &ref);
 275 }
 276
 277 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 278 {
 279         struct r600_context *rctx = (struct r600_context *)ctx;
 280         struct r600_dsa_state *dsa = state;
 281         struct r600_stencil_ref ref;
 282
 283         if (state == NULL) {
 284                 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
 285                 return;
 286         }
 287
 288         r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
 289
 290         ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
 291         ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
 292         ref.valuemask[0] = dsa->valuemask[0];
 293         ref.valuemask[1] = dsa->valuemask[1];
 294         ref.writemask[0] = dsa->writemask[0];
 295         ref.writemask[1] = dsa->writemask[1];
 296         if (rctx->zwritemask != dsa->zwritemask) {
 297                 rctx->zwritemask = dsa->zwritemask;
 298                 if (rctx->b.chip_class >= EVERGREEN) {
 299                         /* work around some issue when not writing to zbuffer
 300                          * we are having lockup on evergreen so do not enable
 301                          * hyperz when not writing zbuffer
 302                          */
 303                         r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
 304                 }
 305         }
 306
 307         r600_set_stencil_ref(ctx, &ref);
 308
 309         /* Update alphatest state. */
 310         if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
 311             rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
 312                 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 313                 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 314                 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
 315         }
 316 }
 317
 318 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 319 {
 320         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 321         struct r600_context *rctx = (struct r600_context *)ctx;
 322
 323         if (state == NULL)
 324                 return;
 325
 326         rctx->rasterizer = rs;
 327
 328         r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
 329
 330         if (rs->offset_enable &&
 331             (rs->offset_units != rctx->poly_offset_state.offset_units ||
 332              rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
 333                 rctx->poly_offset_state.offset_units = rs->offset_units;
 334                 rctx->poly_offset_state.offset_scale = rs->offset_scale;
 335                 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
 336         }
 337
 338         /* Update clip_misc_state. */
 339         if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
 340             rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
 341                 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 342                 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
 343                 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
 344         }
 345
 346         /* Workaround for a missing scissor enable on r600. */
 347         if (rctx->b.chip_class == R600 &&
 348             rs->scissor_enable != rctx->scissor[0].enable) {
 349                 rctx->scissor[0].enable = rs->scissor_enable;
 350                 r600_mark_atom_dirty(rctx, &rctx->scissor[0].atom);
 351         }
 352
 353         /* Re-emit PA_SC_LINE_STIPPLE. */
 354         rctx->last_primitive_type = -1;
 355 }
 356
 357 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 358 {
 359         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 360
 361         r600_release_command_buffer(&rs->buffer);
 362         FREE(rs);
 363 }
 364
 365 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 366                                       struct pipe_sampler_view *state)
 367 {
 368         struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
 369
 370         if (view->tex_resource->gpu_address &&
 371             view->tex_resource->b.b.target == PIPE_BUFFER)
 372                 LIST_DELINIT(&view->list);
 373
 374         pipe_resource_reference(&state->texture, NULL);
 375         FREE(view);
 376 }
 377
 378 void r600_sampler_states_dirty(struct r600_context *rctx,
 379                                struct r600_sampler_states *state)
 380 {
 381         if (state->dirty_mask) {
 382                 if (state->dirty_mask & state->has_bordercolor_mask) {
 383                         rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
 384                 }
 385                 state->atom.num_dw =
 386                         util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
 387                         util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
 388                 r600_mark_atom_dirty(rctx, &state->atom);
 389         }
 390 }
 391
 392 static void r600_bind_sampler_states(struct pipe_context *pipe,
 393                                unsigned shader,
 394                                unsigned start,
 395                                unsigned count, void **states)
 396 {
 397         struct r600_context *rctx = (struct r600_context *)pipe;
 398         struct r600_textures_info *dst = &rctx->samplers[shader];
 399         struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
 400         int seamless_cube_map = -1;
 401         unsigned i;
 402         /* This sets 1-bit for states with index >= count. */
 403         uint32_t disable_mask = ~((1ull << count) - 1);
 404         /* These are the new states set by this function. */
 405         uint32_t new_mask = 0;
 406
 407         assert(start == 0); /* XXX fix below */
 408
 409         if (shader != PIPE_SHADER_VERTEX &&
 410             shader != PIPE_SHADER_FRAGMENT) {
 411                 return;
 412         }
 413
 414         for (i = 0; i < count; i++) {
 415                 struct r600_pipe_sampler_state *rstate = rstates[i];
 416
 417                 if (rstate == dst->states.states[i]) {
 418                         continue;
 419                 }
 420
 421                 if (rstate) {
 422                         if (rstate->border_color_use) {
 423                                 dst->states.has_bordercolor_mask |= 1 << i;
 424                         } else {
 425                                 dst->states.has_bordercolor_mask &= ~(1 << i);
 426                         }
 427                         seamless_cube_map = rstate->seamless_cube_map;
 428
 429                         new_mask |= 1 << i;
 430                 } else {
 431                         disable_mask |= 1 << i;
 432                 }
 433         }
 434
 435         memcpy(dst->states.states, rstates, sizeof(void*) * count);
 436         memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
 437
 438         dst->states.enabled_mask &= ~disable_mask;
 439         dst->states.dirty_mask &= dst->states.enabled_mask;
 440         dst->states.enabled_mask |= new_mask;
 441         dst->states.dirty_mask |= new_mask;
 442         dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
 443
 444         r600_sampler_states_dirty(rctx, &dst->states);
 445
 446         /* Seamless cubemap state. */
 447         if (rctx->b.chip_class <= R700 &&
 448             seamless_cube_map != -1 &&
 449             seamless_cube_map != rctx->seamless_cube_map.enabled) {
 450                 /* change in TA_CNTL_AUX need a pipeline flush */
 451                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
 452                 rctx->seamless_cube_map.enabled = seamless_cube_map;
 453                 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
 454         }
 455 }
 456
 457 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
 458 {
 459         free(state);
 460 }
 461
 462 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
 463 {
 464         struct r600_context *rctx = (struct r600_context *)ctx;
 465         struct r600_blend_state *blend = (struct r600_blend_state*)state;
 466
 467         if (rctx->blend_state.cso == state) {
 468                 ctx->bind_blend_state(ctx, NULL);
 469         }
 470
 471         r600_release_command_buffer(&blend->buffer);
 472         r600_release_command_buffer(&blend->buffer_no_blend);
 473         FREE(blend);
 474 }
 475
 476 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
 477 {
 478         struct r600_context *rctx = (struct r600_context *)ctx;
 479         struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
 480
 481         if (rctx->dsa_state.cso == state) {
 482                 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
 483         }
 484
 485         r600_release_command_buffer(&dsa->buffer);
 486         free(dsa);
 487 }
 488
 489 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 490 {
 491         struct r600_context *rctx = (struct r600_context *)ctx;
 492
 493         r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
 494 }
 495
 496 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 497 {
 498         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
 499         pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
 500         FREE(shader);
 501 }
 502
 503 static void r600_set_index_buffer(struct pipe_context *ctx,
 504                            const struct pipe_index_buffer *ib)
 505 {
 506         struct r600_context *rctx = (struct r600_context *)ctx;
 507
 508         if (ib) {
 509                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 510                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 511                 r600_context_add_resource_size(ctx, ib->buffer);
 512         } else {
 513                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 514         }
 515 }
 516
 517 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 518 {
 519         if (rctx->vertex_buffer_state.dirty_mask) {
 520                 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
 521                 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
 522                                                util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 523                 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
 524         }
 525 }
 526
 527 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 528                                     unsigned start_slot, unsigned count,
 529                                     const struct pipe_vertex_buffer *input)
 530 {
 531         struct r600_context *rctx = (struct r600_context *)ctx;
 532         struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
 533         struct pipe_vertex_buffer *vb = state->vb + start_slot;
 534         unsigned i;
 535         uint32_t disable_mask = 0;
 536         /* These are the new buffers set by this function. */
 537         uint32_t new_buffer_mask = 0;
 538
 539         /* Set vertex buffers. */
 540         if (input) {
 541                 for (i = 0; i < count; i++) {
 542                         if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
 543                                 if (input[i].buffer) {
 544                                         vb[i].stride = input[i].stride;
 545                                         vb[i].buffer_offset = input[i].buffer_offset;
 546                                         pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 547                                         new_buffer_mask |= 1 << i;
 548                                         r600_context_add_resource_size(ctx, input[i].buffer);
 549                                 } else {
 550                                         pipe_resource_reference(&vb[i].buffer, NULL);
 551                                         disable_mask |= 1 << i;
 552                                 }
 553                         }
 554                 }
 555         } else {
 556                 for (i = 0; i < count; i++) {
 557                         pipe_resource_reference(&vb[i].buffer, NULL);
 558                 }
 559                 disable_mask = ((1ull << count) - 1);
 560         }
 561
 562         disable_mask <<= start_slot;
 563         new_buffer_mask <<= start_slot;
 564
 565         rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 566         rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
 567         rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
 568         rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
 569
 570         r600_vertex_buffers_dirty(rctx);
 571 }
 572
 573 void r600_sampler_views_dirty(struct r600_context *rctx,
 574                               struct r600_samplerview_state *state)
 575 {
 576         if (state->dirty_mask) {
 577                 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
 578                 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
 579                                      util_bitcount(state->dirty_mask);
 580                 r600_mark_atom_dirty(rctx, &state->atom);
 581         }
 582 }
 583
 584 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 585                                    unsigned start, unsigned count,
 586                                    struct pipe_sampler_view **views)
 587 {
 588         struct r600_context *rctx = (struct r600_context *) pipe;
 589         struct r600_textures_info *dst = &rctx->samplers[shader];
 590         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 591         uint32_t dirty_sampler_states_mask = 0;
 592         unsigned i;
 593         /* This sets 1-bit for textures with index >= count. */
 594         uint32_t disable_mask = ~((1ull << count) - 1);
 595         /* These are the new textures set by this function. */
 596         uint32_t new_mask = 0;
 597
 598         /* Set textures with index >= count to NULL. */
 599         uint32_t remaining_mask;
 600
 601         assert(start == 0); /* XXX fix below */
 602
 603         if (shader == PIPE_SHADER_COMPUTE) {
 604                 evergreen_set_cs_sampler_view(pipe, start, count, views);
 605                 return;
 606         }
 607
 608         remaining_mask = dst->views.enabled_mask & disable_mask;
 609
 610         while (remaining_mask) {
 611                 i = u_bit_scan(&remaining_mask);
 612                 assert(dst->views.views[i]);
 613
 614                 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 615         }
 616
 617         for (i = 0; i < count; i++) {
 618                 if (rviews[i] == dst->views.views[i]) {
 619                         continue;
 620                 }
 621
 622                 if (rviews[i]) {
 623                         struct r600_texture *rtex =
 624                                 (struct r600_texture*)rviews[i]->base.texture;
 625
 626                         if (rviews[i]->base.texture->target != PIPE_BUFFER) {
 627                                 if (rtex->is_depth && !rtex->is_flushing_texture) {
 628                                         dst->views.compressed_depthtex_mask |= 1 << i;
 629                                 } else {
 630                                         dst->views.compressed_depthtex_mask &= ~(1 << i);
 631                                 }
 632
 633                                 /* Track compressed colorbuffers. */
 634                                 if (rtex->cmask.size) {
 635                                         dst->views.compressed_colortex_mask |= 1 << i;
 636                                 } else {
 637                                         dst->views.compressed_colortex_mask &= ~(1 << i);
 638                                 }
 639                         }
 640                         /* Changing from array to non-arrays textures and vice versa requires
 641                          * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
 642                         if (rctx->b.chip_class <= R700 &&
 643                             (dst->states.enabled_mask & (1 << i)) &&
 644                             (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 645                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
 646                                 dirty_sampler_states_mask |= 1 << i;
 647                         }
 648
 649                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 650                         new_mask |= 1 << i;
 651                         r600_context_add_resource_size(pipe, views[i]->texture);
 652                 } else {
 653                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 654                         disable_mask |= 1 << i;
 655                 }
 656         }
 657
 658         dst->views.enabled_mask &= ~disable_mask;
 659         dst->views.dirty_mask &= dst->views.enabled_mask;
 660         dst->views.enabled_mask |= new_mask;
 661         dst->views.dirty_mask |= new_mask;
 662         dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
 663         dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
 664         dst->views.dirty_buffer_constants = TRUE;
 665         r600_sampler_views_dirty(rctx, &dst->views);
 666
 667         if (dirty_sampler_states_mask) {
 668                 dst->states.dirty_mask |= dirty_sampler_states_mask;
 669                 r600_sampler_states_dirty(rctx, &dst->states);
 670         }
 671 }
 672
 673 static void r600_set_viewport_states(struct pipe_context *ctx,
 674                                      unsigned start_slot,
 675                                      unsigned num_viewports,
 676                                      const struct pipe_viewport_state *state)
 677 {
 678         struct r600_context *rctx = (struct r600_context *)ctx;
 679         int i;
 680
 681         for (i = start_slot; i < start_slot + num_viewports; i++) {
 682                 rctx->viewport[i].state = state[i - start_slot];
 683                 r600_mark_atom_dirty(rctx, &rctx->viewport[i].atom);
 684         }
 685 }
 686
 687 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
 688 {
 689         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 690         struct r600_viewport_state *rstate = (struct r600_viewport_state *)atom;
 691         struct pipe_viewport_state *state = &rstate->state;
 692         int offset = rstate->idx * 6 * 4;
 693
 694         r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
 695         radeon_emit(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
 696         radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
 697         radeon_emit(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
 698         radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
 699         radeon_emit(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
 700         radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
 701 }
 702
 703 /* Compute the key for the hw shader variant */
 704 static inline struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
 705                 struct r600_pipe_shader_selector * sel)
 706 {
 707         struct r600_context *rctx = (struct r600_context *)ctx;
 708         struct r600_shader_key key;
 709         memset(&key, 0, sizeof(key));
 710
 711         if (sel->type == PIPE_SHADER_FRAGMENT) {
 712                 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
 713                 key.alpha_to_one = rctx->alpha_to_one &&
 714                                    rctx->rasterizer && rctx->rasterizer->multisample_enable &&
 715                                    !rctx->framebuffer.cb0_is_integer;
 716                 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
 717                 /* Dual-source blending only makes sense with nr_cbufs == 1. */
 718                 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
 719                         key.nr_cbufs = 2;
 720         } else if (sel->type == PIPE_SHADER_VERTEX) {
 721                 key.vs_as_es = (rctx->gs_shader != NULL);
 722                 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
 723                         key.vs_as_gs_a = true;
 724                         key.vs_prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
 725                 }
 726         }
 727         return key;
 728 }
 729
 730 /* Select the hw shader variant depending on the current state.
 731  * (*dirty) is set to 1 if current variant was changed */
 732 static int r600_shader_select(struct pipe_context *ctx,
 733         struct r600_pipe_shader_selector* sel,
 734         bool *dirty)
 735 {
 736         struct r600_shader_key key;
 737         struct r600_pipe_shader * shader = NULL;
 738         int r;
 739
 740         memset(&key, 0, sizeof(key));
 741         key = r600_shader_selector_key(ctx, sel);
 742
 743         /* Check if we don't need to change anything.
 744          * This path is also used for most shaders that don't need multiple
 745          * variants, it will cost just a computation of the key and this
 746          * test. */
 747         if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
 748                 return 0;
 749         }
 750
 751         /* lookup if we have other variants in the list */
 752         if (sel->num_shaders > 1) {
 753                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 754
 755                 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
 756                         p = c;
 757                         c = c->next_variant;
 758                 }
 759
 760                 if (c) {
 761                         p->next_variant = c->next_variant;
 762                         shader = c;
 763                 }
 764         }
 765
 766         if (unlikely(!shader)) {
 767                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 768                 shader->selector = sel;
 769
 770                 r = r600_pipe_shader_create(ctx, shader, key);
 771                 if (unlikely(r)) {
 772                         R600_ERR("Failed to build shader variant (type=%u) %d\n",
 773                                  sel->type, r);
 774                         sel->current = NULL;
 775                         FREE(shader);
 776                         return r;
 777                 }
 778
 779                 /* We don't know the value of nr_ps_max_color_exports until we built
 780                  * at least one variant, so we may need to recompute the key after
 781                  * building first variant. */
 782                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 783                                 sel->num_shaders == 0) {
 784                         sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
 785                         key = r600_shader_selector_key(ctx, sel);
 786                 }
 787
 788                 memcpy(&shader->key, &key, sizeof(key));
 789                 sel->num_shaders++;
 790         }
 791
 792         if (dirty)
 793                 *dirty = true;
 794
 795         shader->next_variant = sel->current;
 796         sel->current = shader;
 797
 798         return 0;
 799 }
 800
 801 static void *r600_create_shader_state(struct pipe_context *ctx,
 802                                const struct pipe_shader_state *state,
 803                                unsigned pipe_shader_type)
 804 {
 805         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 806
 807         sel->type = pipe_shader_type;
 808         sel->tokens = tgsi_dup_tokens(state->tokens);
 809         sel->so = state->stream_output;
 810         return sel;
 811 }
 812
 813 static void *r600_create_ps_state(struct pipe_context *ctx,
 814                                          const struct pipe_shader_state *state)
 815 {
 816         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 817 }
 818
 819 static void *r600_create_vs_state(struct pipe_context *ctx,
 820                                          const struct pipe_shader_state *state)
 821 {
 822         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 823 }
 824
 825 static void *r600_create_gs_state(struct pipe_context *ctx,
 826                                          const struct pipe_shader_state *state)
 827 {
 828         return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
 829 }
 830
 831 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 832 {
 833         struct r600_context *rctx = (struct r600_context *)ctx;
 834
 835         if (!state)
 836                 state = rctx->dummy_pixel_shader;
 837
 838         rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 839 }
 840
 841 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 842 {
 843         struct r600_context *rctx = (struct r600_context *)ctx;
 844
 845         if (!state)
 846                 return;
 847
 848         rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 849         rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
 850 }
 851
 852 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
 853 {
 854         struct r600_context *rctx = (struct r600_context *)ctx;
 855
 856         rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
 857
 858         if (!state)
 859                 return;
 860         rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
 861 }
 862
 863 static void r600_delete_shader_selector(struct pipe_context *ctx,
 864                 struct r600_pipe_shader_selector *sel)
 865 {
 866         struct r600_pipe_shader *p = sel->current, *c;
 867         while (p) {
 868                 c = p->next_variant;
 869                 r600_pipe_shader_destroy(ctx, p);
 870                 free(p);
 871                 p = c;
 872         }
 873
 874         free(sel->tokens);
 875         free(sel);
 876 }
 877
 878
 879 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
 880 {
 881         struct r600_context *rctx = (struct r600_context *)ctx;
 882         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 883
 884         if (rctx->ps_shader == sel) {
 885                 rctx->ps_shader = NULL;
 886         }
 887
 888         r600_delete_shader_selector(ctx, sel);
 889 }
 890
 891 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
 892 {
 893         struct r600_context *rctx = (struct r600_context *)ctx;
 894         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 895
 896         if (rctx->vs_shader == sel) {
 897                 rctx->vs_shader = NULL;
 898         }
 899
 900         r600_delete_shader_selector(ctx, sel);
 901 }
 902
 903
 904 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
 905 {
 906         struct r600_context *rctx = (struct r600_context *)ctx;
 907         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 908
 909         if (rctx->gs_shader == sel) {
 910                 rctx->gs_shader = NULL;
 911         }
 912
 913         r600_delete_shader_selector(ctx, sel);
 914 }
 915
 916
 917 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 918 {
 919         if (state->dirty_mask) {
 920                 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
 921                 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 922                                                                    : util_bitcount(state->dirty_mask)*19;
 923                 r600_mark_atom_dirty(rctx, &state->atom);
 924         }
 925 }
 926
 927 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 928                                      struct pipe_constant_buffer *input)
 929 {
 930         struct r600_context *rctx = (struct r600_context *)ctx;
 931         struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
 932         struct pipe_constant_buffer *cb;
 933         const uint8_t *ptr;
 934
 935         /* Note that the state tracker can unbind constant buffers by
 936          * passing NULL here.
 937          */
 938         if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
 939                 state->enabled_mask &= ~(1 << index);
 940                 state->dirty_mask &= ~(1 << index);
 941                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 942                 return;
 943         }
 944
 945         cb = &state->cb[index];
 946         cb->buffer_size = input->buffer_size;
 947
 948         ptr = input->user_buffer;
 949
 950         if (ptr) {
 951                 /* Upload the user buffer. */
 952                 if (R600_BIG_ENDIAN) {
 953                         uint32_t *tmpPtr;
 954                         unsigned i, size = input->buffer_size;
 955
 956                         if (!(tmpPtr = malloc(size))) {
 957                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 958                                 return;
 959                         }
 960
 961                         for (i = 0; i < size / 4; ++i) {
 962                                 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
 963                         }
 964
 965                         u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 966                         free(tmpPtr);
 967                 } else {
 968                         u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 969                 }
 970                 /* account it in gtt */
 971                 rctx->b.gtt += input->buffer_size;
 972         } else {
 973                 /* Setup the hw buffer. */
 974                 cb->buffer_offset = input->buffer_offset;
 975                 pipe_resource_reference(&cb->buffer, input->buffer);
 976                 r600_context_add_resource_size(ctx, input->buffer);
 977         }
 978
 979         state->enabled_mask |= 1 << index;
 980         state->dirty_mask |= 1 << index;
 981         r600_constant_buffers_dirty(rctx, state);
 982 }
 983
 984 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 985 {
 986         struct r600_context *rctx = (struct r600_context*)pipe;
 987
 988         if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
 989                 return;
 990
 991         rctx->sample_mask.sample_mask = sample_mask;
 992         r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
 993 }
 994
 995 /*
 996  * On r600/700 hw we don't have vertex fetch swizzle, though TBO
 997  * doesn't require full swizzles it does need masking and setting alpha
 998  * to one, so we setup a set of 5 constants with the masks + alpha value
 999  * then in the shader, we AND the 4 components with 0xffffffff or 0,
1000  * then OR the alpha with the value given here.
1001  * We use a 6th constant to store the txq buffer size in
1002  * we use 7th slot for number of cube layers in a cube map array.
1003  */
1004 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1005 {
1006         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1007         int bits;
1008         uint32_t array_size;
1009         struct pipe_constant_buffer cb;
1010         int i, j;
1011
1012         if (!samplers->views.dirty_buffer_constants)
1013                 return;
1014
1015         samplers->views.dirty_buffer_constants = FALSE;
1016
1017         bits = util_last_bit(samplers->views.enabled_mask);
1018         array_size = bits * 8 * sizeof(uint32_t) * 4;
1019         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1020         memset(samplers->buffer_constants, 0, array_size);
1021         for (i = 0; i < bits; i++) {
1022                 if (samplers->views.enabled_mask & (1 << i)) {
1023                         int offset = i * 8;
1024                         const struct util_format_description *desc;
1025                         desc = util_format_description(samplers->views.views[i]->base.format);
1026
1027                         for (j = 0; j < 4; j++)
1028                                 if (j < desc->nr_channels)
1029                                         samplers->buffer_constants[offset+j] = 0xffffffff;
1030                                 else
1031                                         samplers->buffer_constants[offset+j] = 0x0;
1032                         if (desc->nr_channels < 4) {
1033                                 if (desc->channel[0].pure_integer)
1034                                         samplers->buffer_constants[offset+4] = 1;
1035                                 else
1036                                         samplers->buffer_constants[offset+4] = fui(1.0);
1037                         } else
1038                                 samplers->buffer_constants[offset + 4] = 0;
1039
1040                         samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1041                         samplers->buffer_constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1042                 }
1043         }
1044
1045         cb.buffer = NULL;
1046         cb.user_buffer = samplers->buffer_constants;
1047         cb.buffer_offset = 0;
1048         cb.buffer_size = array_size;
1049         rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1050         pipe_resource_reference(&cb.buffer, NULL);
1051 }
1052
1053 /* On evergreen we store two values
1054  * 1. buffer size for TXQ
1055  * 2. number of cube layers in a cube map array.
1056  */
1057 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1058 {
1059         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1060         int bits;
1061         uint32_t array_size;
1062         struct pipe_constant_buffer cb;
1063         int i;
1064
1065         if (!samplers->views.dirty_buffer_constants)
1066                 return;
1067
1068         samplers->views.dirty_buffer_constants = FALSE;
1069
1070         bits = util_last_bit(samplers->views.enabled_mask);
1071         array_size = bits * 2 * sizeof(uint32_t) * 4;
1072         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1073         memset(samplers->buffer_constants, 0, array_size);
1074         for (i = 0; i < bits; i++) {
1075                 if (samplers->views.enabled_mask & (1 << i)) {
1076                         uint32_t offset = i * 2;
1077                         samplers->buffer_constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1078                         samplers->buffer_constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1079                 }
1080         }
1081
1082         cb.buffer = NULL;
1083         cb.user_buffer = samplers->buffer_constants;
1084         cb.buffer_offset = 0;
1085         cb.buffer_size = array_size;
1086         rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1087         pipe_resource_reference(&cb.buffer, NULL);
1088 }
1089
1090 /* set sample xy locations as array of fragment shader constants */
1091 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1092 {
1093         struct pipe_constant_buffer constbuf = {0};
1094         float values[4*16] = {0.0f};
1095         int i;
1096         struct pipe_context *ctx = &rctx->b.b;
1097
1098         assert(rctx->framebuffer.nr_samples <= Elements(values)/4);
1099         for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1100                 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &values[4*i]);
1101                 /* Also fill in center-zeroed positions used for interpolateAtSample */
1102                 values[4*i + 2] = values[4*i + 0] - 0.5f;
1103                 values[4*i + 3] = values[4*i + 1] - 0.5f;
1104         }
1105
1106         constbuf.user_buffer = values;
1107         constbuf.buffer_size = rctx->framebuffer.nr_samples * 4 * 4;
1108         ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
1109                 R600_SAMPLE_POSITIONS_CONST_BUFFER, &constbuf);
1110         pipe_resource_reference(&constbuf.buffer, NULL);
1111 }
1112
1113 static void update_shader_atom(struct pipe_context *ctx,
1114                                struct r600_shader_state *state,
1115                                struct r600_pipe_shader *shader)
1116 {
1117         struct r600_context *rctx = (struct r600_context *)ctx;
1118
1119         state->shader = shader;
1120         if (shader) {
1121                 state->atom.num_dw = shader->command_buffer.num_dw;
1122                 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1123         } else {
1124                 state->atom.num_dw = 0;
1125         }
1126         r600_mark_atom_dirty(rctx, &state->atom);
1127 }
1128
1129 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1130 {
1131         if (rctx->shader_stages.geom_enable != enable) {
1132                 rctx->shader_stages.geom_enable = enable;
1133                 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1134         }
1135
1136         if (rctx->gs_rings.enable != enable) {
1137                 rctx->gs_rings.enable = enable;
1138                 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1139
1140                 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1141                         unsigned size = 0x1C000;
1142                         rctx->gs_rings.esgs_ring.buffer =
1143                                         pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1144                                                         PIPE_USAGE_DEFAULT, size);
1145                         rctx->gs_rings.esgs_ring.buffer_size = size;
1146
1147                         size = 0x4000000;
1148
1149                         rctx->gs_rings.gsvs_ring.buffer =
1150                                         pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1151                                                         PIPE_USAGE_DEFAULT, size);
1152                         rctx->gs_rings.gsvs_ring.buffer_size = size;
1153                 }
1154
1155                 if (enable) {
1156                         r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1157                                         R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1158                         r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1159                                         R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1160                 } else {
1161                         r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1162                                         R600_GS_RING_CONST_BUFFER, NULL);
1163                         r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1164                                         R600_GS_RING_CONST_BUFFER, NULL);
1165                 }
1166         }
1167 }
1168
1169 static bool r600_update_derived_state(struct r600_context *rctx)
1170 {
1171         struct pipe_context * ctx = (struct pipe_context*)rctx;
1172         bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1173         bool blend_disable;
1174         bool need_buf_const;
1175         if (!rctx->blitter->running) {
1176                 unsigned i;
1177
1178                 /* Decompress textures if needed. */
1179                 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1180                         struct r600_samplerview_state *views = &rctx->samplers[i].views;
1181                         if (views->compressed_depthtex_mask) {
1182                                 r600_decompress_depth_textures(rctx, views);
1183                         }
1184                         if (views->compressed_colortex_mask) {
1185                                 r600_decompress_color_textures(rctx, views);
1186                         }
1187                 }
1188         }
1189
1190         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1191         if (unlikely(!rctx->ps_shader->current))
1192                 return false;
1193
1194         update_gs_block_state(rctx, rctx->gs_shader != NULL);
1195
1196         if (rctx->gs_shader) {
1197                 r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
1198                 if (unlikely(!rctx->gs_shader->current))
1199                         return false;
1200
1201                 if (!rctx->shader_stages.geom_enable) {
1202                         rctx->shader_stages.geom_enable = true;
1203                         r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1204                 }
1205
1206                 /* gs_shader provides GS and VS (copy shader) */
1207                 if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
1208                         update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
1209                         update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
1210                         /* Update clip misc state. */
1211                         if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1212                                         rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1213                                         rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
1214                                 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
1215                                 rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
1216                                 rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
1217                                 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1218                         }
1219                         rctx->b.streamout.enabled_stream_buffers_mask = rctx->gs_shader->current->gs_copy_shader->enabled_stream_buffers_mask;
1220                 }
1221
1222                 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1223                 if (unlikely(!rctx->vs_shader->current))
1224                         return false;
1225
1226                 /* vs_shader is used as ES */
1227                 if (unlikely(vs_dirty || rctx->export_shader.shader != rctx->vs_shader->current)) {
1228                         update_shader_atom(ctx, &rctx->export_shader, rctx->vs_shader->current);
1229                 }
1230         } else {
1231                 if (unlikely(rctx->geometry_shader.shader)) {
1232                         update_shader_atom(ctx, &rctx->geometry_shader, NULL);
1233                         update_shader_atom(ctx, &rctx->export_shader, NULL);
1234                         rctx->shader_stages.geom_enable = false;
1235                         r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1236                 }
1237
1238                 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1239                 if (unlikely(!rctx->vs_shader->current))
1240                         return false;
1241
1242                 if (unlikely(vs_dirty || rctx->vertex_shader.shader != rctx->vs_shader->current)) {
1243                         update_shader_atom(ctx, &rctx->vertex_shader, rctx->vs_shader->current);
1244
1245                         /* Update clip misc state. */
1246                         if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1247                                         rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1248                                         rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
1249                                 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
1250                                 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
1251                                 rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
1252                                 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1253                         }
1254                         rctx->b.streamout.enabled_stream_buffers_mask = rctx->vs_shader->current->enabled_stream_buffers_mask;
1255                 }
1256         }
1257
1258
1259         if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current ||
1260                 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1261                 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1262
1263                 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1264                         rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1265                         r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1266                 }
1267
1268                 if (rctx->b.chip_class <= R700) {
1269                         bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1270
1271                         if (rctx->cb_misc_state.multiwrite != multiwrite) {
1272                                 rctx->cb_misc_state.multiwrite = multiwrite;
1273                                 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1274                         }
1275                 }
1276
1277                 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1278                                 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1279                                                 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1280
1281                         if (rctx->b.chip_class >= EVERGREEN)
1282                                 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1283                         else
1284                                 r600_update_ps_state(ctx, rctx->ps_shader->current);
1285                 }
1286
1287                 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1288                 update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
1289         }
1290
1291         if (rctx->b.chip_class >= EVERGREEN) {
1292                 evergreen_update_db_shader_control(rctx);
1293         } else {
1294                 r600_update_db_shader_control(rctx);
1295         }
1296
1297         /* on R600 we stuff masks + txq info into one constant buffer */
1298         /* on evergreen we only need a txq info one */
1299         if (rctx->ps_shader) {
1300                 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1301                 if (need_buf_const) {
1302                         if (rctx->b.chip_class < EVERGREEN)
1303                                 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1304                         else
1305                                 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1306                 }
1307         }
1308
1309         if (rctx->vs_shader) {
1310                 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1311                 if (need_buf_const) {
1312                         if (rctx->b.chip_class < EVERGREEN)
1313                                 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1314                         else
1315                                 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1316                 }
1317         }
1318
1319         if (rctx->gs_shader) {
1320                 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1321                 if (need_buf_const) {
1322                         if (rctx->b.chip_class < EVERGREEN)
1323                                 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1324                         else
1325                                 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1326                 }
1327         }
1328
1329         if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1330                 if (!r600_adjust_gprs(rctx)) {
1331                         /* discard rendering */
1332                         return false;
1333                 }
1334         }
1335
1336         blend_disable = (rctx->dual_src_blend &&
1337                         rctx->ps_shader->current->nr_ps_color_outputs < 2);
1338
1339         if (blend_disable != rctx->force_blend_disable) {
1340                 rctx->force_blend_disable = blend_disable;
1341                 r600_bind_blend_state_internal(rctx,
1342                                                rctx->blend_state.cso,
1343                                                blend_disable);
1344         }
1345
1346         return true;
1347 }
1348
1349 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1350 {
1351         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1352         struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1353
1354         r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1355                                state->pa_cl_clip_cntl |
1356                                (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1357                                S_028810_CLIP_DISABLE(state->clip_disable));
1358         r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1359                                state->pa_cl_vs_out_cntl |
1360                                (state->clip_plane_enable & state->clip_dist_write));
1361 }
1362
1363 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1364 {
1365         struct r600_context *rctx = (struct r600_context *)ctx;
1366         struct pipe_draw_info info = *dinfo;
1367         struct pipe_index_buffer ib = {};
1368         unsigned i;
1369         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1370
1371         if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
1372                 return;
1373         }
1374
1375         if (!rctx->vs_shader || !rctx->ps_shader) {
1376                 assert(0);
1377                 return;
1378         }
1379
1380         /* make sure that the gfx ring is only one active */
1381         if (rctx->b.rings.dma.cs && rctx->b.rings.dma.cs->cdw) {
1382                 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1383         }
1384
1385         if (!r600_update_derived_state(rctx)) {
1386                 /* useless to render because current rendering command
1387                  * can't be achieved
1388                  */
1389                 return;
1390         }
1391
1392         if (info.indexed) {
1393                 /* Initialize the index buffer struct. */
1394                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1395                 ib.user_buffer = rctx->index_buffer.user_buffer;
1396                 ib.index_size = rctx->index_buffer.index_size;
1397                 ib.offset = rctx->index_buffer.offset;
1398                 if (!info.indirect) {
1399                         ib.offset += info.start * ib.index_size;
1400                 }
1401
1402                 /* Translate 8-bit indices to 16-bit. */
1403                 if (unlikely(ib.index_size == 1)) {
1404                         struct pipe_resource *out_buffer = NULL;
1405                         unsigned out_offset;
1406                         void *ptr;
1407                         unsigned start, count;
1408
1409                         if (likely(!info.indirect)) {
1410                                 start = 0;
1411                                 count = info.count;
1412                         }
1413                         else {
1414                                 /* Have to get start/count from indirect buffer, slow path ahead... */
1415                                 struct r600_resource *indirect_resource = (struct r600_resource *)info.indirect;
1416                                 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1417                                         PIPE_TRANSFER_READ);
1418                                 if (data) {
1419                                         data += info.indirect_offset / sizeof(unsigned);
1420                                         start = data[2] * ib.index_size;
1421                                         count = data[0];
1422                                 }
1423                                 else {
1424                                         start = 0;
1425                                         count = 0;
1426                                 }
1427                         }
1428
1429                         u_upload_alloc(rctx->b.uploader, start, count * 2,
1430                                        &out_offset, &out_buffer, &ptr);
1431
1432                         util_shorten_ubyte_elts_to_userptr(
1433                                                 &rctx->b.b, &ib, 0, ib.offset + start, count, ptr);
1434
1435                         pipe_resource_reference(&ib.buffer, NULL);
1436                         ib.user_buffer = NULL;
1437                         ib.buffer = out_buffer;
1438                         ib.offset = out_offset;
1439                         ib.index_size = 2;
1440                 }
1441
1442                 /* Upload the index buffer.
1443                  * The upload is skipped for small index counts on little-endian machines
1444                  * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1445                  * Indirect draws never use immediate indices.
1446                  * Note: Instanced rendering in combination with immediate indices hangs. */
1447                 if (ib.user_buffer && (R600_BIG_ENDIAN || info.indirect ||
1448                                                  info.instance_count > 1 ||
1449                                                  info.count*ib.index_size > 20)) {
1450                         u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1451                                       ib.user_buffer, &ib.offset, &ib.buffer);
1452                         ib.user_buffer = NULL;
1453                 }
1454         } else {
1455                 info.index_bias = info.start;
1456         }
1457
1458         /* Set the index offset and primitive restart. */
1459         if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1460             rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1461             rctx->vgt_state.vgt_indx_offset != info.index_bias ||
1462             (rctx->vgt_state.last_draw_was_indirect && !info.indirect)) {
1463                 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1464                 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1465                 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1466                 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1467         }
1468
1469         /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1470         if (rctx->b.chip_class == R600) {
1471                 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1472                 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1473         }
1474
1475         /* Emit states. */
1476         r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1477         r600_flush_emit(rctx);
1478
1479         for (i = 0; i < R600_NUM_ATOMS; i++) {
1480                 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1481                         continue;
1482                 }
1483                 r600_emit_atom(rctx, rctx->atoms[i]);
1484         }
1485
1486         if (rctx->b.chip_class == CAYMAN) {
1487                 /* Copied from radeonsi. */
1488                 unsigned primgroup_size = 128; /* recommended without a GS */
1489                 bool ia_switch_on_eop = false;
1490                 bool partial_vs_wave = false;
1491
1492                 if (rctx->gs_shader)
1493                         primgroup_size = 64; /* recommended with a GS */
1494
1495                 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1496                     (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1497                         ia_switch_on_eop = true;
1498                 }
1499
1500                 if (rctx->b.streamout.streamout_enabled ||
1501                     rctx->b.streamout.prims_gen_query_enabled)
1502                         partial_vs_wave = true;
1503
1504                 r600_write_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1505                                        S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1506                                        S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1507                                        S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1508         }
1509
1510         /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1511          * even though it should have no effect on those. */
1512         if (rctx->b.chip_class == R600 && rctx->rasterizer) {
1513                 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
1514                 unsigned prim = info.mode;
1515
1516                 if (rctx->gs_shader) {
1517                         prim = rctx->gs_shader->current->shader.gs_output_prim;
1518                 }
1519                 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
1520
1521                 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
1522                     prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
1523                     info.mode == R600_PRIM_RECTANGLE_LIST) {
1524                         su_sc_mode_cntl &= C_028814_CULL_FRONT;
1525                 }
1526                 r600_write_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
1527         }
1528
1529         /* Update start instance. */
1530         if (!info.indirect && rctx->last_start_instance != info.start_instance) {
1531                 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1532                 rctx->last_start_instance = info.start_instance;
1533         }
1534
1535         /* Update the primitive type. */
1536         if (rctx->last_primitive_type != info.mode) {
1537                 unsigned ls_mask = 0;
1538
1539                 if (info.mode == PIPE_PRIM_LINES)
1540                         ls_mask = 1;
1541                 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1542                          info.mode == PIPE_PRIM_LINE_LOOP)
1543                         ls_mask = 2;
1544
1545                 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1546                                        S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1547                                        (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1548                 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1549                                       r600_conv_pipe_prim(info.mode));
1550
1551                 rctx->last_primitive_type = info.mode;
1552         }
1553
1554         /* Draw packets. */
1555         if (!info.indirect) {
1556                 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
1557                 cs->buf[cs->cdw++] = info.instance_count;
1558         }
1559
1560         if (unlikely(info.indirect)) {
1561                 uint64_t va = r600_resource(info.indirect)->gpu_address;
1562                 assert(rctx->b.chip_class >= EVERGREEN);
1563
1564                 // Invalidate so non-indirect draw calls reset this state
1565                 rctx->vgt_state.last_draw_was_indirect = true;
1566                 rctx->last_start_instance = -1;
1567
1568                 cs->buf[cs->cdw++] = PKT3(EG_PKT3_SET_BASE, 2, rctx->b.predicate_drawing);
1569                 cs->buf[cs->cdw++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE;
1570                 cs->buf[cs->cdw++] = va;
1571                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1572
1573                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1574                 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1575                                                            (struct r600_resource*)info.indirect,
1576                                                            RADEON_USAGE_READ, RADEON_PRIO_MIN);
1577         }
1578
1579         if (info.indexed) {
1580                 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
1581                 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1582                                         (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1583                                         (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1584
1585                 if (ib.user_buffer) {
1586                         unsigned size_bytes = info.count*ib.index_size;
1587                         unsigned size_dw = align(size_bytes, 4) / 4;
1588                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
1589                         cs->buf[cs->cdw++] = info.count;
1590                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1591                         memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1592                         cs->cdw += size_dw;
1593                 } else {
1594                         uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
1595
1596                         if (likely(!info.indirect)) {
1597                                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
1598                                 cs->buf[cs->cdw++] = va;
1599                                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1600                                 cs->buf[cs->cdw++] = info.count;
1601                                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1602                                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1603                                 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1604                                                                            (struct r600_resource*)ib.buffer,
1605                                                                            RADEON_USAGE_READ, RADEON_PRIO_MIN);
1606                         }
1607                         else {
1608                                 uint32_t max_size = (ib.buffer->width0 - ib.offset) / ib.index_size;
1609
1610                                 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BASE, 1, rctx->b.predicate_drawing);
1611                                 cs->buf[cs->cdw++] = va;
1612                                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1613
1614                                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1615                                 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1616                                                                            (struct r600_resource*)ib.buffer,
1617                                                                            RADEON_USAGE_READ, RADEON_PRIO_MIN);
1618
1619                                 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, rctx->b.predicate_drawing);
1620                                 cs->buf[cs->cdw++] = max_size;
1621
1622                                 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, rctx->b.predicate_drawing);
1623                                 cs->buf[cs->cdw++] = info.indirect_offset;
1624                                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1625                         }
1626                 }
1627         } else {
1628                 if (unlikely(info.count_from_stream_output)) {
1629                         struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1630                         uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1631
1632                         r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1633
1634                         cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1635                         cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1636                         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* src address lo */
1637                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1638                         cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1639                         cs->buf[cs->cdw++] = 0; /* unused */
1640
1641                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1642                         cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1643                                                                    t->buf_filled_size, RADEON_USAGE_READ,
1644                                                                    RADEON_PRIO_MIN);
1645                 }
1646
1647                 if (likely(!info.indirect)) {
1648                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
1649                         cs->buf[cs->cdw++] = info.count;
1650                 }
1651                 else {
1652                         cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, rctx->b.predicate_drawing);
1653                         cs->buf[cs->cdw++] = info.indirect_offset;
1654                 }
1655                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1656                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1657         }
1658
1659         if (rctx->screen->b.trace_bo) {
1660                 r600_trace_emit(rctx);
1661         }
1662
1663         /* Set the depth buffer as dirty. */
1664         if (rctx->framebuffer.state.zsbuf) {
1665                 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1666                 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1667
1668                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1669         }
1670         if (rctx->framebuffer.compressed_cb_mask) {
1671                 struct pipe_surface *surf;
1672                 struct r600_texture *rtex;
1673                 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1674
1675                 do {
1676                         unsigned i = u_bit_scan(&mask);
1677                         surf = rctx->framebuffer.state.cbufs[i];
1678                         rtex = (struct r600_texture*)surf->texture;
1679
1680                         rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1681
1682                 } while (mask);
1683         }
1684
1685         pipe_resource_reference(&ib.buffer, NULL);
1686         rctx->b.num_draw_calls++;
1687 }
1688
1689 uint32_t r600_translate_stencil_op(int s_op)
1690 {
1691         switch (s_op) {
1692         case PIPE_STENCIL_OP_KEEP:
1693                 return V_028800_STENCIL_KEEP;
1694         case PIPE_STENCIL_OP_ZERO:
1695                 return V_028800_STENCIL_ZERO;
1696         case PIPE_STENCIL_OP_REPLACE:
1697                 return V_028800_STENCIL_REPLACE;
1698         case PIPE_STENCIL_OP_INCR:
1699                 return V_028800_STENCIL_INCR;
1700         case PIPE_STENCIL_OP_DECR:
1701                 return V_028800_STENCIL_DECR;
1702         case PIPE_STENCIL_OP_INCR_WRAP:
1703                 return V_028800_STENCIL_INCR_WRAP;
1704         case PIPE_STENCIL_OP_DECR_WRAP:
1705                 return V_028800_STENCIL_DECR_WRAP;
1706         case PIPE_STENCIL_OP_INVERT:
1707                 return V_028800_STENCIL_INVERT;
1708         default:
1709                 R600_ERR("Unknown stencil op %d", s_op);
1710                 assert(0);
1711                 break;
1712         }
1713         return 0;
1714 }
1715
1716 uint32_t r600_translate_fill(uint32_t func)
1717 {
1718         switch(func) {
1719         case PIPE_POLYGON_MODE_FILL:
1720                 return 2;
1721         case PIPE_POLYGON_MODE_LINE:
1722                 return 1;
1723         case PIPE_POLYGON_MODE_POINT:
1724                 return 0;
1725         default:
1726                 assert(0);
1727                 return 0;
1728         }
1729 }
1730
1731 unsigned r600_tex_wrap(unsigned wrap)
1732 {
1733         switch (wrap) {
1734         default:
1735         case PIPE_TEX_WRAP_REPEAT:
1736                 return V_03C000_SQ_TEX_WRAP;
1737         case PIPE_TEX_WRAP_CLAMP:
1738                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1739         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1740                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1741         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1742                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1743         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1744                 return V_03C000_SQ_TEX_MIRROR;
1745         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1746                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1747         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1748                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1749         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1750                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1751         }
1752 }
1753
1754 unsigned r600_tex_filter(unsigned filter)
1755 {
1756         switch (filter) {
1757         default:
1758         case PIPE_TEX_FILTER_NEAREST:
1759                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1760         case PIPE_TEX_FILTER_LINEAR:
1761                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1762         }
1763 }
1764
1765 unsigned r600_tex_mipfilter(unsigned filter)
1766 {
1767         switch (filter) {
1768         case PIPE_TEX_MIPFILTER_NEAREST:
1769                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1770         case PIPE_TEX_MIPFILTER_LINEAR:
1771                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1772         default:
1773         case PIPE_TEX_MIPFILTER_NONE:
1774                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1775         }
1776 }
1777
1778 unsigned r600_tex_compare(unsigned compare)
1779 {
1780         switch (compare) {
1781         default:
1782         case PIPE_FUNC_NEVER:
1783                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1784         case PIPE_FUNC_LESS:
1785                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1786         case PIPE_FUNC_EQUAL:
1787                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1788         case PIPE_FUNC_LEQUAL:
1789                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1790         case PIPE_FUNC_GREATER:
1791                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1792         case PIPE_FUNC_NOTEQUAL:
1793                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1794         case PIPE_FUNC_GEQUAL:
1795                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1796         case PIPE_FUNC_ALWAYS:
1797                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1798         }
1799 }
1800
1801 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1802 {
1803         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1804                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1805                (linear_filter &&
1806                 (wrap == PIPE_TEX_WRAP_CLAMP ||
1807                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1808 }
1809
1810 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1811 {
1812         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1813                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1814
1815         return (state->border_color.ui[0] || state->border_color.ui[1] ||
1816                 state->border_color.ui[2] || state->border_color.ui[3]) &&
1817                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1818                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1819                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1820 }
1821
1822 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1823 {
1824
1825         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1826         struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
1827
1828         if (!shader)
1829                 return;
1830
1831         r600_emit_command_buffer(cs, &shader->command_buffer);
1832         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1833         radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
1834                                               RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1835 }
1836
1837 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1838                                    const unsigned char *swizzle_view,
1839                                    boolean vtx)
1840 {
1841         unsigned i;
1842         unsigned char swizzle[4];
1843         unsigned result = 0;
1844         const uint32_t tex_swizzle_shift[4] = {
1845                 16, 19, 22, 25,
1846         };
1847         const uint32_t vtx_swizzle_shift[4] = {
1848                 3, 6, 9, 12,
1849         };
1850         const uint32_t swizzle_bit[4] = {
1851                 0, 1, 2, 3,
1852         };
1853         const uint32_t *swizzle_shift = tex_swizzle_shift;
1854
1855         if (vtx)
1856                 swizzle_shift = vtx_swizzle_shift;
1857
1858         if (swizzle_view) {
1859                 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1860         } else {
1861                 memcpy(swizzle, swizzle_format, 4);
1862         }
1863
1864         /* Get swizzle. */
1865         for (i = 0; i < 4; i++) {
1866                 switch (swizzle[i]) {
1867                 case UTIL_FORMAT_SWIZZLE_Y:
1868                         result |= swizzle_bit[1] << swizzle_shift[i];
1869                         break;
1870                 case UTIL_FORMAT_SWIZZLE_Z:
1871                         result |= swizzle_bit[2] << swizzle_shift[i];
1872                         break;
1873                 case UTIL_FORMAT_SWIZZLE_W:
1874                         result |= swizzle_bit[3] << swizzle_shift[i];
1875                         break;
1876                 case UTIL_FORMAT_SWIZZLE_0:
1877                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1878                         break;
1879                 case UTIL_FORMAT_SWIZZLE_1:
1880                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1881                         break;
1882                 default: /* UTIL_FORMAT_SWIZZLE_X */
1883                         result |= swizzle_bit[0] << swizzle_shift[i];
1884                 }
1885         }
1886         return result;
1887 }
1888
1889 /* texture format translate */
1890 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1891                                   enum pipe_format format,
1892                                   const unsigned char *swizzle_view,
1893                                   uint32_t *word4_p, uint32_t *yuv_format_p)
1894 {
1895         struct r600_screen *rscreen = (struct r600_screen *)screen;
1896         uint32_t result = 0, word4 = 0, yuv_format = 0;
1897         const struct util_format_description *desc;
1898         boolean uniform = TRUE;
1899         bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1900         bool is_srgb_valid = FALSE;
1901         const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1902         const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1903
1904         int i;
1905         const uint32_t sign_bit[4] = {
1906                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1907                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1908                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1909                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1910         };
1911         desc = util_format_description(format);
1912
1913         /* Depth and stencil swizzling is handled separately. */
1914         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1915                 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1916         }
1917
1918         /* Colorspace (return non-RGB formats directly). */
1919         switch (desc->colorspace) {
1920         /* Depth stencil formats */
1921         case UTIL_FORMAT_COLORSPACE_ZS:
1922                 switch (format) {
1923                 /* Depth sampler formats. */
1924                 case PIPE_FORMAT_Z16_UNORM:
1925                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1926                         result = FMT_16;
1927                         goto out_word4;
1928                 case PIPE_FORMAT_Z24X8_UNORM:
1929                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1930                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1931                         result = FMT_8_24;
1932                         goto out_word4;
1933                 case PIPE_FORMAT_X8Z24_UNORM:
1934                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1935                         if (rscreen->b.chip_class < EVERGREEN)
1936                                 goto out_unknown;
1937                         word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1938                         result = FMT_24_8;
1939                         goto out_word4;
1940                 case PIPE_FORMAT_Z32_FLOAT:
1941                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1942                         result = FMT_32_FLOAT;
1943                         goto out_word4;
1944                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1945                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1946                         result = FMT_X24_8_32_FLOAT;
1947                         goto out_word4;
1948                 /* Stencil sampler formats. */
1949                 case PIPE_FORMAT_S8_UINT:
1950                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1951                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1952                         result = FMT_8;
1953                         goto out_word4;
1954                 case PIPE_FORMAT_X24S8_UINT:
1955                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1956                         word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1957                         result = FMT_8_24;
1958                         goto out_word4;
1959                 case PIPE_FORMAT_S8X24_UINT:
1960                         if (rscreen->b.chip_class < EVERGREEN)
1961                                 goto out_unknown;
1962                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1963                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1964                         result = FMT_24_8;
1965                         goto out_word4;
1966                 case PIPE_FORMAT_X32_S8X24_UINT:
1967                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1968                         word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1969                         result = FMT_X24_8_32_FLOAT;
1970                         goto out_word4;
1971                 default:
1972                         goto out_unknown;
1973                 }
1974
1975         case UTIL_FORMAT_COLORSPACE_YUV:
1976                 yuv_format |= (1 << 30);
1977                 switch (format) {
1978                 case PIPE_FORMAT_UYVY:
1979                 case PIPE_FORMAT_YUYV:
1980                 default:
1981                         break;
1982                 }
1983                 goto out_unknown; /* XXX */
1984
1985         case UTIL_FORMAT_COLORSPACE_SRGB:
1986                 word4 |= S_038010_FORCE_DEGAMMA(1);
1987                 break;
1988
1989         default:
1990                 break;
1991         }
1992
1993         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1994                 if (!enable_s3tc)
1995                         goto out_unknown;
1996
1997                 switch (format) {
1998                 case PIPE_FORMAT_RGTC1_SNORM:
1999                 case PIPE_FORMAT_LATC1_SNORM:
2000                         word4 |= sign_bit[0];
2001                 case PIPE_FORMAT_RGTC1_UNORM:
2002                 case PIPE_FORMAT_LATC1_UNORM:
2003                         result = FMT_BC4;
2004                         goto out_word4;
2005                 case PIPE_FORMAT_RGTC2_SNORM:
2006                 case PIPE_FORMAT_LATC2_SNORM:
2007                         word4 |= sign_bit[0] | sign_bit[1];
2008                 case PIPE_FORMAT_RGTC2_UNORM:
2009                 case PIPE_FORMAT_LATC2_UNORM:
2010                         result = FMT_BC5;
2011                         goto out_word4;
2012                 default:
2013                         goto out_unknown;
2014                 }
2015         }
2016
2017         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2018
2019                 if (!enable_s3tc)
2020                         goto out_unknown;
2021
2022                 if (!util_format_s3tc_enabled) {
2023                         goto out_unknown;
2024                 }
2025
2026                 switch (format) {
2027                 case PIPE_FORMAT_DXT1_RGB:
2028                 case PIPE_FORMAT_DXT1_RGBA:
2029                 case PIPE_FORMAT_DXT1_SRGB:
2030                 case PIPE_FORMAT_DXT1_SRGBA:
2031                         result = FMT_BC1;
2032                         is_srgb_valid = TRUE;
2033                         goto out_word4;
2034                 case PIPE_FORMAT_DXT3_RGBA:
2035                 case PIPE_FORMAT_DXT3_SRGBA:
2036                         result = FMT_BC2;
2037                         is_srgb_valid = TRUE;
2038                         goto out_word4;
2039                 case PIPE_FORMAT_DXT5_RGBA:
2040                 case PIPE_FORMAT_DXT5_SRGBA:
2041                         result = FMT_BC3;
2042                         is_srgb_valid = TRUE;
2043                         goto out_word4;
2044                 default:
2045                         goto out_unknown;
2046                 }
2047         }
2048
2049         if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2050                 if (!enable_s3tc)
2051                         goto out_unknown;
2052
2053                 if (rscreen->b.chip_class < EVERGREEN)
2054                         goto out_unknown;
2055
2056                 switch (format) {
2057                         case PIPE_FORMAT_BPTC_RGBA_UNORM:
2058                         case PIPE_FORMAT_BPTC_SRGBA:
2059                                 result = FMT_BC7;
2060                                 is_srgb_valid = TRUE;
2061                                 goto out_word4;
2062                         case PIPE_FORMAT_BPTC_RGB_FLOAT:
2063                                 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2064                                 /* fall through */
2065                         case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2066                                 result = FMT_BC6;
2067                                 goto out_word4;
2068                         default:
2069                                 goto out_unknown;
2070                 }
2071         }
2072
2073         if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2074                 switch (format) {
2075                 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2076                 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2077                         result = FMT_GB_GR;
2078                         goto out_word4;
2079                 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2080                 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2081                         result = FMT_BG_RG;
2082                         goto out_word4;
2083                 default:
2084                         goto out_unknown;
2085                 }
2086         }
2087
2088         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2089                 result = FMT_5_9_9_9_SHAREDEXP;
2090                 goto out_word4;
2091         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2092                 result = FMT_10_11_11_FLOAT;
2093                 goto out_word4;
2094         }
2095
2096
2097         for (i = 0; i < desc->nr_channels; i++) {
2098                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2099                         word4 |= sign_bit[i];
2100                 }
2101         }
2102
2103         /* R8G8Bx_SNORM - XXX CxV8U8 */
2104
2105         /* See whether the components are of the same size. */
2106         for (i = 1; i < desc->nr_channels; i++) {
2107                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2108         }
2109
2110         /* Non-uniform formats. */
2111         if (!uniform) {
2112                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2113                     desc->channel[0].pure_integer)
2114                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2115                 switch(desc->nr_channels) {
2116                 case 3:
2117                         if (desc->channel[0].size == 5 &&
2118                             desc->channel[1].size == 6 &&
2119                             desc->channel[2].size == 5) {
2120                                 result = FMT_5_6_5;
2121                                 goto out_word4;
2122                         }
2123                         goto out_unknown;
2124                 case 4:
2125                         if (desc->channel[0].size == 5 &&
2126                             desc->channel[1].size == 5 &&
2127                             desc->channel[2].size == 5 &&
2128                             desc->channel[3].size == 1) {
2129                                 result = FMT_1_5_5_5;
2130                                 goto out_word4;
2131                         }
2132                         if (desc->channel[0].size == 10 &&
2133                             desc->channel[1].size == 10 &&
2134                             desc->channel[2].size == 10 &&
2135                             desc->channel[3].size == 2) {
2136                                 result = FMT_2_10_10_10;
2137                                 goto out_word4;
2138                         }
2139                         goto out_unknown;
2140                 }
2141                 goto out_unknown;
2142         }
2143
2144         /* Find the first non-VOID channel. */
2145         for (i = 0; i < 4; i++) {
2146                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2147                         break;
2148                 }
2149         }
2150
2151         if (i == 4)
2152                 goto out_unknown;
2153
2154         /* uniform formats */
2155         switch (desc->channel[i].type) {
2156         case UTIL_FORMAT_TYPE_UNSIGNED:
2157         case UTIL_FORMAT_TYPE_SIGNED:
2158 #if 0
2159                 if (!desc->channel[i].normalized &&
2160                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2161                         goto out_unknown;
2162                 }
2163 #endif
2164                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2165                     desc->channel[i].pure_integer)
2166                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2167
2168                 switch (desc->channel[i].size) {
2169                 case 4:
2170                         switch (desc->nr_channels) {
2171                         case 2:
2172                                 result = FMT_4_4;
2173                                 goto out_word4;
2174                         case 4:
2175                                 result = FMT_4_4_4_4;
2176                                 goto out_word4;
2177                         }
2178                         goto out_unknown;
2179                 case 8:
2180                         switch (desc->nr_channels) {
2181                         case 1:
2182                                 result = FMT_8;
2183                                 goto out_word4;
2184                         case 2:
2185                                 result = FMT_8_8;
2186                                 goto out_word4;
2187                         case 4:
2188                                 result = FMT_8_8_8_8;
2189                                 is_srgb_valid = TRUE;
2190                                 goto out_word4;
2191                         }
2192                         goto out_unknown;
2193                 case 16:
2194                         switch (desc->nr_channels) {
2195                         case 1:
2196                                 result = FMT_16;
2197                                 goto out_word4;
2198                         case 2:
2199                                 result = FMT_16_16;
2200                                 goto out_word4;
2201                         case 4:
2202                                 result = FMT_16_16_16_16;
2203                                 goto out_word4;
2204                         }
2205                         goto out_unknown;
2206                 case 32:
2207                         switch (desc->nr_channels) {
2208                         case 1:
2209                                 result = FMT_32;
2210                                 goto out_word4;
2211                         case 2:
2212                                 result = FMT_32_32;
2213                                 goto out_word4;
2214                         case 4:
2215                                 result = FMT_32_32_32_32;
2216                                 goto out_word4;
2217                         }
2218                 }
2219                 goto out_unknown;
2220
2221         case UTIL_FORMAT_TYPE_FLOAT:
2222                 switch (desc->channel[i].size) {
2223                 case 16:
2224                         switch (desc->nr_channels) {
2225                         case 1:
2226                                 result = FMT_16_FLOAT;
2227                                 goto out_word4;
2228                         case 2:
2229                                 result = FMT_16_16_FLOAT;
2230                                 goto out_word4;
2231                         case 4:
2232                                 result = FMT_16_16_16_16_FLOAT;
2233                                 goto out_word4;
2234                         }
2235                         goto out_unknown;
2236                 case 32:
2237                         switch (desc->nr_channels) {
2238                         case 1:
2239                                 result = FMT_32_FLOAT;
2240                                 goto out_word4;
2241                         case 2:
2242                                 result = FMT_32_32_FLOAT;
2243                                 goto out_word4;
2244                         case 4:
2245                                 result = FMT_32_32_32_32_FLOAT;
2246                                 goto out_word4;
2247                         }
2248                 }
2249                 goto out_unknown;
2250         }
2251
2252 out_word4:
2253
2254         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2255                 return ~0;
2256         if (word4_p)
2257                 *word4_p = word4;
2258         if (yuv_format_p)
2259                 *yuv_format_p = yuv_format;
2260         return result;
2261 out_unknown:
2262         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2263         return ~0;
2264 }
2265
2266 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
2267 {
2268         const struct util_format_description *desc = util_format_description(format);
2269         int channel = util_format_get_first_non_void_channel(format);
2270         bool is_float;
2271
2272 #define HAS_SIZE(x,y,z,w) \
2273         (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2274          desc->channel[2].size == (z) && desc->channel[3].size == (w))
2275
2276         if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2277                 return V_0280A0_COLOR_10_11_11_FLOAT;
2278
2279         if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2280             channel == -1)
2281                 return ~0U;
2282
2283         is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2284
2285         switch (desc->nr_channels) {
2286         case 1:
2287                 switch (desc->channel[0].size) {
2288                 case 8:
2289                         return V_0280A0_COLOR_8;
2290                 case 16:
2291                         if (is_float)
2292                                 return V_0280A0_COLOR_16_FLOAT;
2293                         else
2294                                 return V_0280A0_COLOR_16;
2295                 case 32:
2296                         if (is_float)
2297                                 return V_0280A0_COLOR_32_FLOAT;
2298                         else
2299                                 return V_0280A0_COLOR_32;
2300                 }
2301                 break;
2302         case 2:
2303                 if (desc->channel[0].size == desc->channel[1].size) {
2304                         switch (desc->channel[0].size) {
2305                         case 4:
2306                                 if (chip <= R700)
2307                                         return V_0280A0_COLOR_4_4;
2308                                 else
2309                                         return ~0U; /* removed on Evergreen */
2310                         case 8:
2311                                 return V_0280A0_COLOR_8_8;
2312                         case 16:
2313                                 if (is_float)
2314                                         return V_0280A0_COLOR_16_16_FLOAT;
2315                                 else
2316                                         return V_0280A0_COLOR_16_16;
2317                         case 32:
2318                                 if (is_float)
2319                                         return V_0280A0_COLOR_32_32_FLOAT;
2320                                 else
2321                                         return V_0280A0_COLOR_32_32;
2322                         }
2323                 } else if (HAS_SIZE(8,24,0,0)) {
2324                         return V_0280A0_COLOR_24_8;
2325                 } else if (HAS_SIZE(24,8,0,0)) {
2326                         return V_0280A0_COLOR_8_24;
2327                 }
2328                 break;
2329         case 3:
2330                 if (HAS_SIZE(5,6,5,0)) {
2331                         return V_0280A0_COLOR_5_6_5;
2332                 } else if (HAS_SIZE(32,8,24,0)) {
2333                         return V_0280A0_COLOR_X24_8_32_FLOAT;
2334                 }
2335                 break;
2336         case 4:
2337                 if (desc->channel[0].size == desc->channel[1].size &&
2338                     desc->channel[0].size == desc->channel[2].size &&
2339                     desc->channel[0].size == desc->channel[3].size) {
2340                         switch (desc->channel[0].size) {
2341                         case 4:
2342                                 return V_0280A0_COLOR_4_4_4_4;
2343                         case 8:
2344                                 return V_0280A0_COLOR_8_8_8_8;
2345                         case 16:
2346                                 if (is_float)
2347                                         return V_0280A0_COLOR_16_16_16_16_FLOAT;
2348                                 else
2349                                         return V_0280A0_COLOR_16_16_16_16;
2350                         case 32:
2351                                 if (is_float)
2352                                         return V_0280A0_COLOR_32_32_32_32_FLOAT;
2353                                 else
2354                                         return V_0280A0_COLOR_32_32_32_32;
2355                         }
2356                 } else if (HAS_SIZE(5,5,5,1)) {
2357                         return V_0280A0_COLOR_1_5_5_5;
2358                 } else if (HAS_SIZE(10,10,10,2)) {
2359                         return V_0280A0_COLOR_2_10_10_10;
2360                 }
2361                 break;
2362         }
2363         return ~0U;
2364 }
2365
2366 uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
2367 {
2368         if (R600_BIG_ENDIAN) {
2369                 switch(colorformat) {
2370                 /* 8-bit buffers. */
2371                 case V_0280A0_COLOR_4_4:
2372                 case V_0280A0_COLOR_8:
2373                         return ENDIAN_NONE;
2374
2375                 /* 16-bit buffers. */
2376                 case V_0280A0_COLOR_5_6_5:
2377                 case V_0280A0_COLOR_1_5_5_5:
2378                 case V_0280A0_COLOR_4_4_4_4:
2379                 case V_0280A0_COLOR_16:
2380                 case V_0280A0_COLOR_8_8:
2381                         return ENDIAN_8IN16;
2382
2383                 /* 32-bit buffers. */
2384                 case V_0280A0_COLOR_8_8_8_8:
2385                 case V_0280A0_COLOR_2_10_10_10:
2386                 case V_0280A0_COLOR_8_24:
2387                 case V_0280A0_COLOR_24_8:
2388                 case V_0280A0_COLOR_32_FLOAT:
2389                 case V_0280A0_COLOR_16_16_FLOAT:
2390                 case V_0280A0_COLOR_16_16:
2391                         return ENDIAN_8IN32;
2392
2393                 /* 64-bit buffers. */
2394                 case V_0280A0_COLOR_16_16_16_16:
2395                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2396                         return ENDIAN_8IN16;
2397
2398                 case V_0280A0_COLOR_32_32_FLOAT:
2399                 case V_0280A0_COLOR_32_32:
2400                 case V_0280A0_COLOR_X24_8_32_FLOAT:
2401                         return ENDIAN_8IN32;
2402
2403                 /* 128-bit buffers. */
2404                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2405                 case V_0280A0_COLOR_32_32_32_32:
2406                         return ENDIAN_8IN32;
2407                 default:
2408                         return ENDIAN_NONE; /* Unsupported. */
2409                 }
2410         } else {
2411                 return ENDIAN_NONE;
2412         }
2413 }
2414
2415 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2416 {
2417         struct r600_context *rctx = (struct r600_context*)ctx;
2418         struct r600_resource *rbuffer = r600_resource(buf);
2419         unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2420         struct r600_pipe_sampler_view *view;
2421
2422         /* Reallocate the buffer in the same pipe_resource. */
2423         r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
2424                            alignment, TRUE);
2425
2426         /* We changed the buffer, now we need to bind it where the old one was bound. */
2427         /* Vertex buffers. */
2428         mask = rctx->vertex_buffer_state.enabled_mask;
2429         while (mask) {
2430                 i = u_bit_scan(&mask);
2431                 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2432                         rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2433                         r600_vertex_buffers_dirty(rctx);
2434                 }
2435         }
2436         /* Streamout buffers. */
2437         for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2438                 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2439                         if (rctx->b.streamout.begin_emitted) {
2440                                 r600_emit_streamout_end(&rctx->b);
2441                         }
2442                         rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2443                         r600_streamout_buffers_dirty(&rctx->b);
2444                 }
2445         }
2446
2447         /* Constant buffers. */
2448         for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2449                 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2450                 bool found = false;
2451                 uint32_t mask = state->enabled_mask;
2452
2453                 while (mask) {
2454                         unsigned i = u_bit_scan(&mask);
2455                         if (state->cb[i].buffer == &rbuffer->b.b) {
2456                                 found = true;
2457                                 state->dirty_mask |= 1 << i;
2458                         }
2459                 }
2460                 if (found) {
2461                         r600_constant_buffers_dirty(rctx, state);
2462                 }
2463         }
2464
2465         /* Texture buffer objects - update the virtual addresses in descriptors. */
2466         LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
2467                 if (view->base.texture == &rbuffer->b.b) {
2468                         unsigned stride = util_format_get_blocksize(view->base.format);
2469                         uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
2470                         uint64_t va = rbuffer->gpu_address + offset;
2471
2472                         view->tex_resource_words[0] = va;
2473                         view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
2474                         view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
2475                 }
2476         }
2477         /* Texture buffer objects - make bindings dirty if needed. */
2478         for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2479                 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
2480                 bool found = false;
2481                 uint32_t mask = state->enabled_mask;
2482
2483                 while (mask) {
2484                         unsigned i = u_bit_scan(&mask);
2485                         if (state->views[i]->base.texture == &rbuffer->b.b) {
2486                                 found = true;
2487                                 state->dirty_mask |= 1 << i;
2488                         }
2489                 }
2490                 if (found) {
2491                         r600_sampler_views_dirty(rctx, state);
2492                 }
2493         }
2494 }
2495
2496 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2497 {
2498         struct r600_context *rctx = (struct r600_context*)ctx;
2499
2500         if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2501                 rctx->db_misc_state.occlusion_query_enabled = enable;
2502                 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2503         }
2504 }
2505
2506 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2507                                    bool include_draw_vbo)
2508 {
2509         r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2510 }
2511
2512 /* keep this at the end of this file, please */
2513 void r600_init_common_state_functions(struct r600_context *rctx)
2514 {
2515         rctx->b.b.create_fs_state = r600_create_ps_state;
2516         rctx->b.b.create_vs_state = r600_create_vs_state;
2517         rctx->b.b.create_gs_state = r600_create_gs_state;
2518         rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2519         rctx->b.b.bind_blend_state = r600_bind_blend_state;
2520         rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2521         rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2522         rctx->b.b.bind_fs_state = r600_bind_ps_state;
2523         rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2524         rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2525         rctx->b.b.bind_vs_state = r600_bind_vs_state;
2526         rctx->b.b.bind_gs_state = r600_bind_gs_state;
2527         rctx->b.b.delete_blend_state = r600_delete_blend_state;
2528         rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2529         rctx->b.b.delete_fs_state = r600_delete_ps_state;
2530         rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2531         rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2532         rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2533         rctx->b.b.delete_vs_state = r600_delete_vs_state;
2534         rctx->b.b.delete_gs_state = r600_delete_gs_state;
2535         rctx->b.b.set_blend_color = r600_set_blend_color;
2536         rctx->b.b.set_clip_state = r600_set_clip_state;
2537         rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2538         rctx->b.b.set_sample_mask = r600_set_sample_mask;
2539         rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2540         rctx->b.b.set_viewport_states = r600_set_viewport_states;
2541         rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2542         rctx->b.b.set_index_buffer = r600_set_index_buffer;
2543         rctx->b.b.set_sampler_views = r600_set_sampler_views;
2544         rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2545         rctx->b.b.texture_barrier = r600_texture_barrier;
2546         rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2547         rctx->b.b.draw_vbo = r600_draw_vbo;
2548         rctx->b.invalidate_buffer = r600_invalidate_buffer;
2549         rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2550         rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2551 }
2552
2553 void r600_trace_emit(struct r600_context *rctx)
2554 {
2555         struct r600_screen *rscreen = rctx->screen;
2556         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2557         uint64_t va;
2558         uint32_t reloc;
2559
2560         va = rscreen->b.trace_bo->gpu_address;
2561         reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
2562                                       RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
2563         radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2564         radeon_emit(cs, va & 0xFFFFFFFFUL);
2565         radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2566         radeon_emit(cs, cs->cdw);
2567         radeon_emit(cs, rscreen->b.cs_count);
2568         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2569         radeon_emit(cs, reloc);
2570 }