src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600_shader.h"
  29 #include "r600d.h"
  30
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_index_modify.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "tgsi/tgsi_parse.h"
  36 #include <byteswap.h>
  37
  38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
  39
  40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
  41 {
  42         cb->buf = CALLOC(1, 4 * num_dw);
  43         cb->max_num_dw = num_dw;
  44 }
  45
  46 void r600_release_command_buffer(struct r600_command_buffer *cb)
  47 {
  48         FREE(cb->buf);
  49 }
  50
  51 void r600_init_atom(struct r600_context *rctx,
  52                     struct r600_atom *atom,
  53                     unsigned id,
  54                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  55                     unsigned num_dw)
  56 {
  57         assert(id < R600_NUM_ATOMS);
  58         assert(rctx->atoms[id] == NULL);
  59         rctx->atoms[id] = atom;
  60         atom->id = id;
  61         atom->emit = emit;
  62         atom->num_dw = num_dw;
  63         atom->dirty = false;
  64 }
  65
  66 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
  67 {
  68         r600_emit_command_buffer(rctx->rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
  69 }
  70
  71 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
  72 {
  73         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
  74         struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
  75         unsigned alpha_ref = a->sx_alpha_ref;
  76
  77         if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
  78                 alpha_ref &= ~0x1FFF;
  79         }
  80
  81         r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
  82                                a->sx_alpha_test_control |
  83                                S_028410_ALPHA_TEST_BYPASS(a->bypass));
  84         r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
  85 }
  86
  87 static void r600_texture_barrier(struct pipe_context *ctx)
  88 {
  89         struct r600_context *rctx = (struct r600_context *)ctx;
  90
  91         rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
  92         rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
  93         rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
  94 }
  95
  96 static unsigned r600_conv_pipe_prim(unsigned prim)
  97 {
  98         static const unsigned prim_conv[] = {
  99                 V_008958_DI_PT_POINTLIST,
 100                 V_008958_DI_PT_LINELIST,
 101                 V_008958_DI_PT_LINELOOP,
 102                 V_008958_DI_PT_LINESTRIP,
 103                 V_008958_DI_PT_TRILIST,
 104                 V_008958_DI_PT_TRISTRIP,
 105                 V_008958_DI_PT_TRIFAN,
 106                 V_008958_DI_PT_QUADLIST,
 107                 V_008958_DI_PT_QUADSTRIP,
 108                 V_008958_DI_PT_POLYGON,
 109                 V_008958_DI_PT_LINELIST_ADJ,
 110                 V_008958_DI_PT_LINESTRIP_ADJ,
 111                 V_008958_DI_PT_TRILIST_ADJ,
 112                 V_008958_DI_PT_TRISTRIP_ADJ,
 113                 V_008958_DI_PT_RECTLIST
 114         };
 115         return prim_conv[prim];
 116 }
 117
 118 /* common state between evergreen and r600 */
 119
 120 static void r600_bind_blend_state_internal(struct r600_context *rctx,
 121                 struct r600_blend_state *blend, bool blend_disable)
 122 {
 123         unsigned color_control;
 124         bool update_cb = false;
 125
 126         rctx->alpha_to_one = blend->alpha_to_one;
 127         rctx->dual_src_blend = blend->dual_src_blend;
 128
 129         if (!blend_disable) {
 130                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
 131                 color_control = blend->cb_color_control;
 132         } else {
 133                 /* Blending is disabled. */
 134                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
 135                 color_control = blend->cb_color_control_no_blend;
 136         }
 137
 138         /* Update derived states. */
 139         if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 140                 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 141                 update_cb = true;
 142         }
 143         if (rctx->chip_class <= R700 &&
 144             rctx->cb_misc_state.cb_color_control != color_control) {
 145                 rctx->cb_misc_state.cb_color_control = color_control;
 146                 update_cb = true;
 147         }
 148         if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
 149                 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
 150                 update_cb = true;
 151         }
 152         if (update_cb) {
 153                 rctx->cb_misc_state.atom.dirty = true;
 154         }
 155 }
 156
 157 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 158 {
 159         struct r600_context *rctx = (struct r600_context *)ctx;
 160         struct r600_blend_state *blend = (struct r600_blend_state *)state;
 161
 162         if (blend == NULL)
 163                 return;
 164
 165         r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
 166 }
 167
 168 static void r600_set_blend_color(struct pipe_context *ctx,
 169                                  const struct pipe_blend_color *state)
 170 {
 171         struct r600_context *rctx = (struct r600_context *)ctx;
 172
 173         rctx->blend_color.state = *state;
 174         rctx->blend_color.atom.dirty = true;
 175 }
 176
 177 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
 178 {
 179         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 180         struct pipe_blend_color *state = &rctx->blend_color.state;
 181
 182         r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 183         r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
 184         r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
 185         r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
 186         r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 187 }
 188
 189 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
 190 {
 191         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 192         struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
 193
 194         r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
 195         r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
 196 }
 197
 198 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
 199 {
 200         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 201         struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
 202
 203         r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
 204 }
 205
 206 static void r600_set_clip_state(struct pipe_context *ctx,
 207                                 const struct pipe_clip_state *state)
 208 {
 209         struct r600_context *rctx = (struct r600_context *)ctx;
 210         struct pipe_constant_buffer cb;
 211
 212         rctx->clip_state.state = *state;
 213         rctx->clip_state.atom.dirty = true;
 214
 215         cb.buffer = NULL;
 216         cb.user_buffer = state->ucp;
 217         cb.buffer_offset = 0;
 218         cb.buffer_size = 4*4*8;
 219         ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
 220         pipe_resource_reference(&cb.buffer, NULL);
 221 }
 222
 223 static void r600_set_stencil_ref(struct pipe_context *ctx,
 224                                  const struct r600_stencil_ref *state)
 225 {
 226         struct r600_context *rctx = (struct r600_context *)ctx;
 227
 228         rctx->stencil_ref.state = *state;
 229         rctx->stencil_ref.atom.dirty = true;
 230 }
 231
 232 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
 233 {
 234         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 235         struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
 236
 237         r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 238         r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
 239                          S_028430_STENCILREF(a->state.ref_value[0]) |
 240                          S_028430_STENCILMASK(a->state.valuemask[0]) |
 241                          S_028430_STENCILWRITEMASK(a->state.writemask[0]));
 242         r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
 243                          S_028434_STENCILREF_BF(a->state.ref_value[1]) |
 244                          S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
 245                          S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
 246 }
 247
 248 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 249                                       const struct pipe_stencil_ref *state)
 250 {
 251         struct r600_context *rctx = (struct r600_context *)ctx;
 252         struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
 253         struct r600_stencil_ref ref;
 254
 255         rctx->stencil_ref.pipe_state = *state;
 256
 257         if (!dsa)
 258                 return;
 259
 260         ref.ref_value[0] = state->ref_value[0];
 261         ref.ref_value[1] = state->ref_value[1];
 262         ref.valuemask[0] = dsa->valuemask[0];
 263         ref.valuemask[1] = dsa->valuemask[1];
 264         ref.writemask[0] = dsa->writemask[0];
 265         ref.writemask[1] = dsa->writemask[1];
 266
 267         r600_set_stencil_ref(ctx, &ref);
 268 }
 269
 270 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 271 {
 272         struct r600_context *rctx = (struct r600_context *)ctx;
 273         struct r600_dsa_state *dsa = state;
 274         struct r600_stencil_ref ref;
 275
 276         if (state == NULL)
 277                 return;
 278
 279         r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
 280
 281         ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
 282         ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
 283         ref.valuemask[0] = dsa->valuemask[0];
 284         ref.valuemask[1] = dsa->valuemask[1];
 285         ref.writemask[0] = dsa->writemask[0];
 286         ref.writemask[1] = dsa->writemask[1];
 287
 288         r600_set_stencil_ref(ctx, &ref);
 289
 290         /* Update alphatest state. */
 291         if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
 292             rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
 293                 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 294                 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 295                 rctx->alphatest_state.atom.dirty = true;
 296                 if (rctx->chip_class >= EVERGREEN) {
 297                         evergreen_update_db_shader_control(rctx);
 298                 } else {
 299                         r600_update_db_shader_control(rctx);
 300                 }
 301         }
 302 }
 303
 304 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 305 {
 306         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 307         struct r600_context *rctx = (struct r600_context *)ctx;
 308
 309         if (state == NULL)
 310                 return;
 311
 312         rctx->rasterizer = rs;
 313
 314         r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
 315
 316         if (rs->offset_enable &&
 317             (rs->offset_units != rctx->poly_offset_state.offset_units ||
 318              rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
 319                 rctx->poly_offset_state.offset_units = rs->offset_units;
 320                 rctx->poly_offset_state.offset_scale = rs->offset_scale;
 321                 rctx->poly_offset_state.atom.dirty = true;
 322         }
 323
 324         /* Update clip_misc_state. */
 325         if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
 326             rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
 327                 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 328                 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
 329                 rctx->clip_misc_state.atom.dirty = true;
 330         }
 331
 332         /* Workaround for a missing scissor enable on r600. */
 333         if (rctx->chip_class == R600 &&
 334             rs->scissor_enable != rctx->scissor.enable) {
 335                 rctx->scissor.enable = rs->scissor_enable;
 336                 rctx->scissor.atom.dirty = true;
 337         }
 338
 339         /* Re-emit PA_SC_LINE_STIPPLE. */
 340         rctx->last_primitive_type = -1;
 341 }
 342
 343 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 344 {
 345         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 346
 347         r600_release_command_buffer(&rs->buffer);
 348         FREE(rs);
 349 }
 350
 351 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 352                                       struct pipe_sampler_view *state)
 353 {
 354         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 355
 356         pipe_resource_reference(&state->texture, NULL);
 357         FREE(resource);
 358 }
 359
 360 void r600_sampler_states_dirty(struct r600_context *rctx,
 361                                struct r600_sampler_states *state)
 362 {
 363         if (state->dirty_mask) {
 364                 if (state->dirty_mask & state->has_bordercolor_mask) {
 365                         rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
 366                 }
 367                 state->atom.num_dw =
 368                         util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
 369                         util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
 370                 state->atom.dirty = true;
 371         }
 372 }
 373
 374 static void r600_bind_sampler_states(struct pipe_context *pipe,
 375                                unsigned shader,
 376                                unsigned start,
 377                                unsigned count, void **states)
 378 {
 379         struct r600_context *rctx = (struct r600_context *)pipe;
 380         struct r600_textures_info *dst = &rctx->samplers[shader];
 381         struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
 382         int seamless_cube_map = -1;
 383         unsigned i;
 384         /* This sets 1-bit for states with index >= count. */
 385         uint32_t disable_mask = ~((1ull << count) - 1);
 386         /* These are the new states set by this function. */
 387         uint32_t new_mask = 0;
 388
 389         assert(start == 0); /* XXX fix below */
 390
 391         for (i = 0; i < count; i++) {
 392                 struct r600_pipe_sampler_state *rstate = rstates[i];
 393
 394                 if (rstate == dst->states.states[i]) {
 395                         continue;
 396                 }
 397
 398                 if (rstate) {
 399                         if (rstate->border_color_use) {
 400                                 dst->states.has_bordercolor_mask |= 1 << i;
 401                         } else {
 402                                 dst->states.has_bordercolor_mask &= ~(1 << i);
 403                         }
 404                         seamless_cube_map = rstate->seamless_cube_map;
 405
 406                         new_mask |= 1 << i;
 407                 } else {
 408                         disable_mask |= 1 << i;
 409                 }
 410         }
 411
 412         memcpy(dst->states.states, rstates, sizeof(void*) * count);
 413         memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
 414
 415         dst->states.enabled_mask &= ~disable_mask;
 416         dst->states.dirty_mask &= dst->states.enabled_mask;
 417         dst->states.enabled_mask |= new_mask;
 418         dst->states.dirty_mask |= new_mask;
 419         dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
 420
 421         r600_sampler_states_dirty(rctx, &dst->states);
 422
 423         /* Seamless cubemap state. */
 424         if (rctx->chip_class <= R700 &&
 425             seamless_cube_map != -1 &&
 426             seamless_cube_map != rctx->seamless_cube_map.enabled) {
 427                 /* change in TA_CNTL_AUX need a pipeline flush */
 428                 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
 429                 rctx->seamless_cube_map.enabled = seamless_cube_map;
 430                 rctx->seamless_cube_map.atom.dirty = true;
 431         }
 432 }
 433
 434 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
 435 {
 436         r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
 437 }
 438
 439 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
 440 {
 441         r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
 442 }
 443
 444 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
 445 {
 446         free(state);
 447 }
 448
 449 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
 450 {
 451         struct r600_blend_state *blend = (struct r600_blend_state*)state;
 452
 453         r600_release_command_buffer(&blend->buffer);
 454         r600_release_command_buffer(&blend->buffer_no_blend);
 455         FREE(blend);
 456 }
 457
 458 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
 459 {
 460         struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
 461
 462         r600_release_command_buffer(&dsa->buffer);
 463         free(dsa);
 464 }
 465
 466 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 467 {
 468         struct r600_context *rctx = (struct r600_context *)ctx;
 469
 470         r600_set_cso_state(&rctx->vertex_fetch_shader, state);
 471 }
 472
 473 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 474 {
 475         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
 476         pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
 477         FREE(shader);
 478 }
 479
 480 static void r600_set_index_buffer(struct pipe_context *ctx,
 481                            const struct pipe_index_buffer *ib)
 482 {
 483         struct r600_context *rctx = (struct r600_context *)ctx;
 484
 485         if (ib) {
 486                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 487                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 488                 r600_context_add_resource_size(ctx, ib->buffer);
 489         } else {
 490                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 491         }
 492 }
 493
 494 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 495 {
 496         if (rctx->vertex_buffer_state.dirty_mask) {
 497                 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
 498                 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
 499                                                util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 500                 rctx->vertex_buffer_state.atom.dirty = true;
 501         }
 502 }
 503
 504 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 505                                     unsigned start_slot, unsigned count,
 506                                     const struct pipe_vertex_buffer *input)
 507 {
 508         struct r600_context *rctx = (struct r600_context *)ctx;
 509         struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
 510         struct pipe_vertex_buffer *vb = state->vb + start_slot;
 511         unsigned i;
 512         uint32_t disable_mask = 0;
 513         /* These are the new buffers set by this function. */
 514         uint32_t new_buffer_mask = 0;
 515
 516         /* Set vertex buffers. */
 517         if (input) {
 518                 for (i = 0; i < count; i++) {
 519                         if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
 520                                 if (input[i].buffer) {
 521                                         vb[i].stride = input[i].stride;
 522                                         vb[i].buffer_offset = input[i].buffer_offset;
 523                                         pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 524                                         new_buffer_mask |= 1 << i;
 525                                         r600_context_add_resource_size(ctx, input[i].buffer);
 526                                 } else {
 527                                         pipe_resource_reference(&vb[i].buffer, NULL);
 528                                         disable_mask |= 1 << i;
 529                                 }
 530                         }
 531                 }
 532         } else {
 533                 for (i = 0; i < count; i++) {
 534                         pipe_resource_reference(&vb[i].buffer, NULL);
 535                 }
 536                 disable_mask = ((1ull << count) - 1);
 537         }
 538
 539         disable_mask <<= start_slot;
 540         new_buffer_mask <<= start_slot;
 541
 542         rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 543         rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
 544         rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
 545         rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
 546
 547         r600_vertex_buffers_dirty(rctx);
 548 }
 549
 550 void r600_sampler_views_dirty(struct r600_context *rctx,
 551                               struct r600_samplerview_state *state)
 552 {
 553         if (state->dirty_mask) {
 554                 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
 555                 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
 556                                      util_bitcount(state->dirty_mask);
 557                 state->atom.dirty = true;
 558         }
 559 }
 560
 561 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 562                                    unsigned start, unsigned count,
 563                                    struct pipe_sampler_view **views)
 564 {
 565         struct r600_context *rctx = (struct r600_context *) pipe;
 566         struct r600_textures_info *dst = &rctx->samplers[shader];
 567         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 568         uint32_t dirty_sampler_states_mask = 0;
 569         unsigned i;
 570         /* This sets 1-bit for textures with index >= count. */
 571         uint32_t disable_mask = ~((1ull << count) - 1);
 572         /* These are the new textures set by this function. */
 573         uint32_t new_mask = 0;
 574
 575         /* Set textures with index >= count to NULL. */
 576         uint32_t remaining_mask;
 577
 578         assert(start == 0); /* XXX fix below */
 579
 580         remaining_mask = dst->views.enabled_mask & disable_mask;
 581
 582         while (remaining_mask) {
 583                 i = u_bit_scan(&remaining_mask);
 584                 assert(dst->views.views[i]);
 585
 586                 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 587         }
 588
 589         for (i = 0; i < count; i++) {
 590                 if (rviews[i] == dst->views.views[i]) {
 591                         continue;
 592                 }
 593
 594                 if (rviews[i]) {
 595                         struct r600_texture *rtex =
 596                                 (struct r600_texture*)rviews[i]->base.texture;
 597
 598                         if (rviews[i]->base.texture->target != PIPE_BUFFER) {
 599                                 if (rtex->is_depth && !rtex->is_flushing_texture) {
 600                                         dst->views.compressed_depthtex_mask |= 1 << i;
 601                                 } else {
 602                                         dst->views.compressed_depthtex_mask &= ~(1 << i);
 603                                 }
 604
 605                                 /* Track compressed colorbuffers. */
 606                                 if (rtex->cmask_size && rtex->fmask_size) {
 607                                         dst->views.compressed_colortex_mask |= 1 << i;
 608                                 } else {
 609                                         dst->views.compressed_colortex_mask &= ~(1 << i);
 610                                 }
 611                         }
 612                         /* Changing from array to non-arrays textures and vice versa requires
 613                          * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
 614                         if (rctx->chip_class <= R700 &&
 615                             (dst->states.enabled_mask & (1 << i)) &&
 616                             (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 617                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
 618                                 dirty_sampler_states_mask |= 1 << i;
 619                         }
 620
 621                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 622                         new_mask |= 1 << i;
 623                         r600_context_add_resource_size(pipe, views[i]->texture);
 624                 } else {
 625                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 626                         disable_mask |= 1 << i;
 627                 }
 628         }
 629
 630         dst->views.enabled_mask &= ~disable_mask;
 631         dst->views.dirty_mask &= dst->views.enabled_mask;
 632         dst->views.enabled_mask |= new_mask;
 633         dst->views.dirty_mask |= new_mask;
 634         dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
 635         dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
 636         dst->views.dirty_txq_constants = TRUE;
 637         dst->views.dirty_buffer_constants = TRUE;
 638         r600_sampler_views_dirty(rctx, &dst->views);
 639
 640         if (dirty_sampler_states_mask) {
 641                 dst->states.dirty_mask |= dirty_sampler_states_mask;
 642                 r600_sampler_states_dirty(rctx, &dst->states);
 643         }
 644 }
 645
 646 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
 647                                       struct pipe_sampler_view **views)
 648 {
 649         r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
 650 }
 651
 652 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
 653                                       struct pipe_sampler_view **views)
 654 {
 655         r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
 656 }
 657
 658 static void r600_set_viewport_state(struct pipe_context *ctx,
 659                                     const struct pipe_viewport_state *state)
 660 {
 661         struct r600_context *rctx = (struct r600_context *)ctx;
 662
 663         rctx->viewport.state = *state;
 664         rctx->viewport.atom.dirty = true;
 665 }
 666
 667 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
 668 {
 669         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 670         struct pipe_viewport_state *state = &rctx->viewport.state;
 671
 672         r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
 673         r600_write_value(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
 674         r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
 675         r600_write_value(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
 676         r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
 677         r600_write_value(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
 678         r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
 679 }
 680
 681 /* Compute the key for the hw shader variant */
 682 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
 683                 struct r600_pipe_shader_selector * sel)
 684 {
 685         struct r600_context *rctx = (struct r600_context *)ctx;
 686         struct r600_shader_key key;
 687         memset(&key, 0, sizeof(key));
 688
 689         if (sel->type == PIPE_SHADER_FRAGMENT) {
 690                 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
 691                 key.alpha_to_one = rctx->alpha_to_one &&
 692                                    rctx->rasterizer && rctx->rasterizer->multisample_enable &&
 693                                    !rctx->framebuffer.cb0_is_integer;
 694                 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
 695                 /* Dual-source blending only makes sense with nr_cbufs == 1. */
 696                 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
 697                         key.nr_cbufs = 2;
 698         }
 699         return key;
 700 }
 701
 702 /* Select the hw shader variant depending on the current state.
 703  * (*dirty) is set to 1 if current variant was changed */
 704 static int r600_shader_select(struct pipe_context *ctx,
 705         struct r600_pipe_shader_selector* sel,
 706         unsigned *dirty)
 707 {
 708         struct r600_shader_key key;
 709         struct r600_context *rctx = (struct r600_context *)ctx;
 710         struct r600_pipe_shader * shader = NULL;
 711         int r;
 712
 713         key = r600_shader_selector_key(ctx, sel);
 714
 715         /* Check if we don't need to change anything.
 716          * This path is also used for most shaders that don't need multiple
 717          * variants, it will cost just a computation of the key and this
 718          * test. */
 719         if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
 720                 return 0;
 721         }
 722
 723         /* lookup if we have other variants in the list */
 724         if (sel->num_shaders > 1) {
 725                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 726
 727                 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
 728                         p = c;
 729                         c = c->next_variant;
 730                 }
 731
 732                 if (c) {
 733                         p->next_variant = c->next_variant;
 734                         shader = c;
 735                 }
 736         }
 737
 738         if (unlikely(!shader)) {
 739                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 740                 shader->selector = sel;
 741
 742                 r = r600_pipe_shader_create(ctx, shader, key);
 743                 if (unlikely(r)) {
 744                         R600_ERR("Failed to build shader variant (type=%u) %d\n",
 745                                  sel->type, r);
 746                         sel->current = NULL;
 747                         FREE(shader);
 748                         return r;
 749                 }
 750
 751                 /* We don't know the value of nr_ps_max_color_exports until we built
 752                  * at least one variant, so we may need to recompute the key after
 753                  * building first variant. */
 754                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 755                                 sel->num_shaders == 0) {
 756                         sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
 757                         key = r600_shader_selector_key(ctx, sel);
 758                 }
 759
 760                 shader->key = key;
 761                 sel->num_shaders++;
 762         }
 763
 764         if (dirty)
 765                 *dirty = 1;
 766
 767         shader->next_variant = sel->current;
 768         sel->current = shader;
 769
 770         if (rctx->ps_shader &&
 771             rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 772                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 773                 rctx->cb_misc_state.atom.dirty = true;
 774         }
 775         return 0;
 776 }
 777
 778 static void *r600_create_shader_state(struct pipe_context *ctx,
 779                                const struct pipe_shader_state *state,
 780                                unsigned pipe_shader_type)
 781 {
 782         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 783         int r;
 784
 785         sel->type = pipe_shader_type;
 786         sel->tokens = tgsi_dup_tokens(state->tokens);
 787         sel->so = state->stream_output;
 788
 789         r = r600_shader_select(ctx, sel, NULL);
 790         if (r)
 791             return NULL;
 792
 793         return sel;
 794 }
 795
 796 static void *r600_create_ps_state(struct pipe_context *ctx,
 797                                          const struct pipe_shader_state *state)
 798 {
 799         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 800 }
 801
 802 static void *r600_create_vs_state(struct pipe_context *ctx,
 803                                          const struct pipe_shader_state *state)
 804 {
 805         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 806 }
 807
 808 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 809 {
 810         struct r600_context *rctx = (struct r600_context *)ctx;
 811
 812         if (!state)
 813                 state = rctx->dummy_pixel_shader;
 814
 815         rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 816         r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 817
 818         r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
 819
 820         if (rctx->chip_class <= R700) {
 821                 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 822
 823                 if (rctx->cb_misc_state.multiwrite != multiwrite) {
 824                         rctx->cb_misc_state.multiwrite = multiwrite;
 825                         rctx->cb_misc_state.atom.dirty = true;
 826                 }
 827         }
 828
 829         if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 830                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 831                 rctx->cb_misc_state.atom.dirty = true;
 832         }
 833
 834         if (rctx->chip_class >= EVERGREEN) {
 835                 evergreen_update_db_shader_control(rctx);
 836         } else {
 837                 r600_update_db_shader_control(rctx);
 838         }
 839 }
 840
 841 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 842 {
 843         struct r600_context *rctx = (struct r600_context *)ctx;
 844
 845         rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 846         if (state) {
 847                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
 848
 849                 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
 850
 851                 /* Update clip misc state. */
 852                 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
 853                     rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
 854                         rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
 855                         rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
 856                         rctx->clip_misc_state.atom.dirty = true;
 857                 }
 858         }
 859 }
 860
 861 static void r600_delete_shader_selector(struct pipe_context *ctx,
 862                 struct r600_pipe_shader_selector *sel)
 863 {
 864         struct r600_pipe_shader *p = sel->current, *c;
 865         while (p) {
 866                 c = p->next_variant;
 867                 r600_pipe_shader_destroy(ctx, p);
 868                 free(p);
 869                 p = c;
 870         }
 871
 872         free(sel->tokens);
 873         free(sel);
 874 }
 875
 876
 877 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
 878 {
 879         struct r600_context *rctx = (struct r600_context *)ctx;
 880         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 881
 882         if (rctx->ps_shader == sel) {
 883                 rctx->ps_shader = NULL;
 884         }
 885
 886         r600_delete_shader_selector(ctx, sel);
 887 }
 888
 889 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
 890 {
 891         struct r600_context *rctx = (struct r600_context *)ctx;
 892         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 893
 894         if (rctx->vs_shader == sel) {
 895                 rctx->vs_shader = NULL;
 896         }
 897
 898         r600_delete_shader_selector(ctx, sel);
 899 }
 900
 901 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 902 {
 903         if (state->dirty_mask) {
 904                 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
 905                 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 906                                                                    : util_bitcount(state->dirty_mask)*19;
 907                 state->atom.dirty = true;
 908         }
 909 }
 910
 911 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 912                                      struct pipe_constant_buffer *input)
 913 {
 914         struct r600_context *rctx = (struct r600_context *)ctx;
 915         struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
 916         struct pipe_constant_buffer *cb;
 917         const uint8_t *ptr;
 918
 919         /* Note that the state tracker can unbind constant buffers by
 920          * passing NULL here.
 921          */
 922         if (unlikely(!input)) {
 923                 state->enabled_mask &= ~(1 << index);
 924                 state->dirty_mask &= ~(1 << index);
 925                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 926                 return;
 927         }
 928
 929         cb = &state->cb[index];
 930         cb->buffer_size = input->buffer_size;
 931
 932         ptr = input->user_buffer;
 933
 934         if (ptr) {
 935                 /* Upload the user buffer. */
 936                 if (R600_BIG_ENDIAN) {
 937                         uint32_t *tmpPtr;
 938                         unsigned i, size = input->buffer_size;
 939
 940                         if (!(tmpPtr = malloc(size))) {
 941                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 942                                 return;
 943                         }
 944
 945                         for (i = 0; i < size / 4; ++i) {
 946                                 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
 947                         }
 948
 949                         u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 950                         free(tmpPtr);
 951                 } else {
 952                         u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 953                 }
 954                 /* account it in gtt */
 955                 rctx->gtt += input->buffer_size;
 956         } else {
 957                 /* Setup the hw buffer. */
 958                 cb->buffer_offset = input->buffer_offset;
 959                 pipe_resource_reference(&cb->buffer, input->buffer);
 960                 r600_context_add_resource_size(ctx, input->buffer);
 961         }
 962
 963         state->enabled_mask |= 1 << index;
 964         state->dirty_mask |= 1 << index;
 965         r600_constant_buffers_dirty(rctx, state);
 966 }
 967
 968 static struct pipe_stream_output_target *
 969 r600_create_so_target(struct pipe_context *ctx,
 970                       struct pipe_resource *buffer,
 971                       unsigned buffer_offset,
 972                       unsigned buffer_size)
 973 {
 974         struct r600_context *rctx = (struct r600_context *)ctx;
 975         struct r600_so_target *t;
 976
 977         t = CALLOC_STRUCT(r600_so_target);
 978         if (!t) {
 979                 return NULL;
 980         }
 981
 982         u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
 983                              &t->buf_filled_size_offset,
 984                              (struct pipe_resource**)&t->buf_filled_size);
 985         if (!t->buf_filled_size) {
 986                 FREE(t);
 987                 return NULL;
 988         }
 989
 990         t->b.reference.count = 1;
 991         t->b.context = ctx;
 992         pipe_resource_reference(&t->b.buffer, buffer);
 993         t->b.buffer_offset = buffer_offset;
 994         t->b.buffer_size = buffer_size;
 995         return &t->b;
 996 }
 997
 998 static void r600_so_target_destroy(struct pipe_context *ctx,
 999                                    struct pipe_stream_output_target *target)
1000 {
1001         struct r600_so_target *t = (struct r600_so_target*)target;
1002         pipe_resource_reference(&t->b.buffer, NULL);
1003         pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
1004         FREE(t);
1005 }
1006
1007 static void r600_set_so_targets(struct pipe_context *ctx,
1008                                 unsigned num_targets,
1009                                 struct pipe_stream_output_target **targets,
1010                                 unsigned append_bitmask)
1011 {
1012         struct r600_context *rctx = (struct r600_context *)ctx;
1013         unsigned i;
1014
1015         /* Stop streamout. */
1016         if (rctx->num_so_targets && !rctx->streamout_start) {
1017                 r600_context_streamout_end(rctx);
1018         }
1019
1020         /* Set the new targets. */
1021         for (i = 0; i < num_targets; i++) {
1022                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1023                 r600_context_add_resource_size(ctx, targets[i]->buffer);
1024         }
1025         for (; i < rctx->num_so_targets; i++) {
1026                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1027         }
1028
1029         rctx->num_so_targets = num_targets;
1030         rctx->streamout_start = num_targets != 0;
1031         rctx->streamout_append_bitmask = append_bitmask;
1032 }
1033
1034 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1035 {
1036         struct r600_context *rctx = (struct r600_context*)pipe;
1037
1038         if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1039                 return;
1040
1041         rctx->sample_mask.sample_mask = sample_mask;
1042         rctx->sample_mask.atom.dirty = true;
1043 }
1044
1045 /*
1046  * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1047  * doesn't require full swizzles it does need masking and setting alpha
1048  * to one, so we setup a set of 5 constants with the masks + alpha value
1049  * then in the shader, we AND the 4 components with 0xffffffff or 0,
1050  * then OR the alpha with the value given here.
1051  * We use a 6th constant to store the txq buffer size in
1052  */
1053 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1054 {
1055         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1056         int bits;
1057         uint32_t array_size;
1058         struct pipe_constant_buffer cb;
1059         int i, j;
1060
1061         if (!samplers->views.dirty_buffer_constants)
1062                 return;
1063
1064         samplers->views.dirty_buffer_constants = FALSE;
1065
1066         bits = util_last_bit(samplers->views.enabled_mask);
1067         array_size = bits * 8 * sizeof(uint32_t) * 4;
1068         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1069         memset(samplers->buffer_constants, 0, array_size);
1070         for (i = 0; i < bits; i++) {
1071                 if (samplers->views.enabled_mask & (1 << i)) {
1072                         int offset = i * 8;
1073                         const struct util_format_description *desc;
1074                         desc = util_format_description(samplers->views.views[i]->base.format);
1075
1076                         for (j = 0; j < 4; j++)
1077                                 if (j < desc->nr_channels)
1078                                         samplers->buffer_constants[offset+j] = 0xffffffff;
1079                                 else
1080                                         samplers->buffer_constants[offset+j] = 0x0;
1081                         if (desc->nr_channels < 4) {
1082                                 if (desc->channel[0].pure_integer)
1083                                         samplers->buffer_constants[offset+4] = 1;
1084                                 else
1085                                         samplers->buffer_constants[offset+4] = 0x3f800000;
1086                         } else
1087                                 samplers->buffer_constants[offset + 4] = 0;
1088
1089                         samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1090                 }
1091         }
1092
1093         cb.buffer = NULL;
1094         cb.user_buffer = samplers->buffer_constants;
1095         cb.buffer_offset = 0;
1096         cb.buffer_size = array_size;
1097         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1098         pipe_resource_reference(&cb.buffer, NULL);
1099 }
1100
1101 /* On evergreen we only need to store the buffer size for TXQ */
1102 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1103 {
1104         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1105         int bits;
1106         uint32_t array_size;
1107         struct pipe_constant_buffer cb;
1108         int i;
1109
1110         if (!samplers->views.dirty_buffer_constants)
1111                 return;
1112
1113         samplers->views.dirty_buffer_constants = FALSE;
1114
1115         bits = util_last_bit(samplers->views.enabled_mask);
1116         array_size = bits * sizeof(uint32_t) * 4;
1117         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1118         memset(samplers->buffer_constants, 0, array_size);
1119         for (i = 0; i < bits; i++)
1120                 if (samplers->views.enabled_mask & (1 << i))
1121                    samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1122
1123         cb.buffer = NULL;
1124         cb.user_buffer = samplers->buffer_constants;
1125         cb.buffer_offset = 0;
1126         cb.buffer_size = array_size;
1127         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1128         pipe_resource_reference(&cb.buffer, NULL);
1129 }
1130
1131 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1132 {
1133         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1134         int bits;
1135         uint32_t array_size;
1136         struct pipe_constant_buffer cb;
1137         int i;
1138
1139         if (!samplers->views.dirty_txq_constants)
1140                 return;
1141
1142         samplers->views.dirty_txq_constants = FALSE;
1143
1144         bits = util_last_bit(samplers->views.enabled_mask);
1145         array_size = bits * sizeof(uint32_t) * 4;
1146         samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1147         memset(samplers->txq_constants, 0, array_size);
1148         for (i = 0; i < bits; i++)
1149                 if (samplers->views.enabled_mask & (1 << i))
1150                         samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1151
1152         cb.buffer = NULL;
1153         cb.user_buffer = samplers->txq_constants;
1154         cb.buffer_offset = 0;
1155         cb.buffer_size = array_size;
1156         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1157         pipe_resource_reference(&cb.buffer, NULL);
1158 }
1159
1160 static bool r600_update_derived_state(struct r600_context *rctx)
1161 {
1162         struct pipe_context * ctx = (struct pipe_context*)rctx;
1163         unsigned ps_dirty = 0;
1164         bool blend_disable;
1165
1166         if (!rctx->blitter->running) {
1167                 unsigned i;
1168
1169                 /* Decompress textures if needed. */
1170                 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1171                         struct r600_samplerview_state *views = &rctx->samplers[i].views;
1172                         if (views->compressed_depthtex_mask) {
1173                                 r600_decompress_depth_textures(rctx, views);
1174                         }
1175                         if (views->compressed_colortex_mask) {
1176                                 r600_decompress_color_textures(rctx, views);
1177                         }
1178                 }
1179         }
1180
1181         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1182
1183         if (rctx->ps_shader && rctx->rasterizer &&
1184             ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1185              (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1186
1187                 if (rctx->chip_class >= EVERGREEN)
1188                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1189                 else
1190                         r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1191
1192                 ps_dirty = 1;
1193         }
1194
1195         if (ps_dirty)
1196                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1197
1198         /* on R600 we stuff masks + txq info into one constant buffer */
1199         /* on evergreen we only need a txq info one */
1200         if (rctx->chip_class < EVERGREEN) {
1201                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1202                         r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1203                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1204                         r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1205         } else {
1206                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1207                         eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1208                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1209                         eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1210         }
1211
1212
1213         if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1214                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1215         if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1216                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1217
1218         if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1219                 if (!r600_adjust_gprs(rctx)) {
1220                         /* discard rendering */
1221                         return false;
1222                 }
1223         }
1224
1225         blend_disable = (rctx->dual_src_blend &&
1226                         rctx->ps_shader->current->nr_ps_color_outputs < 2);
1227
1228         if (blend_disable != rctx->force_blend_disable) {
1229                 rctx->force_blend_disable = blend_disable;
1230                 r600_bind_blend_state_internal(rctx,
1231                                                rctx->blend_state.cso,
1232                                                blend_disable);
1233         }
1234         return true;
1235 }
1236
1237 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1238 {
1239         static const int prim_conv[] = {
1240                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1241                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1242                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1243                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1244                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1245                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1246                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1247                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1248                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1249                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1250                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1251                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1252                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1253                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1254                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1255         };
1256         assert(mode < Elements(prim_conv));
1257
1258         return prim_conv[mode];
1259 }
1260
1261 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1262 {
1263         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1264         struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1265
1266         r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1267                                state->pa_cl_clip_cntl |
1268                                (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1269         r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1270                                state->pa_cl_vs_out_cntl |
1271                                (state->clip_plane_enable & state->clip_dist_write));
1272 }
1273
1274 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1275 {
1276         struct r600_context *rctx = (struct r600_context *)ctx;
1277         struct pipe_draw_info info = *dinfo;
1278         struct pipe_index_buffer ib = {};
1279         unsigned i;
1280         struct r600_block *dirty_block = NULL, *next_block = NULL;
1281         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1282
1283         if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1284                 assert(0);
1285                 return;
1286         }
1287
1288         if (!rctx->vs_shader) {
1289                 assert(0);
1290                 return;
1291         }
1292
1293         /* make sure that the gfx ring is only one active */
1294         if (rctx->rings.dma.cs) {
1295                 rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1296         }
1297
1298         if (!r600_update_derived_state(rctx)) {
1299                 /* useless to render because current rendering command
1300                  * can't be achieved
1301                  */
1302                 return;
1303         }
1304
1305         if (info.indexed) {
1306                 /* Initialize the index buffer struct. */
1307                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1308                 ib.user_buffer = rctx->index_buffer.user_buffer;
1309                 ib.index_size = rctx->index_buffer.index_size;
1310                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1311
1312                 /* Translate 8-bit indices to 16-bit. */
1313                 if (ib.index_size == 1) {
1314                         struct pipe_resource *out_buffer = NULL;
1315                         unsigned out_offset;
1316                         void *ptr;
1317
1318                         u_upload_alloc(rctx->uploader, 0, info.count * 2,
1319                                        &out_offset, &out_buffer, &ptr);
1320
1321                         util_shorten_ubyte_elts_to_userptr(
1322                                                 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1323
1324                         pipe_resource_reference(&ib.buffer, NULL);
1325                         ib.user_buffer = NULL;
1326                         ib.buffer = out_buffer;
1327                         ib.offset = out_offset;
1328                         ib.index_size = 2;
1329                 }
1330
1331                 /* Upload the index buffer.
1332                  * The upload is skipped for small index counts on little-endian machines
1333                  * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1334                  * Note: Instanced rendering in combination with immediate indices hangs. */
1335                 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1336                                        info.count*ib.index_size > 20)) {
1337                         u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1338                                       ib.user_buffer, &ib.offset, &ib.buffer);
1339                         ib.user_buffer = NULL;
1340                 }
1341         } else {
1342                 info.index_bias = info.start;
1343         }
1344
1345         /* Enable stream out if needed. */
1346         if (rctx->streamout_start) {
1347                 r600_context_streamout_begin(rctx);
1348                 rctx->streamout_start = FALSE;
1349         }
1350
1351         /* Set the index offset and multi primitive */
1352         if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1353                 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1354                 rctx->vgt2_state.atom.dirty = true;
1355         }
1356         if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1357             rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1358                 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1359                 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1360                 rctx->vgt_state.atom.dirty = true;
1361         }
1362
1363         /* Emit states. */
1364         r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1365         r600_flush_emit(rctx);
1366
1367         for (i = 0; i < R600_NUM_ATOMS; i++) {
1368                 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1369                         continue;
1370                 }
1371                 r600_emit_atom(rctx, rctx->atoms[i]);
1372         }
1373         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1374                 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1375         }
1376         rctx->pm4_dirty_cdwords = 0;
1377
1378         /* Update start instance. */
1379         if (rctx->last_start_instance != info.start_instance) {
1380                 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1381                 rctx->last_start_instance = info.start_instance;
1382         }
1383
1384         /* Update the primitive type. */
1385         if (rctx->last_primitive_type != info.mode) {
1386                 unsigned ls_mask = 0;
1387
1388                 if (info.mode == PIPE_PRIM_LINES)
1389                         ls_mask = 1;
1390                 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1391                          info.mode == PIPE_PRIM_LINE_LOOP)
1392                         ls_mask = 2;
1393
1394                 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1395                                        S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1396                                        (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1397                 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1398                                        r600_conv_prim_to_gs_out(info.mode));
1399                 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1400                                       r600_conv_pipe_prim(info.mode));
1401
1402                 rctx->last_primitive_type = info.mode;
1403         }
1404
1405         /* Draw packets. */
1406         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1407         cs->buf[cs->cdw++] = info.instance_count;
1408         if (info.indexed) {
1409                 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1410                 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1411                                         (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1412                                         (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1413
1414                 if (ib.user_buffer) {
1415                         unsigned size_bytes = info.count*ib.index_size;
1416                         unsigned size_dw = align(size_bytes, 4) / 4;
1417                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1418                         cs->buf[cs->cdw++] = info.count;
1419                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1420                         memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1421                         cs->cdw += size_dw;
1422                 } else {
1423                         uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1424                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1425                         cs->buf[cs->cdw++] = va;
1426                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1427                         cs->buf[cs->cdw++] = info.count;
1428                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1429                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1430                         cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1431                 }
1432         } else {
1433                 if (info.count_from_stream_output) {
1434                         struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1435                         uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1436
1437                         r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1438
1439                         cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1440                         cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1441                         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* src address lo */
1442                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1443                         cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1444                         cs->buf[cs->cdw++] = 0; /* unused */
1445
1446                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1447                         cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1448                 }
1449
1450                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1451                 cs->buf[cs->cdw++] = info.count;
1452                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1453                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1454         }
1455
1456 #if R600_TRACE_CS
1457         if (rctx->screen->trace_bo) {
1458                 r600_trace_emit(rctx);
1459         }
1460 #endif
1461
1462         /* Set the depth buffer as dirty. */
1463         if (rctx->framebuffer.state.zsbuf) {
1464                 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1465                 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1466
1467                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1468         }
1469         if (rctx->framebuffer.compressed_cb_mask) {
1470                 struct pipe_surface *surf;
1471                 struct r600_texture *rtex;
1472                 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1473
1474                 do {
1475                         unsigned i = u_bit_scan(&mask);
1476                         surf = rctx->framebuffer.state.cbufs[i];
1477                         rtex = (struct r600_texture*)surf->texture;
1478
1479                         rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1480
1481                 } while (mask);
1482         }
1483
1484         pipe_resource_reference(&ib.buffer, NULL);
1485 }
1486
1487 void r600_draw_rectangle(struct blitter_context *blitter,
1488                          int x1, int y1, int x2, int y2, float depth,
1489                          enum blitter_attrib_type type, const union pipe_color_union *attrib)
1490 {
1491         struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1492         struct pipe_viewport_state viewport;
1493         struct pipe_resource *buf = NULL;
1494         unsigned offset = 0;
1495         float *vb;
1496
1497         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1498                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1499                 return;
1500         }
1501
1502         /* Some operations (like color resolve on r6xx) don't work
1503          * with the conventional primitive types.
1504          * One that works is PT_RECTLIST, which we use here. */
1505
1506         /* setup viewport */
1507         viewport.scale[0] = 1.0f;
1508         viewport.scale[1] = 1.0f;
1509         viewport.scale[2] = 1.0f;
1510         viewport.scale[3] = 1.0f;
1511         viewport.translate[0] = 0.0f;
1512         viewport.translate[1] = 0.0f;
1513         viewport.translate[2] = 0.0f;
1514         viewport.translate[3] = 0.0f;
1515         rctx->context.set_viewport_state(&rctx->context, &viewport);
1516
1517         /* Upload vertices. The hw rectangle has only 3 vertices,
1518          * I guess the 4th one is derived from the first 3.
1519          * The vertex specification should match u_blitter's vertex element state. */
1520         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1521         vb[0] = x1;
1522         vb[1] = y1;
1523         vb[2] = depth;
1524         vb[3] = 1;
1525
1526         vb[8] = x1;
1527         vb[9] = y2;
1528         vb[10] = depth;
1529         vb[11] = 1;
1530
1531         vb[16] = x2;
1532         vb[17] = y1;
1533         vb[18] = depth;
1534         vb[19] = 1;
1535
1536         if (attrib) {
1537                 memcpy(vb+4, attrib->f, sizeof(float)*4);
1538                 memcpy(vb+12, attrib->f, sizeof(float)*4);
1539                 memcpy(vb+20, attrib->f, sizeof(float)*4);
1540         }
1541
1542         /* draw */
1543         util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1544                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
1545         pipe_resource_reference(&buf, NULL);
1546 }
1547
1548 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1549                                  struct r600_pipe_state *state,
1550                                  uint32_t offset, uint32_t value,
1551                                  uint32_t range_id, uint32_t block_id,
1552                                  struct r600_resource *bo,
1553                                  enum radeon_bo_usage usage)
1554
1555 {
1556         struct r600_range *range;
1557         struct r600_block *block;
1558
1559         if (bo) assert(usage);
1560
1561         range = &ctx->range[range_id];
1562         block = range->blocks[block_id];
1563         state->regs[state->nregs].block = block;
1564         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1565
1566         state->regs[state->nregs].value = value;
1567         state->regs[state->nregs].bo = bo;
1568         state->regs[state->nregs].bo_usage = usage;
1569
1570         state->nregs++;
1571         assert(state->nregs < R600_BLOCK_MAX_REG);
1572 }
1573
1574 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1575                               struct r600_pipe_state *state,
1576                               uint32_t offset, uint32_t value,
1577                               uint32_t range_id, uint32_t block_id)
1578 {
1579         _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1580                                     range_id, block_id, NULL, 0);
1581 }
1582
1583 uint32_t r600_translate_stencil_op(int s_op)
1584 {
1585         switch (s_op) {
1586         case PIPE_STENCIL_OP_KEEP:
1587                 return V_028800_STENCIL_KEEP;
1588         case PIPE_STENCIL_OP_ZERO:
1589                 return V_028800_STENCIL_ZERO;
1590         case PIPE_STENCIL_OP_REPLACE:
1591                 return V_028800_STENCIL_REPLACE;
1592         case PIPE_STENCIL_OP_INCR:
1593                 return V_028800_STENCIL_INCR;
1594         case PIPE_STENCIL_OP_DECR:
1595                 return V_028800_STENCIL_DECR;
1596         case PIPE_STENCIL_OP_INCR_WRAP:
1597                 return V_028800_STENCIL_INCR_WRAP;
1598         case PIPE_STENCIL_OP_DECR_WRAP:
1599                 return V_028800_STENCIL_DECR_WRAP;
1600         case PIPE_STENCIL_OP_INVERT:
1601                 return V_028800_STENCIL_INVERT;
1602         default:
1603                 R600_ERR("Unknown stencil op %d", s_op);
1604                 assert(0);
1605                 break;
1606         }
1607         return 0;
1608 }
1609
1610 uint32_t r600_translate_fill(uint32_t func)
1611 {
1612         switch(func) {
1613         case PIPE_POLYGON_MODE_FILL:
1614                 return 2;
1615         case PIPE_POLYGON_MODE_LINE:
1616                 return 1;
1617         case PIPE_POLYGON_MODE_POINT:
1618                 return 0;
1619         default:
1620                 assert(0);
1621                 return 0;
1622         }
1623 }
1624
1625 unsigned r600_tex_wrap(unsigned wrap)
1626 {
1627         switch (wrap) {
1628         default:
1629         case PIPE_TEX_WRAP_REPEAT:
1630                 return V_03C000_SQ_TEX_WRAP;
1631         case PIPE_TEX_WRAP_CLAMP:
1632                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1633         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1634                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1635         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1636                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1637         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1638                 return V_03C000_SQ_TEX_MIRROR;
1639         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1640                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1641         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1642                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1643         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1644                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1645         }
1646 }
1647
1648 unsigned r600_tex_filter(unsigned filter)
1649 {
1650         switch (filter) {
1651         default:
1652         case PIPE_TEX_FILTER_NEAREST:
1653                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1654         case PIPE_TEX_FILTER_LINEAR:
1655                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1656         }
1657 }
1658
1659 unsigned r600_tex_mipfilter(unsigned filter)
1660 {
1661         switch (filter) {
1662         case PIPE_TEX_MIPFILTER_NEAREST:
1663                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1664         case PIPE_TEX_MIPFILTER_LINEAR:
1665                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1666         default:
1667         case PIPE_TEX_MIPFILTER_NONE:
1668                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1669         }
1670 }
1671
1672 unsigned r600_tex_compare(unsigned compare)
1673 {
1674         switch (compare) {
1675         default:
1676         case PIPE_FUNC_NEVER:
1677                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1678         case PIPE_FUNC_LESS:
1679                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1680         case PIPE_FUNC_EQUAL:
1681                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1682         case PIPE_FUNC_LEQUAL:
1683                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1684         case PIPE_FUNC_GREATER:
1685                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1686         case PIPE_FUNC_NOTEQUAL:
1687                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1688         case PIPE_FUNC_GEQUAL:
1689                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1690         case PIPE_FUNC_ALWAYS:
1691                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1692         }
1693 }
1694
1695 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1696 {
1697         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1698                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1699                (linear_filter &&
1700                 (wrap == PIPE_TEX_WRAP_CLAMP ||
1701                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1702 }
1703
1704 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1705 {
1706         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1707                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1708
1709         return (state->border_color.ui[0] || state->border_color.ui[1] ||
1710                 state->border_color.ui[2] || state->border_color.ui[3]) &&
1711                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1712                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1713                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1714 }
1715
1716 /* keep this at the end of this file, please */
1717 void r600_init_common_state_functions(struct r600_context *rctx)
1718 {
1719         rctx->context.create_fs_state = r600_create_ps_state;
1720         rctx->context.create_vs_state = r600_create_vs_state;
1721         rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1722         rctx->context.bind_blend_state = r600_bind_blend_state;
1723         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1724         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1725         rctx->context.bind_fs_state = r600_bind_ps_state;
1726         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1727         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1728         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1729         rctx->context.bind_vs_state = r600_bind_vs_state;
1730         rctx->context.delete_blend_state = r600_delete_blend_state;
1731         rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1732         rctx->context.delete_fs_state = r600_delete_ps_state;
1733         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1734         rctx->context.delete_sampler_state = r600_delete_sampler_state;
1735         rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1736         rctx->context.delete_vs_state = r600_delete_vs_state;
1737         rctx->context.set_blend_color = r600_set_blend_color;
1738         rctx->context.set_clip_state = r600_set_clip_state;
1739         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1740         rctx->context.set_sample_mask = r600_set_sample_mask;
1741         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1742         rctx->context.set_viewport_state = r600_set_viewport_state;
1743         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1744         rctx->context.set_index_buffer = r600_set_index_buffer;
1745         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1746         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1747         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1748         rctx->context.texture_barrier = r600_texture_barrier;
1749         rctx->context.create_stream_output_target = r600_create_so_target;
1750         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1751         rctx->context.set_stream_output_targets = r600_set_so_targets;
1752         rctx->context.draw_vbo = r600_draw_vbo;
1753 }
1754
1755 #if R600_TRACE_CS
1756 void r600_trace_emit(struct r600_context *rctx)
1757 {
1758         struct r600_screen *rscreen = rctx->screen;
1759         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1760         uint64_t va;
1761         uint32_t reloc;
1762
1763         va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
1764         reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
1765         r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
1766         r600_write_value(cs, va & 0xFFFFFFFFUL);
1767         r600_write_value(cs, (va >> 32UL) & 0xFFUL);
1768         r600_write_value(cs, cs->cdw);
1769         r600_write_value(cs, rscreen->cs_count);
1770         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1771         r600_write_value(cs, reloc);
1772 }
1773 #endif