1 //===-- AMDILMachinePeephole.cpp - AMDIL Machine Peephole Pass -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 #define DEBUG_TYPE "machine_peephole"
13 #define DEBUGME (DebugFlag && isCurrentDebugType(DEBUG_TYPE))
15 #define DEBUGME (false)
19 #include "AMDILSubtarget.h"
20 #include "AMDILUtilityFunctions.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Target/TargetMachine.h"
29 class AMDILMachinePeephole : public MachineFunctionPass
33 AMDILMachinePeephole(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
34 //virtual ~AMDILMachinePeephole();
38 runOnMachineFunction(MachineFunction &MF);
40 void insertFence(MachineBasicBlock::iterator &MIB);
43 }; // AMDILMachinePeephole
44 char AMDILMachinePeephole::ID = 0;
45 } // anonymous namespace
50 createAMDILMachinePeephole(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
52 return new AMDILMachinePeephole(tm AMDIL_OPT_LEVEL_VAR);
56 AMDILMachinePeephole::AMDILMachinePeephole(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
57 : MachineFunctionPass(ID), TM(tm)
63 AMDILMachinePeephole::runOnMachineFunction(MachineFunction &MF)
66 const AMDILSubtarget *STM = &TM.getSubtarget<AMDILSubtarget>();
67 for (MachineFunction::iterator MBB = MF.begin(), MBE = MF.end();
69 MachineBasicBlock *mb = MBB;
70 for (MachineBasicBlock::iterator MIB = mb->begin(), MIE = mb->end();
72 MachineInstr *mi = MIB;
74 name = TM.getInstrInfo()->getName(mi->getOpcode());
75 switch (mi->getOpcode()) {
77 if (isAtomicInst(TM.getInstrInfo(), mi)) {
78 // If we don't support the hardware accellerated address spaces,
79 // then the atomic needs to be transformed to the global atomic.
80 if (strstr(name, "_L_")
81 && STM->device()->usesSoftware(AMDILDeviceInfo::LocalMem)) {
82 BuildMI(*mb, MIB, mi->getDebugLoc(),
83 TM.getInstrInfo()->get(AMDIL::ADD_i32), AMDIL::R1011)
84 .addReg(mi->getOperand(1).getReg())
86 mi->getOperand(1).setReg(AMDIL::R1011);
88 TM.getInstrInfo()->get(
89 (mi->getOpcode() - AMDIL::ATOM_L_ADD) + AMDIL::ATOM_G_ADD));
90 } else if (strstr(name, "_R_")
91 && STM->device()->usesSoftware(AMDILDeviceInfo::RegionMem)) {
92 assert(!"Software region memory is not supported!");
94 TM.getInstrInfo()->get(
95 (mi->getOpcode() - AMDIL::ATOM_R_ADD) + AMDIL::ATOM_G_ADD));
97 } else if ((isLoadInst(TM.getInstrInfo(), mi) || isStoreInst(TM.getInstrInfo(), mi)) && isVolatileInst(TM.getInstrInfo(), mi)) {
102 case AMDIL::USHR_i16:
103 case AMDIL::USHR_v2i16:
104 case AMDIL::USHR_v4i16:
105 case AMDIL::USHRVEC_i16:
106 case AMDIL::USHRVEC_v2i16:
107 case AMDIL::USHRVEC_v4i16:
108 if (TM.getSubtarget<AMDILSubtarget>()
109 .device()->usesSoftware(AMDILDeviceInfo::ShortOps)) {
110 unsigned lReg = MF.getRegInfo()
111 .createVirtualRegister(&AMDIL::GPRI32RegClass);
112 unsigned Reg = MF.getRegInfo()
113 .createVirtualRegister(&AMDIL::GPRV4I32RegClass);
114 BuildMI(*mb, MIB, mi->getDebugLoc(),
115 TM.getInstrInfo()->get(AMDIL::LOADCONST_i32),
116 lReg).addImm(0xFFFF);
117 BuildMI(*mb, MIB, mi->getDebugLoc(),
118 TM.getInstrInfo()->get(AMDIL::BINARY_AND_v4i32),
120 .addReg(mi->getOperand(1).getReg())
122 mi->getOperand(1).setReg(Reg);
126 case AMDIL::USHR_v2i8:
127 case AMDIL::USHR_v4i8:
128 case AMDIL::USHRVEC_i8:
129 case AMDIL::USHRVEC_v2i8:
130 case AMDIL::USHRVEC_v4i8:
131 if (TM.getSubtarget<AMDILSubtarget>()
132 .device()->usesSoftware(AMDILDeviceInfo::ByteOps)) {
133 unsigned lReg = MF.getRegInfo()
134 .createVirtualRegister(&AMDIL::GPRI32RegClass);
135 unsigned Reg = MF.getRegInfo()
136 .createVirtualRegister(&AMDIL::GPRV4I32RegClass);
137 BuildMI(*mb, MIB, mi->getDebugLoc(),
138 TM.getInstrInfo()->get(AMDIL::LOADCONST_i32),
140 BuildMI(*mb, MIB, mi->getDebugLoc(),
141 TM.getInstrInfo()->get(AMDIL::BINARY_AND_v4i32),
143 .addReg(mi->getOperand(1).getReg())
145 mi->getOperand(1).setReg(Reg);
155 AMDILMachinePeephole::getPassName() const
157 return "AMDIL Generic Machine Peephole Optimization Pass";
161 AMDILMachinePeephole::insertFence(MachineBasicBlock::iterator &MIB)
163 MachineInstr *MI = MIB;
164 MachineInstr *fence = BuildMI(*(MI->getParent()->getParent()),
166 TM.getInstrInfo()->get(AMDIL::FENCE)).addReg(1);
168 MI->getParent()->insert(MIB, fence);
169 fence = BuildMI(*(MI->getParent()->getParent()),
171 TM.getInstrInfo()->get(AMDIL::FENCE)).addReg(1);
172 MIB = MI->getParent()->insertAfter(MIB, fence);