1 //===-- AMDILTargetMachine.cpp - Define TargetMachine for AMDIL -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "AMDILTargetMachine.h"
13 #include "AMDGPUTargetMachine.h"
14 #include "AMDILDevices.h"
15 #include "AMDILFrameLowering.h"
16 #include "llvm/ADT/OwningPtr.h"
17 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/SchedulerRegistry.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/Pass.h"
25 #include "llvm/PassManager.h"
26 #include "llvm/Support/FormattedStream.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Transforms/Scalar.h"
33 extern "C" void LLVMInitializeAMDILTarget() {
34 // Register the target
35 RegisterTargetMachine<AMDILTargetMachine> X(TheAMDILTarget);
36 RegisterTargetMachine<AMDGPUTargetMachine> Y(TheAMDGPUTarget);
39 /// AMDILTargetMachine ctor -
41 AMDILTargetMachine::AMDILTargetMachine(const Target &T,
42 StringRef TT, StringRef CPU, StringRef FS,
43 TargetOptions Options,
44 Reloc::Model RM, CodeModel::Model CM,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
49 Subtarget(TT, CPU, FS),
50 DataLayout(Subtarget.getDataLayout()),
51 FrameLowering(TargetFrameLowering::StackGrowsUp,
52 Subtarget.device()->getStackAlignment(), 0),
53 InstrInfo(*this), //JITInfo(*this),
56 ELFWriterInfo(false, true)
58 setAsmVerbosityDefault(true);
63 AMDILTargetMachine::getTargetLowering() const
65 return const_cast<AMDILTargetLowering*>(&TLInfo);
69 AMDILTargetMachine::getInstrInfo() const
73 const AMDILFrameLowering*
74 AMDILTargetMachine::getFrameLowering() const
76 return &FrameLowering;
80 AMDILTargetMachine::getSubtargetImpl() const
85 const AMDILRegisterInfo*
86 AMDILTargetMachine::getRegisterInfo() const
88 return &InstrInfo.getRegisterInfo();
92 AMDILTargetMachine::getTargetData() const
97 const AMDILELFWriterInfo*
98 AMDILTargetMachine::getELFWriterInfo() const
100 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
103 const AMDILIntrinsicInfo*
104 AMDILTargetMachine::getIntrinsicInfo() const
106 return &IntrinsicInfo;
110 AMDILTargetMachine::dump(llvm::raw_ostream &O)
115 O << ";AMDIL Target Machine State Dump: \n";
119 AMDILTargetMachine::setDebug(bool debugMode)
121 mDebugMode = debugMode;
125 AMDILTargetMachine::getDebug() const
131 class AMDILPassConfig : public TargetPassConfig {
134 AMDILPassConfig(AMDILTargetMachine *TM, PassManagerBase &PM)
135 : TargetPassConfig(TM, PM) {}
137 AMDILTargetMachine &getAMDILTargetMachine() const {
138 return getTM<AMDILTargetMachine>();
141 virtual bool addPreISel();
142 virtual bool addInstSelector();
143 virtual bool addPreRegAlloc();
144 virtual bool addPostRegAlloc();
145 virtual bool addPreEmitPass();
147 } // End of anonymous namespace
149 TargetPassConfig *AMDILTargetMachine::createPassConfig(PassManagerBase &PM) {
150 return new AMDILPassConfig(this, PM);
153 bool AMDILPassConfig::addPreISel()
158 bool AMDILPassConfig::addInstSelector()
160 PM.add(createAMDILBarrierDetect(*TM));
161 PM.add(createAMDILPrintfConvert(*TM));
162 PM.add(createAMDILInlinePass(*TM));
163 PM.add(createAMDILPeepholeOpt(*TM));
164 PM.add(createAMDILISelDag(getAMDILTargetMachine()));
168 bool AMDILPassConfig::addPreRegAlloc()
170 // If debugging, reduce code motion. Use less aggressive pre-RA scheduler
171 if (TM->getOptLevel() == CodeGenOpt::None) {
172 llvm::RegisterScheduler::setDefault(&llvm::createSourceListDAGScheduler);
175 PM.add(createAMDILMachinePeephole(*TM));
176 PM.add(createAMDILPointerManager(*TM));
180 bool AMDILPassConfig::addPostRegAlloc() {
181 return false; // -print-machineinstr should print after this.
184 /// addPreEmitPass - This pass may be implemented by targets that want to run
185 /// passes immediately before machine code is emitted. This should return
186 /// true if -print-machineinstrs should print out the code after the passes.
187 bool AMDILPassConfig::addPreEmitPass()
189 PM.add(createAMDILCFGPreparationPass(*TM));
190 PM.add(createAMDILCFGStructurizerPass(*TM));
191 PM.add(createAMDILLiteralManager(*TM));
192 PM.add(createAMDILIOExpansion(*TM));