1 //===-- R600ISelLowering.cpp - TODO: Add brief description -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TODO: Add full description
12 //===----------------------------------------------------------------------===//
14 #include "R600ISelLowering.h"
15 #include "R600InstrInfo.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
21 AMDGPUTargetLowering(TM),
22 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
24 setOperationAction(ISD::MUL, MVT::i64, Expand);
25 // setSchedulingPreference(Sched::VLIW);
28 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
29 MachineInstr * MI, MachineBasicBlock * BB) const
31 MachineFunction * MF = BB->getParent();
32 MachineRegisterInfo &MRI = MF->getRegInfo();
34 switch (MI->getOpcode()) {
35 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
36 /* XXX: Use helper function from AMDGPULowerShaderInstructions here */
38 addLiveIn(MI, MF, MRI, TII, AMDIL::T1_X);
41 addLiveIn(MI, MF, MRI, TII, AMDIL::T1_Y);
44 addLiveIn(MI, MF, MRI, TII, AMDIL::T1_Z);
47 addLiveIn(MI, MF, MRI, TII, AMDIL::T0_X);
50 addLiveIn(MI, MF, MRI, TII, AMDIL::T0_Y);
53 addLiveIn(MI, MF, MRI, TII, AMDIL::T0_Z);
55 case AMDIL::NGROUPS_X:
56 lowerImplicitParameter(MI, *BB, MRI, 0);
58 case AMDIL::NGROUPS_Y:
59 lowerImplicitParameter(MI, *BB, MRI, 1);
61 case AMDIL::NGROUPS_Z:
62 lowerImplicitParameter(MI, *BB, MRI, 2);
64 case AMDIL::GLOBAL_SIZE_X:
65 lowerImplicitParameter(MI, *BB, MRI, 3);
67 case AMDIL::GLOBAL_SIZE_Y:
68 lowerImplicitParameter(MI, *BB, MRI, 4);
70 case AMDIL::GLOBAL_SIZE_Z:
71 lowerImplicitParameter(MI, *BB, MRI, 5);
73 case AMDIL::LOCAL_SIZE_X:
74 lowerImplicitParameter(MI, *BB, MRI, 6);
76 case AMDIL::LOCAL_SIZE_Y:
77 lowerImplicitParameter(MI, *BB, MRI, 7);
79 case AMDIL::LOCAL_SIZE_Z:
80 lowerImplicitParameter(MI, *BB, MRI, 8);
83 MI->eraseFromParent();
87 void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
88 MachineRegisterInfo & MRI, unsigned dword_offset) const
90 MachineBasicBlock::iterator I = *MI;
91 unsigned offsetReg = MRI.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
92 MRI.setRegClass(MI->getOperand(0).getReg(), &AMDIL::R600_TReg32_XRegClass);
94 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::MOV), offsetReg)
95 .addReg(AMDIL::ALU_LITERAL_X)
96 .addImm(dword_offset * 4);
98 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::VTX_READ_eg))
99 .addOperand(MI->getOperand(0))