1 //===-- SIInstrInfo.td - TODO: Add brief description -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TODO: Add full description
12 //===----------------------------------------------------------------------===//
16 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
17 AMDGPUInst<outs, ins, asm, pattern> {
19 field bits<4> EncodingType = 0;
20 field bits<1> NeedWait = 0;
22 let TSFlags{3-0} = EncodingType;
23 let TSFlags{4} = NeedWait;
27 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
28 InstSI <outs, ins, asm, pattern> {
33 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
34 InstSI <outs, ins, asm, pattern> {
39 class GPR4Align <RegisterClass rc> : Operand <vAny> {
40 let EncoderMethod = "GPR4AlignEncode";
41 let MIOperandInfo = (ops rc:$reg);
44 class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
45 let EncoderMethod = "GPR2AlignEncode";
46 let MIOperandInfo = (ops rc:$reg);
49 def i32Literal : Operand <i32> {
50 let EncoderMethod = "i32LiteralEncode";
55 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
56 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
57 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
75 let Inst{31-26} = 0x3e;
76 let Inst{39-32} = VSRC0;
77 let Inst{47-40} = VSRC1;
78 let Inst{55-48} = VSRC2;
79 let Inst{63-56} = VSRC3;
80 let EncodingType = 0; //SIInstrEncodingType::EXP
83 let usesCustomInserter = 1;
86 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
87 Enc64 <outs, ins, asm, pattern> {
102 let Inst{11-8} = DMASK;
103 let Inst{12} = UNORM;
109 let Inst{24-18} = op;
111 let Inst{31-26} = 0x3c;
112 let Inst{39-32} = VADDR;
113 let Inst{47-40} = VDATA;
114 let Inst{52-48} = SRSRC;
115 let Inst{57-53} = SSAMP;
117 let EncodingType = 2; //SIInstrEncodingType::MIMG
121 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
122 Enc64<outs, ins, asm, pattern> {
138 let Inst{11-0} = OFFSET;
139 let Inst{12} = OFFEN;
140 let Inst{13} = IDXEN;
142 let Inst{15} = ADDR64;
143 let Inst{18-16} = op;
144 let Inst{22-19} = DFMT;
145 let Inst{25-23} = NFMT;
146 let Inst{31-26} = 0x3a; //encoding
147 let Inst{39-32} = VADDR;
148 let Inst{47-40} = VDATA;
149 let Inst{52-48} = SRSRC;
152 let Inst{63-56} = SOFFSET;
153 let EncodingType = 3; //SIInstrEncodingType::MTBUF
156 let usesCustomInserter = 1;
157 let neverHasSideEffects = 1;
160 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
161 Enc64<outs, ins, asm, pattern> {
176 let Inst{11-0} = OFFSET;
177 let Inst{12} = OFFEN;
178 let Inst{13} = IDXEN;
180 let Inst{15} = ADDR64;
182 let Inst{24-18} = op;
183 let Inst{31-26} = 0x38; //encoding
184 let Inst{39-32} = VADDR;
185 let Inst{47-40} = VDATA;
186 let Inst{52-48} = SRSRC;
189 let Inst{63-56} = SOFFSET;
190 let EncodingType = 4; //SIInstrEncodingType::MUBUF
193 let usesCustomInserter = 1;
194 let neverHasSideEffects = 1;
197 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
198 Enc32<outs, ins, asm, pattern> {
203 bits<1> IMM = 0; // Determined by subclasses
205 let Inst{7-0} = OFFSET;
207 let Inst{14-9} = SBASE;
208 let Inst{21-15} = SDST;
209 let Inst{26-22} = op;
210 let Inst{31-27} = 0x18; //encoding
211 let EncodingType = 5; //SIInstrEncodingType::SMRD
214 let usesCustomInserter = 1;
217 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
218 Enc32<outs, ins, asm, pattern> {
223 let Inst{7-0} = SSRC0;
225 let Inst{22-16} = SDST;
226 let Inst{31-23} = 0x17d; //encoding;
227 let EncodingType = 6; //SIInstrEncodingType::SOP1
230 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
231 Enc32 <outs, ins, asm, pattern> {
237 let Inst{7-0} = SSRC0;
238 let Inst{15-8} = SSRC1;
239 let Inst{22-16} = SDST;
240 let Inst{29-23} = op;
241 let Inst{31-30} = 0x2; // encoding
242 let EncodingType = 7; // SIInstrEncodingType::SOP2
245 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
246 Enc32<outs, ins, asm, pattern> {
251 let Inst{7-0} = SSRC0;
252 let Inst{15-8} = SSRC1;
253 let Inst{22-16} = op;
254 let Inst{31-23} = 0x17e;
255 let EncodingType = 8; // SIInstrEncodingType::SOPC
258 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
259 Enc32 <outs, ins , asm, pattern> {
264 let Inst{15-0} = SIMM16;
265 let Inst{22-16} = SDST;
266 let Inst{27-23} = op;
267 let Inst{31-28} = 0xb; //encoding
268 let EncodingType = 9; // SIInstrEncodingType::SOPK
271 class SOPP <bits<7> op, dag ins, string asm> : Enc32 <
279 let Inst{15-0} = SIMM16;
280 let Inst{22-16} = op;
281 let Inst{31-23} = 0x17f; // encoding
282 let EncodingType = 10; // SIInstrEncodingType::SOPP
286 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
287 Enc32 <outs, ins, asm, pattern> {
294 let Inst{7-0} = VSRC;
295 let Inst{9-8} = ATTRCHAN;
296 let Inst{15-10} = ATTR;
297 let Inst{17-16} = op;
298 let Inst{25-18} = VDST;
299 let Inst{31-26} = 0x32; // encoding
300 let EncodingType = 11; // SIInstrEncodingType::VINTRP
305 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
306 Enc32 <outs, ins, asm, pattern> {
311 let Inst{8-0} = SRC0;
313 let Inst{24-17} = VDST;
314 let Inst{31-25} = 0x3f; //encoding
316 let EncodingType = 12; // SIInstrEncodingType::VOP1
317 let PostEncoderMethod = "VOPPostEncode";
320 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
321 Enc32 <outs, ins, asm, pattern> {
327 let Inst{8-0} = SRC0;
328 let Inst{16-9} = VSRC1;
329 let Inst{24-17} = VDST;
330 let Inst{30-25} = op;
331 let Inst{31} = 0x0; //encoding
333 let EncodingType = 13; // SIInstrEncodingType::VOP2
334 let PostEncoderMethod = "VOPPostEncode";
337 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
338 Enc64 <outs, ins, asm, pattern> {
349 let Inst{7-0} = VDST;
350 let Inst{10-8} = ABS;
351 let Inst{11} = CLAMP;
352 let Inst{25-17} = op;
353 let Inst{31-26} = 0x34; //encoding
354 let Inst{40-32} = SRC0;
355 let Inst{49-41} = SRC1;
356 let Inst{58-50} = SRC2;
357 let Inst{60-59} = OMOD;
358 let Inst{63-61} = NEG;
360 let EncodingType = 14; // SIInstrEncodingType::VOP3
361 let PostEncoderMethod = "VOPPostEncode";
364 class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
365 Enc32 <outs, ins, asm, pattern> {
370 let Inst{8-0} = SRC0;
371 let Inst{16-9} = VSRC1;
372 let Inst{24-17} = op;
373 let Inst{31-25} = 0x3e;
375 let EncodingType = 15; //SIInstrEncodingType::VOPC
376 let PostEncoderMethod = "VOPPostEncode";
381 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
383 (outs VReg_128:$vdata),
384 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
385 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
386 GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
391 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
393 (outs regClass:$dst),
394 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
395 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
396 i1imm:$tfe, SReg_32:$soffset),
402 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
404 (outs regClass:$dst),
405 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
406 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
407 i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
413 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
416 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
417 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
418 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
424 /*XXX: We should be able to infer the imm bit based on the arg types */
425 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
429 (outs dstClass:$dst),
430 (ins SReg_32:$offset, GPR2Align<SReg_64,i64>:$sbase),
439 (outs dstClass:$dst),
440 (ins i32imm:$offset, GPR2Align<SReg_64,i64>:$sbase),
448 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
449 let EncoderMethod = "encodeOperand";
450 let MIOperandInfo = opInfo;
453 def IMM8bit : ImmLeaf <
455 [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
458 def IMM12bit : ImmLeaf <
460 [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
463 include "SIInstrFormats.td"
465 def LOAD_CONST : AMDGPUShaderInst <
468 "LOAD_CONST $dst, $src",
469 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
472 include "SIInstructions.td"