src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "util/u_vbuf.h"
  38 #include "r600.h"
  39 #include "radeonsi_public.h"
  40 #include "r600_resource.h"
  41
  42 #define R600_MAX_CONST_BUFFERS 1
  43 #define R600_MAX_CONST_BUFFER_SIZE 4096
  44
  45 #ifdef PIPE_ARCH_BIG_ENDIAN
  46 #define R600_BIG_ENDIAN 1
  47 #else
  48 #define R600_BIG_ENDIAN 0
  49 #endif
  50
  51 enum r600_atom_flags {
  52         /* When set, atoms are added at the beginning of the dirty list
  53          * instead of the end. */
  54         EMIT_EARLY = (1 << 0)
  55 };
  56
  57 /* This encapsulates a state or an operation which can emitted into the GPU
  58  * command stream. It's not limited to states only, it can be used for anything
  59  * that wants to write commands into the CS (e.g. cache flushes). */
  60 struct r600_atom {
  61         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  62
  63         unsigned                num_dw;
  64         enum r600_atom_flags    flags;
  65         bool                    dirty;
  66
  67         struct list_head        head;
  68 };
  69
  70 struct r600_atom_surface_sync {
  71         struct r600_atom atom;
  72         unsigned flush_flags; /* CP_COHER_CNTL */
  73 };
  74
  75 enum r600_pipe_state_id {
  76         R600_PIPE_STATE_BLEND = 0,
  77         R600_PIPE_STATE_BLEND_COLOR,
  78         R600_PIPE_STATE_CONFIG,
  79         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  80         R600_PIPE_STATE_CLIP,
  81         R600_PIPE_STATE_SCISSOR,
  82         R600_PIPE_STATE_VIEWPORT,
  83         R600_PIPE_STATE_RASTERIZER,
  84         R600_PIPE_STATE_VGT,
  85         R600_PIPE_STATE_FRAMEBUFFER,
  86         R600_PIPE_STATE_DSA,
  87         R600_PIPE_STATE_STENCIL_REF,
  88         R600_PIPE_STATE_PS_SHADER,
  89         R600_PIPE_STATE_VS_SHADER,
  90         R600_PIPE_STATE_CONSTANT,
  91         R600_PIPE_STATE_SAMPLER,
  92         R600_PIPE_STATE_RESOURCE,
  93         R600_PIPE_STATE_POLYGON_OFFSET,
  94         R600_PIPE_NSTATES
  95 };
  96
  97 struct r600_pipe_fences {
  98         struct r600_resource            *bo;
  99         unsigned                        *data;
 100         unsigned                        next_index;
 101         /* linked list of preallocated blocks */
 102         struct list_head                blocks;
 103         /* linked list of freed fences */
 104         struct list_head                pool;
 105         pipe_mutex                      mutex;
 106 };
 107
 108 struct r600_screen {
 109         struct pipe_screen              screen;
 110         struct radeon_winsys            *ws;
 111         unsigned                        family;
 112         enum chip_class                 chip_class;
 113         struct radeon_info              info;
 114         struct r600_tiling_info         tiling_info;
 115         struct util_slab_mempool        pool_buffers;
 116         struct r600_pipe_fences         fences;
 117
 118         unsigned                        num_contexts;
 119
 120         /* for thread-safe write accessing to num_contexts */
 121         pipe_mutex                      mutex_num_contexts;
 122 };
 123
 124 struct si_pipe_sampler_view {
 125         struct pipe_sampler_view        base;
 126         uint32_t                        state[8];
 127 };
 128
 129 struct si_pipe_sampler_state {
 130         uint32_t                        val[4];
 131 };
 132
 133 struct r600_pipe_rasterizer {
 134         struct r600_pipe_state          rstate;
 135         boolean                         flatshade;
 136         unsigned                        sprite_coord_enable;
 137         unsigned                        pa_sc_line_stipple;
 138         unsigned                        pa_su_sc_mode_cntl;
 139         unsigned                        pa_cl_clip_cntl;
 140         unsigned                        pa_cl_vs_out_cntl;
 141         float                           offset_units;
 142         float                           offset_scale;
 143 };
 144
 145 struct r600_pipe_blend {
 146         struct r600_pipe_state          rstate;
 147         unsigned                        cb_target_mask;
 148         unsigned                        cb_color_control;
 149 };
 150
 151 struct r600_pipe_dsa {
 152         struct r600_pipe_state          rstate;
 153         unsigned                        alpha_ref;
 154         unsigned                        db_render_override;
 155         unsigned                        db_render_control;
 156         ubyte                           valuemask[2];
 157         ubyte                           writemask[2];
 158 };
 159
 160 struct r600_vertex_element
 161 {
 162         unsigned                        count;
 163         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 164         struct u_vbuf_elements          *vmgr_elements;
 165         unsigned                        fs_size;
 166         struct r600_pipe_state          rstate;
 167         /* if offset is to big for fetch instructio we need to alterate
 168          * offset of vertex buffer, record here the offset need to add
 169          */
 170         unsigned                        vbuffer_need_offset;
 171         unsigned                        vbuffer_offset[PIPE_MAX_ATTRIBS];
 172 };
 173
 174 struct r600_shader_io {
 175         unsigned                name;
 176         unsigned                gpr;
 177         unsigned                done;
 178         int                     sid;
 179         unsigned                interpolate;
 180         boolean                 centroid;
 181         unsigned                lds_pos; /* for evergreen */
 182 };
 183
 184 struct r600_shader {
 185         unsigned                ninput;
 186         unsigned                noutput;
 187         struct r600_shader_io   input[32];
 188         struct r600_shader_io   output[32];
 189         boolean                 uses_kill;
 190         boolean                 fs_write_all;
 191         unsigned                nr_cbufs;
 192 };
 193
 194 struct si_pipe_shader {
 195         struct r600_shader              shader;
 196         struct r600_pipe_state          rstate;
 197         struct r600_resource            *bo;
 198         struct r600_vertex_element      vertex_elements;
 199         struct tgsi_token               *tokens;
 200         unsigned                        num_sgprs;
 201         unsigned                        num_vgprs;
 202         unsigned                        spi_ps_input_ena;
 203         unsigned        sprite_coord_enable;
 204         struct pipe_stream_output_info  so;
 205         unsigned                        so_strides[4];
 206 };
 207
 208 /* needed for blitter save */
 209 #define NUM_TEX_UNITS 16
 210
 211 struct r600_textures_info {
 212         struct r600_pipe_state          rstate;
 213         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 214         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 215         unsigned                        n_views;
 216         unsigned                        n_samplers;
 217         bool                            samplers_dirty;
 218         bool                            is_array_sampler[NUM_TEX_UNITS];
 219 };
 220
 221 struct r600_fence {
 222         struct pipe_reference           reference;
 223         unsigned                        index; /* in the shared bo */
 224         struct r600_resource            *sleep_bo;
 225         struct list_head                head;
 226 };
 227
 228 #define FENCE_BLOCK_SIZE 16
 229
 230 struct r600_fence_block {
 231         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 232         struct list_head                head;
 233 };
 234
 235 #define R600_CONSTANT_ARRAY_SIZE 256
 236 #define R600_RESOURCE_ARRAY_SIZE 160
 237
 238 struct r600_stencil_ref
 239 {
 240         ubyte ref_value[2];
 241         ubyte valuemask[2];
 242         ubyte writemask[2];
 243 };
 244
 245 struct r600_context {
 246         struct pipe_context             context;
 247         struct blitter_context          *blitter;
 248         enum radeon_family              family;
 249         enum chip_class                 chip_class;
 250         void                            *custom_dsa_flush;
 251         struct r600_screen              *screen;
 252         struct radeon_winsys            *ws;
 253         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 254         struct r600_vertex_element      *vertex_elements;
 255         struct pipe_framebuffer_state   framebuffer;
 256         unsigned                        cb_target_mask;
 257         unsigned                        cb_color_control;
 258         unsigned                        pa_sc_line_stipple;
 259         unsigned                        pa_su_sc_mode_cntl;
 260         unsigned                        pa_cl_clip_cntl;
 261         unsigned                        pa_cl_vs_out_cntl;
 262         /* for saving when using blitter */
 263         struct pipe_stencil_ref         stencil_ref;
 264         struct pipe_viewport_state      viewport;
 265         struct pipe_clip_state          clip;
 266         struct r600_pipe_state          config;
 267         struct si_pipe_shader   *ps_shader;
 268         struct si_pipe_shader   *vs_shader;
 269         struct r600_pipe_state          vs_const_buffer;
 270         struct r600_pipe_state          vs_user_data;
 271         struct r600_pipe_state          ps_const_buffer;
 272         struct r600_pipe_rasterizer     *rasterizer;
 273         struct r600_pipe_state          vgt;
 274         struct r600_pipe_state          spi;
 275         struct pipe_query               *current_render_cond;
 276         unsigned                        current_render_cond_mode;
 277         struct pipe_query               *saved_render_cond;
 278         unsigned                        saved_render_cond_mode;
 279         /* shader information */
 280         unsigned                        sprite_coord_enable;
 281         boolean                         export_16bpc;
 282         unsigned                        alpha_ref;
 283         boolean                         alpha_ref_dirty;
 284         unsigned                        nr_cbufs;
 285         struct r600_textures_info       vs_samplers;
 286         struct r600_textures_info       ps_samplers;
 287         boolean                         shader_dirty;
 288
 289         struct u_vbuf                   *vbuf_mgr;
 290         struct util_slab_mempool        pool_transfers;
 291         boolean                         have_depth_texture, have_depth_fb;
 292
 293         unsigned default_ps_gprs, default_vs_gprs;
 294
 295         /* States based on r600_state. */
 296         struct list_head                dirty_states;
 297         struct r600_atom_surface_sync   atom_surface_sync;
 298         struct r600_atom                atom_r6xx_flush_and_inv;
 299
 300         /* Below are variables from the old r600_context.
 301          */
 302         struct radeon_winsys_cs *cs;
 303
 304         struct r600_range       *range;
 305         unsigned                nblocks;
 306         struct r600_block       **blocks;
 307         struct list_head        dirty;
 308         struct list_head        enable_list;
 309         unsigned                pm4_dirty_cdwords;
 310         unsigned                ctx_pm4_ndwords;
 311         unsigned                init_dwords;
 312
 313         /* The list of active queries. Only one query of each type can be active. */
 314         struct list_head        active_query_list;
 315         unsigned                num_cs_dw_queries_suspend;
 316         unsigned                num_cs_dw_streamout_end;
 317
 318         unsigned                backend_mask;
 319         unsigned                max_db; /* for OQ */
 320         unsigned                flags;
 321         boolean                 predicate_drawing;
 322
 323         unsigned                num_so_targets;
 324         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 325         boolean                 streamout_start;
 326         unsigned                streamout_append_bitmask;
 327         unsigned                *vs_so_stride_in_dw;
 328         unsigned                *vs_shader_so_strides;
 329 };
 330
 331 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 332 {
 333         atom->emit(rctx, atom);
 334         atom->dirty = false;
 335         if (atom->head.next && atom->head.prev)
 336                 LIST_DELINIT(&atom->head);
 337 }
 338
 339 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 340 {
 341         if (!state->dirty) {
 342                 if (state->flags & EMIT_EARLY) {
 343                         LIST_ADD(&state->head, &rctx->dirty_states);
 344                 } else {
 345                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 346                 }
 347                 state->dirty = true;
 348         }
 349 }
 350
 351 /* evergreen_state.c */
 352 void cayman_init_state_functions(struct r600_context *rctx);
 353 void si_init_config(struct r600_context *rctx);
 354 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
 355 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
 356 void si_update_spi_map(struct r600_context *rctx);
 357 void *cayman_create_db_flush_dsa(struct r600_context *rctx);
 358 void cayman_polygon_offset_update(struct r600_context *rctx);
 359 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
 360                                    enum pipe_format format,
 361                                    const struct util_format_description *desc,
 362                                    int first_non_void);
 363 boolean si_is_format_supported(struct pipe_screen *screen,
 364                                enum pipe_format format,
 365                                enum pipe_texture_target target,
 366                                unsigned sample_count,
 367                                unsigned usage);
 368
 369 /* r600_blit.c */
 370 void r600_init_blit_functions(struct r600_context *rctx);
 371 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 372 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 373 void r600_flush_depth_textures(struct r600_context *rctx);
 374
 375 /* r600_buffer.c */
 376 bool r600_init_resource(struct r600_screen *rscreen,
 377                         struct r600_resource *res,
 378                         unsigned size, unsigned alignment,
 379                         unsigned bind, unsigned usage);
 380 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 381                                          const struct pipe_resource *templ);
 382 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 383                                               void *ptr, unsigned bytes,
 384                                               unsigned bind);
 385 void r600_upload_index_buffer(struct r600_context *rctx,
 386                               struct pipe_index_buffer *ib, unsigned count);
 387
 388
 389 /* r600_pipe.c */
 390 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 391                     unsigned flags);
 392
 393 /* r600_query.c */
 394 void r600_init_query_functions(struct r600_context *rctx);
 395
 396 /* r600_resource.c */
 397 void r600_init_context_resource_functions(struct r600_context *r600);
 398
 399 /* radeonsi_shader.c */
 400 int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
 401 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
 402
 403 /* r600_texture.c */
 404 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 405 void r600_init_surface_functions(struct r600_context *r600);
 406 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 407                                         unsigned level, unsigned layer);
 408
 409 /* r600_translate.c */
 410 void r600_translate_index_buffer(struct r600_context *r600,
 411                                  struct pipe_index_buffer *ib,
 412                                  unsigned count);
 413
 414 /* r600_state_common.c */
 415 void r600_init_common_atoms(struct r600_context *rctx);
 416 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 417 void r600_texture_barrier(struct pipe_context *ctx);
 418 void r600_set_index_buffer(struct pipe_context *ctx,
 419                            const struct pipe_index_buffer *ib);
 420 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 421                              const struct pipe_vertex_buffer *buffers);
 422 void *si_create_vertex_elements(struct pipe_context *ctx,
 423                                 unsigned count,
 424                                 const struct pipe_vertex_element *elements);
 425 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 426 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 427 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 428 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 429 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 430 void r600_sampler_view_destroy(struct pipe_context *ctx,
 431                                struct pipe_sampler_view *state);
 432 void r600_delete_state(struct pipe_context *ctx, void *state);
 433 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 434 void *si_create_shader_state(struct pipe_context *ctx,
 435                              const struct pipe_shader_state *state);
 436 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 437 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 438 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 439 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 440 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 441                               struct pipe_resource *buffer);
 442 struct pipe_stream_output_target *
 443 r600_create_so_target(struct pipe_context *ctx,
 444                       struct pipe_resource *buffer,
 445                       unsigned buffer_offset,
 446                       unsigned buffer_size);
 447 void r600_so_target_destroy(struct pipe_context *ctx,
 448                             struct pipe_stream_output_target *target);
 449 void r600_set_so_targets(struct pipe_context *ctx,
 450                          unsigned num_targets,
 451                          struct pipe_stream_output_target **targets,
 452                          unsigned append_bitmask);
 453 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 454                                const struct pipe_stencil_ref *state);
 455 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 456
 457 /*
 458  * common helpers
 459  */
 460 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 461 {
 462         return value * (1 << frac_bits);
 463 }
 464 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 465
 466 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 467 {
 468         if (filter <= 1)   return 0;
 469         if (filter <= 2)   return 1;
 470         if (filter <= 4)   return 2;
 471         if (filter <= 8)   return 3;
 472          /* else */        return 4;
 473 }
 474
 475 /* 12.4 fixed-point */
 476 static INLINE unsigned r600_pack_float_12p4(float x)
 477 {
 478         return x <= 0    ? 0 :
 479                x >= 4096 ? 0xffff : x * 16;
 480 }
 481
 482 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 483 {
 484         struct r600_screen *rscreen = (struct r600_screen*)screen;
 485         struct r600_resource *rresource = (struct r600_resource*)resource;
 486
 487         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 488 }
 489
 490 #endif