2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
60 #include "si_shader.h"
63 #include "util/u_math.h"
64 #include "util/u_memory.h"
65 #include "util/u_suballoc.h"
66 #include "util/u_upload_mgr.h"
69 /* NULL image and buffer descriptor for textures (alpha = 1) and images
72 * For images, all fields must be zero except for the swizzle, which
73 * supports arbitrary combinations of 0s and 1s. The texture type must be
74 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 * This is the only reason why the buffer descriptor must be in words [4:7].
80 static uint32_t null_texture_descriptor[8] = {
84 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
85 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
86 /* the rest must contain zeros, which is also used by the buffer
90 static uint32_t null_image_descriptor[8] = {
94 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
95 /* the rest must contain zeros, which is also used by the buffer
99 static void si_init_descriptors(struct si_descriptors *desc,
100 unsigned shader_userdata_index,
101 unsigned element_dw_size,
102 unsigned num_elements,
103 const uint32_t *null_descriptor,
108 assert(num_elements <= sizeof(desc->enabled_mask)*8);
110 desc->list = CALLOC(num_elements, element_dw_size * 4);
111 desc->element_dw_size = element_dw_size;
112 desc->num_elements = num_elements;
113 desc->dirty_mask = num_elements == 64 ? ~0llu : (1llu << num_elements) - 1;
114 desc->shader_userdata_offset = shader_userdata_index * 4;
117 desc->ce_offset = *ce_offset;
119 /* make sure that ce_offset stays 32 byte aligned */
120 *ce_offset += align(element_dw_size * num_elements * 4, 32);
123 /* Initialize the array to NULL descriptors if the element size is 8. */
124 if (null_descriptor) {
125 assert(element_dw_size % 8 == 0);
126 for (i = 0; i < num_elements * element_dw_size / 8; i++)
127 memcpy(desc->list + i * 8, null_descriptor,
132 static void si_release_descriptors(struct si_descriptors *desc)
134 pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
138 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
139 unsigned *out_offset, struct r600_resource **out_buf) {
142 u_suballocator_alloc(sctx->ce_suballocator, size, out_offset,
143 (struct pipe_resource**)out_buf);
147 va = (*out_buf)->gpu_address + *out_offset;
149 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
150 radeon_emit(sctx->ce_ib, ce_offset);
151 radeon_emit(sctx->ce_ib, size / 4);
152 radeon_emit(sctx->ce_ib, va);
153 radeon_emit(sctx->ce_ib, va >> 32);
155 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
156 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158 sctx->ce_need_synchronization = true;
162 static void si_reinitialize_ce_ram(struct si_context *sctx,
163 struct si_descriptors *desc)
166 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
167 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
168 uint64_t va = buffer->gpu_address + desc->buffer_offset;
169 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
174 list_size = align(list_size, 32);
176 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va >> 32);
179 radeon_emit(ib, list_size / 4);
180 radeon_emit(ib, desc->ce_offset);
182 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
183 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 desc->ce_ram_dirty = false;
188 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
190 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
191 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
192 CONTEXT_CONTROL_LOAD_CE_RAM(1));
193 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
196 static bool si_upload_descriptors(struct si_context *sctx,
197 struct si_descriptors *desc,
198 struct r600_atom * atom)
200 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
202 if (!desc->dirty_mask)
206 uint32_t const* list = (uint32_t const*)desc->list;
208 if (desc->ce_ram_dirty)
209 si_reinitialize_ce_ram(sctx, desc);
211 while(desc->dirty_mask) {
213 u_bit_scan_consecutive_range64(&desc->dirty_mask, &begin,
216 begin *= desc->element_dw_size;
217 count *= desc->element_dw_size;
219 radeon_emit(sctx->ce_ib,
220 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
221 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
222 radeon_emit_array(sctx->ce_ib, list + begin, count);
225 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
226 &desc->buffer_offset, &desc->buffer))
231 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
232 &desc->buffer_offset,
233 (struct pipe_resource**)&desc->buffer, &ptr);
235 return false; /* skip the draw call */
237 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
239 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
240 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
242 desc->pointer_dirty = true;
243 desc->dirty_mask = 0;
246 si_mark_atom_dirty(sctx, atom);
253 static void si_release_sampler_views(struct si_sampler_views *views)
257 for (i = 0; i < Elements(views->views); i++) {
258 pipe_sampler_view_reference(&views->views[i], NULL);
260 si_release_descriptors(&views->desc);
263 static void si_sampler_view_add_buffer(struct si_context *sctx,
264 struct pipe_resource *resource)
266 struct r600_resource *rres = (struct r600_resource*)resource;
271 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rres,
273 r600_get_sampler_view_priority(rres));
276 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
277 struct si_sampler_views *views)
279 uint64_t mask = views->desc.enabled_mask;
281 /* Add buffers to the CS. */
283 int i = u_bit_scan64(&mask);
285 si_sampler_view_add_buffer(sctx, views->views[i]->texture);
288 views->desc.ce_ram_dirty = true;
290 if (!views->desc.buffer)
292 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, views->desc.buffer,
293 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
296 static void si_set_sampler_view(struct si_context *sctx,
297 struct si_sampler_views *views,
298 unsigned slot, struct pipe_sampler_view *view)
300 struct si_sampler_view *rview = (struct si_sampler_view*)view;
302 if (view && view->texture && view->texture->target != PIPE_BUFFER &&
303 G_008F28_COMPRESSION_EN(rview->state[6]) &&
304 ((struct r600_texture*)view->texture)->dcc_offset == 0) {
305 rview->state[6] &= C_008F28_COMPRESSION_EN &
306 C_008F28_ALPHA_IS_ON_MSB;
307 } else if (views->views[slot] == view)
311 struct r600_texture *rtex = (struct r600_texture *)view->texture;
313 si_sampler_view_add_buffer(sctx, view->texture);
315 pipe_sampler_view_reference(&views->views[slot], view);
316 memcpy(views->desc.list + slot * 16, rview->state, 8*4);
318 if (view->texture && view->texture->target != PIPE_BUFFER &&
320 memcpy(views->desc.list + slot*16 + 8,
321 rview->fmask_state, 8*4);
323 /* Disable FMASK and bind sampler state in [12:15]. */
324 memcpy(views->desc.list + slot*16 + 8,
325 null_texture_descriptor, 4*4);
327 if (views->sampler_states[slot])
328 memcpy(views->desc.list + slot*16 + 12,
329 views->sampler_states[slot], 4*4);
332 views->desc.enabled_mask |= 1llu << slot;
334 pipe_sampler_view_reference(&views->views[slot], NULL);
335 memcpy(views->desc.list + slot*16, null_texture_descriptor, 8*4);
336 /* Only clear the lower dwords of FMASK. */
337 memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 4*4);
338 views->desc.enabled_mask &= ~(1llu << slot);
341 views->desc.dirty_mask |= 1llu << slot;
344 static bool is_compressed_colortex(struct r600_texture *rtex)
346 return rtex->cmask.size || rtex->fmask.size ||
347 (rtex->dcc_offset && rtex->dirty_level_mask);
350 static void si_set_sampler_views(struct pipe_context *ctx,
351 unsigned shader, unsigned start,
353 struct pipe_sampler_view **views)
355 struct si_context *sctx = (struct si_context *)ctx;
356 struct si_textures_info *samplers = &sctx->samplers[shader];
359 if (!count || shader >= SI_NUM_SHADERS)
362 for (i = 0; i < count; i++) {
363 unsigned slot = start + i;
365 if (!views || !views[i]) {
366 samplers->depth_texture_mask &= ~(1llu << slot);
367 samplers->compressed_colortex_mask &= ~(1llu << slot);
368 si_set_sampler_view(sctx, &samplers->views, slot, NULL);
372 si_set_sampler_view(sctx, &samplers->views, slot, views[i]);
374 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
375 struct r600_texture *rtex =
376 (struct r600_texture*)views[i]->texture;
378 if (rtex->is_depth && !rtex->is_flushing_texture) {
379 samplers->depth_texture_mask |= 1llu << slot;
381 samplers->depth_texture_mask &= ~(1llu << slot);
383 if (is_compressed_colortex(rtex)) {
384 samplers->compressed_colortex_mask |= 1llu << slot;
386 samplers->compressed_colortex_mask &= ~(1llu << slot);
389 samplers->depth_texture_mask &= ~(1llu << slot);
390 samplers->compressed_colortex_mask &= ~(1llu << slot);
396 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
398 uint64_t mask = samplers->views.desc.enabled_mask;
401 int i = u_bit_scan64(&mask);
402 struct pipe_resource *res = samplers->views.views[i]->texture;
404 if (res && res->target != PIPE_BUFFER) {
405 struct r600_texture *rtex = (struct r600_texture *)res;
407 if (is_compressed_colortex(rtex)) {
408 samplers->compressed_colortex_mask |= 1llu << i;
410 samplers->compressed_colortex_mask &= ~(1llu << i);
419 si_release_image_views(struct si_images_info *images)
423 for (i = 0; i < SI_NUM_IMAGES; ++i) {
424 struct pipe_image_view *view = &images->views[i];
426 pipe_resource_reference(&view->resource, NULL);
429 si_release_descriptors(&images->desc);
433 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
435 uint mask = images->desc.enabled_mask;
437 /* Add buffers to the CS. */
439 int i = u_bit_scan(&mask);
440 struct pipe_image_view *view = &images->views[i];
442 assert(view->resource);
444 si_sampler_view_add_buffer(sctx, view->resource);
447 images->desc.ce_ram_dirty = true;
449 if (images->desc.buffer) {
450 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
453 RADEON_PRIO_DESCRIPTORS);
458 si_disable_shader_image(struct si_images_info *images, unsigned slot)
460 if (images->desc.enabled_mask & (1llu << slot)) {
461 pipe_resource_reference(&images->views[slot].resource, NULL);
462 images->compressed_colortex_mask &= ~(1 << slot);
464 memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
465 images->desc.enabled_mask &= ~(1llu << slot);
466 images->desc.dirty_mask |= 1llu << slot;
471 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
472 unsigned start_slot, unsigned count,
473 struct pipe_image_view *views)
475 struct si_context *ctx = (struct si_context *)pipe;
476 struct si_screen *screen = ctx->screen;
477 struct si_images_info *images = &ctx->images[shader];
480 assert(shader < SI_NUM_SHADERS);
485 assert(start_slot + count <= SI_NUM_IMAGES);
487 for (i = 0, slot = start_slot; i < count; ++i, ++slot) {
488 struct r600_resource *res;
490 if (!views || !views[i].resource) {
491 si_disable_shader_image(images, slot);
495 res = (struct r600_resource *)views[i].resource;
496 util_copy_image_view(&images->views[slot], &views[i]);
498 si_sampler_view_add_buffer(ctx, &res->b.b);
500 if (res->b.b.target == PIPE_BUFFER) {
501 si_make_buffer_descriptor(screen, res,
503 views[i].u.buf.first_element,
504 views[i].u.buf.last_element,
505 images->desc.list + slot * 8);
506 images->compressed_colortex_mask &= ~(1 << slot);
508 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
509 struct r600_texture *tex = (struct r600_texture *)res;
511 unsigned width, height, depth;
513 assert(!tex->is_depth);
514 assert(tex->fmask.size == 0);
516 if (tex->dcc_offset &&
517 views[i].access & PIPE_IMAGE_ACCESS_WRITE)
518 r600_texture_disable_dcc(&screen->b, tex);
520 if (is_compressed_colortex(tex)) {
521 images->compressed_colortex_mask |= 1 << slot;
523 images->compressed_colortex_mask &= ~(1 << slot);
526 /* Always force the base level to the selected level.
528 * This is required for 3D textures, where otherwise
529 * selecting a single slice for non-layered bindings
530 * fails. It doesn't hurt the other targets.
532 level = views[i].u.tex.level;
533 width = u_minify(res->b.b.width0, level);
534 height = u_minify(res->b.b.height0, level);
535 depth = u_minify(res->b.b.depth0, level);
537 si_make_texture_descriptor(screen, tex, false, res->b.b.target,
538 views[i].format, swizzle,
540 views[i].u.tex.first_layer, views[i].u.tex.last_layer,
541 width, height, depth,
542 images->desc.list + slot * 8,
546 images->desc.enabled_mask |= 1llu << slot;
547 images->desc.dirty_mask |= 1llu << slot;
552 si_images_update_compressed_colortex_mask(struct si_images_info *images)
554 uint64_t mask = images->desc.enabled_mask;
557 int i = u_bit_scan64(&mask);
558 struct pipe_resource *res = images->views[i].resource;
560 if (res && res->target != PIPE_BUFFER) {
561 struct r600_texture *rtex = (struct r600_texture *)res;
563 if (is_compressed_colortex(rtex)) {
564 images->compressed_colortex_mask |= 1 << i;
566 images->compressed_colortex_mask &= ~(1 << i);
574 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
575 unsigned start, unsigned count, void **states)
577 struct si_context *sctx = (struct si_context *)ctx;
578 struct si_textures_info *samplers = &sctx->samplers[shader];
579 struct si_descriptors *desc = &samplers->views.desc;
580 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
583 if (!count || shader >= SI_NUM_SHADERS)
586 for (i = 0; i < count; i++) {
587 unsigned slot = start + i;
590 sstates[i] == samplers->views.sampler_states[slot])
593 samplers->views.sampler_states[slot] = sstates[i];
595 /* If FMASK is bound, don't overwrite it.
596 * The sampler state will be set after FMASK is unbound.
598 if (samplers->views.views[i] &&
599 samplers->views.views[i]->texture &&
600 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
601 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
604 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
605 desc->dirty_mask |= 1llu << slot;
609 /* BUFFER RESOURCES */
611 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
612 unsigned num_buffers,
613 unsigned shader_userdata_index,
614 enum radeon_bo_usage shader_usage,
615 enum radeon_bo_priority priority,
618 buffers->shader_usage = shader_usage;
619 buffers->priority = priority;
620 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
622 si_init_descriptors(&buffers->desc, shader_userdata_index, 4,
623 num_buffers, NULL, ce_offset);
626 static void si_release_buffer_resources(struct si_buffer_resources *buffers)
630 for (i = 0; i < buffers->desc.num_elements; i++) {
631 pipe_resource_reference(&buffers->buffers[i], NULL);
634 FREE(buffers->buffers);
635 si_release_descriptors(&buffers->desc);
638 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
639 struct si_buffer_resources *buffers)
641 uint64_t mask = buffers->desc.enabled_mask;
643 /* Add buffers to the CS. */
645 int i = u_bit_scan64(&mask);
647 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
648 (struct r600_resource*)buffers->buffers[i],
649 buffers->shader_usage, buffers->priority);
652 buffers->desc.ce_ram_dirty = true;
654 if (!buffers->desc.buffer)
656 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
657 buffers->desc.buffer, RADEON_USAGE_READWRITE,
658 RADEON_PRIO_DESCRIPTORS);
663 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
665 struct si_descriptors *desc = &sctx->vertex_buffers;
666 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
669 for (i = 0; i < count; i++) {
670 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
672 if (vb >= Elements(sctx->vertex_buffer))
674 if (!sctx->vertex_buffer[vb].buffer)
677 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
678 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
679 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
684 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
685 desc->buffer, RADEON_USAGE_READ,
686 RADEON_PRIO_DESCRIPTORS);
689 static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
691 struct si_descriptors *desc = &sctx->vertex_buffers;
692 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
693 unsigned i, count = sctx->vertex_elements->count;
697 if (!sctx->vertex_buffers_dirty)
699 if (!count || !sctx->vertex_elements)
702 /* Vertex buffer descriptors are the only ones which are uploaded
703 * directly through a staging buffer and don't go through
704 * the fine-grained upload path.
706 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
707 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
711 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
712 desc->buffer, RADEON_USAGE_READ,
713 RADEON_PRIO_DESCRIPTORS);
715 assert(count <= SI_NUM_VERTEX_BUFFERS);
717 for (i = 0; i < count; i++) {
718 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
719 struct pipe_vertex_buffer *vb;
720 struct r600_resource *rbuffer;
722 uint32_t *desc = &ptr[i*4];
724 if (ve->vertex_buffer_index >= Elements(sctx->vertex_buffer)) {
729 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
730 rbuffer = (struct r600_resource*)vb->buffer;
736 offset = vb->buffer_offset + ve->src_offset;
737 va = rbuffer->gpu_address + offset;
739 /* Fill in T# buffer resource description */
741 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
742 S_008F04_STRIDE(vb->stride);
744 if (sctx->b.chip_class <= CIK && vb->stride)
745 /* Round up by rounding down and adding 1 */
746 desc[2] = (vb->buffer->width0 - offset -
747 sctx->vertex_elements->format_size[i]) /
750 desc[2] = vb->buffer->width0 - offset;
752 desc[3] = sctx->vertex_elements->rsrc_word3[i];
754 if (!bound[ve->vertex_buffer_index]) {
755 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
756 (struct r600_resource*)vb->buffer,
757 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
758 bound[ve->vertex_buffer_index] = true;
762 /* Don't flush the const cache. It would have a very negative effect
763 * on performance (confirmed by testing). New descriptors are always
764 * uploaded to a fresh new buffer, so I don't think flushing the const
765 * cache is needed. */
766 desc->pointer_dirty = true;
767 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
768 sctx->vertex_buffers_dirty = false;
773 /* CONSTANT BUFFERS */
775 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
776 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
780 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
781 (struct pipe_resource**)rbuffer, &tmp);
783 util_memcpy_cpu_to_le32(tmp, ptr, size);
786 static void si_set_constant_buffer(struct si_context *sctx,
787 struct si_buffer_resources *buffers,
788 uint slot, struct pipe_constant_buffer *input)
790 assert(slot < buffers->desc.num_elements);
791 pipe_resource_reference(&buffers->buffers[slot], NULL);
793 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
794 * with a NULL buffer). We need to use a dummy buffer instead. */
795 if (sctx->b.chip_class == CIK &&
796 (!input || (!input->buffer && !input->user_buffer)))
797 input = &sctx->null_const_buf;
799 if (input && (input->buffer || input->user_buffer)) {
800 struct pipe_resource *buffer = NULL;
803 /* Upload the user buffer if needed. */
804 if (input->user_buffer) {
805 unsigned buffer_offset;
807 si_upload_const_buffer(sctx,
808 (struct r600_resource**)&buffer, input->user_buffer,
809 input->buffer_size, &buffer_offset);
811 /* Just unbind on failure. */
812 si_set_constant_buffer(sctx, buffers, slot, NULL);
815 va = r600_resource(buffer)->gpu_address + buffer_offset;
817 pipe_resource_reference(&buffer, input->buffer);
818 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
821 /* Set the descriptor. */
822 uint32_t *desc = buffers->desc.list + slot*4;
824 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
826 desc[2] = input->buffer_size;
827 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
828 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
829 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
830 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
831 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
832 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
834 buffers->buffers[slot] = buffer;
835 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
836 (struct r600_resource*)buffer,
837 buffers->shader_usage, buffers->priority);
838 buffers->desc.enabled_mask |= 1llu << slot;
840 /* Clear the descriptor. */
841 memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
842 buffers->desc.enabled_mask &= ~(1llu << slot);
845 buffers->desc.dirty_mask |= 1llu << slot;
848 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
849 uint shader, uint slot,
850 struct pipe_constant_buffer *input)
852 struct si_context *sctx = (struct si_context *)ctx;
854 if (shader >= SI_NUM_SHADERS)
857 si_set_constant_buffer(sctx, &sctx->const_buffers[shader], slot, input);
862 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
863 unsigned start_slot, unsigned count,
864 struct pipe_shader_buffer *sbuffers)
866 struct si_context *sctx = (struct si_context *)ctx;
867 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
870 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
872 for (i = 0; i < count; ++i) {
873 struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
874 struct r600_resource *buf;
875 unsigned slot = start_slot + i;
876 uint32_t *desc = buffers->desc.list + slot * 4;
879 if (!sbuffer || !sbuffer->buffer) {
880 pipe_resource_reference(&buffers->buffers[slot], NULL);
881 memset(desc, 0, sizeof(uint32_t) * 4);
882 buffers->desc.enabled_mask &= ~(1llu << slot);
886 buf = (struct r600_resource *)sbuffer->buffer;
887 va = buf->gpu_address + sbuffer->buffer_offset;
890 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
892 desc[2] = sbuffer->buffer_size;
893 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
894 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
895 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
896 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
897 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
898 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
900 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
901 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
902 buffers->shader_usage, buffers->priority);
903 buffers->desc.enabled_mask |= 1llu << slot;
904 buffers->desc.dirty_mask |= 1llu << slot;
911 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
912 struct pipe_resource *buffer,
913 unsigned stride, unsigned num_records,
914 bool add_tid, bool swizzle,
915 unsigned element_size, unsigned index_stride, uint64_t offset)
917 struct si_context *sctx = (struct si_context *)ctx;
918 struct si_buffer_resources *buffers = &sctx->rw_buffers;
920 if (shader >= SI_NUM_SHADERS)
923 /* The stride field in the resource descriptor has 14 bits */
924 assert(stride < (1 << 14));
926 assert(slot < buffers->desc.num_elements);
927 pipe_resource_reference(&buffers->buffers[slot], NULL);
932 va = r600_resource(buffer)->gpu_address + offset;
934 switch (element_size) {
936 assert(!"Unsupported ring buffer element size");
952 switch (index_stride) {
954 assert(!"Unsupported ring buffer index stride");
970 if (sctx->b.chip_class >= VI && stride)
971 num_records *= stride;
973 /* Set the descriptor. */
974 uint32_t *desc = buffers->desc.list + slot*4;
976 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
977 S_008F04_STRIDE(stride) |
978 S_008F04_SWIZZLE_ENABLE(swizzle);
979 desc[2] = num_records;
980 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
981 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
982 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
983 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
984 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
985 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
986 S_008F0C_ELEMENT_SIZE(element_size) |
987 S_008F0C_INDEX_STRIDE(index_stride) |
988 S_008F0C_ADD_TID_ENABLE(add_tid);
990 pipe_resource_reference(&buffers->buffers[slot], buffer);
991 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
992 (struct r600_resource*)buffer,
993 buffers->shader_usage, buffers->priority);
994 buffers->desc.enabled_mask |= 1llu << slot;
996 /* Clear the descriptor. */
997 memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
998 buffers->desc.enabled_mask &= ~(1llu << slot);
1001 buffers->desc.dirty_mask |= 1llu << slot;
1004 /* STREAMOUT BUFFERS */
1006 static void si_set_streamout_targets(struct pipe_context *ctx,
1007 unsigned num_targets,
1008 struct pipe_stream_output_target **targets,
1009 const unsigned *offsets)
1011 struct si_context *sctx = (struct si_context *)ctx;
1012 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1013 unsigned old_num_targets = sctx->b.streamout.num_targets;
1016 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1017 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1018 /* Since streamout uses vector writes which go through TC L2
1019 * and most other clients can use TC L2 as well, we don't need
1022 * The only case which requires flushing it is VGT DMA index
1023 * fetching, which is a rare case. Thus, flag the TC L2
1024 * dirtiness in the resource and handle it when index fetching
1027 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1028 if (sctx->b.streamout.targets[i])
1029 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1031 /* Invalidate the scalar cache in case a streamout buffer is
1032 * going to be used as a constant buffer.
1034 * Invalidate TC L1, because streamout bypasses it (done by
1035 * setting GLC=1 in the store instruction), but it can contain
1036 * outdated data of streamout buffers.
1038 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1039 * used as an input immediately.
1041 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1042 SI_CONTEXT_INV_VMEM_L1 |
1043 SI_CONTEXT_VS_PARTIAL_FLUSH;
1046 /* All readers of the streamout targets need to be finished before we can
1047 * start writing to the targets.
1050 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1051 SI_CONTEXT_CS_PARTIAL_FLUSH;
1053 /* Streamout buffers must be bound in 2 places:
1054 * 1) in VGT by setting the VGT_STRMOUT registers
1055 * 2) as shader resources
1058 /* Set the VGT regs. */
1059 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1061 /* Set the shader resources.*/
1062 for (i = 0; i < num_targets; i++) {
1063 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1066 struct pipe_resource *buffer = targets[i]->buffer;
1067 uint64_t va = r600_resource(buffer)->gpu_address;
1069 /* Set the descriptor.
1071 * On VI, the format must be non-INVALID, otherwise
1072 * the buffer will be considered not bound and store
1073 * instructions will be no-ops.
1075 uint32_t *desc = buffers->desc.list + bufidx*4;
1077 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1078 desc[2] = 0xffffffff;
1079 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1080 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1081 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1082 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1083 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1085 /* Set the resource. */
1086 pipe_resource_reference(&buffers->buffers[bufidx],
1088 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1089 (struct r600_resource*)buffer,
1090 buffers->shader_usage, buffers->priority);
1091 buffers->desc.enabled_mask |= 1llu << bufidx;
1093 /* Clear the descriptor and unset the resource. */
1094 memset(buffers->desc.list + bufidx*4, 0,
1095 sizeof(uint32_t) * 4);
1096 pipe_resource_reference(&buffers->buffers[bufidx],
1098 buffers->desc.enabled_mask &= ~(1llu << bufidx);
1100 buffers->desc.dirty_mask |= 1llu << bufidx;
1102 for (; i < old_num_targets; i++) {
1103 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1104 /* Clear the descriptor and unset the resource. */
1105 memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
1106 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1107 buffers->desc.enabled_mask &= ~(1llu << bufidx);
1108 buffers->desc.dirty_mask |= 1llu << bufidx;
1113 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1114 uint32_t *desc, uint64_t old_buf_va,
1115 struct pipe_resource *new_buf)
1117 /* Retrieve the buffer offset from the descriptor. */
1118 uint64_t old_desc_va =
1119 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1121 assert(old_buf_va <= old_desc_va);
1122 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1124 /* Update the descriptor. */
1125 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1128 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1129 S_008F04_BASE_ADDRESS_HI(va >> 32);
1132 /* TEXTURE METADATA ENABLE/DISABLE */
1134 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1135 * while the texture is bound, possibly by a different context. In that case,
1136 * call this function to update compressed_colortex_masks.
1138 void si_update_compressed_colortex_masks(struct si_context *sctx)
1140 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1141 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1142 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1146 /* BUFFER DISCARD/INVALIDATION */
1148 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1149 static void si_reset_buffer_resources(struct si_context *sctx,
1150 struct si_buffer_resources *buffers,
1151 struct pipe_resource *buf,
1154 uint64_t mask = buffers->desc.enabled_mask;
1157 unsigned i = u_bit_scan64(&mask);
1158 if (buffers->buffers[i] == buf) {
1159 si_desc_reset_buffer_offset(&sctx->b.b,
1160 buffers->desc.list + i*4,
1162 buffers->desc.dirty_mask |= 1llu << i;
1164 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1165 (struct r600_resource *)buf,
1166 buffers->shader_usage,
1172 /* Reallocate a buffer a update all resource bindings where the buffer is
1175 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1176 * idle by discarding its contents. Apps usually tell us when to do this using
1177 * map_buffer flags, for example.
1179 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1181 struct si_context *sctx = (struct si_context*)ctx;
1182 struct r600_resource *rbuffer = r600_resource(buf);
1183 unsigned i, shader, alignment = rbuffer->buf->alignment;
1184 uint64_t old_va = rbuffer->gpu_address;
1185 unsigned num_elems = sctx->vertex_elements ?
1186 sctx->vertex_elements->count : 0;
1187 struct si_sampler_view *view;
1189 /* Reallocate the buffer in the same pipe_resource. */
1190 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1193 /* We changed the buffer, now we need to bind it where the old one
1194 * was bound. This consists of 2 things:
1195 * 1) Updating the resource descriptor and dirtying it.
1196 * 2) Adding a relocation to the CS, so that it's usable.
1199 /* Vertex buffers. */
1200 for (i = 0; i < num_elems; i++) {
1201 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1203 if (vb >= Elements(sctx->vertex_buffer))
1205 if (!sctx->vertex_buffer[vb].buffer)
1208 if (sctx->vertex_buffer[vb].buffer == buf) {
1209 sctx->vertex_buffers_dirty = true;
1214 /* Streamout buffers. (other internal buffers can't be invalidated) */
1215 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1216 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1218 if (buffers->buffers[i] != buf)
1221 si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4,
1223 buffers->desc.dirty_mask |= 1u << i;
1225 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1226 rbuffer, buffers->shader_usage,
1229 /* Update the streamout state. */
1230 if (sctx->b.streamout.begin_emitted)
1231 r600_emit_streamout_end(&sctx->b);
1232 sctx->b.streamout.append_bitmask =
1233 sctx->b.streamout.enabled_mask;
1234 r600_streamout_buffers_dirty(&sctx->b);
1237 /* Constant and shader buffers. */
1238 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1239 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1241 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1245 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1246 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1247 if (view->base.texture == buf) {
1248 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1251 /* Texture buffers - update bindings. */
1252 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1253 struct si_sampler_views *views = &sctx->samplers[shader].views;
1254 uint64_t mask = views->desc.enabled_mask;
1257 unsigned i = u_bit_scan64(&mask);
1258 if (views->views[i]->texture == buf) {
1259 si_desc_reset_buffer_offset(ctx,
1263 views->desc.dirty_mask |= 1llu << i;
1265 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1266 rbuffer, RADEON_USAGE_READ,
1267 RADEON_PRIO_SAMPLER_BUFFER);
1273 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1274 struct si_images_info *images = &sctx->images[shader];
1275 unsigned mask = images->desc.enabled_mask;
1278 unsigned i = u_bit_scan(&mask);
1280 if (images->views[i].resource == buf) {
1281 si_desc_reset_buffer_offset(
1282 ctx, images->desc.list + i * 8 + 4,
1284 images->desc.dirty_mask |= 1llu << i;
1286 radeon_add_to_buffer_list(
1287 &sctx->b, &sctx->b.gfx, rbuffer,
1288 RADEON_USAGE_READWRITE,
1289 RADEON_PRIO_SAMPLER_BUFFER);
1295 /* SHADER USER DATA */
1297 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1300 sctx->const_buffers[shader].desc.pointer_dirty = true;
1301 sctx->shader_buffers[shader].desc.pointer_dirty = true;
1302 sctx->samplers[shader].views.desc.pointer_dirty = true;
1303 sctx->images[shader].desc.pointer_dirty = true;
1305 if (shader == PIPE_SHADER_VERTEX)
1306 sctx->vertex_buffers.pointer_dirty = true;
1308 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1311 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1315 for (i = 0; i < SI_NUM_SHADERS; i++) {
1316 si_mark_shader_pointers_dirty(sctx, i);
1318 sctx->rw_buffers.desc.pointer_dirty = true;
1321 /* Set a base register address for user data constants in the given shader.
1322 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1324 static void si_set_user_data_base(struct si_context *sctx,
1325 unsigned shader, uint32_t new_base)
1327 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1329 if (*base != new_base) {
1333 si_mark_shader_pointers_dirty(sctx, shader);
1337 /* This must be called when these shaders are changed from non-NULL to NULL
1340 * - tessellation control shader
1341 * - tessellation evaluation shader
1343 void si_shader_change_notify(struct si_context *sctx)
1345 /* VS can be bound as VS, ES, or LS. */
1346 if (sctx->tes_shader.cso)
1347 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1348 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1349 else if (sctx->gs_shader.cso)
1350 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1351 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1353 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1354 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1356 /* TES can be bound as ES, VS, or not bound. */
1357 if (sctx->tes_shader.cso) {
1358 if (sctx->gs_shader.cso)
1359 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1360 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1362 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1363 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1365 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1369 static void si_emit_shader_pointer(struct si_context *sctx,
1370 struct si_descriptors *desc,
1371 unsigned sh_base, bool keep_dirty)
1373 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1376 if (!desc->pointer_dirty || !desc->buffer)
1379 va = desc->buffer->gpu_address +
1380 desc->buffer_offset;
1382 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1383 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1384 radeon_emit(cs, va);
1385 radeon_emit(cs, va >> 32);
1387 desc->pointer_dirty = keep_dirty;
1390 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1391 struct r600_atom *atom)
1394 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1396 if (sctx->gs_shader.cso) {
1397 /* The VS copy shader needs this for clipping. */
1398 unsigned vs_base = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1399 unsigned i = PIPE_SHADER_VERTEX;
1401 si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, vs_base, true);
1404 if (sctx->rw_buffers.desc.pointer_dirty) {
1405 si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
1406 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1407 si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
1408 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1409 si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
1410 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1411 si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
1412 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1413 sctx->rw_buffers.desc.pointer_dirty = false;
1416 for (i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
1417 unsigned base = sh_base[i];
1422 si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, false);
1423 si_emit_shader_pointer(sctx, &sctx->shader_buffers[i].desc, base, false);
1424 si_emit_shader_pointer(sctx, &sctx->samplers[i].views.desc, base, false);
1425 si_emit_shader_pointer(sctx, &sctx->images[i].desc, base, false);
1427 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1430 void si_emit_compute_shader_userdata(struct si_context *sctx)
1432 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1434 si_emit_shader_pointer(sctx, &sctx->const_buffers[PIPE_SHADER_COMPUTE].desc,
1436 si_emit_shader_pointer(sctx, &sctx->shader_buffers[PIPE_SHADER_COMPUTE].desc,
1438 si_emit_shader_pointer(sctx, &sctx->samplers[PIPE_SHADER_COMPUTE].views.desc,
1440 si_emit_shader_pointer(sctx, &sctx->images[PIPE_SHADER_COMPUTE].desc,
1444 /* INIT/DEINIT/UPLOAD */
1446 void si_init_all_descriptors(struct si_context *sctx)
1449 unsigned ce_offset = 0;
1451 for (i = 0; i < SI_NUM_SHADERS; i++) {
1452 si_init_buffer_resources(&sctx->const_buffers[i],
1453 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1454 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1456 si_init_buffer_resources(&sctx->shader_buffers[i],
1457 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1458 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1461 si_init_descriptors(&sctx->samplers[i].views.desc,
1462 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1463 null_texture_descriptor, &ce_offset);
1465 si_init_descriptors(&sctx->images[i].desc,
1466 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1467 null_image_descriptor, &ce_offset);
1470 si_init_buffer_resources(&sctx->rw_buffers,
1471 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1472 RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
1474 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1475 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1477 assert(ce_offset <= 32768);
1479 /* Set pipe_context functions. */
1480 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1481 sctx->b.b.set_shader_images = si_set_shader_images;
1482 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1483 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1484 sctx->b.b.set_sampler_views = si_set_sampler_views;
1485 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1486 sctx->b.invalidate_buffer = si_invalidate_buffer;
1488 /* Shader user data. */
1489 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1490 si_emit_graphics_shader_userdata);
1492 /* Set default and immutable mappings. */
1493 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1494 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1495 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1496 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1499 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1503 for (i = 0; i < SI_NUM_SHADERS; i++) {
1504 if (!si_upload_descriptors(sctx, &sctx->const_buffers[i].desc,
1505 &sctx->shader_userdata.atom) ||
1506 !si_upload_descriptors(sctx, &sctx->shader_buffers[i].desc,
1507 &sctx->shader_userdata.atom) ||
1508 !si_upload_descriptors(sctx, &sctx->samplers[i].views.desc,
1509 &sctx->shader_userdata.atom) ||
1510 !si_upload_descriptors(sctx, &sctx->images[i].desc,
1511 &sctx->shader_userdata.atom))
1514 return si_upload_descriptors(sctx, &sctx->rw_buffers.desc,
1515 &sctx->shader_userdata.atom) &&
1516 si_upload_vertex_buffer_descriptors(sctx);
1519 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1521 /* Does not update rw_buffers as that is not needed for compute shaders
1522 * and the input buffer is using the same SGPR's anyway.
1524 return si_upload_descriptors(sctx,
1525 &sctx->const_buffers[PIPE_SHADER_COMPUTE].desc, NULL) &&
1526 si_upload_descriptors(sctx,
1527 &sctx->shader_buffers[PIPE_SHADER_COMPUTE].desc, NULL) &&
1528 si_upload_descriptors(sctx,
1529 &sctx->samplers[PIPE_SHADER_COMPUTE].views.desc, NULL) &&
1530 si_upload_descriptors(sctx,
1531 &sctx->images[PIPE_SHADER_COMPUTE].desc, NULL);
1534 void si_release_all_descriptors(struct si_context *sctx)
1538 for (i = 0; i < SI_NUM_SHADERS; i++) {
1539 si_release_buffer_resources(&sctx->const_buffers[i]);
1540 si_release_buffer_resources(&sctx->shader_buffers[i]);
1541 si_release_sampler_views(&sctx->samplers[i].views);
1542 si_release_image_views(&sctx->images[i]);
1544 si_release_buffer_resources(&sctx->rw_buffers);
1545 si_release_descriptors(&sctx->vertex_buffers);
1548 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1552 for (i = 0; i < SI_NUM_SHADERS; i++) {
1553 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1554 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1555 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1556 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1558 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1559 si_vertex_buffers_begin_new_cs(sctx);
1560 si_shader_userdata_begin_new_cs(sctx);