src/gallium/drivers/radeonsi/si_descriptors.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák <marek.olsak@amd.com>
  25  */
  26
  27 /* Resource binding slots and sampler states (each described with 8 or
  28  * 4 dwords) are stored in lists in memory which is accessed by shaders
  29  * using scalar load instructions.
  30  *
  31  * This file is responsible for managing such lists. It keeps a copy of all
  32  * descriptors in CPU memory and re-uploads a whole list if some slots have
  33  * been changed.
  34  *
  35  * This code is also reponsible for updating shader pointers to those lists.
  36  *
  37  * Note that CP DMA can't be used for updating the lists, because a GPU hang
  38  * could leave the list in a mid-IB state and the next IB would get wrong
  39  * descriptors and the whole context would be unusable at that point.
  40  * (Note: The register shadowing can't be used due to the same reason)
  41  *
  42  * Also, uploading descriptors to newly allocated memory doesn't require
  43  * a KCACHE flush.
  44  *
  45  *
  46  * Possible scenarios for one 16 dword image+sampler slot:
  47  *
  48  *       | Image        | w/ FMASK   | Buffer       | NULL
  49  * [ 0: 3] Image[0:3]   | Image[0:3] | Null[0:3]    | Null[0:3]
  50  * [ 4: 7] Image[4:7]   | Image[4:7] | Buffer[0:3]  | 0
  51  * [ 8:11] Null[0:3]    | Fmask[0:3] | Null[0:3]    | Null[0:3]
  52  * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
  53  *
  54  * FMASK implies MSAA, therefore no sampler state.
  55  * Sampler states are never unbound except when FMASK is bound.
  56  */
  57
  58 #include "radeon/r600_cs.h"
  59 #include "si_pipe.h"
  60 #include "si_shader.h"
  61 #include "sid.h"
  62
  63 #include "util/u_math.h"
  64 #include "util/u_memory.h"
  65 #include "util/u_suballoc.h"
  66 #include "util/u_upload_mgr.h"
  67
  68
  69 /* NULL image and buffer descriptor for textures (alpha = 1) and images
  70  * (alpha = 0).
  71  *
  72  * For images, all fields must be zero except for the swizzle, which
  73  * supports arbitrary combinations of 0s and 1s. The texture type must be
  74  * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
  75  *
  76  * For buffers, all fields must be zero. If they are not, the hw hangs.
  77  *
  78  * This is the only reason why the buffer descriptor must be in words [4:7].
  79  */
  80 static uint32_t null_texture_descriptor[8] = {
  81         0,
  82         0,
  83         0,
  84         S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
  85         S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
  86         /* the rest must contain zeros, which is also used by the buffer
  87          * descriptor */
  88 };
  89
  90 static uint32_t null_image_descriptor[8] = {
  91         0,
  92         0,
  93         0,
  94         S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
  95         /* the rest must contain zeros, which is also used by the buffer
  96          * descriptor */
  97 };
  98
  99 static void si_init_descriptors(struct si_descriptors *desc,
 100                                 unsigned shader_userdata_index,
 101                                 unsigned element_dw_size,
 102                                 unsigned num_elements,
 103                                 const uint32_t *null_descriptor,
 104                                 unsigned *ce_offset)
 105 {
 106         int i;
 107
 108         assert(num_elements <= sizeof(desc->enabled_mask)*8);
 109
 110         desc->list = CALLOC(num_elements, element_dw_size * 4);
 111         desc->element_dw_size = element_dw_size;
 112         desc->num_elements = num_elements;
 113         desc->dirty_mask = num_elements == 64 ? ~0llu : (1llu << num_elements) - 1;
 114         desc->shader_userdata_offset = shader_userdata_index * 4;
 115
 116         if (ce_offset) {
 117                 desc->ce_offset = *ce_offset;
 118
 119                 /* make sure that ce_offset stays 32 byte aligned */
 120                 *ce_offset += align(element_dw_size * num_elements * 4, 32);
 121         }
 122
 123         /* Initialize the array to NULL descriptors if the element size is 8. */
 124         if (null_descriptor) {
 125                 assert(element_dw_size % 8 == 0);
 126                 for (i = 0; i < num_elements * element_dw_size / 8; i++)
 127                         memcpy(desc->list + i * 8, null_descriptor,
 128                                8 * 4);
 129         }
 130 }
 131
 132 static void si_release_descriptors(struct si_descriptors *desc)
 133 {
 134         pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
 135         FREE(desc->list);
 136 }
 137
 138 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
 139                          unsigned *out_offset, struct r600_resource **out_buf) {
 140         uint64_t va;
 141
 142         u_suballocator_alloc(sctx->ce_suballocator, size, out_offset,
 143                              (struct pipe_resource**)out_buf);
 144         if (!out_buf)
 145                         return false;
 146
 147         va = (*out_buf)->gpu_address + *out_offset;
 148
 149         radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
 150         radeon_emit(sctx->ce_ib, ce_offset);
 151         radeon_emit(sctx->ce_ib, size / 4);
 152         radeon_emit(sctx->ce_ib, va);
 153         radeon_emit(sctx->ce_ib, va >> 32);
 154
 155         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
 156                                RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
 157
 158         sctx->ce_need_synchronization = true;
 159         return true;
 160 }
 161
 162 static void si_reinitialize_ce_ram(struct si_context *sctx,
 163                             struct si_descriptors *desc)
 164 {
 165         if (desc->buffer) {
 166                 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
 167                 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
 168                 uint64_t va = buffer->gpu_address + desc->buffer_offset;
 169                 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
 170
 171                 if (!ib)
 172                         ib = sctx->ce_ib;
 173
 174                 list_size = align(list_size, 32);
 175
 176                 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
 177                 radeon_emit(ib, va);
 178                 radeon_emit(ib, va >> 32);
 179                 radeon_emit(ib, list_size / 4);
 180                 radeon_emit(ib, desc->ce_offset);
 181
 182                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
 183                                     RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
 184         }
 185         desc->ce_ram_dirty = false;
 186 }
 187
 188 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
 189 {
 190         radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
 191         radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
 192                         CONTEXT_CONTROL_LOAD_CE_RAM(1));
 193         radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
 194 }
 195
 196 static bool si_upload_descriptors(struct si_context *sctx,
 197                                   struct si_descriptors *desc,
 198                                   struct r600_atom * atom)
 199 {
 200         unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
 201
 202         if (!desc->dirty_mask)
 203                 return true;
 204
 205         if (sctx->ce_ib) {
 206                 uint32_t const* list = (uint32_t const*)desc->list;
 207
 208                 if (desc->ce_ram_dirty)
 209                         si_reinitialize_ce_ram(sctx, desc);
 210
 211                 while(desc->dirty_mask) {
 212                         int begin, count;
 213                         u_bit_scan_consecutive_range64(&desc->dirty_mask, &begin,
 214                                                        &count);
 215
 216                         begin *= desc->element_dw_size;
 217                         count *= desc->element_dw_size;
 218
 219                         radeon_emit(sctx->ce_ib,
 220                                     PKT3(PKT3_WRITE_CONST_RAM, count, 0));
 221                         radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
 222                         radeon_emit_array(sctx->ce_ib, list + begin, count);
 223                 }
 224
 225                 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
 226                                            &desc->buffer_offset, &desc->buffer))
 227                         return false;
 228         } else {
 229                 void *ptr;
 230
 231                 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
 232                         &desc->buffer_offset,
 233                         (struct pipe_resource**)&desc->buffer, &ptr);
 234                 if (!desc->buffer)
 235                         return false; /* skip the draw call */
 236
 237                 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
 238
 239                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
 240                                     RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
 241         }
 242         desc->pointer_dirty = true;
 243         desc->dirty_mask = 0;
 244
 245         if (atom)
 246                 si_mark_atom_dirty(sctx, atom);
 247
 248         return true;
 249 }
 250
 251 /* SAMPLER VIEWS */
 252
 253 static void si_release_sampler_views(struct si_sampler_views *views)
 254 {
 255         int i;
 256
 257         for (i = 0; i < Elements(views->views); i++) {
 258                 pipe_sampler_view_reference(&views->views[i], NULL);
 259         }
 260         si_release_descriptors(&views->desc);
 261 }
 262
 263 static void si_sampler_view_add_buffer(struct si_context *sctx,
 264                                        struct pipe_resource *resource)
 265 {
 266         struct r600_resource *rres = (struct r600_resource*)resource;
 267
 268         if (!resource)
 269                 return;
 270
 271         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rres,
 272                                   RADEON_USAGE_READ,
 273                                   r600_get_sampler_view_priority(rres));
 274 }
 275
 276 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
 277                                           struct si_sampler_views *views)
 278 {
 279         uint64_t mask = views->desc.enabled_mask;
 280
 281         /* Add buffers to the CS. */
 282         while (mask) {
 283                 int i = u_bit_scan64(&mask);
 284
 285                 si_sampler_view_add_buffer(sctx, views->views[i]->texture);
 286         }
 287
 288         views->desc.ce_ram_dirty = true;
 289
 290         if (!views->desc.buffer)
 291                 return;
 292         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, views->desc.buffer,
 293                               RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
 294 }
 295
 296 static void si_set_sampler_view(struct si_context *sctx,
 297                                 struct si_sampler_views *views,
 298                                 unsigned slot, struct pipe_sampler_view *view)
 299 {
 300         struct si_sampler_view *rview = (struct si_sampler_view*)view;
 301
 302         if (view && view->texture && view->texture->target != PIPE_BUFFER &&
 303             G_008F28_COMPRESSION_EN(rview->state[6]) &&
 304             ((struct r600_texture*)view->texture)->dcc_offset == 0) {
 305                 rview->state[6] &= C_008F28_COMPRESSION_EN &
 306                                    C_008F28_ALPHA_IS_ON_MSB;
 307         } else if (views->views[slot] == view)
 308                 return;
 309
 310         if (view) {
 311                 struct r600_texture *rtex = (struct r600_texture *)view->texture;
 312
 313                 si_sampler_view_add_buffer(sctx, view->texture);
 314
 315                 pipe_sampler_view_reference(&views->views[slot], view);
 316                 memcpy(views->desc.list + slot * 16, rview->state, 8*4);
 317
 318                 if (view->texture && view->texture->target != PIPE_BUFFER &&
 319                     rtex->fmask.size) {
 320                         memcpy(views->desc.list + slot*16 + 8,
 321                                rview->fmask_state, 8*4);
 322                 } else {
 323                         /* Disable FMASK and bind sampler state in [12:15]. */
 324                         memcpy(views->desc.list + slot*16 + 8,
 325                                null_texture_descriptor, 4*4);
 326
 327                         if (views->sampler_states[slot])
 328                                 memcpy(views->desc.list + slot*16 + 12,
 329                                        views->sampler_states[slot], 4*4);
 330                 }
 331
 332                 views->desc.enabled_mask |= 1llu << slot;
 333         } else {
 334                 pipe_sampler_view_reference(&views->views[slot], NULL);
 335                 memcpy(views->desc.list + slot*16, null_texture_descriptor, 8*4);
 336                 /* Only clear the lower dwords of FMASK. */
 337                 memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 4*4);
 338                 views->desc.enabled_mask &= ~(1llu << slot);
 339         }
 340
 341         views->desc.dirty_mask |= 1llu << slot;
 342 }
 343
 344 static bool is_compressed_colortex(struct r600_texture *rtex)
 345 {
 346         return rtex->cmask.size || rtex->fmask.size ||
 347                (rtex->dcc_offset && rtex->dirty_level_mask);
 348 }
 349
 350 static void si_set_sampler_views(struct pipe_context *ctx,
 351                                  unsigned shader, unsigned start,
 352                                  unsigned count,
 353                                  struct pipe_sampler_view **views)
 354 {
 355         struct si_context *sctx = (struct si_context *)ctx;
 356         struct si_textures_info *samplers = &sctx->samplers[shader];
 357         int i;
 358
 359         if (!count || shader >= SI_NUM_SHADERS)
 360                 return;
 361
 362         for (i = 0; i < count; i++) {
 363                 unsigned slot = start + i;
 364
 365                 if (!views || !views[i]) {
 366                         samplers->depth_texture_mask &= ~(1llu << slot);
 367                         samplers->compressed_colortex_mask &= ~(1llu << slot);
 368                         si_set_sampler_view(sctx, &samplers->views, slot, NULL);
 369                         continue;
 370                 }
 371
 372                 si_set_sampler_view(sctx, &samplers->views, slot, views[i]);
 373
 374                 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
 375                         struct r600_texture *rtex =
 376                                 (struct r600_texture*)views[i]->texture;
 377
 378                         if (rtex->is_depth && !rtex->is_flushing_texture) {
 379                                 samplers->depth_texture_mask |= 1llu << slot;
 380                         } else {
 381                                 samplers->depth_texture_mask &= ~(1llu << slot);
 382                         }
 383                         if (is_compressed_colortex(rtex)) {
 384                                 samplers->compressed_colortex_mask |= 1llu << slot;
 385                         } else {
 386                                 samplers->compressed_colortex_mask &= ~(1llu << slot);
 387                         }
 388                 } else {
 389                         samplers->depth_texture_mask &= ~(1llu << slot);
 390                         samplers->compressed_colortex_mask &= ~(1llu << slot);
 391                 }
 392         }
 393 }
 394
 395 static void
 396 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
 397 {
 398         uint64_t mask = samplers->views.desc.enabled_mask;
 399
 400         while (mask) {
 401                 int i = u_bit_scan64(&mask);
 402                 struct pipe_resource *res = samplers->views.views[i]->texture;
 403
 404                 if (res && res->target != PIPE_BUFFER) {
 405                         struct r600_texture *rtex = (struct r600_texture *)res;
 406
 407                         if (is_compressed_colortex(rtex)) {
 408                                 samplers->compressed_colortex_mask |= 1llu << i;
 409                         } else {
 410                                 samplers->compressed_colortex_mask &= ~(1llu << i);
 411                         }
 412                 }
 413         }
 414 }
 415
 416 /* IMAGE VIEWS */
 417
 418 static void
 419 si_release_image_views(struct si_images_info *images)
 420 {
 421         unsigned i;
 422
 423         for (i = 0; i < SI_NUM_IMAGES; ++i) {
 424                 struct pipe_image_view *view = &images->views[i];
 425
 426                 pipe_resource_reference(&view->resource, NULL);
 427         }
 428
 429         si_release_descriptors(&images->desc);
 430 }
 431
 432 static void
 433 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
 434 {
 435         uint mask = images->desc.enabled_mask;
 436
 437         /* Add buffers to the CS. */
 438         while (mask) {
 439                 int i = u_bit_scan(&mask);
 440                 struct pipe_image_view *view = &images->views[i];
 441
 442                 assert(view->resource);
 443
 444                 si_sampler_view_add_buffer(sctx, view->resource);
 445         }
 446
 447         images->desc.ce_ram_dirty = true;
 448
 449         if (images->desc.buffer) {
 450                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 451                                           images->desc.buffer,
 452                                           RADEON_USAGE_READ,
 453                                           RADEON_PRIO_DESCRIPTORS);
 454         }
 455 }
 456
 457 static void
 458 si_disable_shader_image(struct si_images_info *images, unsigned slot)
 459 {
 460         if (images->desc.enabled_mask & (1llu << slot)) {
 461                 pipe_resource_reference(&images->views[slot].resource, NULL);
 462                 images->compressed_colortex_mask &= ~(1 << slot);
 463
 464                 memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
 465                 images->desc.enabled_mask &= ~(1llu << slot);
 466                 images->desc.dirty_mask |= 1llu << slot;
 467         }
 468 }
 469
 470 static void
 471 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
 472                      unsigned start_slot, unsigned count,
 473                      struct pipe_image_view *views)
 474 {
 475         struct si_context *ctx = (struct si_context *)pipe;
 476         struct si_screen *screen = ctx->screen;
 477         struct si_images_info *images = &ctx->images[shader];
 478         unsigned i, slot;
 479
 480         assert(shader < SI_NUM_SHADERS);
 481
 482         if (!count)
 483                 return;
 484
 485         assert(start_slot + count <= SI_NUM_IMAGES);
 486
 487         for (i = 0, slot = start_slot; i < count; ++i, ++slot) {
 488                 struct r600_resource *res;
 489
 490                 if (!views || !views[i].resource) {
 491                         si_disable_shader_image(images, slot);
 492                         continue;
 493                 }
 494
 495                 res = (struct r600_resource *)views[i].resource;
 496                 util_copy_image_view(&images->views[slot], &views[i]);
 497
 498                 si_sampler_view_add_buffer(ctx, &res->b.b);
 499
 500                 if (res->b.b.target == PIPE_BUFFER) {
 501                         si_make_buffer_descriptor(screen, res,
 502                                                   views[i].format,
 503                                                   views[i].u.buf.first_element,
 504                                                   views[i].u.buf.last_element,
 505                                                   images->desc.list + slot * 8);
 506                         images->compressed_colortex_mask &= ~(1 << slot);
 507                 } else {
 508                         static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
 509                         struct r600_texture *tex = (struct r600_texture *)res;
 510                         unsigned level;
 511                         unsigned width, height, depth;
 512
 513                         assert(!tex->is_depth);
 514                         assert(tex->fmask.size == 0);
 515
 516                         if (tex->dcc_offset &&
 517                             views[i].access & PIPE_IMAGE_ACCESS_WRITE)
 518                                 r600_texture_disable_dcc(&screen->b, tex);
 519
 520                         if (is_compressed_colortex(tex)) {
 521                                 images->compressed_colortex_mask |= 1 << slot;
 522                         } else {
 523                                 images->compressed_colortex_mask &= ~(1 << slot);
 524                         }
 525
 526                         /* Always force the base level to the selected level.
 527                          *
 528                          * This is required for 3D textures, where otherwise
 529                          * selecting a single slice for non-layered bindings
 530                          * fails. It doesn't hurt the other targets.
 531                          */
 532                         level = views[i].u.tex.level;
 533                         width = u_minify(res->b.b.width0, level);
 534                         height = u_minify(res->b.b.height0, level);
 535                         depth = u_minify(res->b.b.depth0, level);
 536
 537                         si_make_texture_descriptor(screen, tex, false, res->b.b.target,
 538                                                    views[i].format, swizzle,
 539                                                    level, 0, 0,
 540                                                    views[i].u.tex.first_layer, views[i].u.tex.last_layer,
 541                                                    width, height, depth,
 542                                                    images->desc.list + slot * 8,
 543                                                    NULL);
 544                 }
 545
 546                 images->desc.enabled_mask |= 1llu << slot;
 547                 images->desc.dirty_mask |= 1llu << slot;
 548         }
 549 }
 550
 551 static void
 552 si_images_update_compressed_colortex_mask(struct si_images_info *images)
 553 {
 554         uint64_t mask = images->desc.enabled_mask;
 555
 556         while (mask) {
 557                 int i = u_bit_scan64(&mask);
 558                 struct pipe_resource *res = images->views[i].resource;
 559
 560                 if (res && res->target != PIPE_BUFFER) {
 561                         struct r600_texture *rtex = (struct r600_texture *)res;
 562
 563                         if (is_compressed_colortex(rtex)) {
 564                                 images->compressed_colortex_mask |= 1 << i;
 565                         } else {
 566                                 images->compressed_colortex_mask &= ~(1 << i);
 567                         }
 568                 }
 569         }
 570 }
 571
 572 /* SAMPLER STATES */
 573
 574 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
 575                                    unsigned start, unsigned count, void **states)
 576 {
 577         struct si_context *sctx = (struct si_context *)ctx;
 578         struct si_textures_info *samplers = &sctx->samplers[shader];
 579         struct si_descriptors *desc = &samplers->views.desc;
 580         struct si_sampler_state **sstates = (struct si_sampler_state**)states;
 581         int i;
 582
 583         if (!count || shader >= SI_NUM_SHADERS)
 584                 return;
 585
 586         for (i = 0; i < count; i++) {
 587                 unsigned slot = start + i;
 588
 589                 if (!sstates[i] ||
 590                     sstates[i] == samplers->views.sampler_states[slot])
 591                         continue;
 592
 593                 samplers->views.sampler_states[slot] = sstates[i];
 594
 595                 /* If FMASK is bound, don't overwrite it.
 596                  * The sampler state will be set after FMASK is unbound.
 597                  */
 598                 if (samplers->views.views[i] &&
 599                     samplers->views.views[i]->texture &&
 600                     samplers->views.views[i]->texture->target != PIPE_BUFFER &&
 601                     ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
 602                         continue;
 603
 604                 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
 605                 desc->dirty_mask |= 1llu << slot;
 606         }
 607 }
 608
 609 /* BUFFER RESOURCES */
 610
 611 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
 612                                      unsigned num_buffers,
 613                                      unsigned shader_userdata_index,
 614                                      enum radeon_bo_usage shader_usage,
 615                                      enum radeon_bo_priority priority,
 616                                      unsigned *ce_offset)
 617 {
 618         buffers->shader_usage = shader_usage;
 619         buffers->priority = priority;
 620         buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
 621
 622         si_init_descriptors(&buffers->desc, shader_userdata_index, 4,
 623                             num_buffers, NULL, ce_offset);
 624 }
 625
 626 static void si_release_buffer_resources(struct si_buffer_resources *buffers)
 627 {
 628         int i;
 629
 630         for (i = 0; i < buffers->desc.num_elements; i++) {
 631                 pipe_resource_reference(&buffers->buffers[i], NULL);
 632         }
 633
 634         FREE(buffers->buffers);
 635         si_release_descriptors(&buffers->desc);
 636 }
 637
 638 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
 639                                              struct si_buffer_resources *buffers)
 640 {
 641         uint64_t mask = buffers->desc.enabled_mask;
 642
 643         /* Add buffers to the CS. */
 644         while (mask) {
 645                 int i = u_bit_scan64(&mask);
 646
 647                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 648                                       (struct r600_resource*)buffers->buffers[i],
 649                                       buffers->shader_usage, buffers->priority);
 650         }
 651
 652         buffers->desc.ce_ram_dirty = true;
 653
 654         if (!buffers->desc.buffer)
 655                 return;
 656         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 657                               buffers->desc.buffer, RADEON_USAGE_READWRITE,
 658                               RADEON_PRIO_DESCRIPTORS);
 659 }
 660
 661 /* VERTEX BUFFERS */
 662
 663 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
 664 {
 665         struct si_descriptors *desc = &sctx->vertex_buffers;
 666         int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
 667         int i;
 668
 669         for (i = 0; i < count; i++) {
 670                 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
 671
 672                 if (vb >= Elements(sctx->vertex_buffer))
 673                         continue;
 674                 if (!sctx->vertex_buffer[vb].buffer)
 675                         continue;
 676
 677                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 678                                       (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
 679                                       RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
 680         }
 681
 682         if (!desc->buffer)
 683                 return;
 684         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 685                               desc->buffer, RADEON_USAGE_READ,
 686                               RADEON_PRIO_DESCRIPTORS);
 687 }
 688
 689 static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
 690 {
 691         struct si_descriptors *desc = &sctx->vertex_buffers;
 692         bool bound[SI_NUM_VERTEX_BUFFERS] = {};
 693         unsigned i, count = sctx->vertex_elements->count;
 694         uint64_t va;
 695         uint32_t *ptr;
 696
 697         if (!sctx->vertex_buffers_dirty)
 698                 return true;
 699         if (!count || !sctx->vertex_elements)
 700                 return true;
 701
 702         /* Vertex buffer descriptors are the only ones which are uploaded
 703          * directly through a staging buffer and don't go through
 704          * the fine-grained upload path.
 705          */
 706         u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
 707                        (struct pipe_resource**)&desc->buffer, (void**)&ptr);
 708         if (!desc->buffer)
 709                 return false;
 710
 711         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 712                               desc->buffer, RADEON_USAGE_READ,
 713                               RADEON_PRIO_DESCRIPTORS);
 714
 715         assert(count <= SI_NUM_VERTEX_BUFFERS);
 716
 717         for (i = 0; i < count; i++) {
 718                 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
 719                 struct pipe_vertex_buffer *vb;
 720                 struct r600_resource *rbuffer;
 721                 unsigned offset;
 722                 uint32_t *desc = &ptr[i*4];
 723
 724                 if (ve->vertex_buffer_index >= Elements(sctx->vertex_buffer)) {
 725                         memset(desc, 0, 16);
 726                         continue;
 727                 }
 728
 729                 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
 730                 rbuffer = (struct r600_resource*)vb->buffer;
 731                 if (!rbuffer) {
 732                         memset(desc, 0, 16);
 733                         continue;
 734                 }
 735
 736                 offset = vb->buffer_offset + ve->src_offset;
 737                 va = rbuffer->gpu_address + offset;
 738
 739                 /* Fill in T# buffer resource description */
 740                 desc[0] = va;
 741                 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
 742                           S_008F04_STRIDE(vb->stride);
 743
 744                 if (sctx->b.chip_class <= CIK && vb->stride)
 745                         /* Round up by rounding down and adding 1 */
 746                         desc[2] = (vb->buffer->width0 - offset -
 747                                    sctx->vertex_elements->format_size[i]) /
 748                                   vb->stride + 1;
 749                 else
 750                         desc[2] = vb->buffer->width0 - offset;
 751
 752                 desc[3] = sctx->vertex_elements->rsrc_word3[i];
 753
 754                 if (!bound[ve->vertex_buffer_index]) {
 755                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 756                                               (struct r600_resource*)vb->buffer,
 757                                               RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
 758                         bound[ve->vertex_buffer_index] = true;
 759                 }
 760         }
 761
 762         /* Don't flush the const cache. It would have a very negative effect
 763          * on performance (confirmed by testing). New descriptors are always
 764          * uploaded to a fresh new buffer, so I don't think flushing the const
 765          * cache is needed. */
 766         desc->pointer_dirty = true;
 767         si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
 768         sctx->vertex_buffers_dirty = false;
 769         return true;
 770 }
 771
 772
 773 /* CONSTANT BUFFERS */
 774
 775 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 776                             const uint8_t *ptr, unsigned size, uint32_t *const_offset)
 777 {
 778         void *tmp;
 779
 780         u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
 781                        (struct pipe_resource**)rbuffer, &tmp);
 782         if (rbuffer)
 783                 util_memcpy_cpu_to_le32(tmp, ptr, size);
 784 }
 785
 786 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint slot,
 787                                    struct pipe_constant_buffer *input)
 788 {
 789         struct si_context *sctx = (struct si_context *)ctx;
 790         struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
 791
 792         if (shader >= SI_NUM_SHADERS)
 793                 return;
 794
 795         assert(slot < buffers->desc.num_elements);
 796         pipe_resource_reference(&buffers->buffers[slot], NULL);
 797
 798         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 799          * with a NULL buffer). We need to use a dummy buffer instead. */
 800         if (sctx->b.chip_class == CIK &&
 801             (!input || (!input->buffer && !input->user_buffer)))
 802                 input = &sctx->null_const_buf;
 803
 804         if (input && (input->buffer || input->user_buffer)) {
 805                 struct pipe_resource *buffer = NULL;
 806                 uint64_t va;
 807
 808                 /* Upload the user buffer if needed. */
 809                 if (input->user_buffer) {
 810                         unsigned buffer_offset;
 811
 812                         si_upload_const_buffer(sctx,
 813                                                (struct r600_resource**)&buffer, input->user_buffer,
 814                                                input->buffer_size, &buffer_offset);
 815                         if (!buffer) {
 816                                 /* Just unbind on failure. */
 817                                 si_set_constant_buffer(ctx, shader, slot, NULL);
 818                                 return;
 819                         }
 820                         va = r600_resource(buffer)->gpu_address + buffer_offset;
 821                 } else {
 822                         pipe_resource_reference(&buffer, input->buffer);
 823                         va = r600_resource(buffer)->gpu_address + input->buffer_offset;
 824                 }
 825
 826                 /* Set the descriptor. */
 827                 uint32_t *desc = buffers->desc.list + slot*4;
 828                 desc[0] = va;
 829                 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
 830                           S_008F04_STRIDE(0);
 831                 desc[2] = input->buffer_size;
 832                 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 833                           S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 834                           S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 835                           S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 836                           S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
 837                           S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 838
 839                 buffers->buffers[slot] = buffer;
 840                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 841                                       (struct r600_resource*)buffer,
 842                                       buffers->shader_usage, buffers->priority);
 843                 buffers->desc.enabled_mask |= 1llu << slot;
 844         } else {
 845                 /* Clear the descriptor. */
 846                 memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
 847                 buffers->desc.enabled_mask &= ~(1llu << slot);
 848         }
 849
 850         buffers->desc.dirty_mask |= 1llu << slot;
 851 }
 852
 853 /* SHADER BUFFERS */
 854
 855 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
 856                                   unsigned start_slot, unsigned count,
 857                                   struct pipe_shader_buffer *sbuffers)
 858 {
 859         struct si_context *sctx = (struct si_context *)ctx;
 860         struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
 861         unsigned i;
 862
 863         assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
 864
 865         for (i = 0; i < count; ++i) {
 866                 struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
 867                 struct r600_resource *buf;
 868                 unsigned slot = start_slot + i;
 869                 uint32_t *desc = buffers->desc.list + slot * 4;
 870                 uint64_t va;
 871
 872                 if (!sbuffer || !sbuffer->buffer) {
 873                         pipe_resource_reference(&buffers->buffers[slot], NULL);
 874                         memset(desc, 0, sizeof(uint32_t) * 4);
 875                         buffers->desc.enabled_mask &= ~(1llu << slot);
 876                         continue;
 877                 }
 878
 879                 buf = (struct r600_resource *)sbuffer->buffer;
 880                 va = buf->gpu_address + sbuffer->buffer_offset;
 881
 882                 desc[0] = va;
 883                 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
 884                           S_008F04_STRIDE(0);
 885                 desc[2] = sbuffer->buffer_size;
 886                 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 887                           S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 888                           S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 889                           S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 890                           S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
 891                           S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 892
 893                 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
 894                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
 895                                       buffers->shader_usage, buffers->priority);
 896                 buffers->desc.enabled_mask |= 1llu << slot;
 897                 buffers->desc.dirty_mask |= 1llu << slot;
 898         }
 899
 900 }
 901
 902 /* RING BUFFERS */
 903
 904 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 905                         struct pipe_resource *buffer,
 906                         unsigned stride, unsigned num_records,
 907                         bool add_tid, bool swizzle,
 908                         unsigned element_size, unsigned index_stride, uint64_t offset)
 909 {
 910         struct si_context *sctx = (struct si_context *)ctx;
 911         struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
 912
 913         if (shader >= SI_NUM_SHADERS)
 914                 return;
 915
 916         /* The stride field in the resource descriptor has 14 bits */
 917         assert(stride < (1 << 14));
 918
 919         assert(slot < buffers->desc.num_elements);
 920         pipe_resource_reference(&buffers->buffers[slot], NULL);
 921
 922         if (buffer) {
 923                 uint64_t va;
 924
 925                 va = r600_resource(buffer)->gpu_address + offset;
 926
 927                 switch (element_size) {
 928                 default:
 929                         assert(!"Unsupported ring buffer element size");
 930                 case 0:
 931                 case 2:
 932                         element_size = 0;
 933                         break;
 934                 case 4:
 935                         element_size = 1;
 936                         break;
 937                 case 8:
 938                         element_size = 2;
 939                         break;
 940                 case 16:
 941                         element_size = 3;
 942                         break;
 943                 }
 944
 945                 switch (index_stride) {
 946                 default:
 947                         assert(!"Unsupported ring buffer index stride");
 948                 case 0:
 949                 case 8:
 950                         index_stride = 0;
 951                         break;
 952                 case 16:
 953                         index_stride = 1;
 954                         break;
 955                 case 32:
 956                         index_stride = 2;
 957                         break;
 958                 case 64:
 959                         index_stride = 3;
 960                         break;
 961                 }
 962
 963                 if (sctx->b.chip_class >= VI && stride)
 964                         num_records *= stride;
 965
 966                 /* Set the descriptor. */
 967                 uint32_t *desc = buffers->desc.list + slot*4;
 968                 desc[0] = va;
 969                 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
 970                           S_008F04_STRIDE(stride) |
 971                           S_008F04_SWIZZLE_ENABLE(swizzle);
 972                 desc[2] = num_records;
 973                 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 974                           S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 975                           S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 976                           S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 977                           S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
 978                           S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
 979                           S_008F0C_ELEMENT_SIZE(element_size) |
 980                           S_008F0C_INDEX_STRIDE(index_stride) |
 981                           S_008F0C_ADD_TID_ENABLE(add_tid);
 982
 983                 pipe_resource_reference(&buffers->buffers[slot], buffer);
 984                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 985                                       (struct r600_resource*)buffer,
 986                                       buffers->shader_usage, buffers->priority);
 987                 buffers->desc.enabled_mask |= 1llu << slot;
 988         } else {
 989                 /* Clear the descriptor. */
 990                 memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
 991                 buffers->desc.enabled_mask &= ~(1llu << slot);
 992         }
 993
 994         buffers->desc.dirty_mask |= 1llu << slot;
 995 }
 996
 997 /* STREAMOUT BUFFERS */
 998
 999 static void si_set_streamout_targets(struct pipe_context *ctx,
1000                                      unsigned num_targets,
1001                                      struct pipe_stream_output_target **targets,
1002                                      const unsigned *offsets)
1003 {
1004         struct si_context *sctx = (struct si_context *)ctx;
1005         struct si_buffer_resources *buffers = &sctx->rw_buffers[PIPE_SHADER_VERTEX];
1006         unsigned old_num_targets = sctx->b.streamout.num_targets;
1007         unsigned i, bufidx;
1008
1009         /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1010         if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1011                 /* Since streamout uses vector writes which go through TC L2
1012                  * and most other clients can use TC L2 as well, we don't need
1013                  * to flush it.
1014                  *
1015                  * The only case which requires flushing it is VGT DMA index
1016                  * fetching, which is a rare case. Thus, flag the TC L2
1017                  * dirtiness in the resource and handle it when index fetching
1018                  * is used.
1019                  */
1020                 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1021                         if (sctx->b.streamout.targets[i])
1022                                 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1023
1024                 /* Invalidate the scalar cache in case a streamout buffer is
1025                  * going to be used as a constant buffer.
1026                  *
1027                  * Invalidate TC L1, because streamout bypasses it (done by
1028                  * setting GLC=1 in the store instruction), but it can contain
1029                  * outdated data of streamout buffers.
1030                  *
1031                  * VS_PARTIAL_FLUSH is required if the buffers are going to be
1032                  * used as an input immediately.
1033                  */
1034                 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1035                                  SI_CONTEXT_INV_VMEM_L1 |
1036                                  SI_CONTEXT_VS_PARTIAL_FLUSH;
1037         }
1038
1039         /* All readers of the streamout targets need to be finished before we can
1040          * start writing to the targets.
1041          */
1042         if (num_targets)
1043                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1044                                  SI_CONTEXT_CS_PARTIAL_FLUSH;
1045
1046         /* Streamout buffers must be bound in 2 places:
1047          * 1) in VGT by setting the VGT_STRMOUT registers
1048          * 2) as shader resources
1049          */
1050
1051         /* Set the VGT regs. */
1052         r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1053
1054         /* Set the shader resources.*/
1055         for (i = 0; i < num_targets; i++) {
1056                 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1057
1058                 if (targets[i]) {
1059                         struct pipe_resource *buffer = targets[i]->buffer;
1060                         uint64_t va = r600_resource(buffer)->gpu_address;
1061
1062                         /* Set the descriptor.
1063                          *
1064                          * On VI, the format must be non-INVALID, otherwise
1065                          * the buffer will be considered not bound and store
1066                          * instructions will be no-ops.
1067                          */
1068                         uint32_t *desc = buffers->desc.list + bufidx*4;
1069                         desc[0] = va;
1070                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1071                         desc[2] = 0xffffffff;
1072                         desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1073                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1074                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1075                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1076                                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1077
1078                         /* Set the resource. */
1079                         pipe_resource_reference(&buffers->buffers[bufidx],
1080                                                 buffer);
1081                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1082                                               (struct r600_resource*)buffer,
1083                                               buffers->shader_usage, buffers->priority);
1084                         buffers->desc.enabled_mask |= 1llu << bufidx;
1085                 } else {
1086                         /* Clear the descriptor and unset the resource. */
1087                         memset(buffers->desc.list + bufidx*4, 0,
1088                                sizeof(uint32_t) * 4);
1089                         pipe_resource_reference(&buffers->buffers[bufidx],
1090                                                 NULL);
1091                         buffers->desc.enabled_mask &= ~(1llu << bufidx);
1092                 }
1093                 buffers->desc.dirty_mask |= 1llu << bufidx;
1094         }
1095         for (; i < old_num_targets; i++) {
1096                 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1097                 /* Clear the descriptor and unset the resource. */
1098                 memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
1099                 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1100                 buffers->desc.enabled_mask &= ~(1llu << bufidx);
1101                 buffers->desc.dirty_mask |= 1llu << bufidx;
1102         }
1103
1104 }
1105
1106 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1107                                         uint32_t *desc, uint64_t old_buf_va,
1108                                         struct pipe_resource *new_buf)
1109 {
1110         /* Retrieve the buffer offset from the descriptor. */
1111         uint64_t old_desc_va =
1112                 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1113
1114         assert(old_buf_va <= old_desc_va);
1115         uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1116
1117         /* Update the descriptor. */
1118         uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1119
1120         desc[0] = va;
1121         desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1122                   S_008F04_BASE_ADDRESS_HI(va >> 32);
1123 }
1124
1125 /* TEXTURE METADATA ENABLE/DISABLE */
1126
1127 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1128  * while the texture is bound, possibly by a different context. In that case,
1129  * call this function to update compressed_colortex_masks.
1130  */
1131 void si_update_compressed_colortex_masks(struct si_context *sctx)
1132 {
1133         for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1134                 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1135                 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1136         }
1137 }
1138
1139 /* BUFFER DISCARD/INVALIDATION */
1140
1141 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1142 static void si_reset_buffer_resources(struct si_context *sctx,
1143                                       struct si_buffer_resources *buffers,
1144                                       struct pipe_resource *buf,
1145                                       uint64_t old_va)
1146 {
1147         uint64_t mask = buffers->desc.enabled_mask;
1148
1149         while (mask) {
1150                 unsigned i = u_bit_scan64(&mask);
1151                 if (buffers->buffers[i] == buf) {
1152                         si_desc_reset_buffer_offset(&sctx->b.b,
1153                                                     buffers->desc.list + i*4,
1154                                                     old_va, buf);
1155                         buffers->desc.dirty_mask |= 1llu << i;
1156
1157                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1158                                                 (struct r600_resource *)buf,
1159                                                 buffers->shader_usage,
1160                                                 buffers->priority);
1161                 }
1162         }
1163 }
1164
1165 /* Reallocate a buffer a update all resource bindings where the buffer is
1166  * bound.
1167  *
1168  * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1169  * idle by discarding its contents. Apps usually tell us when to do this using
1170  * map_buffer flags, for example.
1171  */
1172 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1173 {
1174         struct si_context *sctx = (struct si_context*)ctx;
1175         struct r600_resource *rbuffer = r600_resource(buf);
1176         unsigned i, shader, alignment = rbuffer->buf->alignment;
1177         uint64_t old_va = rbuffer->gpu_address;
1178         unsigned num_elems = sctx->vertex_elements ?
1179                                        sctx->vertex_elements->count : 0;
1180         struct si_sampler_view *view;
1181
1182         /* Reallocate the buffer in the same pipe_resource. */
1183         r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1184                            alignment, TRUE);
1185
1186         /* We changed the buffer, now we need to bind it where the old one
1187          * was bound. This consists of 2 things:
1188          *   1) Updating the resource descriptor and dirtying it.
1189          *   2) Adding a relocation to the CS, so that it's usable.
1190          */
1191
1192         /* Vertex buffers. */
1193         for (i = 0; i < num_elems; i++) {
1194                 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1195
1196                 if (vb >= Elements(sctx->vertex_buffer))
1197                         continue;
1198                 if (!sctx->vertex_buffer[vb].buffer)
1199                         continue;
1200
1201                 if (sctx->vertex_buffer[vb].buffer == buf) {
1202                         sctx->vertex_buffers_dirty = true;
1203                         break;
1204                 }
1205         }
1206
1207         /* Read/Write buffers. */
1208         for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1209                 struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
1210                 uint64_t mask = buffers->desc.enabled_mask;
1211
1212                 while (mask) {
1213                         i = u_bit_scan64(&mask);
1214                         if (buffers->buffers[i] == buf) {
1215                                 si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4,
1216                                                             old_va, buf);
1217                                 buffers->desc.dirty_mask |= 1llu << i;
1218
1219                                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1220                                                       rbuffer, buffers->shader_usage,
1221                                                       buffers->priority);
1222
1223                                 if (i >= SI_VS_STREAMOUT_BUF0 && shader == PIPE_SHADER_VERTEX) {
1224                                         /* Update the streamout state. */
1225                                         if (sctx->b.streamout.begin_emitted) {
1226                                                 r600_emit_streamout_end(&sctx->b);
1227                                         }
1228                                         sctx->b.streamout.append_bitmask =
1229                                                 sctx->b.streamout.enabled_mask;
1230                                         r600_streamout_buffers_dirty(&sctx->b);
1231                                 }
1232                         }
1233                 }
1234         }
1235
1236         /* Constant and shader buffers. */
1237         for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1238                 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1239                                           buf, old_va);
1240                 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1241                                           buf, old_va);
1242         }
1243
1244         /* Texture buffers - update virtual addresses in sampler view descriptors. */
1245         LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1246                 if (view->base.texture == buf) {
1247                         si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1248                 }
1249         }
1250         /* Texture buffers - update bindings. */
1251         for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1252                 struct si_sampler_views *views = &sctx->samplers[shader].views;
1253                 uint64_t mask = views->desc.enabled_mask;
1254
1255                 while (mask) {
1256                         unsigned i = u_bit_scan64(&mask);
1257                         if (views->views[i]->texture == buf) {
1258                                 si_desc_reset_buffer_offset(ctx,
1259                                                             views->desc.list +
1260                                                             i * 16 + 4,
1261                                                             old_va, buf);
1262                                 views->desc.dirty_mask |= 1llu << i;
1263
1264                                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1265                                                       rbuffer, RADEON_USAGE_READ,
1266                                                       RADEON_PRIO_SAMPLER_BUFFER);
1267                         }
1268                 }
1269         }
1270
1271         /* Shader images */
1272         for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1273                 struct si_images_info *images = &sctx->images[shader];
1274                 unsigned mask = images->desc.enabled_mask;
1275
1276                 while (mask) {
1277                         unsigned i = u_bit_scan(&mask);
1278
1279                         if (images->views[i].resource == buf) {
1280                                 si_desc_reset_buffer_offset(
1281                                         ctx, images->desc.list + i * 8 + 4,
1282                                         old_va, buf);
1283                                 images->desc.dirty_mask |= 1llu << i;
1284
1285                                 radeon_add_to_buffer_list(
1286                                         &sctx->b, &sctx->b.gfx, rbuffer,
1287                                         RADEON_USAGE_READWRITE,
1288                                         RADEON_PRIO_SAMPLER_BUFFER);
1289                         }
1290                 }
1291         }
1292 }
1293
1294 /* SHADER USER DATA */
1295
1296 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1297                                           unsigned shader)
1298 {
1299         sctx->const_buffers[shader].desc.pointer_dirty = true;
1300         sctx->rw_buffers[shader].desc.pointer_dirty = true;
1301         sctx->shader_buffers[shader].desc.pointer_dirty = true;
1302         sctx->samplers[shader].views.desc.pointer_dirty = true;
1303         sctx->images[shader].desc.pointer_dirty = true;
1304
1305         if (shader == PIPE_SHADER_VERTEX)
1306                 sctx->vertex_buffers.pointer_dirty = true;
1307
1308         si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1309 }
1310
1311 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1312 {
1313         int i;
1314
1315         for (i = 0; i < SI_NUM_SHADERS; i++) {
1316                 si_mark_shader_pointers_dirty(sctx, i);
1317         }
1318 }
1319
1320 /* Set a base register address for user data constants in the given shader.
1321  * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1322  */
1323 static void si_set_user_data_base(struct si_context *sctx,
1324                                   unsigned shader, uint32_t new_base)
1325 {
1326         uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1327
1328         if (*base != new_base) {
1329                 *base = new_base;
1330
1331                 if (new_base)
1332                         si_mark_shader_pointers_dirty(sctx, shader);
1333         }
1334 }
1335
1336 /* This must be called when these shaders are changed from non-NULL to NULL
1337  * and vice versa:
1338  * - geometry shader
1339  * - tessellation control shader
1340  * - tessellation evaluation shader
1341  */
1342 void si_shader_change_notify(struct si_context *sctx)
1343 {
1344         /* VS can be bound as VS, ES, or LS. */
1345         if (sctx->tes_shader.cso)
1346                 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1347                                       R_00B530_SPI_SHADER_USER_DATA_LS_0);
1348         else if (sctx->gs_shader.cso)
1349                 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1350                                       R_00B330_SPI_SHADER_USER_DATA_ES_0);
1351         else
1352                 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1353                                       R_00B130_SPI_SHADER_USER_DATA_VS_0);
1354
1355         /* TES can be bound as ES, VS, or not bound. */
1356         if (sctx->tes_shader.cso) {
1357                 if (sctx->gs_shader.cso)
1358                         si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1359                                               R_00B330_SPI_SHADER_USER_DATA_ES_0);
1360                 else
1361                         si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1362                                               R_00B130_SPI_SHADER_USER_DATA_VS_0);
1363         } else {
1364                 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1365         }
1366 }
1367
1368 static void si_emit_shader_pointer(struct si_context *sctx,
1369                                    struct si_descriptors *desc,
1370                                    unsigned sh_base, bool keep_dirty)
1371 {
1372         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1373         uint64_t va;
1374
1375         if (!desc->pointer_dirty || !desc->buffer)
1376                 return;
1377
1378         va = desc->buffer->gpu_address +
1379              desc->buffer_offset;
1380
1381         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1382         radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1383         radeon_emit(cs, va);
1384         radeon_emit(cs, va >> 32);
1385
1386         desc->pointer_dirty = keep_dirty;
1387 }
1388
1389 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1390                                       struct r600_atom *atom)
1391 {
1392         unsigned i;
1393         uint32_t *sh_base = sctx->shader_userdata.sh_base;
1394
1395         if (sctx->gs_shader.cso) {
1396                 /* The VS copy shader needs these for clipping, streamout, and rings. */
1397                 unsigned vs_base = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1398                 unsigned i = PIPE_SHADER_VERTEX;
1399
1400                 si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, vs_base, true);
1401                 si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc, vs_base, true);
1402
1403                 if (sctx->tes_shader.cso) {
1404                         /* The TESSEVAL shader needs this for the ESGS ring buffer. */
1405                         si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc,
1406                                                R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1407                 }
1408         } else if (sctx->tes_shader.cso) {
1409                 /* The TESSEVAL shader needs this for streamout. */
1410                 si_emit_shader_pointer(sctx, &sctx->rw_buffers[PIPE_SHADER_VERTEX].desc,
1411                                        R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1412         }
1413
1414         for (i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
1415                 unsigned base = sh_base[i];
1416
1417                 if (!base)
1418                         continue;
1419
1420                 if (i != PIPE_SHADER_TESS_EVAL)
1421                         si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc, base, false);
1422
1423                 si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, false);
1424                 si_emit_shader_pointer(sctx, &sctx->shader_buffers[i].desc, base, false);
1425                 si_emit_shader_pointer(sctx, &sctx->samplers[i].views.desc, base, false);
1426                 si_emit_shader_pointer(sctx, &sctx->images[i].desc, base, false);
1427         }
1428         si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1429 }
1430
1431 void si_emit_compute_shader_userdata(struct si_context *sctx)
1432 {
1433         unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1434
1435         si_emit_shader_pointer(sctx, &sctx->const_buffers[PIPE_SHADER_COMPUTE].desc,
1436                                base, false);
1437         si_emit_shader_pointer(sctx, &sctx->shader_buffers[PIPE_SHADER_COMPUTE].desc,
1438                                base, false);
1439         si_emit_shader_pointer(sctx, &sctx->samplers[PIPE_SHADER_COMPUTE].views.desc,
1440                                base, false);
1441         si_emit_shader_pointer(sctx, &sctx->images[PIPE_SHADER_COMPUTE].desc,
1442                                base, false);
1443 }
1444
1445 /* INIT/DEINIT/UPLOAD */
1446
1447 void si_init_all_descriptors(struct si_context *sctx)
1448 {
1449         int i;
1450         unsigned ce_offset = 0;
1451
1452         for (i = 0; i < SI_NUM_SHADERS; i++) {
1453                 si_init_buffer_resources(&sctx->const_buffers[i],
1454                                          SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1455                                          RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1456                                          &ce_offset);
1457                 si_init_buffer_resources(&sctx->rw_buffers[i],
1458                                          SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1459                                          RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
1460                                          &ce_offset);
1461                 si_init_buffer_resources(&sctx->shader_buffers[i],
1462                                          SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1463                                          RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1464                                          &ce_offset);
1465
1466                 si_init_descriptors(&sctx->samplers[i].views.desc,
1467                                     SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1468                                     null_texture_descriptor, &ce_offset);
1469
1470                 si_init_descriptors(&sctx->images[i].desc,
1471                                     SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1472                                     null_image_descriptor, &ce_offset);
1473         }
1474
1475         si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1476                             4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1477
1478         assert(ce_offset <= 32768);
1479
1480         /* Set pipe_context functions. */
1481         sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1482         sctx->b.b.set_shader_images = si_set_shader_images;
1483         sctx->b.b.set_constant_buffer = si_set_constant_buffer;
1484         sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1485         sctx->b.b.set_sampler_views = si_set_sampler_views;
1486         sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1487         sctx->b.invalidate_buffer = si_invalidate_buffer;
1488
1489         /* Shader user data. */
1490         si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1491                      si_emit_graphics_shader_userdata);
1492
1493         /* Set default and immutable mappings. */
1494         si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1495         si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1496         si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1497         si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1498 }
1499
1500 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1501 {
1502         int i;
1503
1504         for (i = 0; i < SI_NUM_SHADERS; i++) {
1505                 if (!si_upload_descriptors(sctx, &sctx->const_buffers[i].desc,
1506                                            &sctx->shader_userdata.atom) ||
1507                     !si_upload_descriptors(sctx, &sctx->rw_buffers[i].desc,
1508                                            &sctx->shader_userdata.atom) ||
1509                     !si_upload_descriptors(sctx, &sctx->shader_buffers[i].desc,
1510                                            &sctx->shader_userdata.atom) ||
1511                     !si_upload_descriptors(sctx, &sctx->samplers[i].views.desc,
1512                                            &sctx->shader_userdata.atom) ||
1513                     !si_upload_descriptors(sctx, &sctx->images[i].desc,
1514                                            &sctx->shader_userdata.atom))
1515                         return false;
1516         }
1517         return si_upload_vertex_buffer_descriptors(sctx);
1518 }
1519
1520 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1521 {
1522         /* Does not update rw_buffers as that is not needed for compute shaders
1523          * and the input buffer is using the same SGPR's anyway.
1524          */
1525         return si_upload_descriptors(sctx,
1526                         &sctx->const_buffers[PIPE_SHADER_COMPUTE].desc, NULL) &&
1527                si_upload_descriptors(sctx,
1528                        &sctx->shader_buffers[PIPE_SHADER_COMPUTE].desc, NULL) &&
1529                si_upload_descriptors(sctx,
1530                        &sctx->samplers[PIPE_SHADER_COMPUTE].views.desc, NULL) &&
1531                si_upload_descriptors(sctx,
1532                        &sctx->images[PIPE_SHADER_COMPUTE].desc,  NULL);
1533 }
1534
1535 void si_release_all_descriptors(struct si_context *sctx)
1536 {
1537         int i;
1538
1539         for (i = 0; i < SI_NUM_SHADERS; i++) {
1540                 si_release_buffer_resources(&sctx->const_buffers[i]);
1541                 si_release_buffer_resources(&sctx->rw_buffers[i]);
1542                 si_release_buffer_resources(&sctx->shader_buffers[i]);
1543                 si_release_sampler_views(&sctx->samplers[i].views);
1544                 si_release_image_views(&sctx->images[i]);
1545         }
1546         si_release_descriptors(&sctx->vertex_buffers);
1547 }
1548
1549 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1550 {
1551         int i;
1552
1553         for (i = 0; i < SI_NUM_SHADERS; i++) {
1554                 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1555                 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers[i]);
1556                 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1557                 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1558                 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1559         }
1560         si_vertex_buffers_begin_new_cs(sctx);
1561         si_shader_userdata_begin_new_cs(sctx);
1562 }