2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_screen.h"
33 #include "util/u_video.h"
34 #include "compiler/nir/nir.h"
36 #include <sys/utsname.h>
38 static const char *si_get_vendor(struct pipe_screen *pscreen)
40 /* Don't change this. Games such as Alien Isolation are broken if this
41 * returns "Advanced Micro Devices, Inc."
46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
53 if (!ws->get_chip_name)
55 return ws->get_chip_name(ws);
58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
60 struct si_screen *sscreen = (struct si_screen *)pscreen;
63 /* Supported features (boolean caps). */
64 case PIPE_CAP_ACCELERATED:
65 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
66 case PIPE_CAP_ANISOTROPIC_FILTER:
67 case PIPE_CAP_POINT_SPRITE:
68 case PIPE_CAP_OCCLUSION_QUERY:
69 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
70 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
71 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
72 case PIPE_CAP_TEXTURE_SWIZZLE:
73 case PIPE_CAP_DEPTH_CLIP_DISABLE:
74 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
75 case PIPE_CAP_SHADER_STENCIL_EXPORT:
76 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
77 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
78 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
79 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
80 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
82 case PIPE_CAP_SEAMLESS_CUBE_MAP:
83 case PIPE_CAP_PRIMITIVE_RESTART:
84 case PIPE_CAP_CONDITIONAL_RENDER:
85 case PIPE_CAP_TEXTURE_BARRIER:
86 case PIPE_CAP_INDEP_BLEND_ENABLE:
87 case PIPE_CAP_INDEP_BLEND_FUNC:
88 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
89 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
90 case PIPE_CAP_START_INSTANCE:
91 case PIPE_CAP_NPOT_TEXTURES:
92 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
93 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
94 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
95 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
96 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
97 case PIPE_CAP_TGSI_INSTANCEID:
98 case PIPE_CAP_COMPUTE:
99 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
100 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
101 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
102 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
103 case PIPE_CAP_CUBE_MAP_ARRAY:
104 case PIPE_CAP_SAMPLE_SHADING:
105 case PIPE_CAP_DRAW_INDIRECT:
106 case PIPE_CAP_CLIP_HALFZ:
107 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
108 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
109 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
110 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
111 case PIPE_CAP_TGSI_TEXCOORD:
112 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
113 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
114 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
115 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
116 case PIPE_CAP_SHAREABLE_SHADERS:
117 case PIPE_CAP_DEPTH_BOUNDS_TEST:
118 case PIPE_CAP_SAMPLER_VIEW_TARGET:
119 case PIPE_CAP_TEXTURE_QUERY_LOD:
120 case PIPE_CAP_TEXTURE_GATHER_SM5:
121 case PIPE_CAP_TGSI_TXQS:
122 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
123 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
124 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
125 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
126 case PIPE_CAP_INVALIDATE_BUFFER:
127 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
128 case PIPE_CAP_QUERY_BUFFER_OBJECT:
129 case PIPE_CAP_QUERY_MEMORY_INFO:
130 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
131 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
132 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
133 case PIPE_CAP_GENERATE_MIPMAP:
134 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
135 case PIPE_CAP_STRING_MARKER:
136 case PIPE_CAP_CLEAR_TEXTURE:
137 case PIPE_CAP_CULL_DISTANCE:
138 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
139 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
140 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
141 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
142 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
143 case PIPE_CAP_DOUBLES:
144 case PIPE_CAP_TGSI_TEX_TXF_LZ:
145 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
146 case PIPE_CAP_BINDLESS_TEXTURE:
147 case PIPE_CAP_QUERY_TIMESTAMP:
148 case PIPE_CAP_QUERY_TIME_ELAPSED:
149 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
150 case PIPE_CAP_QUERY_SO_OVERFLOW:
151 case PIPE_CAP_MEMOBJ:
152 case PIPE_CAP_LOAD_CONSTBUF:
154 case PIPE_CAP_INT64_DIVMOD:
155 case PIPE_CAP_TGSI_CLOCK:
156 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
157 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
158 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
159 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
160 case PIPE_CAP_TGSI_BALLOT:
161 case PIPE_CAP_TGSI_VOTE:
162 case PIPE_CAP_TGSI_FS_FBFETCH:
165 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
166 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
168 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
169 return sscreen->info.has_gpu_reset_status_query ||
170 sscreen->info.has_gpu_reset_counter_query;
172 case PIPE_CAP_TEXTURE_MULTISAMPLE:
173 return sscreen->info.has_2d_tiling;
175 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
176 return SI_MAP_BUFFER_ALIGNMENT;
178 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
179 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
180 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
181 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
182 case PIPE_CAP_MAX_VERTEX_STREAMS:
183 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
184 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
187 case PIPE_CAP_GLSL_FEATURE_LEVEL:
188 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
189 if (sscreen->info.has_indirect_compute_dispatch)
193 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
194 /* Optimal number for good TexSubImage performance on Polaris10. */
195 return 64 * 1024 * 1024;
197 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
198 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
199 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
201 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
202 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
203 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
204 return !sscreen->info.has_unaligned_shader_loads;
206 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
207 return sscreen->info.has_sparse_vm_mappings ?
208 RADEON_SPARSE_PAGE_SIZE : 0;
210 case PIPE_CAP_PACKED_UNIFORMS:
211 if (sscreen->debug_flags & DBG(NIR))
215 /* Unsupported features. */
216 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
217 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
218 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
219 case PIPE_CAP_USER_VERTEX_BUFFERS:
220 case PIPE_CAP_FAKE_SW_MSAA:
221 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
222 case PIPE_CAP_VERTEXID_NOBASE:
223 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
224 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
226 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
227 case PIPE_CAP_POST_DEPTH_COVERAGE:
228 case PIPE_CAP_TILE_RASTER_ORDER:
229 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
230 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
231 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
232 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
233 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
234 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
235 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
236 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
237 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
240 case PIPE_CAP_FENCE_SIGNAL:
241 return sscreen->info.has_syncobj;
243 case PIPE_CAP_CONSTBUF0_FLAGS:
244 return SI_RESOURCE_FLAG_32BIT;
246 case PIPE_CAP_NATIVE_FENCE_FD:
247 return sscreen->info.has_fence_to_handle;
249 case PIPE_CAP_DRAW_PARAMETERS:
250 case PIPE_CAP_MULTI_DRAW_INDIRECT:
251 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
252 return sscreen->has_draw_indirect_multi;
254 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
257 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
258 return sscreen->info.chip_class <= VI ?
259 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
262 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
263 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
266 /* Geometry shader output. */
267 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
269 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
271 case PIPE_CAP_MAX_GS_INVOCATIONS:
272 /* The closed driver exposes 127, but 125 is the greatest
273 * number that works. */
276 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
280 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
281 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
282 return 15; /* 16384 */
283 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
284 /* textures support 8192, but layered rendering supports 2048 */
286 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
287 /* textures support 8192, but layered rendering supports 2048 */
290 /* Viewports and render targets. */
291 case PIPE_CAP_MAX_VIEWPORTS:
292 return SI_MAX_VIEWPORTS;
293 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
294 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
295 case PIPE_CAP_MAX_RENDER_TARGETS:
297 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
298 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
300 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
301 case PIPE_CAP_MIN_TEXEL_OFFSET:
304 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
305 case PIPE_CAP_MAX_TEXEL_OFFSET:
308 case PIPE_CAP_ENDIANNESS:
309 return PIPE_ENDIAN_LITTLE;
311 case PIPE_CAP_VENDOR_ID:
312 return ATI_VENDOR_ID;
313 case PIPE_CAP_DEVICE_ID:
314 return sscreen->info.pci_id;
315 case PIPE_CAP_VIDEO_MEMORY:
316 return sscreen->info.vram_size >> 20;
317 case PIPE_CAP_PCI_GROUP:
318 return sscreen->info.pci_domain;
319 case PIPE_CAP_PCI_BUS:
320 return sscreen->info.pci_bus;
321 case PIPE_CAP_PCI_DEVICE:
322 return sscreen->info.pci_dev;
323 case PIPE_CAP_PCI_FUNCTION:
324 return sscreen->info.pci_func;
327 return u_pipe_screen_get_param_defaults(pscreen, param);
331 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
334 case PIPE_CAPF_MAX_LINE_WIDTH:
335 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
336 /* This depends on the quant mode, though the precise interactions
339 case PIPE_CAPF_MAX_POINT_WIDTH:
340 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
341 return SI_MAX_POINT_SIZE;
342 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
344 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
346 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
347 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
348 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
354 static int si_get_shader_param(struct pipe_screen* pscreen,
355 enum pipe_shader_type shader,
356 enum pipe_shader_cap param)
358 struct si_screen *sscreen = (struct si_screen *)pscreen;
362 case PIPE_SHADER_FRAGMENT:
363 case PIPE_SHADER_VERTEX:
364 case PIPE_SHADER_GEOMETRY:
365 case PIPE_SHADER_TESS_CTRL:
366 case PIPE_SHADER_TESS_EVAL:
368 case PIPE_SHADER_COMPUTE:
370 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
371 int ir = 1 << PIPE_SHADER_IR_NATIVE;
373 if (sscreen->info.has_indirect_compute_dispatch)
374 ir |= 1 << PIPE_SHADER_IR_TGSI;
379 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
380 uint64_t max_const_buffer_size;
381 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
382 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
383 &max_const_buffer_size);
384 return MIN2(max_const_buffer_size, INT_MAX);
387 /* If compute shaders don't require a special value
388 * for this cap, we can return the same value we
389 * do for other shader types. */
399 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
400 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
401 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
402 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
403 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
405 case PIPE_SHADER_CAP_MAX_INPUTS:
406 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
407 case PIPE_SHADER_CAP_MAX_OUTPUTS:
408 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
409 case PIPE_SHADER_CAP_MAX_TEMPS:
410 return 256; /* Max native temporaries. */
411 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
412 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
413 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
414 return SI_NUM_CONST_BUFFERS;
415 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
416 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
417 return SI_NUM_SAMPLERS;
418 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
419 return SI_NUM_SHADER_BUFFERS;
420 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
421 return SI_NUM_IMAGES;
422 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
423 if (sscreen->debug_flags & DBG(NIR))
426 case PIPE_SHADER_CAP_PREFERRED_IR:
427 if (sscreen->debug_flags & DBG(NIR))
428 return PIPE_SHADER_IR_NIR;
429 return PIPE_SHADER_IR_TGSI;
430 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
433 /* Supported boolean features. */
434 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
435 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
436 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
437 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
438 case PIPE_SHADER_CAP_INTEGERS:
439 case PIPE_SHADER_CAP_INT64_ATOMICS:
440 case PIPE_SHADER_CAP_FP16:
441 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
442 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
443 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
444 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
445 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
446 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
449 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
450 /* TODO: Indirect indexing of GS inputs is unimplemented. */
451 if (shader == PIPE_SHADER_GEOMETRY)
454 if (shader == PIPE_SHADER_VERTEX &&
455 !sscreen->llvm_has_working_vgpr_indexing)
458 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
459 * This means we don't support INTERP instructions with
460 * indirect indexing on inputs.
462 if (shader == PIPE_SHADER_FRAGMENT &&
463 !sscreen->llvm_has_working_vgpr_indexing &&
467 /* TCS and TES load inputs directly from LDS or offchip
468 * memory, so indirect indexing is always supported.
469 * PS has to support indirect indexing, because we can't
470 * lower that to TEMPs for INTERP instructions.
474 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
475 return sscreen->llvm_has_working_vgpr_indexing ||
476 /* TCS stores outputs directly to memory. */
477 shader == PIPE_SHADER_TESS_CTRL;
479 /* Unsupported boolean features. */
480 case PIPE_SHADER_CAP_SUBROUTINES:
481 case PIPE_SHADER_CAP_SUPPORTED_IRS:
482 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
483 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
485 case PIPE_SHADER_CAP_SCALAR_ISA:
491 static const struct nir_shader_compiler_options nir_options = {
493 .lower_flrp32 = true,
494 .lower_flrp64 = true,
500 .lower_pack_snorm_2x16 = true,
501 .lower_pack_snorm_4x8 = true,
502 .lower_pack_unorm_2x16 = true,
503 .lower_pack_unorm_4x8 = true,
504 .lower_unpack_snorm_2x16 = true,
505 .lower_unpack_snorm_4x8 = true,
506 .lower_unpack_unorm_2x16 = true,
507 .lower_unpack_unorm_4x8 = true,
508 .lower_extract_byte = true,
509 .lower_extract_word = true,
510 .max_unroll_iterations = 32,
511 .native_integers = true,
515 si_get_compiler_options(struct pipe_screen *screen,
516 enum pipe_shader_ir ir,
517 enum pipe_shader_type shader)
519 assert(ir == PIPE_SHADER_IR_NIR);
523 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
525 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
528 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
530 struct si_screen *sscreen = (struct si_screen *)pscreen;
532 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
535 static const char* si_get_name(struct pipe_screen *pscreen)
537 struct si_screen *sscreen = (struct si_screen*)pscreen;
539 return sscreen->renderer_string;
542 static int si_get_video_param_no_decode(struct pipe_screen *screen,
543 enum pipe_video_profile profile,
544 enum pipe_video_entrypoint entrypoint,
545 enum pipe_video_cap param)
548 case PIPE_VIDEO_CAP_SUPPORTED:
549 return vl_profile_supported(screen, profile, entrypoint);
550 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
552 case PIPE_VIDEO_CAP_MAX_WIDTH:
553 case PIPE_VIDEO_CAP_MAX_HEIGHT:
554 return vl_video_buffer_max_size(screen);
555 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
556 return PIPE_FORMAT_NV12;
557 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
559 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
561 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
563 case PIPE_VIDEO_CAP_MAX_LEVEL:
564 return vl_level_supported(screen, profile);
570 static int si_get_video_param(struct pipe_screen *screen,
571 enum pipe_video_profile profile,
572 enum pipe_video_entrypoint entrypoint,
573 enum pipe_video_cap param)
575 struct si_screen *sscreen = (struct si_screen *)screen;
576 enum pipe_video_format codec = u_reduce_video_profile(profile);
578 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
580 case PIPE_VIDEO_CAP_SUPPORTED:
581 return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
582 (si_vce_is_fw_version_supported(sscreen) ||
583 sscreen->info.family == CHIP_RAVEN ||
584 sscreen->info.family == CHIP_RAVEN2)) ||
585 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
586 (sscreen->info.family == CHIP_RAVEN ||
587 sscreen->info.family == CHIP_RAVEN2 ||
588 si_radeon_uvd_enc_supported(sscreen)));
589 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
591 case PIPE_VIDEO_CAP_MAX_WIDTH:
592 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
593 case PIPE_VIDEO_CAP_MAX_HEIGHT:
594 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
595 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
596 return PIPE_FORMAT_NV12;
597 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
599 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
601 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
603 case PIPE_VIDEO_CAP_STACKED_FRAMES:
604 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
611 case PIPE_VIDEO_CAP_SUPPORTED:
613 case PIPE_VIDEO_FORMAT_MPEG12:
614 return profile != PIPE_VIDEO_PROFILE_MPEG1;
615 case PIPE_VIDEO_FORMAT_MPEG4:
617 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
618 if ((sscreen->info.family == CHIP_POLARIS10 ||
619 sscreen->info.family == CHIP_POLARIS11) &&
620 sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
621 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
625 case PIPE_VIDEO_FORMAT_VC1:
627 case PIPE_VIDEO_FORMAT_HEVC:
628 /* Carrizo only supports HEVC Main */
629 if (sscreen->info.family >= CHIP_STONEY)
630 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
631 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
632 else if (sscreen->info.family >= CHIP_CARRIZO)
633 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
635 case PIPE_VIDEO_FORMAT_JPEG:
636 if (sscreen->info.family == CHIP_RAVEN ||
637 sscreen->info.family == CHIP_RAVEN2)
639 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
641 if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
642 RVID_ERR("No MJPEG support for the kernel version\n");
646 case PIPE_VIDEO_FORMAT_VP9:
647 if (sscreen->info.family < CHIP_RAVEN)
653 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
655 case PIPE_VIDEO_CAP_MAX_WIDTH:
656 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
657 case PIPE_VIDEO_CAP_MAX_HEIGHT:
658 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
659 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
660 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
661 profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
662 return PIPE_FORMAT_P016;
664 return PIPE_FORMAT_NV12;
666 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
667 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
668 enum pipe_video_format format = u_reduce_video_profile(profile);
670 if (format == PIPE_VIDEO_FORMAT_HEVC)
671 return false; //The firmware doesn't support interlaced HEVC.
672 else if (format == PIPE_VIDEO_FORMAT_JPEG)
674 else if (format == PIPE_VIDEO_FORMAT_VP9)
678 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
680 case PIPE_VIDEO_CAP_MAX_LEVEL:
682 case PIPE_VIDEO_PROFILE_MPEG1:
684 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
685 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
687 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
689 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
691 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
693 case PIPE_VIDEO_PROFILE_VC1_MAIN:
695 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
697 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
698 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
699 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
700 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
701 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
702 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
712 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
713 enum pipe_format format,
714 enum pipe_video_profile profile,
715 enum pipe_video_entrypoint entrypoint)
717 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
718 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
719 return (format == PIPE_FORMAT_NV12) ||
720 (format == PIPE_FORMAT_P016);
722 /* we can only handle this one with UVD */
723 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
724 return format == PIPE_FORMAT_NV12;
726 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
729 static unsigned get_max_threads_per_block(struct si_screen *screen,
730 enum pipe_shader_ir ir_type)
732 if (ir_type == PIPE_SHADER_IR_NATIVE)
735 /* Only 16 waves per thread-group on gfx9. */
736 if (screen->info.chip_class >= GFX9)
739 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
745 static int si_get_compute_param(struct pipe_screen *screen,
746 enum pipe_shader_ir ir_type,
747 enum pipe_compute_cap param,
750 struct si_screen *sscreen = (struct si_screen *)screen;
752 //TODO: select these params by asic
754 case PIPE_COMPUTE_CAP_IR_TARGET: {
755 const char *gpu, *triple;
757 triple = "amdgcn-mesa-mesa3d";
758 gpu = ac_get_llvm_processor_name(sscreen->info.family);
760 sprintf(ret, "%s-%s", gpu, triple);
762 /* +2 for dash and terminating NIL byte */
763 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
765 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
767 uint64_t *grid_dimension = ret;
768 grid_dimension[0] = 3;
770 return 1 * sizeof(uint64_t);
772 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
774 uint64_t *grid_size = ret;
775 grid_size[0] = 65535;
776 grid_size[1] = 65535;
777 grid_size[2] = 65535;
779 return 3 * sizeof(uint64_t) ;
781 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
783 uint64_t *block_size = ret;
784 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
785 block_size[0] = threads_per_block;
786 block_size[1] = threads_per_block;
787 block_size[2] = threads_per_block;
789 return 3 * sizeof(uint64_t);
791 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
793 uint64_t *max_threads_per_block = ret;
794 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
796 return sizeof(uint64_t);
797 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
799 uint32_t *address_bits = ret;
800 address_bits[0] = 64;
802 return 1 * sizeof(uint32_t);
804 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
806 uint64_t *max_global_size = ret;
807 uint64_t max_mem_alloc_size;
809 si_get_compute_param(screen, ir_type,
810 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
811 &max_mem_alloc_size);
813 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
814 * 1/4 of the MAX_GLOBAL_SIZE. Since the
815 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
816 * make sure we never report more than
817 * 4 * MAX_MEM_ALLOC_SIZE.
819 *max_global_size = MIN2(4 * max_mem_alloc_size,
820 MAX2(sscreen->info.gart_size,
821 sscreen->info.vram_size));
823 return sizeof(uint64_t);
825 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
827 uint64_t *max_local_size = ret;
828 /* Value reported by the closed source driver. */
829 *max_local_size = 32768;
831 return sizeof(uint64_t);
833 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
835 uint64_t *max_input_size = ret;
836 /* Value reported by the closed source driver. */
837 *max_input_size = 1024;
839 return sizeof(uint64_t);
841 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
843 uint64_t *max_mem_alloc_size = ret;
845 *max_mem_alloc_size = sscreen->info.max_alloc_size;
847 return sizeof(uint64_t);
849 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
851 uint32_t *max_clock_frequency = ret;
852 *max_clock_frequency = sscreen->info.max_shader_clock;
854 return sizeof(uint32_t);
856 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
858 uint32_t *max_compute_units = ret;
859 *max_compute_units = sscreen->info.num_good_compute_units;
861 return sizeof(uint32_t);
863 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
865 uint32_t *images_supported = ret;
866 *images_supported = 0;
868 return sizeof(uint32_t);
869 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
871 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
873 uint32_t *subgroup_size = ret;
876 return sizeof(uint32_t);
877 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
879 uint64_t *max_variable_threads_per_block = ret;
880 if (ir_type == PIPE_SHADER_IR_NATIVE)
881 *max_variable_threads_per_block = 0;
883 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
885 return sizeof(uint64_t);
888 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
892 static uint64_t si_get_timestamp(struct pipe_screen *screen)
894 struct si_screen *sscreen = (struct si_screen*)screen;
896 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
897 sscreen->info.clock_crystal_freq;
900 static void si_query_memory_info(struct pipe_screen *screen,
901 struct pipe_memory_info *info)
903 struct si_screen *sscreen = (struct si_screen*)screen;
904 struct radeon_winsys *ws = sscreen->ws;
905 unsigned vram_usage, gtt_usage;
907 info->total_device_memory = sscreen->info.vram_size / 1024;
908 info->total_staging_memory = sscreen->info.gart_size / 1024;
910 /* The real TTM memory usage is somewhat random, because:
912 * 1) TTM delays freeing memory, because it can only free it after
915 * 2) The memory usage can be really low if big VRAM evictions are
916 * taking place, but the real usage is well above the size of VRAM.
918 * Instead, return statistics of this process.
920 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
921 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
923 info->avail_device_memory =
924 vram_usage <= info->total_device_memory ?
925 info->total_device_memory - vram_usage : 0;
926 info->avail_staging_memory =
927 gtt_usage <= info->total_staging_memory ?
928 info->total_staging_memory - gtt_usage : 0;
930 info->device_memory_evicted =
931 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
933 if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
934 info->nr_device_memory_evictions =
935 ws->query_value(ws, RADEON_NUM_EVICTIONS);
937 /* Just return the number of evicted 64KB pages. */
938 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
941 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
943 struct si_screen *sscreen = (struct si_screen*)pscreen;
945 return sscreen->disk_shader_cache;
948 static void si_init_renderer_string(struct si_screen *sscreen)
950 struct radeon_winsys *ws = sscreen->ws;
951 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
952 struct utsname uname_data;
954 const char *marketing_name = si_get_marketing_name(ws);
956 if (marketing_name) {
957 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
958 snprintf(second_name, sizeof(second_name), "%s, ",
961 snprintf(first_name, sizeof(first_name), "AMD %s",
965 if (uname(&uname_data) == 0)
966 snprintf(kernel_version, sizeof(kernel_version),
967 ", %s", uname_data.release);
969 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
970 "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
971 first_name, second_name, sscreen->info.drm_major,
972 sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
974 (HAVE_LLVM >> 8) & 0xff,
976 MESA_LLVM_VERSION_PATCH);
979 void si_init_screen_get_functions(struct si_screen *sscreen)
981 sscreen->b.get_name = si_get_name;
982 sscreen->b.get_vendor = si_get_vendor;
983 sscreen->b.get_device_vendor = si_get_device_vendor;
984 sscreen->b.get_param = si_get_param;
985 sscreen->b.get_paramf = si_get_paramf;
986 sscreen->b.get_compute_param = si_get_compute_param;
987 sscreen->b.get_timestamp = si_get_timestamp;
988 sscreen->b.get_shader_param = si_get_shader_param;
989 sscreen->b.get_compiler_options = si_get_compiler_options;
990 sscreen->b.get_device_uuid = si_get_device_uuid;
991 sscreen->b.get_driver_uuid = si_get_driver_uuid;
992 sscreen->b.query_memory_info = si_query_memory_info;
993 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
995 if (sscreen->info.has_hw_decode) {
996 sscreen->b.get_video_param = si_get_video_param;
997 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
999 sscreen->b.get_video_param = si_get_video_param_no_decode;
1000 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1003 si_init_renderer_string(sscreen);