src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_uvd.h"
  29 #include "util/u_memory.h"
  30 #include "vl/vl_decoder.h"
  31
  32 /*
  33  * pipe_context
  34  */
  35 static void si_destroy_context(struct pipe_context *context)
  36 {
  37         struct si_context *sctx = (struct si_context *)context;
  38
  39         si_release_all_descriptors(sctx);
  40
  41         pipe_resource_reference(&sctx->esgs_ring, NULL);
  42         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  43         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  44         r600_resource_reference(&sctx->border_color_table, NULL);
  45
  46         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  47         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  48         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  49
  50         if (sctx->dummy_pixel_shader) {
  51                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  52         }
  53         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  54         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  55         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  56         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  57         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  58
  59         util_blitter_destroy(sctx->blitter);
  60
  61         si_pm4_cleanup(sctx);
  62
  63         r600_common_context_cleanup(&sctx->b);
  64         FREE(sctx);
  65 }
  66
  67 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  68 {
  69         struct si_context *sctx = CALLOC_STRUCT(si_context);
  70         struct si_screen* sscreen = (struct si_screen *)screen;
  71         struct radeon_winsys *ws = sscreen->b.ws;
  72         int shader, i;
  73
  74         if (sctx == NULL)
  75                 return NULL;
  76
  77         sctx->b.b.screen = screen; /* this must be set first */
  78         sctx->b.b.priv = priv;
  79         sctx->b.b.destroy = si_destroy_context;
  80         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  81
  82         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  83                 goto fail;
  84
  85         si_init_blit_functions(sctx);
  86         si_init_compute_functions(sctx);
  87
  88         if (sscreen->b.info.has_uvd) {
  89                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
  90                 sctx->b.b.create_video_buffer = si_video_buffer_create;
  91         } else {
  92                 sctx->b.b.create_video_codec = vl_create_decoder;
  93                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
  94         }
  95
  96         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
  97                                              sctx, sscreen->b.trace_bo ?
  98                                                 sscreen->b.trace_bo->cs_buf : NULL);
  99         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 100
 101         si_init_all_descriptors(sctx);
 102
 103         /* Initialize cache_flush. */
 104         sctx->cache_flush = si_atom_cache_flush;
 105         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 106
 107         sctx->msaa_config = si_atom_msaa_config;
 108         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 109
 110         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 111         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 112
 113         switch (sctx->b.chip_class) {
 114         case SI:
 115         case CIK:
 116                 si_init_state_functions(sctx);
 117                 si_init_config(sctx);
 118                 break;
 119         default:
 120                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 121                 goto fail;
 122         }
 123
 124         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 125                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 126
 127         sctx->blitter = util_blitter_create(&sctx->b.b);
 128         if (sctx->blitter == NULL)
 129                 goto fail;
 130         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 131
 132         /* these must be last */
 133         si_begin_new_cs(sctx);
 134         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 135
 136         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 137          * with a NULL buffer). We need to use a dummy buffer instead. */
 138         if (sctx->b.chip_class == CIK) {
 139                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 140                                                                  PIPE_USAGE_DEFAULT, 16);
 141                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 142
 143                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 144                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 145                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 146                                                               &sctx->null_const_buf);
 147                         }
 148                 }
 149
 150                 /* Clear the NULL constant buffer, because loads should return zeros. */
 151                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 152                                      sctx->null_const_buf.buffer->width0, 0);
 153         }
 154
 155         return &sctx->b.b;
 156 fail:
 157         si_destroy_context(&sctx->b.b);
 158         return NULL;
 159 }
 160
 161 /*
 162  * pipe_screen
 163  */
 164
 165 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 166 {
 167         struct si_screen *sscreen = (struct si_screen *)pscreen;
 168
 169         switch (param) {
 170         /* Supported features (boolean caps). */
 171         case PIPE_CAP_TWO_SIDED_STENCIL:
 172         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 173         case PIPE_CAP_ANISOTROPIC_FILTER:
 174         case PIPE_CAP_POINT_SPRITE:
 175         case PIPE_CAP_OCCLUSION_QUERY:
 176         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 177         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 178         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 179         case PIPE_CAP_TEXTURE_SWIZZLE:
 180         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 181         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 182         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 183         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 184         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 185         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 186         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 187         case PIPE_CAP_SM3:
 188         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 189         case PIPE_CAP_PRIMITIVE_RESTART:
 190         case PIPE_CAP_CONDITIONAL_RENDER:
 191         case PIPE_CAP_TEXTURE_BARRIER:
 192         case PIPE_CAP_INDEP_BLEND_ENABLE:
 193         case PIPE_CAP_INDEP_BLEND_FUNC:
 194         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 195         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 196         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 197         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 199         case PIPE_CAP_USER_INDEX_BUFFERS:
 200         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 201         case PIPE_CAP_START_INSTANCE:
 202         case PIPE_CAP_NPOT_TEXTURES:
 203         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 204         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 205         case PIPE_CAP_TGSI_INSTANCEID:
 206         case PIPE_CAP_COMPUTE:
 207         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 209         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 210         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 211         case PIPE_CAP_CUBE_MAP_ARRAY:
 212         case PIPE_CAP_SAMPLE_SHADING:
 213         case PIPE_CAP_DRAW_INDIRECT:
 214         case PIPE_CAP_CLIP_HALFZ:
 215         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 216                 return 1;
 217
 218         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 219                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 220                 return sscreen->b.chip_class < CIK ||
 221                        sscreen->b.info.drm_minor >= 35;
 222
 223         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 224                 return R600_MAP_BUFFER_ALIGNMENT;
 225
 226         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 227         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 228                 return 4;
 229
 230         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 231                 return 330;
 232
 233         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 234                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 235
 236         case PIPE_CAP_TEXTURE_QUERY_LOD:
 237         case PIPE_CAP_TEXTURE_GATHER_SM5:
 238                 return HAVE_LLVM >= 0x0305;
 239         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 240                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 241
 242         /* Unsupported features. */
 243         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 244         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 245         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 246         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 247         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 248         case PIPE_CAP_USER_VERTEX_BUFFERS:
 249         case PIPE_CAP_TGSI_TEXCOORD:
 250         case PIPE_CAP_FAKE_SW_MSAA:
 251         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 252         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 253         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 254         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 255                 return 0;
 256
 257         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 258                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 259
 260         /* Stream output. */
 261         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 262                 return sscreen->b.has_streamout ? 4 : 0;
 263         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 264                 return sscreen->b.has_streamout ? 1 : 0;
 265         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 266         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 267                 return sscreen->b.has_streamout ? 32*4 : 0;
 268
 269         /* Geometry shader output. */
 270         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 271                 return 1024;
 272         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 273                 return 4095;
 274         case PIPE_CAP_MAX_VERTEX_STREAMS:
 275                 return 1;
 276
 277         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 278                 return 2048;
 279
 280         /* Texturing. */
 281         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 282         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 283                 return 15; /* 16384 */
 284         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 285                 /* textures support 8192, but layered rendering supports 2048 */
 286                 return 12;
 287         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 288                 /* textures support 8192, but layered rendering supports 2048 */
 289                 return 2048;
 290
 291         /* Render targets. */
 292         case PIPE_CAP_MAX_RENDER_TARGETS:
 293                 return 8;
 294
 295         case PIPE_CAP_MAX_VIEWPORTS:
 296                 return 1;
 297
 298         /* Timer queries, present when the clock frequency is non zero. */
 299         case PIPE_CAP_QUERY_TIMESTAMP:
 300         case PIPE_CAP_QUERY_TIME_ELAPSED:
 301                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 302
 303         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 304         case PIPE_CAP_MIN_TEXEL_OFFSET:
 305                 return -32;
 306
 307         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 308         case PIPE_CAP_MAX_TEXEL_OFFSET:
 309                 return 31;
 310
 311         case PIPE_CAP_ENDIANNESS:
 312                 return PIPE_ENDIAN_LITTLE;
 313
 314         case PIPE_CAP_VENDOR_ID:
 315                 return 0x1002;
 316         case PIPE_CAP_DEVICE_ID:
 317                 return sscreen->b.info.pci_id;
 318         case PIPE_CAP_ACCELERATED:
 319                 return 1;
 320         case PIPE_CAP_VIDEO_MEMORY:
 321                 return sscreen->b.info.vram_size >> 20;
 322         case PIPE_CAP_UMA:
 323                 return 0;
 324         }
 325         return 0;
 326 }
 327
 328 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 329 {
 330         switch(shader)
 331         {
 332         case PIPE_SHADER_FRAGMENT:
 333         case PIPE_SHADER_VERTEX:
 334         case PIPE_SHADER_GEOMETRY:
 335                 break;
 336         case PIPE_SHADER_COMPUTE:
 337                 switch (param) {
 338                 case PIPE_SHADER_CAP_PREFERRED_IR:
 339 #if HAVE_LLVM < 0x0306
 340                         return PIPE_SHADER_IR_LLVM;
 341 #else
 342                         return PIPE_SHADER_IR_NATIVE;
 343 #endif
 344                 case PIPE_SHADER_CAP_DOUBLES:
 345                         return 0; /* XXX: Enable doubles once the compiler can
 346                                      handle them. */
 347                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 348                         uint64_t max_const_buffer_size;
 349                         pscreen->get_compute_param(pscreen,
 350                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 351                                 &max_const_buffer_size);
 352                         return max_const_buffer_size;
 353                 }
 354                 default:
 355                         return 0;
 356                 }
 357         default:
 358                 /* TODO: support tessellation */
 359                 return 0;
 360         }
 361
 362         switch (param) {
 363         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 364         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 365         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 366         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 367                 return 16384;
 368         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 369                 return 32;
 370         case PIPE_SHADER_CAP_MAX_INPUTS:
 371                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 372         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 373                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 374         case PIPE_SHADER_CAP_MAX_TEMPS:
 375                 return 256; /* Max native temporaries. */
 376         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 377                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 378         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 379                 return SI_NUM_USER_CONST_BUFFERS;
 380         case PIPE_SHADER_CAP_MAX_PREDS:
 381                 return 0; /* FIXME */
 382         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 383                 return 1;
 384         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 385                 return 0;
 386         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 387                 /* Indirection of geometry shader input dimension is not
 388                  * handled yet
 389                  */
 390                 return shader < PIPE_SHADER_GEOMETRY;
 391         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 392         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 393         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 394                 return 1;
 395         case PIPE_SHADER_CAP_INTEGERS:
 396                 return 1;
 397         case PIPE_SHADER_CAP_SUBROUTINES:
 398                 return 0;
 399         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 400         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 401                 return 16;
 402         case PIPE_SHADER_CAP_PREFERRED_IR:
 403                 return PIPE_SHADER_IR_TGSI;
 404         case PIPE_SHADER_CAP_DOUBLES:
 405                 return 0;
 406         }
 407         return 0;
 408 }
 409
 410 static void si_destroy_screen(struct pipe_screen* pscreen)
 411 {
 412         struct si_screen *sscreen = (struct si_screen *)pscreen;
 413
 414         if (sscreen == NULL)
 415                 return;
 416
 417         if (!sscreen->b.ws->unref(sscreen->b.ws))
 418                 return;
 419
 420         r600_destroy_common_screen(&sscreen->b);
 421 }
 422
 423 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 424
 425 /* Initialize pipe config. This is especially important for GPUs
 426  * with 16 pipes and more where it's initialized incorrectly by
 427  * the TILING_CONFIG ioctl. */
 428 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 429 {
 430         unsigned mode2d;
 431
 432         /* This is okay, because there can be no 2D tiling without
 433          * the tile mode array, so we won't need the pipe config.
 434          * Return "success".
 435          */
 436         if (!sscreen->b.info.si_tile_mode_array_valid)
 437                 return true;
 438
 439         /* The same index is used for the 2D mode on CIK too. */
 440         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 441
 442         switch (G_009910_PIPE_CONFIG(mode2d)) {
 443         case V_02803C_ADDR_SURF_P2:
 444                 sscreen->b.tiling_info.num_channels = 2;
 445                 break;
 446         case V_02803C_X_ADDR_SURF_P4_8X16:
 447         case V_02803C_X_ADDR_SURF_P4_16X16:
 448         case V_02803C_X_ADDR_SURF_P4_16X32:
 449         case V_02803C_X_ADDR_SURF_P4_32X32:
 450                 sscreen->b.tiling_info.num_channels = 4;
 451                 break;
 452         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 453         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 454         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 455         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 456         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 457         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 458         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 459                 sscreen->b.tiling_info.num_channels = 8;
 460                 break;
 461         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 462         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 463                 sscreen->b.tiling_info.num_channels = 16;
 464                 break;
 465         default:
 466                 assert(0);
 467                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 468                         G_009910_PIPE_CONFIG(mode2d));
 469                 return false;
 470         }
 471         return true;
 472 }
 473
 474 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 475 {
 476         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 477         if (sscreen == NULL) {
 478                 return NULL;
 479         }
 480
 481         /* Set functions first. */
 482         sscreen->b.b.context_create = si_create_context;
 483         sscreen->b.b.destroy = si_destroy_screen;
 484         sscreen->b.b.get_param = si_get_param;
 485         sscreen->b.b.get_shader_param = si_get_shader_param;
 486         sscreen->b.b.is_format_supported = si_is_format_supported;
 487         sscreen->b.b.resource_create = r600_resource_create_common;
 488
 489         if (!r600_common_screen_init(&sscreen->b, ws) ||
 490             !si_initialize_pipe_config(sscreen)) {
 491                 FREE(sscreen);
 492                 return NULL;
 493         }
 494
 495         sscreen->b.has_cp_dma = true;
 496         sscreen->b.has_streamout = true;
 497
 498         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 499                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 500
 501         /* Create the auxiliary context. This must be done last. */
 502         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 503
 504         return &sscreen->b.b;
 505 }