2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader.h"
26 #include "si_public.h"
29 #include "radeon/radeon_llvm_emit.h"
30 #include "radeon/radeon_uvd.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "vl/vl_decoder.h"
38 static void si_destroy_context(struct pipe_context *context)
40 struct si_context *sctx = (struct si_context *)context;
43 si_release_all_descriptors(sctx);
45 if (sctx->ce_suballocator)
46 u_suballocator_destroy(sctx->ce_suballocator);
48 pipe_resource_reference(&sctx->esgs_ring, NULL);
49 pipe_resource_reference(&sctx->gsvs_ring, NULL);
50 pipe_resource_reference(&sctx->tf_ring, NULL);
51 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
52 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
53 r600_resource_reference(&sctx->border_color_buffer, NULL);
54 free(sctx->border_color_table);
55 r600_resource_reference(&sctx->scratch_buffer, NULL);
56 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
57 sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
59 si_pm4_free_state(sctx, sctx->init_config, ~0);
60 if (sctx->init_config_gs_rings)
61 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
62 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
63 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
65 if (sctx->fixed_func_tcs_shader.cso)
66 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
67 if (sctx->custom_dsa_flush)
68 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
69 if (sctx->custom_blend_resolve)
70 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
71 if (sctx->custom_blend_decompress)
72 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
73 if (sctx->custom_blend_fastclear)
74 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
75 if (sctx->custom_blend_dcc_decompress)
76 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
77 util_unreference_framebuffer_state(&sctx->framebuffer.state);
80 util_blitter_destroy(sctx->blitter);
82 r600_common_context_cleanup(&sctx->b);
84 LLVMDisposeTargetMachine(sctx->tm);
86 r600_resource_reference(&sctx->trace_buf, NULL);
87 r600_resource_reference(&sctx->last_trace_buf, NULL);
89 if (sctx->last_bo_list) {
90 for (i = 0; i < sctx->last_bo_count; i++)
91 pb_reference(&sctx->last_bo_list[i].buf, NULL);
92 free(sctx->last_bo_list);
97 static enum pipe_reset_status
98 si_amdgpu_get_reset_status(struct pipe_context *ctx)
100 struct si_context *sctx = (struct si_context *)ctx;
102 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
105 static struct pipe_context *si_create_context(struct pipe_screen *screen,
106 void *priv, unsigned flags)
108 struct si_context *sctx = CALLOC_STRUCT(si_context);
109 struct si_screen* sscreen = (struct si_screen *)screen;
110 struct radeon_winsys *ws = sscreen->b.ws;
111 LLVMTargetRef r600_target;
112 const char *triple = "amdgcn--";
118 if (sscreen->b.debug_flags & DBG_CHECK_VM)
119 flags |= PIPE_CONTEXT_DEBUG;
121 sctx->b.b.screen = screen; /* this must be set first */
122 sctx->b.b.priv = priv;
123 sctx->b.b.destroy = si_destroy_context;
124 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
125 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
126 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
128 if (!r600_common_context_init(&sctx->b, &sscreen->b))
131 if (sscreen->b.info.drm_major == 3)
132 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
134 si_init_blit_functions(sctx);
135 si_init_compute_functions(sctx);
136 si_init_cp_dma_functions(sctx);
137 si_init_debug_functions(sctx);
139 if (sscreen->b.info.has_uvd) {
140 sctx->b.b.create_video_codec = si_uvd_create_decoder;
141 sctx->b.b.create_video_buffer = si_video_buffer_create;
143 sctx->b.b.create_video_codec = vl_create_decoder;
144 sctx->b.b.create_video_buffer = vl_video_buffer_create;
147 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
148 si_context_gfx_flush, sctx);
150 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
151 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
155 if (ws->cs_add_const_preamble_ib) {
156 sctx->ce_preamble_ib =
157 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
159 if (!sctx->ce_preamble_ib)
163 sctx->ce_suballocator =
164 u_suballocator_create(&sctx->b.b, 1024 * 1024,
165 64, PIPE_BIND_CUSTOM,
166 PIPE_USAGE_DEFAULT, FALSE);
167 if (!sctx->ce_suballocator)
171 sctx->b.gfx.flush = si_context_gfx_flush;
174 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
175 sizeof(*sctx->border_color_table));
176 if (!sctx->border_color_table)
179 sctx->border_color_buffer = (struct r600_resource*)
180 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
181 SI_MAX_BORDER_COLORS *
182 sizeof(*sctx->border_color_table));
183 if (!sctx->border_color_buffer)
186 sctx->border_color_map =
187 ws->buffer_map(sctx->border_color_buffer->buf,
188 NULL, PIPE_TRANSFER_WRITE);
189 if (!sctx->border_color_map)
192 si_init_all_descriptors(sctx);
193 si_init_state_functions(sctx);
194 si_init_shader_functions(sctx);
196 if (sctx->b.chip_class >= CIK)
197 cik_init_sdma_functions(sctx);
199 si_init_dma_functions(sctx);
201 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
202 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
204 sctx->blitter = util_blitter_create(&sctx->b.b);
205 if (sctx->blitter == NULL)
207 sctx->blitter->draw_rectangle = r600_draw_rectangle;
209 sctx->sample_mask.sample_mask = 0xffff;
211 /* these must be last */
212 si_begin_new_cs(sctx);
213 r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
215 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
216 * with a NULL buffer). We need to use a dummy buffer instead. */
217 if (sctx->b.chip_class == CIK) {
218 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
219 PIPE_USAGE_DEFAULT, 16);
220 if (!sctx->null_const_buf.buffer)
222 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
224 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
225 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
226 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
227 &sctx->null_const_buf);
231 /* Clear the NULL constant buffer, because loads should return zeros. */
232 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
233 sctx->null_const_buf.buffer->width0, 0,
234 R600_COHERENCY_SHADER);
237 /* XXX: This is the maximum value allowed. I'm not sure how to compute
238 * this for non-cs shaders. Using the wrong value here can result in
239 * GPU lockups, but the maximum value seems to always work.
241 sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
243 /* Initialize LLVM TargetMachine */
244 r600_target = radeon_llvm_get_r600_target(triple);
245 sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
246 r600_get_llvm_processor_name(sscreen->b.family),
247 #if HAVE_LLVM >= 0x0308
248 sscreen->b.debug_flags & DBG_SI_SCHED ?
249 "+DumpCode,+vgpr-spilling,+si-scheduler" :
251 "+DumpCode,+vgpr-spilling",
252 LLVMCodeGenLevelDefault,
254 LLVMCodeModelDefault);
258 fprintf(stderr, "radeonsi: Failed to create a context.\n");
259 si_destroy_context(&sctx->b.b);
267 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
269 struct si_screen *sscreen = (struct si_screen *)pscreen;
272 /* Supported features (boolean caps). */
273 case PIPE_CAP_TWO_SIDED_STENCIL:
274 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
275 case PIPE_CAP_ANISOTROPIC_FILTER:
276 case PIPE_CAP_POINT_SPRITE:
277 case PIPE_CAP_OCCLUSION_QUERY:
278 case PIPE_CAP_TEXTURE_SHADOW_MAP:
279 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
280 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
281 case PIPE_CAP_TEXTURE_SWIZZLE:
282 case PIPE_CAP_DEPTH_CLIP_DISABLE:
283 case PIPE_CAP_SHADER_STENCIL_EXPORT:
284 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
285 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
286 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
287 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
288 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
290 case PIPE_CAP_SEAMLESS_CUBE_MAP:
291 case PIPE_CAP_PRIMITIVE_RESTART:
292 case PIPE_CAP_CONDITIONAL_RENDER:
293 case PIPE_CAP_TEXTURE_BARRIER:
294 case PIPE_CAP_INDEP_BLEND_ENABLE:
295 case PIPE_CAP_INDEP_BLEND_FUNC:
296 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
297 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
298 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
299 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
300 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
301 case PIPE_CAP_USER_INDEX_BUFFERS:
302 case PIPE_CAP_USER_CONSTANT_BUFFERS:
303 case PIPE_CAP_START_INSTANCE:
304 case PIPE_CAP_NPOT_TEXTURES:
305 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
306 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
307 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
308 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
309 case PIPE_CAP_TGSI_INSTANCEID:
310 case PIPE_CAP_COMPUTE:
311 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
312 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
313 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
314 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
315 case PIPE_CAP_CUBE_MAP_ARRAY:
316 case PIPE_CAP_SAMPLE_SHADING:
317 case PIPE_CAP_DRAW_INDIRECT:
318 case PIPE_CAP_CLIP_HALFZ:
319 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
320 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
321 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
322 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
323 case PIPE_CAP_TGSI_TEXCOORD:
324 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
325 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
326 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
327 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
328 case PIPE_CAP_SHAREABLE_SHADERS:
329 case PIPE_CAP_DEPTH_BOUNDS_TEST:
330 case PIPE_CAP_SAMPLER_VIEW_TARGET:
331 case PIPE_CAP_TEXTURE_QUERY_LOD:
332 case PIPE_CAP_TEXTURE_GATHER_SM5:
333 case PIPE_CAP_TGSI_TXQS:
334 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
335 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
336 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
337 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
338 case PIPE_CAP_INVALIDATE_BUFFER:
339 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
340 case PIPE_CAP_QUERY_MEMORY_INFO:
341 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
342 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
343 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
346 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
347 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
349 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
350 return (sscreen->b.info.drm_major == 2 &&
351 sscreen->b.info.drm_minor >= 43) ||
352 sscreen->b.info.drm_major == 3;
354 case PIPE_CAP_TEXTURE_MULTISAMPLE:
355 /* 2D tiling on CIK is supported since DRM 2.35.0 */
356 return sscreen->b.chip_class < CIK ||
357 (sscreen->b.info.drm_major == 2 &&
358 sscreen->b.info.drm_minor >= 35) ||
359 sscreen->b.info.drm_major == 3;
361 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
362 return R600_MAP_BUFFER_ALIGNMENT;
364 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
365 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
366 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
368 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
369 return HAVE_LLVM >= 0x0309 ? 4 : 0;
371 case PIPE_CAP_GLSL_FEATURE_LEVEL:
372 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
373 PIPE_SHADER_CAP_SUPPORTED_IRS) &
374 (1 << PIPE_SHADER_IR_TGSI))
376 return HAVE_LLVM >= 0x0309 ? 420 :
377 HAVE_LLVM >= 0x0307 ? 410 : 330;
379 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
380 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
382 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
385 /* Unsupported features. */
386 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
387 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
388 case PIPE_CAP_USER_VERTEX_BUFFERS:
389 case PIPE_CAP_FAKE_SW_MSAA:
390 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
391 case PIPE_CAP_VERTEXID_NOBASE:
392 case PIPE_CAP_CLEAR_TEXTURE:
393 case PIPE_CAP_DRAW_PARAMETERS:
394 case PIPE_CAP_MULTI_DRAW_INDIRECT:
395 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
396 case PIPE_CAP_GENERATE_MIPMAP:
397 case PIPE_CAP_STRING_MARKER:
398 case PIPE_CAP_QUERY_BUFFER_OBJECT:
399 case PIPE_CAP_CULL_DISTANCE:
400 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
403 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
406 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
407 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
410 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
411 return sscreen->b.has_streamout ? 4 : 0;
412 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
413 return sscreen->b.has_streamout ? 1 : 0;
414 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
415 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
416 return sscreen->b.has_streamout ? 32*4 : 0;
418 /* Geometry shader output. */
419 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
421 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
423 case PIPE_CAP_MAX_VERTEX_STREAMS:
426 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
430 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
431 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
432 return 15; /* 16384 */
433 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
434 /* textures support 8192, but layered rendering supports 2048 */
436 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
437 /* textures support 8192, but layered rendering supports 2048 */
440 /* Render targets. */
441 case PIPE_CAP_MAX_RENDER_TARGETS:
444 case PIPE_CAP_MAX_VIEWPORTS:
445 return R600_MAX_VIEWPORTS;
447 /* Timer queries, present when the clock frequency is non zero. */
448 case PIPE_CAP_QUERY_TIMESTAMP:
449 case PIPE_CAP_QUERY_TIME_ELAPSED:
450 return sscreen->b.info.clock_crystal_freq != 0;
452 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
453 case PIPE_CAP_MIN_TEXEL_OFFSET:
456 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
457 case PIPE_CAP_MAX_TEXEL_OFFSET:
460 case PIPE_CAP_ENDIANNESS:
461 return PIPE_ENDIAN_LITTLE;
463 case PIPE_CAP_VENDOR_ID:
464 return ATI_VENDOR_ID;
465 case PIPE_CAP_DEVICE_ID:
466 return sscreen->b.info.pci_id;
467 case PIPE_CAP_ACCELERATED:
469 case PIPE_CAP_VIDEO_MEMORY:
470 return sscreen->b.info.vram_size >> 20;
473 case PIPE_CAP_PCI_GROUP:
474 return sscreen->b.info.pci_domain;
475 case PIPE_CAP_PCI_BUS:
476 return sscreen->b.info.pci_bus;
477 case PIPE_CAP_PCI_DEVICE:
478 return sscreen->b.info.pci_dev;
479 case PIPE_CAP_PCI_FUNCTION:
480 return sscreen->b.info.pci_func;
485 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
487 struct si_screen *sscreen = (struct si_screen *)pscreen;
491 case PIPE_SHADER_FRAGMENT:
492 case PIPE_SHADER_VERTEX:
493 case PIPE_SHADER_GEOMETRY:
495 case PIPE_SHADER_TESS_CTRL:
496 case PIPE_SHADER_TESS_EVAL:
497 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
498 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
501 case PIPE_SHADER_COMPUTE:
503 case PIPE_SHADER_CAP_PREFERRED_IR:
504 return PIPE_SHADER_IR_NATIVE;
506 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
507 int ir = 1 << PIPE_SHADER_IR_NATIVE;
509 /* Old kernels disallowed some register writes for SI
510 * that are used for indirect dispatches. */
511 if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
512 sscreen->b.info.drm_major == 3 ||
513 (sscreen->b.info.drm_major == 2 &&
514 sscreen->b.info.drm_minor >= 45)))
515 ir |= 1 << PIPE_SHADER_IR_TGSI;
519 case PIPE_SHADER_CAP_DOUBLES:
520 return HAVE_LLVM >= 0x0307;
522 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
523 uint64_t max_const_buffer_size;
524 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
525 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
526 &max_const_buffer_size);
527 return max_const_buffer_size;
530 /* If compute shaders don't require a special value
531 * for this cap, we can return the same value we
532 * do for other shader types. */
541 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
542 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
543 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
544 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
546 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
548 case PIPE_SHADER_CAP_MAX_INPUTS:
549 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
550 case PIPE_SHADER_CAP_MAX_OUTPUTS:
551 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
552 case PIPE_SHADER_CAP_MAX_TEMPS:
553 return 256; /* Max native temporaries. */
554 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
555 return 4096 * sizeof(float[4]); /* actually only memory limits this */
556 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
557 return SI_NUM_CONST_BUFFERS;
558 case PIPE_SHADER_CAP_MAX_PREDS:
559 return 0; /* FIXME */
560 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
562 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
564 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
565 /* Indirection of geometry shader input dimension is not
568 return shader != PIPE_SHADER_GEOMETRY;
569 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
570 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
571 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
573 case PIPE_SHADER_CAP_INTEGERS:
575 case PIPE_SHADER_CAP_SUBROUTINES:
577 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
578 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
579 return SI_NUM_SAMPLERS;
580 case PIPE_SHADER_CAP_PREFERRED_IR:
581 return PIPE_SHADER_IR_TGSI;
582 case PIPE_SHADER_CAP_SUPPORTED_IRS:
584 case PIPE_SHADER_CAP_DOUBLES:
585 return HAVE_LLVM >= 0x0307;
586 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
587 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
589 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
590 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
592 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
594 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
595 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
596 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
597 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
602 static void si_destroy_screen(struct pipe_screen* pscreen)
604 struct si_screen *sscreen = (struct si_screen *)pscreen;
605 struct si_shader_part *parts[] = {
608 sscreen->tcs_epilogs,
617 if (!sscreen->b.ws->unref(sscreen->b.ws))
620 /* Free shader parts. */
621 for (i = 0; i < ARRAY_SIZE(parts); i++) {
623 struct si_shader_part *part = parts[i];
625 parts[i] = part->next;
626 radeon_shader_binary_clean(&part->binary);
630 pipe_mutex_destroy(sscreen->shader_parts_mutex);
631 si_destroy_shader_cache(sscreen);
632 r600_destroy_common_screen(&sscreen->b);
635 static bool si_init_gs_info(struct si_screen *sscreen)
637 switch (sscreen->b.family) {
646 sscreen->gs_table_depth = 16;
657 sscreen->gs_table_depth = 32;
664 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
666 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
672 /* Set functions first. */
673 sscreen->b.b.context_create = si_create_context;
674 sscreen->b.b.destroy = si_destroy_screen;
675 sscreen->b.b.get_param = si_get_param;
676 sscreen->b.b.get_shader_param = si_get_shader_param;
677 sscreen->b.b.is_format_supported = si_is_format_supported;
678 sscreen->b.b.resource_create = r600_resource_create_common;
680 si_init_screen_state_functions(sscreen);
682 if (!r600_common_screen_init(&sscreen->b, ws) ||
683 !si_init_gs_info(sscreen) ||
684 !si_init_shader_cache(sscreen)) {
689 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
690 si_init_perfcounters(sscreen);
692 sscreen->b.has_cp_dma = true;
693 sscreen->b.has_streamout = true;
694 pipe_mutex_init(sscreen->shader_parts_mutex);
695 sscreen->use_monolithic_shaders =
696 HAVE_LLVM < 0x0308 ||
697 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
699 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
700 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
702 /* Create the auxiliary context. This must be done last. */
703 sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
705 if (sscreen->b.debug_flags & DBG_TEST_DMA)
706 r600_test_dma(&sscreen->b);
708 return &sscreen->b.b;