src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34
  35 /*
  36  * pipe_context
  37  */
  38 static void si_destroy_context(struct pipe_context *context)
  39 {
  40         struct si_context *sctx = (struct si_context *)context;
  41         int i;
  42
  43         si_release_all_descriptors(sctx);
  44
  45         if (sctx->ce_suballocator)
  46                 u_suballocator_destroy(sctx->ce_suballocator);
  47
  48         pipe_resource_reference(&sctx->esgs_ring, NULL);
  49         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  50         pipe_resource_reference(&sctx->tf_ring, NULL);
  51         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  52         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  53         r600_resource_reference(&sctx->border_color_buffer, NULL);
  54         free(sctx->border_color_table);
  55         r600_resource_reference(&sctx->scratch_buffer, NULL);
  56         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  57         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  58
  59         si_pm4_free_state(sctx, sctx->init_config, ~0);
  60         if (sctx->init_config_gs_rings)
  61                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  62         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  63                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  64
  65         if (sctx->fixed_func_tcs_shader.cso)
  66                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  67         if (sctx->custom_dsa_flush)
  68                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  69         if (sctx->custom_blend_resolve)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  71         if (sctx->custom_blend_decompress)
  72                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  73         if (sctx->custom_blend_fastclear)
  74                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  75         if (sctx->custom_blend_dcc_decompress)
  76                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  77         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  78
  79         if (sctx->blitter)
  80                 util_blitter_destroy(sctx->blitter);
  81
  82         r600_common_context_cleanup(&sctx->b);
  83
  84         LLVMDisposeTargetMachine(sctx->tm);
  85
  86         r600_resource_reference(&sctx->trace_buf, NULL);
  87         r600_resource_reference(&sctx->last_trace_buf, NULL);
  88         free(sctx->last_ib);
  89         if (sctx->last_bo_list) {
  90                 for (i = 0; i < sctx->last_bo_count; i++)
  91                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  92                 free(sctx->last_bo_list);
  93         }
  94         FREE(sctx);
  95 }
  96
  97 static enum pipe_reset_status
  98 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  99 {
 100         struct si_context *sctx = (struct si_context *)ctx;
 101
 102         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 103 }
 104
 105 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 106                                               void *priv, unsigned flags)
 107 {
 108         struct si_context *sctx = CALLOC_STRUCT(si_context);
 109         struct si_screen* sscreen = (struct si_screen *)screen;
 110         struct radeon_winsys *ws = sscreen->b.ws;
 111         LLVMTargetRef r600_target;
 112         const char *triple = "amdgcn--";
 113         int shader, i;
 114
 115         if (!sctx)
 116                 return NULL;
 117
 118         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 119                 flags |= PIPE_CONTEXT_DEBUG;
 120
 121         sctx->b.b.screen = screen; /* this must be set first */
 122         sctx->b.b.priv = priv;
 123         sctx->b.b.destroy = si_destroy_context;
 124         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 125         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 126         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 127
 128         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 129                 goto fail;
 130
 131         if (sscreen->b.info.drm_major == 3)
 132                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 133
 134         si_init_blit_functions(sctx);
 135         si_init_compute_functions(sctx);
 136         si_init_cp_dma_functions(sctx);
 137         si_init_debug_functions(sctx);
 138
 139         if (sscreen->b.info.has_uvd) {
 140                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 141                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 142         } else {
 143                 sctx->b.b.create_video_codec = vl_create_decoder;
 144                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 145         }
 146
 147         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 148                                        si_context_gfx_flush, sctx);
 149
 150         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 151                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 152                 if (!sctx->ce_ib)
 153                         goto fail;
 154
 155                 if (ws->cs_add_const_preamble_ib) {
 156                         sctx->ce_preamble_ib =
 157                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 158
 159                         if (!sctx->ce_preamble_ib)
 160                                 goto fail;
 161                 }
 162
 163                 sctx->ce_suballocator =
 164                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 165                                                       64, PIPE_BIND_CUSTOM,
 166                                                       PIPE_USAGE_DEFAULT, FALSE);
 167                 if (!sctx->ce_suballocator)
 168                         goto fail;
 169         }
 170
 171         sctx->b.gfx.flush = si_context_gfx_flush;
 172
 173         /* Border colors. */
 174         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 175                                           sizeof(*sctx->border_color_table));
 176         if (!sctx->border_color_table)
 177                 goto fail;
 178
 179         sctx->border_color_buffer = (struct r600_resource*)
 180                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 181                                    SI_MAX_BORDER_COLORS *
 182                                    sizeof(*sctx->border_color_table));
 183         if (!sctx->border_color_buffer)
 184                 goto fail;
 185
 186         sctx->border_color_map =
 187                 ws->buffer_map(sctx->border_color_buffer->buf,
 188                                NULL, PIPE_TRANSFER_WRITE);
 189         if (!sctx->border_color_map)
 190                 goto fail;
 191
 192         si_init_all_descriptors(sctx);
 193         si_init_state_functions(sctx);
 194         si_init_shader_functions(sctx);
 195
 196         if (sctx->b.chip_class >= CIK)
 197                 cik_init_sdma_functions(sctx);
 198         else
 199                 si_init_dma_functions(sctx);
 200
 201         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 202                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 203
 204         sctx->blitter = util_blitter_create(&sctx->b.b);
 205         if (sctx->blitter == NULL)
 206                 goto fail;
 207         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 208
 209         sctx->sample_mask.sample_mask = 0xffff;
 210
 211         /* these must be last */
 212         si_begin_new_cs(sctx);
 213         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 214
 215         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 216          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 217         if (sctx->b.chip_class == CIK) {
 218                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 219                                                                  PIPE_USAGE_DEFAULT, 16);
 220                 if (!sctx->null_const_buf.buffer)
 221                         goto fail;
 222                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 223
 224                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 225                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 226                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 227                                                               &sctx->null_const_buf);
 228                         }
 229                 }
 230
 231                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 232                                  &sctx->null_const_buf);
 233                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 234                                  &sctx->null_const_buf);
 235                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 236                                  &sctx->null_const_buf);
 237                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 238                                  &sctx->null_const_buf);
 239
 240                 /* Clear the NULL constant buffer, because loads should return zeros. */
 241                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 242                                      sctx->null_const_buf.buffer->width0, 0,
 243                                      R600_COHERENCY_SHADER);
 244         }
 245
 246         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 247          * this for non-cs shaders.  Using the wrong value here can result in
 248          * GPU lockups, but the maximum value seems to always work.
 249          */
 250         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 251
 252         /* Initialize LLVM TargetMachine */
 253         r600_target = radeon_llvm_get_r600_target(triple);
 254         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 255                                            r600_get_llvm_processor_name(sscreen->b.family),
 256 #if HAVE_LLVM >= 0x0308
 257                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 258                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 259 #endif
 260                                                 "+DumpCode,+vgpr-spilling",
 261                                            LLVMCodeGenLevelDefault,
 262                                            LLVMRelocDefault,
 263                                            LLVMCodeModelDefault);
 264
 265         return &sctx->b.b;
 266 fail:
 267         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 268         si_destroy_context(&sctx->b.b);
 269         return NULL;
 270 }
 271
 272 /*
 273  * pipe_screen
 274  */
 275
 276 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 277 {
 278         struct si_screen *sscreen = (struct si_screen *)pscreen;
 279
 280         switch (param) {
 281         /* Supported features (boolean caps). */
 282         case PIPE_CAP_TWO_SIDED_STENCIL:
 283         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 284         case PIPE_CAP_ANISOTROPIC_FILTER:
 285         case PIPE_CAP_POINT_SPRITE:
 286         case PIPE_CAP_OCCLUSION_QUERY:
 287         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 288         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 289         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 290         case PIPE_CAP_TEXTURE_SWIZZLE:
 291         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 292         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 293         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 294         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 295         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 296         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 297         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 298         case PIPE_CAP_SM3:
 299         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 300         case PIPE_CAP_PRIMITIVE_RESTART:
 301         case PIPE_CAP_CONDITIONAL_RENDER:
 302         case PIPE_CAP_TEXTURE_BARRIER:
 303         case PIPE_CAP_INDEP_BLEND_ENABLE:
 304         case PIPE_CAP_INDEP_BLEND_FUNC:
 305         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 306         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 307         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 308         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 309         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 310         case PIPE_CAP_USER_INDEX_BUFFERS:
 311         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 312         case PIPE_CAP_START_INSTANCE:
 313         case PIPE_CAP_NPOT_TEXTURES:
 314         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 315         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 316         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 317         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 318         case PIPE_CAP_TGSI_INSTANCEID:
 319         case PIPE_CAP_COMPUTE:
 320         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 321         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 322         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 323         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 324         case PIPE_CAP_CUBE_MAP_ARRAY:
 325         case PIPE_CAP_SAMPLE_SHADING:
 326         case PIPE_CAP_DRAW_INDIRECT:
 327         case PIPE_CAP_CLIP_HALFZ:
 328         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 329         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 330         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 331         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 332         case PIPE_CAP_TGSI_TEXCOORD:
 333         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 334         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 335         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 336         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 337         case PIPE_CAP_SHAREABLE_SHADERS:
 338         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 339         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 340         case PIPE_CAP_TEXTURE_QUERY_LOD:
 341         case PIPE_CAP_TEXTURE_GATHER_SM5:
 342         case PIPE_CAP_TGSI_TXQS:
 343         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 344         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 345         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 346         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 347         case PIPE_CAP_INVALIDATE_BUFFER:
 348         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 349         case PIPE_CAP_QUERY_MEMORY_INFO:
 350         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 351         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 352         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 353                 return 1;
 354
 355         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 356                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 357
 358         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 359                 return (sscreen->b.info.drm_major == 2 &&
 360                         sscreen->b.info.drm_minor >= 43) ||
 361                        sscreen->b.info.drm_major == 3;
 362
 363         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 364                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 365                 return sscreen->b.chip_class < CIK ||
 366                        (sscreen->b.info.drm_major == 2 &&
 367                         sscreen->b.info.drm_minor >= 35) ||
 368                        sscreen->b.info.drm_major == 3;
 369
 370         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 371                 return R600_MAP_BUFFER_ALIGNMENT;
 372
 373         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 374         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 375         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 376                 return 4;
 377         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 378                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 379
 380         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 381                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 382                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 383                     (1 << PIPE_SHADER_IR_TGSI))
 384                         return 430;
 385                 return HAVE_LLVM >= 0x0309 ? 420 :
 386                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 387
 388         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 389                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 390
 391         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 392                 return 0;
 393
 394         /* Unsupported features. */
 395         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 396         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 397         case PIPE_CAP_USER_VERTEX_BUFFERS:
 398         case PIPE_CAP_FAKE_SW_MSAA:
 399         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 400         case PIPE_CAP_VERTEXID_NOBASE:
 401         case PIPE_CAP_CLEAR_TEXTURE:
 402         case PIPE_CAP_DRAW_PARAMETERS:
 403         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 404         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 405         case PIPE_CAP_GENERATE_MIPMAP:
 406         case PIPE_CAP_STRING_MARKER:
 407         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 408         case PIPE_CAP_CULL_DISTANCE:
 409         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 410                 return 0;
 411
 412         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 413                 return 30;
 414
 415         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 416                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 417
 418         /* Stream output. */
 419         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 420                 return sscreen->b.has_streamout ? 4 : 0;
 421         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 422                 return sscreen->b.has_streamout ? 1 : 0;
 423         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 424         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 425                 return sscreen->b.has_streamout ? 32*4 : 0;
 426
 427         /* Geometry shader output. */
 428         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 429                 return 1024;
 430         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 431                 return 4095;
 432         case PIPE_CAP_MAX_VERTEX_STREAMS:
 433                 return 4;
 434
 435         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 436                 return 2048;
 437
 438         /* Texturing. */
 439         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 440         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 441                 return 15; /* 16384 */
 442         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 443                 /* textures support 8192, but layered rendering supports 2048 */
 444                 return 12;
 445         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 446                 /* textures support 8192, but layered rendering supports 2048 */
 447                 return 2048;
 448
 449         /* Render targets. */
 450         case PIPE_CAP_MAX_RENDER_TARGETS:
 451                 return 8;
 452
 453         case PIPE_CAP_MAX_VIEWPORTS:
 454                 return R600_MAX_VIEWPORTS;
 455
 456         /* Timer queries, present when the clock frequency is non zero. */
 457         case PIPE_CAP_QUERY_TIMESTAMP:
 458         case PIPE_CAP_QUERY_TIME_ELAPSED:
 459                 return sscreen->b.info.clock_crystal_freq != 0;
 460
 461         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 462         case PIPE_CAP_MIN_TEXEL_OFFSET:
 463                 return -32;
 464
 465         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 466         case PIPE_CAP_MAX_TEXEL_OFFSET:
 467                 return 31;
 468
 469         case PIPE_CAP_ENDIANNESS:
 470                 return PIPE_ENDIAN_LITTLE;
 471
 472         case PIPE_CAP_VENDOR_ID:
 473                 return ATI_VENDOR_ID;
 474         case PIPE_CAP_DEVICE_ID:
 475                 return sscreen->b.info.pci_id;
 476         case PIPE_CAP_ACCELERATED:
 477                 return 1;
 478         case PIPE_CAP_VIDEO_MEMORY:
 479                 return sscreen->b.info.vram_size >> 20;
 480         case PIPE_CAP_UMA:
 481                 return 0;
 482         case PIPE_CAP_PCI_GROUP:
 483                 return sscreen->b.info.pci_domain;
 484         case PIPE_CAP_PCI_BUS:
 485                 return sscreen->b.info.pci_bus;
 486         case PIPE_CAP_PCI_DEVICE:
 487                 return sscreen->b.info.pci_dev;
 488         case PIPE_CAP_PCI_FUNCTION:
 489                 return sscreen->b.info.pci_func;
 490         }
 491         return 0;
 492 }
 493
 494 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 495 {
 496         struct si_screen *sscreen = (struct si_screen *)pscreen;
 497
 498         switch(shader)
 499         {
 500         case PIPE_SHADER_FRAGMENT:
 501         case PIPE_SHADER_VERTEX:
 502         case PIPE_SHADER_GEOMETRY:
 503                 break;
 504         case PIPE_SHADER_TESS_CTRL:
 505         case PIPE_SHADER_TESS_EVAL:
 506                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 507                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 508                         return 0;
 509                 break;
 510         case PIPE_SHADER_COMPUTE:
 511                 switch (param) {
 512                 case PIPE_SHADER_CAP_PREFERRED_IR:
 513                         return PIPE_SHADER_IR_NATIVE;
 514
 515                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 516                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 517
 518                         /* Old kernels disallowed some register writes for SI
 519                          * that are used for indirect dispatches. */
 520                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 521                                                    sscreen->b.info.drm_major == 3 ||
 522                                                    (sscreen->b.info.drm_major == 2 &&
 523                                                     sscreen->b.info.drm_minor >= 45)))
 524                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 525
 526                         return ir;
 527                 }
 528                 case PIPE_SHADER_CAP_DOUBLES:
 529                         return HAVE_LLVM >= 0x0307;
 530
 531                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 532                         uint64_t max_const_buffer_size;
 533                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 534                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 535                                 &max_const_buffer_size);
 536                         return max_const_buffer_size;
 537                 }
 538                 default:
 539                         /* If compute shaders don't require a special value
 540                          * for this cap, we can return the same value we
 541                          * do for other shader types. */
 542                         break;
 543                 }
 544                 break;
 545         default:
 546                 return 0;
 547         }
 548
 549         switch (param) {
 550         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 551         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 552         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 553         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 554                 return 16384;
 555         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 556                 return 32;
 557         case PIPE_SHADER_CAP_MAX_INPUTS:
 558                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 559         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 560                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 561         case PIPE_SHADER_CAP_MAX_TEMPS:
 562                 return 256; /* Max native temporaries. */
 563         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 564                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 565         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 566                 return SI_NUM_CONST_BUFFERS;
 567         case PIPE_SHADER_CAP_MAX_PREDS:
 568                 return 0; /* FIXME */
 569         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 570                 return 1;
 571         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 572                 return 1;
 573         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 574                 /* Indirection of geometry shader input dimension is not
 575                  * handled yet
 576                  */
 577                 return shader != PIPE_SHADER_GEOMETRY;
 578         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 579         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 580         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 581                 return 1;
 582         case PIPE_SHADER_CAP_INTEGERS:
 583                 return 1;
 584         case PIPE_SHADER_CAP_SUBROUTINES:
 585                 return 0;
 586         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 587         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 588                 return SI_NUM_SAMPLERS;
 589         case PIPE_SHADER_CAP_PREFERRED_IR:
 590                 return PIPE_SHADER_IR_TGSI;
 591         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 592                 return 0;
 593         case PIPE_SHADER_CAP_DOUBLES:
 594                 return HAVE_LLVM >= 0x0307;
 595         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 596         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 597                 return 0;
 598         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 599         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 600                 return 1;
 601         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 602                 return 32;
 603         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 604                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 605         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 606                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 607         }
 608         return 0;
 609 }
 610
 611 static void si_destroy_screen(struct pipe_screen* pscreen)
 612 {
 613         struct si_screen *sscreen = (struct si_screen *)pscreen;
 614         struct si_shader_part *parts[] = {
 615                 sscreen->vs_prologs,
 616                 sscreen->vs_epilogs,
 617                 sscreen->tcs_epilogs,
 618                 sscreen->ps_prologs,
 619                 sscreen->ps_epilogs
 620         };
 621         unsigned i;
 622
 623         if (!sscreen)
 624                 return;
 625
 626         if (!sscreen->b.ws->unref(sscreen->b.ws))
 627                 return;
 628
 629         /* Free shader parts. */
 630         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 631                 while (parts[i]) {
 632                         struct si_shader_part *part = parts[i];
 633
 634                         parts[i] = part->next;
 635                         radeon_shader_binary_clean(&part->binary);
 636                         FREE(part);
 637                 }
 638         }
 639         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 640         si_destroy_shader_cache(sscreen);
 641         r600_destroy_common_screen(&sscreen->b);
 642 }
 643
 644 static bool si_init_gs_info(struct si_screen *sscreen)
 645 {
 646         switch (sscreen->b.family) {
 647         case CHIP_OLAND:
 648         case CHIP_HAINAN:
 649         case CHIP_KAVERI:
 650         case CHIP_KABINI:
 651         case CHIP_MULLINS:
 652         case CHIP_ICELAND:
 653         case CHIP_CARRIZO:
 654         case CHIP_STONEY:
 655                 sscreen->gs_table_depth = 16;
 656                 return true;
 657         case CHIP_TAHITI:
 658         case CHIP_PITCAIRN:
 659         case CHIP_VERDE:
 660         case CHIP_BONAIRE:
 661         case CHIP_HAWAII:
 662         case CHIP_TONGA:
 663         case CHIP_FIJI:
 664         case CHIP_POLARIS10:
 665         case CHIP_POLARIS11:
 666                 sscreen->gs_table_depth = 32;
 667                 return true;
 668         default:
 669                 return false;
 670         }
 671 }
 672
 673 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 674 {
 675         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 676
 677         if (!sscreen) {
 678                 return NULL;
 679         }
 680
 681         /* Set functions first. */
 682         sscreen->b.b.context_create = si_create_context;
 683         sscreen->b.b.destroy = si_destroy_screen;
 684         sscreen->b.b.get_param = si_get_param;
 685         sscreen->b.b.get_shader_param = si_get_shader_param;
 686         sscreen->b.b.is_format_supported = si_is_format_supported;
 687         sscreen->b.b.resource_create = r600_resource_create_common;
 688
 689         si_init_screen_state_functions(sscreen);
 690
 691         if (!r600_common_screen_init(&sscreen->b, ws) ||
 692             !si_init_gs_info(sscreen) ||
 693             !si_init_shader_cache(sscreen)) {
 694                 FREE(sscreen);
 695                 return NULL;
 696         }
 697
 698         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 699                 si_init_perfcounters(sscreen);
 700
 701         sscreen->b.has_cp_dma = true;
 702         sscreen->b.has_streamout = true;
 703         pipe_mutex_init(sscreen->shader_parts_mutex);
 704         sscreen->use_monolithic_shaders =
 705                 HAVE_LLVM < 0x0308 ||
 706                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 707
 708         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 709                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 710
 711         /* Create the auxiliary context. This must be done last. */
 712         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 713
 714         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 715                 r600_test_dma(&sscreen->b);
 716
 717         return &sscreen->b.b;
 718 }