2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SI_SHADER_PRIVATE_H
25 #define SI_SHADER_PRIVATE_H
27 #include "si_shader.h"
28 #include "gallivm/lp_bld_init.h"
29 #include "gallivm/lp_bld_tgsi.h"
30 #include "tgsi/tgsi_parse.h"
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
35 struct pipe_debug_callback;
36 struct radeon_shader_binary;
38 #define RADEON_LLVM_MAX_INPUT_SLOTS 32
39 #define RADEON_LLVM_MAX_INPUTS 32 * 4
40 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
42 #define RADEON_LLVM_INITIAL_CF_DEPTH 4
44 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
48 struct si_shader_context {
49 struct lp_build_tgsi_soa_context soa;
50 struct gallivm_state gallivm;
51 struct si_shader *shader;
52 struct si_screen *screen;
54 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
55 bool is_gs_copy_shader;
57 /* Whether the prolog will be compiled separately. */
60 /** This function is responsible for initilizing the inputs array and will be
61 * called once for each input declared in the TGSI shader.
63 void (*load_input)(struct si_shader_context *,
65 const struct tgsi_full_declaration *decl,
68 void (*load_system_value)(struct si_shader_context *,
70 const struct tgsi_full_declaration *decl);
72 void (*declare_memory_region)(struct si_shader_context *,
73 const struct tgsi_full_declaration *decl);
75 /** This array contains the input values for the shader. Typically these
76 * values will be in the form of a target intrinsic that will inform the
77 * backend how to load the actual inputs to the shader.
79 struct tgsi_full_declaration input_decls[RADEON_LLVM_MAX_INPUT_SLOTS];
80 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
81 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
83 /** This pointer is used to contain the temporary values.
84 * The amount of temporary used in tgsi can't be bound to a max value and
85 * thus we must allocate this array at runtime.
89 LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
91 struct si_llvm_flow *flow;
93 unsigned flow_depth_max;
95 struct tgsi_array_info *temp_arrays;
96 LLVMValueRef *temp_array_allocas;
98 LLVMValueRef undef_alloca;
100 LLVMValueRef main_fn;
101 LLVMTypeRef return_type;
103 int param_streamout_config;
104 int param_streamout_write_index;
105 int param_streamout_offset[4];
107 int param_rel_auto_id;
108 int param_vs_prim_id;
109 int param_instance_id;
110 int param_vertex_index0;
113 int param_tes_rel_patch_id;
114 int param_tes_patch_id;
115 int param_es2gs_offset;
118 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
119 * 0x800000 for VS, 0x1 for ES.
121 int param_tess_offchip;
123 LLVMTargetMachineRef tm;
125 unsigned invariant_load_md_kind;
126 unsigned range_md_kind;
127 unsigned uniform_md_kind;
128 unsigned fpmath_md_kind;
129 LLVMValueRef fpmath_md_2p5_ulp;
130 LLVMValueRef empty_md;
132 /* Preloaded descriptors. */
133 LLVMValueRef esgs_ring;
134 LLVMValueRef gsvs_ring[4];
137 LLVMValueRef gs_next_vertex[4];
138 LLVMValueRef return_value;
153 LLVMValueRef shared_memory;
156 static inline struct si_shader_context *
157 si_shader_context(struct lp_build_tgsi_context *bld_base)
159 return (struct si_shader_context*)bld_base;
162 void si_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
163 void si_llvm_shader_type(LLVMValueRef F, unsigned type);
165 LLVMTargetRef si_llvm_get_amdgpu_target(const char *triple);
167 unsigned si_llvm_compile(LLVMModuleRef M, struct radeon_shader_binary *binary,
168 LLVMTargetMachineRef tm,
169 struct pipe_debug_callback *debug);
171 LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
172 enum tgsi_opcode_type type);
174 LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
175 enum tgsi_opcode_type type, LLVMValueRef value);
177 LLVMValueRef si_llvm_bound_index(struct si_shader_context *ctx,
181 void si_llvm_context_init(struct si_shader_context *ctx,
183 const struct tgsi_shader_info *info,
184 const struct tgsi_token *tokens);
186 void si_llvm_create_func(struct si_shader_context *ctx,
188 LLVMTypeRef *return_types, unsigned num_return_elems,
189 LLVMTypeRef *ParamTypes, unsigned ParamCount);
191 void si_llvm_dispose(struct si_shader_context *ctx);
193 void si_llvm_finalize_module(struct si_shader_context *ctx,
196 LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
197 enum tgsi_opcode_type type,
201 LLVMValueRef si_llvm_saturate(struct lp_build_tgsi_context *bld_base,
204 LLVMValueRef si_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
205 const struct tgsi_full_src_register *reg,
206 enum tgsi_opcode_type type,
209 void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
210 const struct tgsi_full_instruction *inst,
211 const struct tgsi_opcode_info *info,
212 LLVMValueRef dst[4]);
214 void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
215 void si_prepare_cube_coords(struct lp_build_tgsi_context *bld_base,
216 struct lp_build_emit_data *emit_data,
217 LLVMValueRef *coords_arg,
218 LLVMValueRef *derivs_arg);