src/gallium/drivers/radeonsi/si_state.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "sid.h"
  29 #include "radeon/r600_cs.h"
  30 #include "radeon/r600_query.h"
  31
  32 #include "util/u_dual_blend.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_resource.h"
  37
  38 /* Initialize an external atom (owned by ../radeon). */
  39 static void
  40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
  41                       struct r600_atom **list_elem)
  42 {
  43         atom->id = list_elem - sctx->atoms.array + 1;
  44         *list_elem = atom;
  45 }
  46
  47 /* Initialize an atom owned by radeonsi.  */
  48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
  49                   struct r600_atom **list_elem,
  50                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
  51 {
  52         atom->emit = (void*)emit_func;
  53         atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
  54         *list_elem = atom;
  55 }
  56
  57 static unsigned si_map_swizzle(unsigned swizzle)
  58 {
  59         switch (swizzle) {
  60         case PIPE_SWIZZLE_Y:
  61                 return V_008F0C_SQ_SEL_Y;
  62         case PIPE_SWIZZLE_Z:
  63                 return V_008F0C_SQ_SEL_Z;
  64         case PIPE_SWIZZLE_W:
  65                 return V_008F0C_SQ_SEL_W;
  66         case PIPE_SWIZZLE_0:
  67                 return V_008F0C_SQ_SEL_0;
  68         case PIPE_SWIZZLE_1:
  69                 return V_008F0C_SQ_SEL_1;
  70         default: /* PIPE_SWIZZLE_X */
  71                 return V_008F0C_SQ_SEL_X;
  72         }
  73 }
  74
  75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
  76 {
  77         return value * (1 << frac_bits);
  78 }
  79
  80 /* 12.4 fixed-point */
  81 static unsigned si_pack_float_12p4(float x)
  82 {
  83         return x <= 0    ? 0 :
  84                x >= 4096 ? 0xffff : x * 16;
  85 }
  86
  87 /*
  88  * Inferred framebuffer and blender state.
  89  *
  90  * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
  91  * if there is not enough PS outputs.
  92  */
  93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
  94 {
  95         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  96         struct si_state_blend *blend = sctx->queued.named.blend;
  97         uint32_t cb_target_mask, i;
  98
  99         /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
 100         if (blend)
 101                 cb_target_mask = blend->cb_target_mask;
 102         else
 103                 cb_target_mask = 0xffffffff;
 104
 105         /* Avoid a hang that happens when dual source blending is enabled
 106          * but there is not enough color outputs. This is undefined behavior,
 107          * so disable color writes completely.
 108          *
 109          * Reproducible with Unigine Heaven 4.0 and drirc missing.
 110          */
 111         if (blend && blend->dual_src_blend &&
 112             sctx->ps_shader.cso &&
 113             (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
 114                 cb_target_mask = 0;
 115
 116         radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
 117
 118         /* STONEY-specific register settings. */
 119         if (sctx->b.family == CHIP_STONEY) {
 120                 unsigned spi_shader_col_format =
 121                         sctx->ps_shader.cso ?
 122                         sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
 123                 unsigned sx_ps_downconvert = 0;
 124                 unsigned sx_blend_opt_epsilon = 0;
 125                 unsigned sx_blend_opt_control = 0;
 126
 127                 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
 128                         struct r600_surface *surf =
 129                                 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
 130                         unsigned format, swap, spi_format, colormask;
 131                         bool has_alpha, has_rgb;
 132
 133                         if (!surf)
 134                                 continue;
 135
 136                         format = G_028C70_FORMAT(surf->cb_color_info);
 137                         swap = G_028C70_COMP_SWAP(surf->cb_color_info);
 138                         spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
 139                         colormask = (cb_target_mask >> (i * 4)) & 0xf;
 140
 141                         /* Set if RGB and A are present. */
 142                         has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
 143
 144                         if (format == V_028C70_COLOR_8 ||
 145                             format == V_028C70_COLOR_16 ||
 146                             format == V_028C70_COLOR_32)
 147                                 has_rgb = !has_alpha;
 148                         else
 149                                 has_rgb = true;
 150
 151                         /* Check the colormask and export format. */
 152                         if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
 153                                 has_rgb = false;
 154                         if (!(colormask & PIPE_MASK_A))
 155                                 has_alpha = false;
 156
 157                         if (spi_format == V_028714_SPI_SHADER_ZERO) {
 158                                 has_rgb = false;
 159                                 has_alpha = false;
 160                         }
 161
 162                         /* Disable value checking for disabled channels. */
 163                         if (!has_rgb)
 164                                 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 165                         if (!has_alpha)
 166                                 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 167
 168                         /* Enable down-conversion for 32bpp and smaller formats. */
 169                         switch (format) {
 170                         case V_028C70_COLOR_8:
 171                         case V_028C70_COLOR_8_8:
 172                         case V_028C70_COLOR_8_8_8_8:
 173                                 /* For 1 and 2-channel formats, use the superset thereof. */
 174                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 175                                     spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 176                                     spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 177                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 178                                         sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 179                                 }
 180                                 break;
 181
 182                         case V_028C70_COLOR_5_6_5:
 183                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 184                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 185                                         sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 186                                 }
 187                                 break;
 188
 189                         case V_028C70_COLOR_1_5_5_5:
 190                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 191                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 192                                         sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 193                                 }
 194                                 break;
 195
 196                         case V_028C70_COLOR_4_4_4_4:
 197                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 198                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 199                                         sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 200                                 }
 201                                 break;
 202
 203                         case V_028C70_COLOR_32:
 204                                 if (swap == V_0280A0_SWAP_STD &&
 205                                     spi_format == V_028714_SPI_SHADER_32_R)
 206                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 207                                 else if (swap == V_0280A0_SWAP_ALT_REV &&
 208                                          spi_format == V_028714_SPI_SHADER_32_AR)
 209                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 210                                 break;
 211
 212                         case V_028C70_COLOR_16:
 213                         case V_028C70_COLOR_16_16:
 214                                 /* For 1-channel formats, use the superset thereof. */
 215                                 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 216                                     spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 217                                     spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 218                                     spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 219                                         if (swap == V_0280A0_SWAP_STD ||
 220                                             swap == V_0280A0_SWAP_STD_REV)
 221                                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 222                                         else
 223                                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 224                                 }
 225                                 break;
 226
 227                         case V_028C70_COLOR_10_11_11:
 228                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 229                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 230                                         sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 231                                 }
 232                                 break;
 233
 234                         case V_028C70_COLOR_2_10_10_10:
 235                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 236                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 237                                         sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 238                                 }
 239                                 break;
 240                         }
 241                 }
 242
 243                 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
 244                         sx_ps_downconvert = 0;
 245                         sx_blend_opt_epsilon = 0;
 246                         sx_blend_opt_control = 0;
 247                 }
 248
 249                 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
 250                 radeon_emit(cs, sx_ps_downconvert);     /* R_028754_SX_PS_DOWNCONVERT */
 251                 radeon_emit(cs, sx_blend_opt_epsilon);  /* R_028758_SX_BLEND_OPT_EPSILON */
 252                 radeon_emit(cs, sx_blend_opt_control);  /* R_02875C_SX_BLEND_OPT_CONTROL */
 253         }
 254 }
 255
 256 /*
 257  * Blender functions
 258  */
 259
 260 static uint32_t si_translate_blend_function(int blend_func)
 261 {
 262         switch (blend_func) {
 263         case PIPE_BLEND_ADD:
 264                 return V_028780_COMB_DST_PLUS_SRC;
 265         case PIPE_BLEND_SUBTRACT:
 266                 return V_028780_COMB_SRC_MINUS_DST;
 267         case PIPE_BLEND_REVERSE_SUBTRACT:
 268                 return V_028780_COMB_DST_MINUS_SRC;
 269         case PIPE_BLEND_MIN:
 270                 return V_028780_COMB_MIN_DST_SRC;
 271         case PIPE_BLEND_MAX:
 272                 return V_028780_COMB_MAX_DST_SRC;
 273         default:
 274                 R600_ERR("Unknown blend function %d\n", blend_func);
 275                 assert(0);
 276                 break;
 277         }
 278         return 0;
 279 }
 280
 281 static uint32_t si_translate_blend_factor(int blend_fact)
 282 {
 283         switch (blend_fact) {
 284         case PIPE_BLENDFACTOR_ONE:
 285                 return V_028780_BLEND_ONE;
 286         case PIPE_BLENDFACTOR_SRC_COLOR:
 287                 return V_028780_BLEND_SRC_COLOR;
 288         case PIPE_BLENDFACTOR_SRC_ALPHA:
 289                 return V_028780_BLEND_SRC_ALPHA;
 290         case PIPE_BLENDFACTOR_DST_ALPHA:
 291                 return V_028780_BLEND_DST_ALPHA;
 292         case PIPE_BLENDFACTOR_DST_COLOR:
 293                 return V_028780_BLEND_DST_COLOR;
 294         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 295                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 296         case PIPE_BLENDFACTOR_CONST_COLOR:
 297                 return V_028780_BLEND_CONSTANT_COLOR;
 298         case PIPE_BLENDFACTOR_CONST_ALPHA:
 299                 return V_028780_BLEND_CONSTANT_ALPHA;
 300         case PIPE_BLENDFACTOR_ZERO:
 301                 return V_028780_BLEND_ZERO;
 302         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 303                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 304         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 305                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 306         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 307                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 308         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 309                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 310         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 311                 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
 312         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 313                 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
 314         case PIPE_BLENDFACTOR_SRC1_COLOR:
 315                 return V_028780_BLEND_SRC1_COLOR;
 316         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 317                 return V_028780_BLEND_SRC1_ALPHA;
 318         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 319                 return V_028780_BLEND_INV_SRC1_COLOR;
 320         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 321                 return V_028780_BLEND_INV_SRC1_ALPHA;
 322         default:
 323                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 324                 assert(0);
 325                 break;
 326         }
 327         return 0;
 328 }
 329
 330 static uint32_t si_translate_blend_opt_function(int blend_func)
 331 {
 332         switch (blend_func) {
 333         case PIPE_BLEND_ADD:
 334                 return V_028760_OPT_COMB_ADD;
 335         case PIPE_BLEND_SUBTRACT:
 336                 return V_028760_OPT_COMB_SUBTRACT;
 337         case PIPE_BLEND_REVERSE_SUBTRACT:
 338                 return V_028760_OPT_COMB_REVSUBTRACT;
 339         case PIPE_BLEND_MIN:
 340                 return V_028760_OPT_COMB_MIN;
 341         case PIPE_BLEND_MAX:
 342                 return V_028760_OPT_COMB_MAX;
 343         default:
 344                 return V_028760_OPT_COMB_BLEND_DISABLED;
 345         }
 346 }
 347
 348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
 349 {
 350         switch (blend_fact) {
 351         case PIPE_BLENDFACTOR_ZERO:
 352                 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
 353         case PIPE_BLENDFACTOR_ONE:
 354                 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
 355         case PIPE_BLENDFACTOR_SRC_COLOR:
 356                 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
 357                                 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
 358         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 359                 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
 360                                 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
 361         case PIPE_BLENDFACTOR_SRC_ALPHA:
 362                 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
 363         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 364                 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
 365         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 366                 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
 367                                 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
 368         default:
 369                 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
 370         }
 371 }
 372
 373 /**
 374  * Get rid of DST in the blend factors by commuting the operands:
 375  *    func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
 376  */
 377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
 378                                 unsigned *dst_factor, unsigned expected_dst,
 379                                 unsigned replacement_src)
 380 {
 381         if (*src_factor == expected_dst &&
 382             *dst_factor == PIPE_BLENDFACTOR_ZERO) {
 383                 *src_factor = PIPE_BLENDFACTOR_ZERO;
 384                 *dst_factor = replacement_src;
 385
 386                 /* Commuting the operands requires reversing subtractions. */
 387                 if (*func == PIPE_BLEND_SUBTRACT)
 388                         *func = PIPE_BLEND_REVERSE_SUBTRACT;
 389                 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
 390                         *func = PIPE_BLEND_SUBTRACT;
 391         }
 392 }
 393
 394 static bool si_blend_factor_uses_dst(unsigned factor)
 395 {
 396         return factor == PIPE_BLENDFACTOR_DST_COLOR ||
 397                 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
 398                 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
 399                 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
 400                 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
 401 }
 402
 403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
 404                                         const struct pipe_blend_state *state,
 405                                         unsigned mode)
 406 {
 407         struct si_context *sctx = (struct si_context*)ctx;
 408         struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
 409         struct si_pm4_state *pm4 = &blend->pm4;
 410         uint32_t sx_mrt_blend_opt[8] = {0};
 411         uint32_t color_control = 0;
 412
 413         if (!blend)
 414                 return NULL;
 415
 416         blend->alpha_to_coverage = state->alpha_to_coverage;
 417         blend->alpha_to_one = state->alpha_to_one;
 418         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 419
 420         if (state->logicop_enable) {
 421                 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
 422         } else {
 423                 color_control |= S_028808_ROP3(0xcc);
 424         }
 425
 426         si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
 427                        S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 428                        S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
 429                        S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
 430                        S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
 431                        S_028B70_ALPHA_TO_MASK_OFFSET3(2));
 432
 433         if (state->alpha_to_coverage)
 434                 blend->need_src_alpha_4bit |= 0xf;
 435
 436         blend->cb_target_mask = 0;
 437         for (int i = 0; i < 8; i++) {
 438                 /* state->rt entries > 0 only written if independent blending */
 439                 const int j = state->independent_blend_enable ? i : 0;
 440
 441                 unsigned eqRGB = state->rt[j].rgb_func;
 442                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 443                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 444                 unsigned eqA = state->rt[j].alpha_func;
 445                 unsigned srcA = state->rt[j].alpha_src_factor;
 446                 unsigned dstA = state->rt[j].alpha_dst_factor;
 447
 448                 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
 449                 unsigned blend_cntl = 0;
 450
 451                 sx_mrt_blend_opt[i] =
 452                         S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
 453                         S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
 454
 455                 /* Only set dual source blending for MRT0 to avoid a hang. */
 456                 if (i >= 1 && blend->dual_src_blend)
 457                         continue;
 458
 459                 /* Only addition and subtraction equations are supported with
 460                  * dual source blending.
 461                  */
 462                 if (blend->dual_src_blend &&
 463                     (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
 464                      eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
 465                         assert(!"Unsupported equation for dual source blending");
 466                         continue;
 467                 }
 468
 469                 if (!state->rt[j].colormask)
 470                         continue;
 471
 472                 /* cb_render_state will disable unused ones */
 473                 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
 474
 475                 if (!state->rt[j].blend_enable) {
 476                         si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
 477                         continue;
 478                 }
 479
 480                 /* Blending optimizations for Stoney.
 481                  * These transformations don't change the behavior.
 482                  *
 483                  * First, get rid of DST in the blend factors:
 484                  *    func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
 485                  */
 486                 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
 487                                     PIPE_BLENDFACTOR_DST_COLOR,
 488                                     PIPE_BLENDFACTOR_SRC_COLOR);
 489                 si_blend_remove_dst(&eqA, &srcA, &dstA,
 490                                     PIPE_BLENDFACTOR_DST_COLOR,
 491                                     PIPE_BLENDFACTOR_SRC_COLOR);
 492                 si_blend_remove_dst(&eqA, &srcA, &dstA,
 493                                     PIPE_BLENDFACTOR_DST_ALPHA,
 494                                     PIPE_BLENDFACTOR_SRC_ALPHA);
 495
 496                 /* Look up the ideal settings from tables. */
 497                 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
 498                 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
 499                 srcA_opt = si_translate_blend_opt_factor(srcA, true);
 500                 dstA_opt = si_translate_blend_opt_factor(dstA, true);
 501
 502                 /* Handle interdependencies. */
 503                 if (si_blend_factor_uses_dst(srcRGB))
 504                         dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
 505                 if (si_blend_factor_uses_dst(srcA))
 506                         dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
 507
 508                 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
 509                     (dstRGB == PIPE_BLENDFACTOR_ZERO ||
 510                      dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
 511                      dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
 512                         dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
 513
 514                 /* Set the final value. */
 515                 sx_mrt_blend_opt[i] =
 516                         S_028760_COLOR_SRC_OPT(srcRGB_opt) |
 517                         S_028760_COLOR_DST_OPT(dstRGB_opt) |
 518                         S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
 519                         S_028760_ALPHA_SRC_OPT(srcA_opt) |
 520                         S_028760_ALPHA_DST_OPT(dstA_opt) |
 521                         S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
 522
 523                 /* Set blend state. */
 524                 blend_cntl |= S_028780_ENABLE(1);
 525                 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
 526                 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
 527                 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
 528
 529                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 530                         blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
 531                         blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
 532                         blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
 533                         blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
 534                 }
 535                 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
 536
 537                 blend->blend_enable_4bit |= 0xfu << (i * 4);
 538
 539                 /* This is only important for formats without alpha. */
 540                 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
 541                     dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
 542                     srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
 543                     dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
 544                     srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
 545                     dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
 546                         blend->need_src_alpha_4bit |= 0xfu << (i * 4);
 547         }
 548
 549         if (blend->cb_target_mask) {
 550                 color_control |= S_028808_MODE(mode);
 551         } else {
 552                 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 553         }
 554
 555         if (sctx->b.family == CHIP_STONEY) {
 556                 for (int i = 0; i < 8; i++)
 557                         si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
 558                                        sx_mrt_blend_opt[i]);
 559
 560                 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
 561                 if (blend->dual_src_blend || state->logicop_enable ||
 562                     mode == V_028808_CB_RESOLVE)
 563                         color_control |= S_028808_DISABLE_DUAL_QUAD(1);
 564         }
 565
 566         si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
 567         return blend;
 568 }
 569
 570 static void *si_create_blend_state(struct pipe_context *ctx,
 571                                    const struct pipe_blend_state *state)
 572 {
 573         return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
 574 }
 575
 576 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
 577 {
 578         struct si_context *sctx = (struct si_context *)ctx;
 579         si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
 580         si_mark_atom_dirty(sctx, &sctx->cb_render_state);
 581         sctx->do_update_shaders = true;
 582 }
 583
 584 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
 585 {
 586         struct si_context *sctx = (struct si_context *)ctx;
 587         si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
 588 }
 589
 590 static void si_set_blend_color(struct pipe_context *ctx,
 591                                const struct pipe_blend_color *state)
 592 {
 593         struct si_context *sctx = (struct si_context *)ctx;
 594
 595         if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
 596                 return;
 597
 598         sctx->blend_color.state = *state;
 599         si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
 600 }
 601
 602 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
 603 {
 604         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 605
 606         radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 607         radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
 608 }
 609
 610 /*
 611  * Clipping
 612  */
 613
 614 static void si_set_clip_state(struct pipe_context *ctx,
 615                               const struct pipe_clip_state *state)
 616 {
 617         struct si_context *sctx = (struct si_context *)ctx;
 618         struct pipe_constant_buffer cb;
 619
 620         if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
 621                 return;
 622
 623         sctx->clip_state.state = *state;
 624         si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
 625
 626         cb.buffer = NULL;
 627         cb.user_buffer = state->ucp;
 628         cb.buffer_offset = 0;
 629         cb.buffer_size = 4*4*8;
 630         si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
 631         pipe_resource_reference(&cb.buffer, NULL);
 632 }
 633
 634 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
 635 {
 636         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 637
 638         radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
 639         radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
 640 }
 641
 642 #define SIX_BITS 0x3F
 643
 644 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
 645 {
 646         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 647         struct tgsi_shader_info *info = si_get_vs_info(sctx);
 648         unsigned window_space =
 649            info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 650         unsigned clipdist_mask =
 651                 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
 652         unsigned total_mask = clipdist_mask | (info->culldist_writemask << info->num_written_clipdistance);
 653
 654         radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
 655                 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
 656                 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
 657                 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
 658                 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
 659                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
 660                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
 661                 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
 662                                             info->writes_edgeflag ||
 663                                             info->writes_layer ||
 664                                              info->writes_viewport_index) |
 665                 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
 666                 (sctx->queued.named.rasterizer->clip_plane_enable &
 667                  clipdist_mask) | (info->culldist_writemask << 8));
 668         radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
 669                 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
 670                 (clipdist_mask ? 0 :
 671                  sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
 672                 S_028810_CLIP_DISABLE(window_space));
 673
 674         /* reuse needs to be set off if we write oViewport */
 675         radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
 676                                S_028AB4_REUSE_OFF(info->writes_viewport_index));
 677 }
 678
 679 /*
 680  * inferred state between framebuffer and rasterizer
 681  */
 682 static void si_update_poly_offset_state(struct si_context *sctx)
 683 {
 684         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
 685
 686         if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
 687                 return;
 688
 689         /* Use the user format, not db_render_format, so that the polygon
 690          * offset behaves as expected by applications.
 691          */
 692         switch (sctx->framebuffer.state.zsbuf->texture->format) {
 693         case PIPE_FORMAT_Z16_UNORM:
 694                 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
 695                 break;
 696         default: /* 24-bit */
 697                 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
 698                 break;
 699         case PIPE_FORMAT_Z32_FLOAT:
 700         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 701                 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
 702                 break;
 703         }
 704 }
 705
 706 /*
 707  * Rasterizer
 708  */
 709
 710 static uint32_t si_translate_fill(uint32_t func)
 711 {
 712         switch(func) {
 713         case PIPE_POLYGON_MODE_FILL:
 714                 return V_028814_X_DRAW_TRIANGLES;
 715         case PIPE_POLYGON_MODE_LINE:
 716                 return V_028814_X_DRAW_LINES;
 717         case PIPE_POLYGON_MODE_POINT:
 718                 return V_028814_X_DRAW_POINTS;
 719         default:
 720                 assert(0);
 721                 return V_028814_X_DRAW_POINTS;
 722         }
 723 }
 724
 725 static void *si_create_rs_state(struct pipe_context *ctx,
 726                                 const struct pipe_rasterizer_state *state)
 727 {
 728         struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
 729         struct si_pm4_state *pm4 = &rs->pm4;
 730         unsigned tmp, i;
 731         float psize_min, psize_max;
 732
 733         if (!rs) {
 734                 return NULL;
 735         }
 736
 737         rs->scissor_enable = state->scissor;
 738         rs->clip_halfz = state->clip_halfz;
 739         rs->two_side = state->light_twoside;
 740         rs->multisample_enable = state->multisample;
 741         rs->force_persample_interp = state->force_persample_interp;
 742         rs->clip_plane_enable = state->clip_plane_enable;
 743         rs->line_stipple_enable = state->line_stipple_enable;
 744         rs->poly_stipple_enable = state->poly_stipple_enable;
 745         rs->line_smooth = state->line_smooth;
 746         rs->poly_smooth = state->poly_smooth;
 747         rs->uses_poly_offset = state->offset_point || state->offset_line ||
 748                                state->offset_tri;
 749         rs->clamp_fragment_color = state->clamp_fragment_color;
 750         rs->flatshade = state->flatshade;
 751         rs->sprite_coord_enable = state->sprite_coord_enable;
 752         rs->rasterizer_discard = state->rasterizer_discard;
 753         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 754                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 755                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 756         rs->pa_cl_clip_cntl =
 757                 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
 758                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 759                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 760                 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
 761                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 762
 763         si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
 764                 S_0286D4_FLAT_SHADE_ENA(1) |
 765                 S_0286D4_PNT_SPRITE_ENA(1) |
 766                 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
 767                 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
 768                 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
 769                 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
 770                 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
 771
 772         /* point size 12.4 fixed point */
 773         tmp = (unsigned)(state->point_size * 8.0);
 774         si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 775
 776         if (state->point_size_per_vertex) {
 777                 psize_min = util_get_min_point_size(state);
 778                 psize_max = 8192;
 779         } else {
 780                 /* Force the point size to be as if the vertex output was disabled. */
 781                 psize_min = state->point_size;
 782                 psize_max = state->point_size;
 783         }
 784         /* Divide by two, because 0.5 = 1 pixel. */
 785         si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
 786                         S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
 787                         S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
 788
 789         tmp = (unsigned)state->line_width * 8;
 790         si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
 791         si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
 792                        S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
 793                        S_028A48_MSAA_ENABLE(state->multisample ||
 794                                             state->poly_smooth ||
 795                                             state->line_smooth) |
 796                        S_028A48_VPORT_SCISSOR_ENABLE(1));
 797
 798         si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
 799                        S_028BE4_PIX_CENTER(state->half_pixel_center) |
 800                        S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
 801
 802         si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 803         si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
 804                 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 805                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 806                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 807                 S_028814_FACE(!state->front_ccw) |
 808                 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
 809                 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
 810                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
 811                 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
 812                                    state->fill_back != PIPE_POLYGON_MODE_FILL) |
 813                 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
 814                 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
 815         si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
 816                        SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
 817
 818         /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
 819         for (i = 0; i < 3; i++) {
 820                 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
 821                 float offset_units = state->offset_units;
 822                 float offset_scale = state->offset_scale * 16.0f;
 823                 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
 824
 825                 if (!state->offset_units_unscaled) {
 826                         switch (i) {
 827                         case 0: /* 16-bit zbuffer */
 828                                 offset_units *= 4.0f;
 829                                 pa_su_poly_offset_db_fmt_cntl =
 830                                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
 831                                 break;
 832                         case 1: /* 24-bit zbuffer */
 833                                 offset_units *= 2.0f;
 834                                 pa_su_poly_offset_db_fmt_cntl =
 835                                         S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
 836                                 break;
 837                         case 2: /* 32-bit zbuffer */
 838                                 offset_units *= 1.0f;
 839                                 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
 840                                                                 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 841                                 break;
 842                         }
 843                 }
 844
 845                 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
 846                                fui(offset_scale));
 847                 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 848                                fui(offset_units));
 849                 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
 850                                fui(offset_scale));
 851                 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 852                                fui(offset_units));
 853                 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 854                                pa_su_poly_offset_db_fmt_cntl);
 855         }
 856
 857         return rs;
 858 }
 859
 860 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
 861 {
 862         struct si_context *sctx = (struct si_context *)ctx;
 863         struct si_state_rasterizer *old_rs =
 864                 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
 865         struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
 866
 867         if (!state)
 868                 return;
 869
 870         if (sctx->framebuffer.nr_samples > 1 &&
 871             (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
 872                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
 873
 874                 if (sctx->b.family >= CHIP_POLARIS10)
 875                         si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
 876         }
 877
 878         r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
 879
 880         si_pm4_bind_state(sctx, rasterizer, rs);
 881         si_update_poly_offset_state(sctx);
 882
 883         si_mark_atom_dirty(sctx, &sctx->clip_regs);
 884         sctx->do_update_shaders = true;
 885 }
 886
 887 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
 888 {
 889         struct si_context *sctx = (struct si_context *)ctx;
 890
 891         if (sctx->queued.named.rasterizer == state)
 892                 si_pm4_bind_state(sctx, poly_offset, NULL);
 893         si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
 894 }
 895
 896 /*
 897  * infeered state between dsa and stencil ref
 898  */
 899 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
 900 {
 901         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 902         struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
 903         struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
 904
 905         radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 906         radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
 907                         S_028430_STENCILMASK(dsa->valuemask[0]) |
 908                         S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
 909                         S_028430_STENCILOPVAL(1));
 910         radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
 911                         S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
 912                         S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
 913                         S_028434_STENCILOPVAL_BF(1));
 914 }
 915
 916 static void si_set_stencil_ref(struct pipe_context *ctx,
 917                                const struct pipe_stencil_ref *state)
 918 {
 919         struct si_context *sctx = (struct si_context *)ctx;
 920
 921         if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
 922                 return;
 923
 924         sctx->stencil_ref.state = *state;
 925         si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
 926 }
 927
 928
 929 /*
 930  * DSA
 931  */
 932
 933 static uint32_t si_translate_stencil_op(int s_op)
 934 {
 935         switch (s_op) {
 936         case PIPE_STENCIL_OP_KEEP:
 937                 return V_02842C_STENCIL_KEEP;
 938         case PIPE_STENCIL_OP_ZERO:
 939                 return V_02842C_STENCIL_ZERO;
 940         case PIPE_STENCIL_OP_REPLACE:
 941                 return V_02842C_STENCIL_REPLACE_TEST;
 942         case PIPE_STENCIL_OP_INCR:
 943                 return V_02842C_STENCIL_ADD_CLAMP;
 944         case PIPE_STENCIL_OP_DECR:
 945                 return V_02842C_STENCIL_SUB_CLAMP;
 946         case PIPE_STENCIL_OP_INCR_WRAP:
 947                 return V_02842C_STENCIL_ADD_WRAP;
 948         case PIPE_STENCIL_OP_DECR_WRAP:
 949                 return V_02842C_STENCIL_SUB_WRAP;
 950         case PIPE_STENCIL_OP_INVERT:
 951                 return V_02842C_STENCIL_INVERT;
 952         default:
 953                 R600_ERR("Unknown stencil op %d", s_op);
 954                 assert(0);
 955                 break;
 956         }
 957         return 0;
 958 }
 959
 960 static void *si_create_dsa_state(struct pipe_context *ctx,
 961                                  const struct pipe_depth_stencil_alpha_state *state)
 962 {
 963         struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
 964         struct si_pm4_state *pm4 = &dsa->pm4;
 965         unsigned db_depth_control;
 966         uint32_t db_stencil_control = 0;
 967
 968         if (!dsa) {
 969                 return NULL;
 970         }
 971
 972         dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
 973         dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
 974         dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
 975         dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
 976
 977         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 978                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 979                 S_028800_ZFUNC(state->depth.func) |
 980                 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
 981
 982         /* stencil */
 983         if (state->stencil[0].enabled) {
 984                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 985                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
 986                 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
 987                 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
 988                 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
 989
 990                 if (state->stencil[1].enabled) {
 991                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 992                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
 993                         db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
 994                         db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
 995                         db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
 996                 }
 997         }
 998
 999         /* alpha */
1000         if (state->alpha.enabled) {
1001                 dsa->alpha_func = state->alpha.func;
1002
1003                 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1004                                SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1005         } else {
1006                 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1007         }
1008
1009         si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1010         si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1011         if (state->depth.bounds_test) {
1012                 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1013                 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1014         }
1015
1016         return dsa;
1017 }
1018
1019 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1020 {
1021         struct si_context *sctx = (struct si_context *)ctx;
1022         struct si_state_dsa *dsa = state;
1023
1024         if (!state)
1025                 return;
1026
1027         si_pm4_bind_state(sctx, dsa, dsa);
1028
1029         if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1030                    sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1031                 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1032                 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1033         }
1034         sctx->do_update_shaders = true;
1035 }
1036
1037 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1038 {
1039         struct si_context *sctx = (struct si_context *)ctx;
1040         si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1041 }
1042
1043 static void *si_create_db_flush_dsa(struct si_context *sctx)
1044 {
1045         struct pipe_depth_stencil_alpha_state dsa = {};
1046
1047         return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1048 }
1049
1050 /* DB RENDER STATE */
1051
1052 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1053 {
1054         struct si_context *sctx = (struct si_context*)ctx;
1055
1056         /* Pipeline stat & streamout queries. */
1057         if (enable) {
1058                 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1059                 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1060         } else {
1061                 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1062                 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1063         }
1064
1065         /* Occlusion queries. */
1066         if (sctx->occlusion_queries_disabled != !enable) {
1067                 sctx->occlusion_queries_disabled = !enable;
1068                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1069         }
1070 }
1071
1072 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1073 {
1074         struct si_context *sctx = (struct si_context*)ctx;
1075
1076         si_mark_atom_dirty(sctx, &sctx->db_render_state);
1077 }
1078
1079 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1080 {
1081         struct si_context *sctx = (struct si_context*)ctx;
1082
1083         st->saved_compute = sctx->cs_shader_state.program;
1084
1085         si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1086         si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1087 }
1088
1089 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1090 {
1091         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1092         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1093         unsigned db_shader_control;
1094
1095         radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1096
1097         /* DB_RENDER_CONTROL */
1098         if (sctx->dbcb_depth_copy_enabled ||
1099             sctx->dbcb_stencil_copy_enabled) {
1100                 radeon_emit(cs,
1101                             S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1102                             S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1103                             S_028000_COPY_CENTROID(1) |
1104                             S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1105         } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1106                 radeon_emit(cs,
1107                             S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1108                             S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1109         } else {
1110                 radeon_emit(cs,
1111                             S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1112                             S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1113         }
1114
1115         /* DB_COUNT_CONTROL (occlusion queries) */
1116         if (sctx->b.num_occlusion_queries > 0 &&
1117             !sctx->occlusion_queries_disabled) {
1118                 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1119
1120                 if (sctx->b.chip_class >= CIK) {
1121                         radeon_emit(cs,
1122                                     S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1123                                     S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1124                                     S_028004_ZPASS_ENABLE(1) |
1125                                     S_028004_SLICE_EVEN_ENABLE(1) |
1126                                     S_028004_SLICE_ODD_ENABLE(1));
1127                 } else {
1128                         radeon_emit(cs,
1129                                     S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1130                                     S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1131                 }
1132         } else {
1133                 /* Disable occlusion queries. */
1134                 if (sctx->b.chip_class >= CIK) {
1135                         radeon_emit(cs, 0);
1136                 } else {
1137                         radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1138                 }
1139         }
1140
1141         /* DB_RENDER_OVERRIDE2 */
1142         radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1143                 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1144                 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1145                 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1146
1147         db_shader_control = sctx->ps_db_shader_control;
1148
1149         /* Bug workaround for smoothing (overrasterization) on SI. */
1150         if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1151                 db_shader_control &= C_02880C_Z_ORDER;
1152                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1153         }
1154
1155         /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1156         if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1157                 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1158
1159         if (sctx->b.family == CHIP_STONEY &&
1160             sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1161                 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1162
1163         radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1164                                db_shader_control);
1165 }
1166
1167 /*
1168  * format translation
1169  */
1170 static uint32_t si_translate_colorformat(enum pipe_format format)
1171 {
1172         const struct util_format_description *desc = util_format_description(format);
1173
1174 #define HAS_SIZE(x,y,z,w) \
1175         (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1176          desc->channel[2].size == (z) && desc->channel[3].size == (w))
1177
1178         if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1179                 return V_028C70_COLOR_10_11_11;
1180
1181         if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1182                 return V_028C70_COLOR_INVALID;
1183
1184         /* hw cannot support mixed formats (except depth/stencil, since
1185          * stencil is not written to). */
1186         if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1187                 return V_028C70_COLOR_INVALID;
1188
1189         switch (desc->nr_channels) {
1190         case 1:
1191                 switch (desc->channel[0].size) {
1192                 case 8:
1193                         return V_028C70_COLOR_8;
1194                 case 16:
1195                         return V_028C70_COLOR_16;
1196                 case 32:
1197                         return V_028C70_COLOR_32;
1198                 }
1199                 break;
1200         case 2:
1201                 if (desc->channel[0].size == desc->channel[1].size) {
1202                         switch (desc->channel[0].size) {
1203                         case 8:
1204                                 return V_028C70_COLOR_8_8;
1205                         case 16:
1206                                 return V_028C70_COLOR_16_16;
1207                         case 32:
1208                                 return V_028C70_COLOR_32_32;
1209                         }
1210                 } else if (HAS_SIZE(8,24,0,0)) {
1211                         return V_028C70_COLOR_24_8;
1212                 } else if (HAS_SIZE(24,8,0,0)) {
1213                         return V_028C70_COLOR_8_24;
1214                 }
1215                 break;
1216         case 3:
1217                 if (HAS_SIZE(5,6,5,0)) {
1218                         return V_028C70_COLOR_5_6_5;
1219                 } else if (HAS_SIZE(32,8,24,0)) {
1220                         return V_028C70_COLOR_X24_8_32_FLOAT;
1221                 }
1222                 break;
1223         case 4:
1224                 if (desc->channel[0].size == desc->channel[1].size &&
1225                     desc->channel[0].size == desc->channel[2].size &&
1226                     desc->channel[0].size == desc->channel[3].size) {
1227                         switch (desc->channel[0].size) {
1228                         case 4:
1229                                 return V_028C70_COLOR_4_4_4_4;
1230                         case 8:
1231                                 return V_028C70_COLOR_8_8_8_8;
1232                         case 16:
1233                                 return V_028C70_COLOR_16_16_16_16;
1234                         case 32:
1235                                 return V_028C70_COLOR_32_32_32_32;
1236                         }
1237                 } else if (HAS_SIZE(5,5,5,1)) {
1238                         return V_028C70_COLOR_1_5_5_5;
1239                 } else if (HAS_SIZE(10,10,10,2)) {
1240                         return V_028C70_COLOR_2_10_10_10;
1241                 }
1242                 break;
1243         }
1244         return V_028C70_COLOR_INVALID;
1245 }
1246
1247 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1248 {
1249         if (SI_BIG_ENDIAN) {
1250                 switch(colorformat) {
1251                 /* 8-bit buffers. */
1252                 case V_028C70_COLOR_8:
1253                         return V_028C70_ENDIAN_NONE;
1254
1255                 /* 16-bit buffers. */
1256                 case V_028C70_COLOR_5_6_5:
1257                 case V_028C70_COLOR_1_5_5_5:
1258                 case V_028C70_COLOR_4_4_4_4:
1259                 case V_028C70_COLOR_16:
1260                 case V_028C70_COLOR_8_8:
1261                         return V_028C70_ENDIAN_8IN16;
1262
1263                 /* 32-bit buffers. */
1264                 case V_028C70_COLOR_8_8_8_8:
1265                 case V_028C70_COLOR_2_10_10_10:
1266                 case V_028C70_COLOR_8_24:
1267                 case V_028C70_COLOR_24_8:
1268                 case V_028C70_COLOR_16_16:
1269                         return V_028C70_ENDIAN_8IN32;
1270
1271                 /* 64-bit buffers. */
1272                 case V_028C70_COLOR_16_16_16_16:
1273                         return V_028C70_ENDIAN_8IN16;
1274
1275                 case V_028C70_COLOR_32_32:
1276                         return V_028C70_ENDIAN_8IN32;
1277
1278                 /* 128-bit buffers. */
1279                 case V_028C70_COLOR_32_32_32_32:
1280                         return V_028C70_ENDIAN_8IN32;
1281                 default:
1282                         return V_028C70_ENDIAN_NONE; /* Unsupported. */
1283                 }
1284         } else {
1285                 return V_028C70_ENDIAN_NONE;
1286         }
1287 }
1288
1289 static uint32_t si_translate_dbformat(enum pipe_format format)
1290 {
1291         switch (format) {
1292         case PIPE_FORMAT_Z16_UNORM:
1293                 return V_028040_Z_16;
1294         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1295         case PIPE_FORMAT_X8Z24_UNORM:
1296         case PIPE_FORMAT_Z24X8_UNORM:
1297         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1298                 return V_028040_Z_24; /* deprecated on SI */
1299         case PIPE_FORMAT_Z32_FLOAT:
1300         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1301                 return V_028040_Z_32_FLOAT;
1302         default:
1303                 return V_028040_Z_INVALID;
1304         }
1305 }
1306
1307 /*
1308  * Texture translation
1309  */
1310
1311 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1312                                        enum pipe_format format,
1313                                        const struct util_format_description *desc,
1314                                        int first_non_void)
1315 {
1316         struct si_screen *sscreen = (struct si_screen*)screen;
1317         bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1318                                           sscreen->b.info.drm_minor >= 31) ||
1319                                          sscreen->b.info.drm_major == 3;
1320         bool uniform = true;
1321         int i;
1322
1323         /* Colorspace (return non-RGB formats directly). */
1324         switch (desc->colorspace) {
1325         /* Depth stencil formats */
1326         case UTIL_FORMAT_COLORSPACE_ZS:
1327                 switch (format) {
1328                 case PIPE_FORMAT_Z16_UNORM:
1329                         return V_008F14_IMG_DATA_FORMAT_16;
1330                 case PIPE_FORMAT_X24S8_UINT:
1331                 case PIPE_FORMAT_Z24X8_UNORM:
1332                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1333                         return V_008F14_IMG_DATA_FORMAT_8_24;
1334                 case PIPE_FORMAT_X8Z24_UNORM:
1335                 case PIPE_FORMAT_S8X24_UINT:
1336                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1337                         return V_008F14_IMG_DATA_FORMAT_24_8;
1338                 case PIPE_FORMAT_S8_UINT:
1339                         return V_008F14_IMG_DATA_FORMAT_8;
1340                 case PIPE_FORMAT_Z32_FLOAT:
1341                         return V_008F14_IMG_DATA_FORMAT_32;
1342                 case PIPE_FORMAT_X32_S8X24_UINT:
1343                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1344                         return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1345                 default:
1346                         goto out_unknown;
1347                 }
1348
1349         case UTIL_FORMAT_COLORSPACE_YUV:
1350                 goto out_unknown; /* TODO */
1351
1352         case UTIL_FORMAT_COLORSPACE_SRGB:
1353                 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1354                         goto out_unknown;
1355                 break;
1356
1357         default:
1358                 break;
1359         }
1360
1361         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1362                 if (!enable_compressed_formats)
1363                         goto out_unknown;
1364
1365                 switch (format) {
1366                 case PIPE_FORMAT_RGTC1_SNORM:
1367                 case PIPE_FORMAT_LATC1_SNORM:
1368                 case PIPE_FORMAT_RGTC1_UNORM:
1369                 case PIPE_FORMAT_LATC1_UNORM:
1370                         return V_008F14_IMG_DATA_FORMAT_BC4;
1371                 case PIPE_FORMAT_RGTC2_SNORM:
1372                 case PIPE_FORMAT_LATC2_SNORM:
1373                 case PIPE_FORMAT_RGTC2_UNORM:
1374                 case PIPE_FORMAT_LATC2_UNORM:
1375                         return V_008F14_IMG_DATA_FORMAT_BC5;
1376                 default:
1377                         goto out_unknown;
1378                 }
1379         }
1380
1381         if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1382             sscreen->b.family == CHIP_STONEY) {
1383                 switch (format) {
1384                 case PIPE_FORMAT_ETC1_RGB8:
1385                 case PIPE_FORMAT_ETC2_RGB8:
1386                 case PIPE_FORMAT_ETC2_SRGB8:
1387                         return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1388                 case PIPE_FORMAT_ETC2_RGB8A1:
1389                 case PIPE_FORMAT_ETC2_SRGB8A1:
1390                         return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1391                 case PIPE_FORMAT_ETC2_RGBA8:
1392                 case PIPE_FORMAT_ETC2_SRGBA8:
1393                         return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1394                 case PIPE_FORMAT_ETC2_R11_UNORM:
1395                 case PIPE_FORMAT_ETC2_R11_SNORM:
1396                         return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1397                 case PIPE_FORMAT_ETC2_RG11_UNORM:
1398                 case PIPE_FORMAT_ETC2_RG11_SNORM:
1399                         return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1400                 default:
1401                         goto out_unknown;
1402                 }
1403         }
1404
1405         if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1406                 if (!enable_compressed_formats)
1407                         goto out_unknown;
1408
1409                 switch (format) {
1410                 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1411                 case PIPE_FORMAT_BPTC_SRGBA:
1412                         return V_008F14_IMG_DATA_FORMAT_BC7;
1413                 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1414                 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1415                         return V_008F14_IMG_DATA_FORMAT_BC6;
1416                 default:
1417                         goto out_unknown;
1418                 }
1419         }
1420
1421         if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1422                 switch (format) {
1423                 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1424                 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1425                         return V_008F14_IMG_DATA_FORMAT_GB_GR;
1426                 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1427                 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1428                         return V_008F14_IMG_DATA_FORMAT_BG_RG;
1429                 default:
1430                         goto out_unknown;
1431                 }
1432         }
1433
1434         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1435                 if (!enable_compressed_formats)
1436                         goto out_unknown;
1437
1438                 if (!util_format_s3tc_enabled) {
1439                         goto out_unknown;
1440                 }
1441
1442                 switch (format) {
1443                 case PIPE_FORMAT_DXT1_RGB:
1444                 case PIPE_FORMAT_DXT1_RGBA:
1445                 case PIPE_FORMAT_DXT1_SRGB:
1446                 case PIPE_FORMAT_DXT1_SRGBA:
1447                         return V_008F14_IMG_DATA_FORMAT_BC1;
1448                 case PIPE_FORMAT_DXT3_RGBA:
1449                 case PIPE_FORMAT_DXT3_SRGBA:
1450                         return V_008F14_IMG_DATA_FORMAT_BC2;
1451                 case PIPE_FORMAT_DXT5_RGBA:
1452                 case PIPE_FORMAT_DXT5_SRGBA:
1453                         return V_008F14_IMG_DATA_FORMAT_BC3;
1454                 default:
1455                         goto out_unknown;
1456                 }
1457         }
1458
1459         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1460                 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1461         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1462                 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1463         }
1464
1465         /* R8G8Bx_SNORM - TODO CxV8U8 */
1466
1467         /* hw cannot support mixed formats (except depth/stencil, since only
1468          * depth is read).*/
1469         if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1470                 goto out_unknown;
1471
1472         /* See whether the components are of the same size. */
1473         for (i = 1; i < desc->nr_channels; i++) {
1474                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1475         }
1476
1477         /* Non-uniform formats. */
1478         if (!uniform) {
1479                 switch(desc->nr_channels) {
1480                 case 3:
1481                         if (desc->channel[0].size == 5 &&
1482                             desc->channel[1].size == 6 &&
1483                             desc->channel[2].size == 5) {
1484                                 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1485                         }
1486                         goto out_unknown;
1487                 case 4:
1488                         if (desc->channel[0].size == 5 &&
1489                             desc->channel[1].size == 5 &&
1490                             desc->channel[2].size == 5 &&
1491                             desc->channel[3].size == 1) {
1492                                 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1493                         }
1494                         if (desc->channel[0].size == 10 &&
1495                             desc->channel[1].size == 10 &&
1496                             desc->channel[2].size == 10 &&
1497                             desc->channel[3].size == 2) {
1498                                 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1499                         }
1500                         goto out_unknown;
1501                 }
1502                 goto out_unknown;
1503         }
1504
1505         if (first_non_void < 0 || first_non_void > 3)
1506                 goto out_unknown;
1507
1508         /* uniform formats */
1509         switch (desc->channel[first_non_void].size) {
1510         case 4:
1511                 switch (desc->nr_channels) {
1512 #if 0 /* Not supported for render targets */
1513                 case 2:
1514                         return V_008F14_IMG_DATA_FORMAT_4_4;
1515 #endif
1516                 case 4:
1517                         return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1518                 }
1519                 break;
1520         case 8:
1521                 switch (desc->nr_channels) {
1522                 case 1:
1523                         return V_008F14_IMG_DATA_FORMAT_8;
1524                 case 2:
1525                         return V_008F14_IMG_DATA_FORMAT_8_8;
1526                 case 4:
1527                         return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1528                 }
1529                 break;
1530         case 16:
1531                 switch (desc->nr_channels) {
1532                 case 1:
1533                         return V_008F14_IMG_DATA_FORMAT_16;
1534                 case 2:
1535                         return V_008F14_IMG_DATA_FORMAT_16_16;
1536                 case 4:
1537                         return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1538                 }
1539                 break;
1540         case 32:
1541                 switch (desc->nr_channels) {
1542                 case 1:
1543                         return V_008F14_IMG_DATA_FORMAT_32;
1544                 case 2:
1545                         return V_008F14_IMG_DATA_FORMAT_32_32;
1546 #if 0 /* Not supported for render targets */
1547                 case 3:
1548                         return V_008F14_IMG_DATA_FORMAT_32_32_32;
1549 #endif
1550                 case 4:
1551                         return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1552                 }
1553         }
1554
1555 out_unknown:
1556         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1557         return ~0;
1558 }
1559
1560 static unsigned si_tex_wrap(unsigned wrap)
1561 {
1562         switch (wrap) {
1563         default:
1564         case PIPE_TEX_WRAP_REPEAT:
1565                 return V_008F30_SQ_TEX_WRAP;
1566         case PIPE_TEX_WRAP_CLAMP:
1567                 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1568         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1569                 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1570         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1571                 return V_008F30_SQ_TEX_CLAMP_BORDER;
1572         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1573                 return V_008F30_SQ_TEX_MIRROR;
1574         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1575                 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1576         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1577                 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1578         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1579                 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1580         }
1581 }
1582
1583 static unsigned si_tex_mipfilter(unsigned filter)
1584 {
1585         switch (filter) {
1586         case PIPE_TEX_MIPFILTER_NEAREST:
1587                 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1588         case PIPE_TEX_MIPFILTER_LINEAR:
1589                 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1590         default:
1591         case PIPE_TEX_MIPFILTER_NONE:
1592                 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1593         }
1594 }
1595
1596 static unsigned si_tex_compare(unsigned compare)
1597 {
1598         switch (compare) {
1599         default:
1600         case PIPE_FUNC_NEVER:
1601                 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1602         case PIPE_FUNC_LESS:
1603                 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1604         case PIPE_FUNC_EQUAL:
1605                 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1606         case PIPE_FUNC_LEQUAL:
1607                 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1608         case PIPE_FUNC_GREATER:
1609                 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1610         case PIPE_FUNC_NOTEQUAL:
1611                 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1612         case PIPE_FUNC_GEQUAL:
1613                 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1614         case PIPE_FUNC_ALWAYS:
1615                 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1616         }
1617 }
1618
1619 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1620                            unsigned nr_samples)
1621 {
1622         if (view_target == PIPE_TEXTURE_CUBE ||
1623             view_target == PIPE_TEXTURE_CUBE_ARRAY)
1624                 res_target = view_target;
1625         /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1626         else if (res_target == PIPE_TEXTURE_CUBE ||
1627                  res_target == PIPE_TEXTURE_CUBE_ARRAY)
1628                 res_target = PIPE_TEXTURE_2D_ARRAY;
1629
1630         switch (res_target) {
1631         default:
1632         case PIPE_TEXTURE_1D:
1633                 return V_008F1C_SQ_RSRC_IMG_1D;
1634         case PIPE_TEXTURE_1D_ARRAY:
1635                 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1636         case PIPE_TEXTURE_2D:
1637         case PIPE_TEXTURE_RECT:
1638                 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1639                                         V_008F1C_SQ_RSRC_IMG_2D;
1640         case PIPE_TEXTURE_2D_ARRAY:
1641                 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1642                                         V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1643         case PIPE_TEXTURE_3D:
1644                 return V_008F1C_SQ_RSRC_IMG_3D;
1645         case PIPE_TEXTURE_CUBE:
1646         case PIPE_TEXTURE_CUBE_ARRAY:
1647                 return V_008F1C_SQ_RSRC_IMG_CUBE;
1648         }
1649 }
1650
1651 /*
1652  * Format support testing
1653  */
1654
1655 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1656 {
1657         return si_translate_texformat(screen, format, util_format_description(format),
1658                                       util_format_get_first_non_void_channel(format)) != ~0U;
1659 }
1660
1661 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1662                                                const struct util_format_description *desc,
1663                                                int first_non_void)
1664 {
1665         unsigned type;
1666         int i;
1667
1668         if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1669                 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1670
1671         assert(first_non_void >= 0);
1672         type = desc->channel[first_non_void].type;
1673
1674         if (type == UTIL_FORMAT_TYPE_FIXED)
1675                 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1676
1677         if (desc->nr_channels == 4 &&
1678             desc->channel[0].size == 10 &&
1679             desc->channel[1].size == 10 &&
1680             desc->channel[2].size == 10 &&
1681             desc->channel[3].size == 2)
1682                 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1683
1684         /* See whether the components are of the same size. */
1685         for (i = 0; i < desc->nr_channels; i++) {
1686                 if (desc->channel[first_non_void].size != desc->channel[i].size)
1687                         return V_008F0C_BUF_DATA_FORMAT_INVALID;
1688         }
1689
1690         switch (desc->channel[first_non_void].size) {
1691         case 8:
1692                 switch (desc->nr_channels) {
1693                 case 1:
1694                         return V_008F0C_BUF_DATA_FORMAT_8;
1695                 case 2:
1696                         return V_008F0C_BUF_DATA_FORMAT_8_8;
1697                 case 3:
1698                 case 4:
1699                         return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1700                 }
1701                 break;
1702         case 16:
1703                 switch (desc->nr_channels) {
1704                 case 1:
1705                         return V_008F0C_BUF_DATA_FORMAT_16;
1706                 case 2:
1707                         return V_008F0C_BUF_DATA_FORMAT_16_16;
1708                 case 3:
1709                 case 4:
1710                         return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1711                 }
1712                 break;
1713         case 32:
1714                 /* From the Southern Islands ISA documentation about MTBUF:
1715                  * 'Memory reads of data in memory that is 32 or 64 bits do not
1716                  * undergo any format conversion.'
1717                  */
1718                 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1719                     !desc->channel[first_non_void].pure_integer)
1720                         return V_008F0C_BUF_DATA_FORMAT_INVALID;
1721
1722                 switch (desc->nr_channels) {
1723                 case 1:
1724                         return V_008F0C_BUF_DATA_FORMAT_32;
1725                 case 2:
1726                         return V_008F0C_BUF_DATA_FORMAT_32_32;
1727                 case 3:
1728                         return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1729                 case 4:
1730                         return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1731                 }
1732                 break;
1733         }
1734
1735         return V_008F0C_BUF_DATA_FORMAT_INVALID;
1736 }
1737
1738 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1739                                               const struct util_format_description *desc,
1740                                               int first_non_void)
1741 {
1742         if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1743                 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1744
1745         assert(first_non_void >= 0);
1746
1747         switch (desc->channel[first_non_void].type) {
1748         case UTIL_FORMAT_TYPE_SIGNED:
1749                 if (desc->channel[first_non_void].normalized)
1750                         return V_008F0C_BUF_NUM_FORMAT_SNORM;
1751                 else if (desc->channel[first_non_void].pure_integer)
1752                         return V_008F0C_BUF_NUM_FORMAT_SINT;
1753                 else
1754                         return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1755                 break;
1756         case UTIL_FORMAT_TYPE_UNSIGNED:
1757                 if (desc->channel[first_non_void].normalized)
1758                         return V_008F0C_BUF_NUM_FORMAT_UNORM;
1759                 else if (desc->channel[first_non_void].pure_integer)
1760                         return V_008F0C_BUF_NUM_FORMAT_UINT;
1761                 else
1762                         return V_008F0C_BUF_NUM_FORMAT_USCALED;
1763                 break;
1764         case UTIL_FORMAT_TYPE_FLOAT:
1765         default:
1766                 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1767         }
1768 }
1769
1770 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1771 {
1772         const struct util_format_description *desc;
1773         int first_non_void;
1774         unsigned data_format;
1775
1776         desc = util_format_description(format);
1777         first_non_void = util_format_get_first_non_void_channel(format);
1778         data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1779         return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1780 }
1781
1782 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1783 {
1784         return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1785                 r600_translate_colorswap(format, false) != ~0U;
1786 }
1787
1788 static bool si_is_zs_format_supported(enum pipe_format format)
1789 {
1790         return si_translate_dbformat(format) != V_028040_Z_INVALID;
1791 }
1792
1793 static boolean si_is_format_supported(struct pipe_screen *screen,
1794                                       enum pipe_format format,
1795                                       enum pipe_texture_target target,
1796                                       unsigned sample_count,
1797                                       unsigned usage)
1798 {
1799         unsigned retval = 0;
1800
1801         if (target >= PIPE_MAX_TEXTURE_TYPES) {
1802                 R600_ERR("r600: unsupported texture type %d\n", target);
1803                 return false;
1804         }
1805
1806         if (!util_format_is_supported(format, usage))
1807                 return false;
1808
1809         if (sample_count > 1) {
1810                 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1811                         return false;
1812
1813                 if (usage & PIPE_BIND_SHADER_IMAGE)
1814                         return false;
1815
1816                 switch (sample_count) {
1817                 case 2:
1818                 case 4:
1819                 case 8:
1820                         break;
1821                 case 16:
1822                         if (format == PIPE_FORMAT_NONE)
1823                                 return true;
1824                         else
1825                                 return false;
1826                 default:
1827                         return false;
1828                 }
1829         }
1830
1831         if (usage & (PIPE_BIND_SAMPLER_VIEW |
1832                      PIPE_BIND_SHADER_IMAGE)) {
1833                 if (target == PIPE_BUFFER) {
1834                         if (si_is_vertex_format_supported(screen, format))
1835                                 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1836                                                    PIPE_BIND_SHADER_IMAGE);
1837                 } else {
1838                         if (si_is_sampler_format_supported(screen, format))
1839                                 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1840                                                    PIPE_BIND_SHADER_IMAGE);
1841                 }
1842         }
1843
1844         if ((usage & (PIPE_BIND_RENDER_TARGET |
1845                       PIPE_BIND_DISPLAY_TARGET |
1846                       PIPE_BIND_SCANOUT |
1847                       PIPE_BIND_SHARED |
1848                       PIPE_BIND_BLENDABLE)) &&
1849             si_is_colorbuffer_format_supported(format)) {
1850                 retval |= usage &
1851                           (PIPE_BIND_RENDER_TARGET |
1852                            PIPE_BIND_DISPLAY_TARGET |
1853                            PIPE_BIND_SCANOUT |
1854                            PIPE_BIND_SHARED);
1855                 if (!util_format_is_pure_integer(format) &&
1856                     !util_format_is_depth_or_stencil(format))
1857                         retval |= usage & PIPE_BIND_BLENDABLE;
1858         }
1859
1860         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1861             si_is_zs_format_supported(format)) {
1862                 retval |= PIPE_BIND_DEPTH_STENCIL;
1863         }
1864
1865         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1866             si_is_vertex_format_supported(screen, format)) {
1867                 retval |= PIPE_BIND_VERTEX_BUFFER;
1868         }
1869
1870         if ((usage & PIPE_BIND_LINEAR) &&
1871             !util_format_is_compressed(format) &&
1872             !(usage & PIPE_BIND_DEPTH_STENCIL))
1873                 retval |= PIPE_BIND_LINEAR;
1874
1875         return retval == usage;
1876 }
1877
1878 /*
1879  * framebuffer handling
1880  */
1881
1882 static void si_choose_spi_color_formats(struct r600_surface *surf,
1883                                         unsigned format, unsigned swap,
1884                                         unsigned ntype, bool is_depth)
1885 {
1886         /* Alpha is needed for alpha-to-coverage.
1887          * Blending may be with or without alpha.
1888          */
1889         unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1890         unsigned alpha = 0; /* exports alpha, but may not support blending */
1891         unsigned blend = 0; /* supports blending, but may not export alpha */
1892         unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1893
1894         /* Choose the SPI color formats. These are required values for Stoney/RB+.
1895          * Other chips have multiple choices, though they are not necessarily better.
1896          */
1897         switch (format) {
1898         case V_028C70_COLOR_5_6_5:
1899         case V_028C70_COLOR_1_5_5_5:
1900         case V_028C70_COLOR_5_5_5_1:
1901         case V_028C70_COLOR_4_4_4_4:
1902         case V_028C70_COLOR_10_11_11:
1903         case V_028C70_COLOR_11_11_10:
1904         case V_028C70_COLOR_8:
1905         case V_028C70_COLOR_8_8:
1906         case V_028C70_COLOR_8_8_8_8:
1907         case V_028C70_COLOR_10_10_10_2:
1908         case V_028C70_COLOR_2_10_10_10:
1909                 if (ntype == V_028C70_NUMBER_UINT)
1910                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1911                 else if (ntype == V_028C70_NUMBER_SINT)
1912                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1913                 else
1914                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1915                 break;
1916
1917         case V_028C70_COLOR_16:
1918         case V_028C70_COLOR_16_16:
1919         case V_028C70_COLOR_16_16_16_16:
1920                 if (ntype == V_028C70_NUMBER_UNORM ||
1921                     ntype == V_028C70_NUMBER_SNORM) {
1922                         /* UNORM16 and SNORM16 don't support blending */
1923                         if (ntype == V_028C70_NUMBER_UNORM)
1924                                 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1925                         else
1926                                 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1927
1928                         /* Use 32 bits per channel for blending. */
1929                         if (format == V_028C70_COLOR_16) {
1930                                 if (swap == V_028C70_SWAP_STD) { /* R */
1931                                         blend = V_028714_SPI_SHADER_32_R;
1932                                         blend_alpha = V_028714_SPI_SHADER_32_AR;
1933                                 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1934                                         blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1935                                 else
1936                                         assert(0);
1937                         } else if (format == V_028C70_COLOR_16_16) {
1938                                 if (swap == V_028C70_SWAP_STD) { /* RG */
1939                                         blend = V_028714_SPI_SHADER_32_GR;
1940                                         blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1941                                 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1942                                         blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1943                                 else
1944                                         assert(0);
1945                         } else /* 16_16_16_16 */
1946                                 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1947                 } else if (ntype == V_028C70_NUMBER_UINT)
1948                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1949                 else if (ntype == V_028C70_NUMBER_SINT)
1950                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1951                 else if (ntype == V_028C70_NUMBER_FLOAT)
1952                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1953                 else
1954                         assert(0);
1955                 break;
1956
1957         case V_028C70_COLOR_32:
1958                 if (swap == V_028C70_SWAP_STD) { /* R */
1959                         blend = normal = V_028714_SPI_SHADER_32_R;
1960                         alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1961                 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1962                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1963                 else
1964                         assert(0);
1965                 break;
1966
1967         case V_028C70_COLOR_32_32:
1968                 if (swap == V_028C70_SWAP_STD) { /* RG */
1969                         blend = normal = V_028714_SPI_SHADER_32_GR;
1970                         alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1971                 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1972                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1973                 else
1974                         assert(0);
1975                 break;
1976
1977         case V_028C70_COLOR_32_32_32_32:
1978         case V_028C70_COLOR_8_24:
1979         case V_028C70_COLOR_24_8:
1980         case V_028C70_COLOR_X24_8_32_FLOAT:
1981                 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1982                 break;
1983
1984         default:
1985                 assert(0);
1986                 return;
1987         }
1988
1989         /* The DB->CB copy needs 32_ABGR. */
1990         if (is_depth)
1991                 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1992
1993         surf->spi_shader_col_format = normal;
1994         surf->spi_shader_col_format_alpha = alpha;
1995         surf->spi_shader_col_format_blend = blend;
1996         surf->spi_shader_col_format_blend_alpha = blend_alpha;
1997 }
1998
1999 static void si_initialize_color_surface(struct si_context *sctx,
2000                                         struct r600_surface *surf)
2001 {
2002         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2003         unsigned color_info, color_attrib, color_view;
2004         unsigned format, swap, ntype, endian;
2005         const struct util_format_description *desc;
2006         int i;
2007         unsigned blend_clamp = 0, blend_bypass = 0;
2008
2009         color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2010                      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2011
2012         desc = util_format_description(surf->base.format);
2013         for (i = 0; i < 4; i++) {
2014                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2015                         break;
2016                 }
2017         }
2018         if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2019                 ntype = V_028C70_NUMBER_FLOAT;
2020         } else {
2021                 ntype = V_028C70_NUMBER_UNORM;
2022                 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2023                         ntype = V_028C70_NUMBER_SRGB;
2024                 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2025                         if (desc->channel[i].pure_integer) {
2026                                 ntype = V_028C70_NUMBER_SINT;
2027                         } else {
2028                                 assert(desc->channel[i].normalized);
2029                                 ntype = V_028C70_NUMBER_SNORM;
2030                         }
2031                 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2032                         if (desc->channel[i].pure_integer) {
2033                                 ntype = V_028C70_NUMBER_UINT;
2034                         } else {
2035                                 assert(desc->channel[i].normalized);
2036                                 ntype = V_028C70_NUMBER_UNORM;
2037                         }
2038                 }
2039         }
2040
2041         format = si_translate_colorformat(surf->base.format);
2042         if (format == V_028C70_COLOR_INVALID) {
2043                 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2044         }
2045         assert(format != V_028C70_COLOR_INVALID);
2046         swap = r600_translate_colorswap(surf->base.format, false);
2047         endian = si_colorformat_endian_swap(format);
2048
2049         /* blend clamp should be set for all NORM/SRGB types */
2050         if (ntype == V_028C70_NUMBER_UNORM ||
2051             ntype == V_028C70_NUMBER_SNORM ||
2052             ntype == V_028C70_NUMBER_SRGB)
2053                 blend_clamp = 1;
2054
2055         /* set blend bypass according to docs if SINT/UINT or
2056            8/24 COLOR variants */
2057         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2058             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2059             format == V_028C70_COLOR_X24_8_32_FLOAT) {
2060                 blend_clamp = 0;
2061                 blend_bypass = 1;
2062         }
2063
2064         if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2065             (format == V_028C70_COLOR_8 ||
2066              format == V_028C70_COLOR_8_8 ||
2067              format == V_028C70_COLOR_8_8_8_8))
2068                 surf->color_is_int8 = true;
2069
2070         color_info = S_028C70_FORMAT(format) |
2071                 S_028C70_COMP_SWAP(swap) |
2072                 S_028C70_BLEND_CLAMP(blend_clamp) |
2073                 S_028C70_BLEND_BYPASS(blend_bypass) |
2074                 S_028C70_SIMPLE_FLOAT(1) |
2075                 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2076                                     ntype != V_028C70_NUMBER_SNORM &&
2077                                     ntype != V_028C70_NUMBER_SRGB &&
2078                                     format != V_028C70_COLOR_8_24 &&
2079                                     format != V_028C70_COLOR_24_8) |
2080                 S_028C70_NUMBER_TYPE(ntype) |
2081                 S_028C70_ENDIAN(endian);
2082
2083         /* Intensity is implemented as Red, so treat it that way. */
2084         color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2085                                                   util_format_is_intensity(surf->base.format));
2086
2087         if (rtex->resource.b.b.nr_samples > 1) {
2088                 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2089
2090                 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2091                                 S_028C74_NUM_FRAGMENTS(log_samples);
2092
2093                 if (rtex->fmask.size) {
2094                         color_info |= S_028C70_COMPRESSION(1);
2095                         unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2096
2097                         if (sctx->b.chip_class == SI) {
2098                                 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2099                                 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2100                         }
2101                 }
2102         }
2103
2104         surf->cb_color_view = color_view;
2105         surf->cb_color_info = color_info;
2106         surf->cb_color_attrib = color_attrib;
2107
2108         if (sctx->b.chip_class >= VI) {
2109                 unsigned max_uncompressed_block_size = 2;
2110
2111                 if (rtex->resource.b.b.nr_samples > 1) {
2112                         if (rtex->surface.bpe == 1)
2113                                 max_uncompressed_block_size = 0;
2114                         else if (rtex->surface.bpe == 2)
2115                                 max_uncompressed_block_size = 1;
2116                 }
2117
2118                 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2119                                        S_028C78_INDEPENDENT_64B_BLOCKS(1);
2120         }
2121
2122         /* This must be set for fast clear to work without FMASK. */
2123         if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2124                 unsigned bankh = util_logbase2(rtex->surface.bankh);
2125                 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2126         }
2127
2128         /* Determine pixel shader export format */
2129         si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2130
2131         surf->color_initialized = true;
2132 }
2133
2134 static void si_init_depth_surface(struct si_context *sctx,
2135                                   struct r600_surface *surf)
2136 {
2137         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2138         unsigned level = surf->base.u.tex.level;
2139         struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2140         unsigned format;
2141         uint32_t z_info, s_info, db_depth_info;
2142         uint64_t z_offs, s_offs;
2143         uint32_t db_htile_data_base, db_htile_surface;
2144
2145         format = si_translate_dbformat(rtex->db_render_format);
2146
2147         if (format == V_028040_Z_INVALID) {
2148                 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2149         }
2150         assert(format != V_028040_Z_INVALID);
2151
2152         s_offs = z_offs = rtex->resource.gpu_address;
2153         z_offs += rtex->surface.level[level].offset;
2154         s_offs += rtex->surface.stencil_level[level].offset;
2155
2156         db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2157
2158         z_info = S_028040_FORMAT(format);
2159         if (rtex->resource.b.b.nr_samples > 1) {
2160                 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2161         }
2162
2163         if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2164                 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2165         else
2166                 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2167
2168         if (sctx->b.chip_class >= CIK) {
2169                 struct radeon_info *info = &sctx->screen->b.info;
2170                 unsigned index = rtex->surface.tiling_index[level];
2171                 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2172                 unsigned macro_index = rtex->surface.macro_tile_index;
2173                 unsigned tile_mode = info->si_tile_mode_array[index];
2174                 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2175                 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2176
2177                 db_depth_info |=
2178                         S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2179                         S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2180                         S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2181                         S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2182                         S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2183                         S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2184                 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2185                 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2186         } else {
2187                 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2188                 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2189                 tile_mode_index = si_tile_mode_index(rtex, level, true);
2190                 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2191         }
2192
2193         /* HiZ aka depth buffer htile */
2194         /* use htile only for first level */
2195         if (rtex->htile_buffer && !level) {
2196                 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2197                           S_028040_ALLOW_EXPCLEAR(1);
2198
2199                 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2200                         /* Workaround: For a not yet understood reason, the
2201                          * combination of MSAA, fast stencil clear and stencil
2202                          * decompress messes with subsequent stencil buffer
2203                          * uses. Problem was reproduced on Verde, Bonaire,
2204                          * Tonga, and Carrizo.
2205                          *
2206                          * Disabling EXPCLEAR works around the problem.
2207                          *
2208                          * Check piglit's arb_texture_multisample-stencil-clear
2209                          * test if you want to try changing this.
2210                          */
2211                         if (rtex->resource.b.b.nr_samples <= 1)
2212                                 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2213                 } else if (!rtex->tc_compatible_htile) {
2214                         /* Use all of the htile_buffer for depth if there's no stencil.
2215                          * This must not be set when TC-compatible HTILE is enabled
2216                          * due to a hw bug.
2217                          */
2218                         s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2219                 }
2220
2221                 uint64_t va = rtex->htile_buffer->gpu_address;
2222                 db_htile_data_base = va >> 8;
2223                 db_htile_surface = S_028ABC_FULL_CACHE(1);
2224
2225                 if (rtex->tc_compatible_htile) {
2226                         db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2227
2228                         switch (rtex->resource.b.b.nr_samples) {
2229                         case 0:
2230                         case 1:
2231                                 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2232                                 break;
2233                         case 2:
2234                         case 4:
2235                                 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2236                                 break;
2237                         case 8:
2238                                 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2239                                 break;
2240                         default:
2241                                 assert(0);
2242                         }
2243                 }
2244         } else {
2245                 db_htile_data_base = 0;
2246                 db_htile_surface = 0;
2247         }
2248
2249         assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2250
2251         surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2252                               S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2253         surf->db_htile_data_base = db_htile_data_base;
2254         surf->db_depth_info = db_depth_info;
2255         surf->db_z_info = z_info;
2256         surf->db_stencil_info = s_info;
2257         surf->db_depth_base = z_offs >> 8;
2258         surf->db_stencil_base = s_offs >> 8;
2259         surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2260                               S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2261         surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2262                                                         levelinfo->nblk_y) / 64 - 1);
2263         surf->db_htile_surface = db_htile_surface;
2264
2265         surf->depth_initialized = true;
2266 }
2267
2268 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2269 {
2270         for (int i = 0; i < state->nr_cbufs; ++i) {
2271                 struct r600_surface *surf = NULL;
2272                 struct r600_texture *rtex;
2273
2274                 if (!state->cbufs[i])
2275                         continue;
2276                 surf = (struct r600_surface*)state->cbufs[i];
2277                 rtex = (struct r600_texture*)surf->base.texture;
2278
2279                 p_atomic_dec(&rtex->framebuffers_bound);
2280         }
2281 }
2282
2283 static void si_set_framebuffer_state(struct pipe_context *ctx,
2284                                      const struct pipe_framebuffer_state *state)
2285 {
2286         struct si_context *sctx = (struct si_context *)ctx;
2287         struct pipe_constant_buffer constbuf = {0};
2288         struct r600_surface *surf = NULL;
2289         struct r600_texture *rtex;
2290         bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2291         unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2292         int i;
2293
2294         for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2295                 if (!sctx->framebuffer.state.cbufs[i])
2296                         continue;
2297
2298                 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2299                 if (rtex->dcc_gather_statistics)
2300                         vi_separate_dcc_stop_query(ctx, rtex);
2301         }
2302
2303         /* Only flush TC when changing the framebuffer state, because
2304          * the only client not using TC that can change textures is
2305          * the framebuffer.
2306          *
2307          * Flush all CB and DB caches here because all buffers can be used
2308          * for write by both TC (with shader image stores) and CB/DB.
2309          */
2310         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2311                          SI_CONTEXT_INV_GLOBAL_L2 |
2312                          SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2313                          SI_CONTEXT_CS_PARTIAL_FLUSH;
2314
2315         /* Take the maximum of the old and new count. If the new count is lower,
2316          * dirtying is needed to disable the unbound colorbuffers.
2317          */
2318         sctx->framebuffer.dirty_cbufs |=
2319                 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2320         sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2321
2322         si_dec_framebuffer_counters(&sctx->framebuffer.state);
2323         util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2324
2325         sctx->framebuffer.spi_shader_col_format = 0;
2326         sctx->framebuffer.spi_shader_col_format_alpha = 0;
2327         sctx->framebuffer.spi_shader_col_format_blend = 0;
2328         sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2329         sctx->framebuffer.color_is_int8 = 0;
2330
2331         sctx->framebuffer.compressed_cb_mask = 0;
2332         sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2333         sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2334         sctx->framebuffer.any_dst_linear = false;
2335
2336         for (i = 0; i < state->nr_cbufs; i++) {
2337                 if (!state->cbufs[i])
2338                         continue;
2339
2340                 surf = (struct r600_surface*)state->cbufs[i];
2341                 rtex = (struct r600_texture*)surf->base.texture;
2342
2343                 if (!surf->color_initialized) {
2344                         si_initialize_color_surface(sctx, surf);
2345                 }
2346
2347                 sctx->framebuffer.spi_shader_col_format |=
2348                         surf->spi_shader_col_format << (i * 4);
2349                 sctx->framebuffer.spi_shader_col_format_alpha |=
2350                         surf->spi_shader_col_format_alpha << (i * 4);
2351                 sctx->framebuffer.spi_shader_col_format_blend |=
2352                         surf->spi_shader_col_format_blend << (i * 4);
2353                 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2354                         surf->spi_shader_col_format_blend_alpha << (i * 4);
2355
2356                 if (surf->color_is_int8)
2357                         sctx->framebuffer.color_is_int8 |= 1 << i;
2358
2359                 if (rtex->fmask.size) {
2360                         sctx->framebuffer.compressed_cb_mask |= 1 << i;
2361                 }
2362
2363                 if (rtex->surface.is_linear)
2364                         sctx->framebuffer.any_dst_linear = true;
2365
2366                 r600_context_add_resource_size(ctx, surf->base.texture);
2367
2368                 p_atomic_inc(&rtex->framebuffers_bound);
2369
2370                 if (rtex->dcc_gather_statistics) {
2371                         /* Dirty tracking must be enabled for DCC usage analysis. */
2372                         sctx->framebuffer.compressed_cb_mask |= 1 << i;
2373                         vi_separate_dcc_start_query(ctx, rtex);
2374                 }
2375         }
2376
2377         if (state->zsbuf) {
2378                 surf = (struct r600_surface*)state->zsbuf;
2379                 rtex = (struct r600_texture*)surf->base.texture;
2380
2381                 if (!surf->depth_initialized) {
2382                         si_init_depth_surface(sctx, surf);
2383                 }
2384                 r600_context_add_resource_size(ctx, surf->base.texture);
2385         }
2386
2387         si_update_poly_offset_state(sctx);
2388         si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2389         si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2390
2391         if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2392                 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2393
2394         if (sctx->framebuffer.nr_samples != old_nr_samples) {
2395                 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2396                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2397
2398                 /* Set sample locations as fragment shader constants. */
2399                 switch (sctx->framebuffer.nr_samples) {
2400                 case 1:
2401                         constbuf.user_buffer = sctx->b.sample_locations_1x;
2402                         break;
2403                 case 2:
2404                         constbuf.user_buffer = sctx->b.sample_locations_2x;
2405                         break;
2406                 case 4:
2407                         constbuf.user_buffer = sctx->b.sample_locations_4x;
2408                         break;
2409                 case 8:
2410                         constbuf.user_buffer = sctx->b.sample_locations_8x;
2411                         break;
2412                 case 16:
2413                         constbuf.user_buffer = sctx->b.sample_locations_16x;
2414                         break;
2415                 default:
2416                         R600_ERR("Requested an invalid number of samples %i.\n",
2417                                  sctx->framebuffer.nr_samples);
2418                         assert(0);
2419                 }
2420                 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2421                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2422
2423                 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2424         }
2425
2426         sctx->need_check_render_feedback = true;
2427         sctx->do_update_shaders = true;
2428 }
2429
2430 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2431 {
2432         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2433         struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2434         unsigned i, nr_cbufs = state->nr_cbufs;
2435         struct r600_texture *tex = NULL;
2436         struct r600_surface *cb = NULL;
2437         unsigned cb_color_info = 0;
2438
2439         /* Colorbuffers. */
2440         for (i = 0; i < nr_cbufs; i++) {
2441                 const struct radeon_surf_level *level_info;
2442                 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2443                 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2444                 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2445
2446                 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2447                         continue;
2448
2449                 cb = (struct r600_surface*)state->cbufs[i];
2450                 if (!cb) {
2451                         radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2452                                                S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2453                         continue;
2454                 }
2455
2456                 tex = (struct r600_texture *)cb->base.texture;
2457                 level_info =  &tex->surface.level[cb->base.u.tex.level];
2458                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2459                                       &tex->resource, RADEON_USAGE_READWRITE,
2460                                       tex->resource.b.b.nr_samples > 1 ?
2461                                               RADEON_PRIO_COLOR_BUFFER_MSAA :
2462                                               RADEON_PRIO_COLOR_BUFFER);
2463
2464                 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2465                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2466                                 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2467                                 RADEON_PRIO_CMASK);
2468                 }
2469
2470                 if (tex->dcc_separate_buffer)
2471                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2472                                                   tex->dcc_separate_buffer,
2473                                                   RADEON_USAGE_READWRITE,
2474                                                   RADEON_PRIO_DCC);
2475
2476                 /* Compute mutable surface parameters. */
2477                 pitch_tile_max = level_info->nblk_x / 8 - 1;
2478                 slice_tile_max = level_info->nblk_x *
2479                                  level_info->nblk_y / 64 - 1;
2480                 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2481
2482                 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2483                 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2484                 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2485                 cb_color_attrib = cb->cb_color_attrib |
2486                                   S_028C74_TILE_MODE_INDEX(tile_mode_index);
2487
2488                 if (tex->fmask.size) {
2489                         if (sctx->b.chip_class >= CIK)
2490                                 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2491                         cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2492                         cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2493                         cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2494                 } else {
2495                         /* This must be set for fast clear to work without FMASK. */
2496                         if (sctx->b.chip_class >= CIK)
2497                                 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2498                         cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2499                         cb_color_fmask = cb_color_base;
2500                         cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2501                 }
2502
2503                 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2504
2505                 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2506                         bool is_msaa_resolve_dst = state->cbufs[0] &&
2507                                                    state->cbufs[0]->texture->nr_samples > 1 &&
2508                                                    state->cbufs[1] == &cb->base &&
2509                                                    state->cbufs[1]->texture->nr_samples <= 1;
2510
2511                         if (!is_msaa_resolve_dst)
2512                                 cb_color_info |= S_028C70_DCC_ENABLE(1);
2513                 }
2514
2515                 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2516                                            sctx->b.chip_class >= VI ? 14 : 13);
2517                 radeon_emit(cs, cb_color_base);         /* R_028C60_CB_COLOR0_BASE */
2518                 radeon_emit(cs, cb_color_pitch);        /* R_028C64_CB_COLOR0_PITCH */
2519                 radeon_emit(cs, cb_color_slice);        /* R_028C68_CB_COLOR0_SLICE */
2520                 radeon_emit(cs, cb->cb_color_view);     /* R_028C6C_CB_COLOR0_VIEW */
2521                 radeon_emit(cs, cb_color_info);         /* R_028C70_CB_COLOR0_INFO */
2522                 radeon_emit(cs, cb_color_attrib);       /* R_028C74_CB_COLOR0_ATTRIB */
2523                 radeon_emit(cs, cb->cb_dcc_control);    /* R_028C78_CB_COLOR0_DCC_CONTROL */
2524                 radeon_emit(cs, tex->cmask.base_address_reg);   /* R_028C7C_CB_COLOR0_CMASK */
2525                 radeon_emit(cs, tex->cmask.slice_tile_max);     /* R_028C80_CB_COLOR0_CMASK_SLICE */
2526                 radeon_emit(cs, cb_color_fmask);                /* R_028C84_CB_COLOR0_FMASK */
2527                 radeon_emit(cs, cb_color_fmask_slice);          /* R_028C88_CB_COLOR0_FMASK_SLICE */
2528                 radeon_emit(cs, tex->color_clear_value[0]);     /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2529                 radeon_emit(cs, tex->color_clear_value[1]);     /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2530
2531                 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2532                         radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2533                                          tex->dcc_offset +
2534                                          tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2535         }
2536         for (; i < 8 ; i++)
2537                 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2538                         radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2539
2540         /* ZS buffer. */
2541         if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2542                 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2543                 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2544
2545                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2546                                       &rtex->resource, RADEON_USAGE_READWRITE,
2547                                       zb->base.texture->nr_samples > 1 ?
2548                                               RADEON_PRIO_DEPTH_BUFFER_MSAA :
2549                                               RADEON_PRIO_DEPTH_BUFFER);
2550
2551                 if (zb->db_htile_data_base) {
2552                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2553                                               rtex->htile_buffer, RADEON_USAGE_READWRITE,
2554                                               RADEON_PRIO_HTILE);
2555                 }
2556
2557                 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2558                 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2559
2560                 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2561                 radeon_emit(cs, zb->db_depth_info);     /* R_02803C_DB_DEPTH_INFO */
2562                 radeon_emit(cs, zb->db_z_info |         /* R_028040_DB_Z_INFO */
2563                             S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2564                 radeon_emit(cs, zb->db_stencil_info);   /* R_028044_DB_STENCIL_INFO */
2565                 radeon_emit(cs, zb->db_depth_base);     /* R_028048_DB_Z_READ_BASE */
2566                 radeon_emit(cs, zb->db_stencil_base);   /* R_02804C_DB_STENCIL_READ_BASE */
2567                 radeon_emit(cs, zb->db_depth_base);     /* R_028050_DB_Z_WRITE_BASE */
2568                 radeon_emit(cs, zb->db_stencil_base);   /* R_028054_DB_STENCIL_WRITE_BASE */
2569                 radeon_emit(cs, zb->db_depth_size);     /* R_028058_DB_DEPTH_SIZE */
2570                 radeon_emit(cs, zb->db_depth_slice);    /* R_02805C_DB_DEPTH_SLICE */
2571
2572                 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2573                 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2574                 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2575
2576                 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2577         } else if (sctx->framebuffer.dirty_zsbuf) {
2578                 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2579                 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2580                 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2581         }
2582
2583         /* Framebuffer dimensions. */
2584         /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2585         radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2586                                S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2587
2588         sctx->framebuffer.dirty_cbufs = 0;
2589         sctx->framebuffer.dirty_zsbuf = false;
2590 }
2591
2592 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2593                                      struct r600_atom *atom)
2594 {
2595         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2596         unsigned nr_samples = sctx->framebuffer.nr_samples;
2597
2598         /* Smoothing (only possible with nr_samples == 1) uses the same
2599          * sample locations as the MSAA it simulates.
2600          */
2601         if (nr_samples <= 1 && sctx->smoothing_enabled)
2602                 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2603
2604         /* On Polaris, the small primitive filter uses the sample locations
2605          * even when MSAA is off, so we need to make sure they're set to 0.
2606          */
2607         if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2608             (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2609                 sctx->msaa_sample_locs.nr_samples = nr_samples;
2610                 cayman_emit_msaa_sample_locs(cs, nr_samples);
2611         }
2612
2613         if (sctx->b.family >= CHIP_POLARIS10) {
2614                 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2615                 unsigned small_prim_filter_cntl =
2616                         S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2617                         S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2618
2619                 /* The alternative of setting sample locations to 0 would
2620                  * require a DB flush to avoid Z errors, see
2621                  * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2622                  */
2623                 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2624                         small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2625
2626                 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2627                                        small_prim_filter_cntl);
2628         }
2629 }
2630
2631 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2632 {
2633         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2634         unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2635         /* 33% faster rendering to linear color buffers */
2636         bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2637         unsigned sc_mode_cntl_1 =
2638                 S_028A4C_WALK_SIZE(dst_is_linear) |
2639                 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2640                 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2641                 /* always 1: */
2642                 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2643                 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2644                 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2645                 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2646                 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2647                 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2648
2649         cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2650                                 sctx->ps_iter_samples,
2651                                 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2652                                 sc_mode_cntl_1);
2653 }
2654
2655 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2656 {
2657         struct si_context *sctx = (struct si_context *)ctx;
2658
2659         if (sctx->ps_iter_samples == min_samples)
2660                 return;
2661
2662         sctx->ps_iter_samples = min_samples;
2663         sctx->do_update_shaders = true;
2664
2665         if (sctx->framebuffer.nr_samples > 1)
2666                 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2667 }
2668
2669 /*
2670  * Samplers
2671  */
2672
2673 /**
2674  * Build the sampler view descriptor for a buffer texture.
2675  * @param state 256-bit descriptor; only the high 128 bits are filled in
2676  */
2677 void
2678 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2679                           enum pipe_format format,
2680                           unsigned offset, unsigned size,
2681                           uint32_t *state)
2682 {
2683         const struct util_format_description *desc;
2684         int first_non_void;
2685         unsigned stride;
2686         unsigned num_records;
2687         unsigned num_format, data_format;
2688
2689         desc = util_format_description(format);
2690         first_non_void = util_format_get_first_non_void_channel(format);
2691         stride = desc->block.bits / 8;
2692         num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2693         data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2694
2695         num_records = size / stride;
2696         num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2697
2698         if (screen->b.chip_class >= VI)
2699                 num_records *= stride;
2700
2701         state[4] = 0;
2702         state[5] = S_008F04_STRIDE(stride);
2703         state[6] = num_records;
2704         state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2705                    S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2706                    S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2707                    S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2708                    S_008F0C_NUM_FORMAT(num_format) |
2709                    S_008F0C_DATA_FORMAT(data_format);
2710 }
2711
2712 /**
2713  * Build the sampler view descriptor for a texture.
2714  */
2715 void
2716 si_make_texture_descriptor(struct si_screen *screen,
2717                            struct r600_texture *tex,
2718                            bool sampler,
2719                            enum pipe_texture_target target,
2720                            enum pipe_format pipe_format,
2721                            const unsigned char state_swizzle[4],
2722                            unsigned first_level, unsigned last_level,
2723                            unsigned first_layer, unsigned last_layer,
2724                            unsigned width, unsigned height, unsigned depth,
2725                            uint32_t *state,
2726                            uint32_t *fmask_state)
2727 {
2728         struct pipe_resource *res = &tex->resource.b.b;
2729         const struct util_format_description *desc;
2730         unsigned char swizzle[4];
2731         int first_non_void;
2732         unsigned num_format, data_format, type;
2733         uint64_t va;
2734
2735         desc = util_format_description(pipe_format);
2736
2737         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2738                 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2739                 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2740
2741                 switch (pipe_format) {
2742                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2743                 case PIPE_FORMAT_X24S8_UINT:
2744                 case PIPE_FORMAT_X32_S8X24_UINT:
2745                 case PIPE_FORMAT_X8Z24_UNORM:
2746                         util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2747                         break;
2748                 default:
2749                         util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2750                 }
2751         } else {
2752                 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2753         }
2754
2755         first_non_void = util_format_get_first_non_void_channel(pipe_format);
2756
2757         switch (pipe_format) {
2758         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2759                 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2760                 break;
2761         default:
2762                 if (first_non_void < 0) {
2763                         if (util_format_is_compressed(pipe_format)) {
2764                                 switch (pipe_format) {
2765                                 case PIPE_FORMAT_DXT1_SRGB:
2766                                 case PIPE_FORMAT_DXT1_SRGBA:
2767                                 case PIPE_FORMAT_DXT3_SRGBA:
2768                                 case PIPE_FORMAT_DXT5_SRGBA:
2769                                 case PIPE_FORMAT_BPTC_SRGBA:
2770                                 case PIPE_FORMAT_ETC2_SRGB8:
2771                                 case PIPE_FORMAT_ETC2_SRGB8A1:
2772                                 case PIPE_FORMAT_ETC2_SRGBA8:
2773                                         num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2774                                         break;
2775                                 case PIPE_FORMAT_RGTC1_SNORM:
2776                                 case PIPE_FORMAT_LATC1_SNORM:
2777                                 case PIPE_FORMAT_RGTC2_SNORM:
2778                                 case PIPE_FORMAT_LATC2_SNORM:
2779                                 case PIPE_FORMAT_ETC2_R11_SNORM:
2780                                 case PIPE_FORMAT_ETC2_RG11_SNORM:
2781                                 /* implies float, so use SNORM/UNORM to determine
2782                                    whether data is signed or not */
2783                                 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2784                                         num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2785                                         break;
2786                                 default:
2787                                         num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2788                                         break;
2789                                 }
2790                         } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2791                                 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2792                         } else {
2793                                 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2794                         }
2795                 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2796                         num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2797                 } else {
2798                         num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2799
2800                         switch (desc->channel[first_non_void].type) {
2801                         case UTIL_FORMAT_TYPE_FLOAT:
2802                                 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2803                                 break;
2804                         case UTIL_FORMAT_TYPE_SIGNED:
2805                                 if (desc->channel[first_non_void].normalized)
2806                                         num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2807                                 else if (desc->channel[first_non_void].pure_integer)
2808                                         num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2809                                 else
2810                                         num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2811                                 break;
2812                         case UTIL_FORMAT_TYPE_UNSIGNED:
2813                                 if (desc->channel[first_non_void].normalized)
2814                                         num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2815                                 else if (desc->channel[first_non_void].pure_integer)
2816                                         num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2817                                 else
2818                                         num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2819                         }
2820                 }
2821         }
2822
2823         data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2824         if (data_format == ~0) {
2825                 data_format = 0;
2826         }
2827
2828         if (!sampler &&
2829             (res->target == PIPE_TEXTURE_CUBE ||
2830              res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2831              res->target == PIPE_TEXTURE_3D)) {
2832                 /* For the purpose of shader images, treat cube maps and 3D
2833                  * textures as 2D arrays. For 3D textures, the address
2834                  * calculations for mipmaps are different, so we rely on the
2835                  * caller to effectively disable mipmaps.
2836                  */
2837                 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2838
2839                 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2840         } else {
2841                 type = si_tex_dim(res->target, target, res->nr_samples);
2842         }
2843
2844         if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2845                 height = 1;
2846                 depth = res->array_size;
2847         } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2848                    type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2849                 if (sampler || res->target != PIPE_TEXTURE_3D)
2850                         depth = res->array_size;
2851         } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2852                 depth = res->array_size / 6;
2853
2854         state[0] = 0;
2855         state[1] = (S_008F14_DATA_FORMAT(data_format) |
2856                     S_008F14_NUM_FORMAT(num_format));
2857         state[2] = (S_008F18_WIDTH(width - 1) |
2858                     S_008F18_HEIGHT(height - 1) |
2859                     S_008F18_PERF_MOD(4));
2860         state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2861                     S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2862                     S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2863                     S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2864                     S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2865                                         0 : first_level) |
2866                     S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2867                                         util_logbase2(res->nr_samples) :
2868                                         last_level) |
2869                     S_008F1C_POW2_PAD(res->last_level > 0) |
2870                     S_008F1C_TYPE(type));
2871         state[4] = S_008F20_DEPTH(depth - 1);
2872         state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2873                     S_008F24_LAST_ARRAY(last_layer));
2874         state[6] = 0;
2875         state[7] = 0;
2876
2877         if (tex->dcc_offset) {
2878                 unsigned swap = r600_translate_colorswap(pipe_format, false);
2879
2880                 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2881         } else {
2882                 /* The last dword is unused by hw. The shader uses it to clear
2883                  * bits in the first dword of sampler state.
2884                  */
2885                 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2886                         if (first_level == last_level)
2887                                 state[7] = C_008F30_MAX_ANISO_RATIO;
2888                         else
2889                                 state[7] = 0xffffffff;
2890                 }
2891         }
2892
2893         /* Initialize the sampler view for FMASK. */
2894         if (tex->fmask.size) {
2895                 uint32_t fmask_format;
2896
2897                 va = tex->resource.gpu_address + tex->fmask.offset;
2898
2899                 switch (res->nr_samples) {
2900                 case 2:
2901                         fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2902                         break;
2903                 case 4:
2904                         fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2905                         break;
2906                 case 8:
2907                         fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2908                         break;
2909                 default:
2910                         assert(0);
2911                         fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2912                 }
2913
2914                 fmask_state[0] = va >> 8;
2915                 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2916                                  S_008F14_DATA_FORMAT(fmask_format) |
2917                                  S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2918                 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2919                                  S_008F18_HEIGHT(height - 1);
2920                 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2921                                  S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2922                                  S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2923                                  S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2924                                  S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2925                                  S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2926                 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2927                                  S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2928                 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2929                                  S_008F24_LAST_ARRAY(last_layer);
2930                 fmask_state[6] = 0;
2931                 fmask_state[7] = 0;
2932         }
2933 }
2934
2935 /**
2936  * Create a sampler view.
2937  *
2938  * @param ctx           context
2939  * @param texture       texture
2940  * @param state         sampler view template
2941  * @param width0        width0 override (for compressed textures as int)
2942  * @param height0       height0 override (for compressed textures as int)
2943  * @param force_level   set the base address to the level (for compressed textures)
2944  */
2945 struct pipe_sampler_view *
2946 si_create_sampler_view_custom(struct pipe_context *ctx,
2947                               struct pipe_resource *texture,
2948                               const struct pipe_sampler_view *state,
2949                               unsigned width0, unsigned height0,
2950                               unsigned force_level)
2951 {
2952         struct si_context *sctx = (struct si_context*)ctx;
2953         struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2954         struct r600_texture *tmp = (struct r600_texture*)texture;
2955         unsigned base_level, first_level, last_level;
2956         unsigned char state_swizzle[4];
2957         unsigned height, depth, width;
2958         unsigned last_layer = state->u.tex.last_layer;
2959         enum pipe_format pipe_format;
2960         const struct radeon_surf_level *surflevel;
2961
2962         if (!view)
2963                 return NULL;
2964
2965         /* initialize base object */
2966         view->base = *state;
2967         view->base.texture = NULL;
2968         view->base.reference.count = 1;
2969         view->base.context = ctx;
2970
2971         assert(texture);
2972         pipe_resource_reference(&view->base.texture, texture);
2973
2974         if (state->format == PIPE_FORMAT_X24S8_UINT ||
2975             state->format == PIPE_FORMAT_S8X24_UINT ||
2976             state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2977             state->format == PIPE_FORMAT_S8_UINT)
2978                 view->is_stencil_sampler = true;
2979
2980         /* Buffer resource. */
2981         if (texture->target == PIPE_BUFFER) {
2982                 si_make_buffer_descriptor(sctx->screen,
2983                                           (struct r600_resource *)texture,
2984                                           state->format,
2985                                           state->u.buf.offset,
2986                                           state->u.buf.size,
2987                                           view->state);
2988                 return &view->base;
2989         }
2990
2991         state_swizzle[0] = state->swizzle_r;
2992         state_swizzle[1] = state->swizzle_g;
2993         state_swizzle[2] = state->swizzle_b;
2994         state_swizzle[3] = state->swizzle_a;
2995
2996         base_level = 0;
2997         first_level = state->u.tex.first_level;
2998         last_level = state->u.tex.last_level;
2999         width = width0;
3000         height = height0;
3001         depth = texture->depth0;
3002
3003         if (force_level) {
3004                 assert(force_level == first_level &&
3005                        force_level == last_level);
3006                 base_level = force_level;
3007                 first_level = 0;
3008                 last_level = 0;
3009                 width = u_minify(width, force_level);
3010                 height = u_minify(height, force_level);
3011                 depth = u_minify(depth, force_level);
3012         }
3013
3014         /* This is not needed if state trackers set last_layer correctly. */
3015         if (state->target == PIPE_TEXTURE_1D ||
3016             state->target == PIPE_TEXTURE_2D ||
3017             state->target == PIPE_TEXTURE_RECT ||
3018             state->target == PIPE_TEXTURE_CUBE)
3019                 last_layer = state->u.tex.first_layer;
3020
3021         /* Texturing with separate depth and stencil. */
3022         pipe_format = state->format;
3023
3024         /* Depth/stencil texturing sometimes needs separate texture. */
3025         if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3026                 if (!tmp->flushed_depth_texture &&
3027                     !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3028                         pipe_resource_reference(&view->base.texture, NULL);
3029                         FREE(view);
3030                         return NULL;
3031                 }
3032
3033                 assert(tmp->flushed_depth_texture);
3034
3035                 /* Override format for the case where the flushed texture
3036                  * contains only Z or only S.
3037                  */
3038                 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3039                         pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3040
3041                 tmp = tmp->flushed_depth_texture;
3042         }
3043
3044         surflevel = tmp->surface.level;
3045
3046         if (tmp->db_compatible) {
3047                 if (!view->is_stencil_sampler)
3048                         pipe_format = tmp->db_render_format;
3049
3050                 switch (pipe_format) {
3051                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3052                         pipe_format = PIPE_FORMAT_Z32_FLOAT;
3053                         break;
3054                 case PIPE_FORMAT_X8Z24_UNORM:
3055                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3056                         /* Z24 is always stored like this for DB
3057                          * compatibility.
3058                          */
3059                         pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3060                         break;
3061                 case PIPE_FORMAT_X24S8_UINT:
3062                 case PIPE_FORMAT_S8X24_UINT:
3063                 case PIPE_FORMAT_X32_S8X24_UINT:
3064                         pipe_format = PIPE_FORMAT_S8_UINT;
3065                         surflevel = tmp->surface.stencil_level;
3066                         break;
3067                 default:;
3068                 }
3069         }
3070
3071         vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3072                                               state->u.tex.first_level,
3073                                               state->format);
3074
3075         si_make_texture_descriptor(sctx->screen, tmp, true,
3076                                    state->target, pipe_format, state_swizzle,
3077                                    first_level, last_level,
3078                                    state->u.tex.first_layer, last_layer,
3079                                    width, height, depth,
3080                                    view->state, view->fmask_state);
3081
3082         view->base_level_info = &surflevel[base_level];
3083         view->base_level = base_level;
3084         view->block_width = util_format_get_blockwidth(pipe_format);
3085         return &view->base;
3086 }
3087
3088 static struct pipe_sampler_view *
3089 si_create_sampler_view(struct pipe_context *ctx,
3090                        struct pipe_resource *texture,
3091                        const struct pipe_sampler_view *state)
3092 {
3093         return si_create_sampler_view_custom(ctx, texture, state,
3094                                              texture ? texture->width0 : 0,
3095                                              texture ? texture->height0 : 0, 0);
3096 }
3097
3098 static void si_sampler_view_destroy(struct pipe_context *ctx,
3099                                     struct pipe_sampler_view *state)
3100 {
3101         struct si_sampler_view *view = (struct si_sampler_view *)state;
3102
3103         pipe_resource_reference(&state->texture, NULL);
3104         FREE(view);
3105 }
3106
3107 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3108 {
3109         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3110                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3111                (linear_filter &&
3112                 (wrap == PIPE_TEX_WRAP_CLAMP ||
3113                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3114 }
3115
3116 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3117 {
3118         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3119                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3120
3121         return (state->border_color.ui[0] || state->border_color.ui[1] ||
3122                 state->border_color.ui[2] || state->border_color.ui[3]) &&
3123                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3124                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3125                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3126 }
3127
3128 static void *si_create_sampler_state(struct pipe_context *ctx,
3129                                      const struct pipe_sampler_state *state)
3130 {
3131         struct si_context *sctx = (struct si_context *)ctx;
3132         struct r600_common_screen *rscreen = sctx->b.screen;
3133         struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3134         unsigned border_color_type, border_color_index = 0;
3135         unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3136                                                        : state->max_anisotropy;
3137         unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3138
3139         if (!rstate) {
3140                 return NULL;
3141         }
3142
3143         if (!sampler_state_needs_border_color(state))
3144                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3145         else if (state->border_color.f[0] == 0 &&
3146                  state->border_color.f[1] == 0 &&
3147                  state->border_color.f[2] == 0 &&
3148                  state->border_color.f[3] == 0)
3149                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3150         else if (state->border_color.f[0] == 0 &&
3151                  state->border_color.f[1] == 0 &&
3152                  state->border_color.f[2] == 0 &&
3153                  state->border_color.f[3] == 1)
3154                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3155         else if (state->border_color.f[0] == 1 &&
3156                  state->border_color.f[1] == 1 &&
3157                  state->border_color.f[2] == 1 &&
3158                  state->border_color.f[3] == 1)
3159                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3160         else {
3161                 int i;
3162
3163                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3164
3165                 /* Check if the border has been uploaded already. */
3166                 for (i = 0; i < sctx->border_color_count; i++)
3167                         if (memcmp(&sctx->border_color_table[i], &state->border_color,
3168                                    sizeof(state->border_color)) == 0)
3169                                 break;
3170
3171                 if (i >= SI_MAX_BORDER_COLORS) {
3172                         /* Getting 4096 unique border colors is very unlikely. */
3173                         fprintf(stderr, "radeonsi: The border color table is full. "
3174                                 "Any new border colors will be just black. "
3175                                 "Please file a bug.\n");
3176                         border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3177                 } else {
3178                         if (i == sctx->border_color_count) {
3179                                 /* Upload a new border color. */
3180                                 memcpy(&sctx->border_color_table[i], &state->border_color,
3181                                        sizeof(state->border_color));
3182                                 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3183                                                         &state->border_color,
3184                                                         sizeof(state->border_color));
3185                                 sctx->border_color_count++;
3186                         }
3187
3188                         border_color_index = i;
3189                 }
3190         }
3191
3192         rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3193                           S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3194                           S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3195                           S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3196                           S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3197                           S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3198                           S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3199                           S_008F30_ANISO_BIAS(max_aniso_ratio) |
3200                           S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3201                           S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3202         rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3203                           S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3204                           S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3205         rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3206                           S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3207                           S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3208                           S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3209                           S_008F38_MIP_POINT_PRECLAMP(1) |
3210                           S_008F38_DISABLE_LSB_CEIL(1) |
3211                           S_008F38_FILTER_PREC_FIX(1) |
3212                           S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3213         rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3214                          S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3215         return rstate;
3216 }
3217
3218 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3219 {
3220         struct si_context *sctx = (struct si_context *)ctx;
3221
3222         if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3223                 return;
3224
3225         sctx->sample_mask.sample_mask = sample_mask;
3226         si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3227 }
3228
3229 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3230 {
3231         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3232         unsigned mask = sctx->sample_mask.sample_mask;
3233
3234         /* Needed for line and polygon smoothing as well as for the Polaris
3235          * small primitive filter. We expect the state tracker to take care of
3236          * this for us.
3237          */
3238         assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3239                (mask & 1 && sctx->blitter->running));
3240
3241         radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3242         radeon_emit(cs, mask | (mask << 16));
3243         radeon_emit(cs, mask | (mask << 16));
3244 }
3245
3246 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3247 {
3248         free(state);
3249 }
3250
3251 /*
3252  * Vertex elements & buffers
3253  */
3254
3255 static void *si_create_vertex_elements(struct pipe_context *ctx,
3256                                        unsigned count,
3257                                        const struct pipe_vertex_element *elements)
3258 {
3259         struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3260         int i;
3261
3262         assert(count <= SI_MAX_ATTRIBS);
3263         if (!v)
3264                 return NULL;
3265
3266         v->count = count;
3267         for (i = 0; i < count; ++i) {
3268                 const struct util_format_description *desc;
3269                 unsigned data_format, num_format;
3270                 int first_non_void;
3271
3272                 desc = util_format_description(elements[i].src_format);
3273                 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3274                 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3275                 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3276
3277                 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3278                                    S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3279                                    S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3280                                    S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3281                                    S_008F0C_NUM_FORMAT(num_format) |
3282                                    S_008F0C_DATA_FORMAT(data_format);
3283                 v->format_size[i] = desc->block.bits / 8;
3284
3285                 /* The hardware always treats the 2-bit alpha channel as
3286                  * unsigned, so a shader workaround is needed.
3287                  */
3288                 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3289                         if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3290                                 v->fix_fetch |= SI_FIX_FETCH_A2_SNORM << (2 * i);
3291                         } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3292                                 v->fix_fetch |= SI_FIX_FETCH_A2_SSCALED << (2 * i);
3293                         } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3294                                 /* This isn't actually used in OpenGL. */
3295                                 v->fix_fetch |= SI_FIX_FETCH_A2_SINT << (2 * i);
3296                         }
3297                 }
3298         }
3299         memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3300
3301         return v;
3302 }
3303
3304 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3305 {
3306         struct si_context *sctx = (struct si_context *)ctx;
3307         struct si_vertex_element *v = (struct si_vertex_element*)state;
3308
3309         sctx->vertex_elements = v;
3310         sctx->vertex_buffers_dirty = true;
3311         sctx->do_update_shaders = true;
3312 }
3313
3314 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3315 {
3316         struct si_context *sctx = (struct si_context *)ctx;
3317
3318         if (sctx->vertex_elements == state)
3319                 sctx->vertex_elements = NULL;
3320         FREE(state);
3321 }
3322
3323 static void si_set_vertex_buffers(struct pipe_context *ctx,
3324                                   unsigned start_slot, unsigned count,
3325                                   const struct pipe_vertex_buffer *buffers)
3326 {
3327         struct si_context *sctx = (struct si_context *)ctx;
3328         struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3329         int i;
3330
3331         assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3332
3333         if (buffers) {
3334                 for (i = 0; i < count; i++) {
3335                         const struct pipe_vertex_buffer *src = buffers + i;
3336                         struct pipe_vertex_buffer *dsti = dst + i;
3337                         struct pipe_resource *buf = src->buffer;
3338
3339                         pipe_resource_reference(&dsti->buffer, buf);
3340                         dsti->buffer_offset = src->buffer_offset;
3341                         dsti->stride = src->stride;
3342                         r600_context_add_resource_size(ctx, buf);
3343                         if (buf)
3344                                 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3345                 }
3346         } else {
3347                 for (i = 0; i < count; i++) {
3348                         pipe_resource_reference(&dst[i].buffer, NULL);
3349                 }
3350         }
3351         sctx->vertex_buffers_dirty = true;
3352 }
3353
3354 static void si_set_index_buffer(struct pipe_context *ctx,
3355                                 const struct pipe_index_buffer *ib)
3356 {
3357         struct si_context *sctx = (struct si_context *)ctx;
3358
3359         if (ib) {
3360                 struct pipe_resource *buf = ib->buffer;
3361
3362                 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3363                 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3364                 r600_context_add_resource_size(ctx, buf);
3365                 if (buf)
3366                         r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3367         } else {
3368                 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3369         }
3370 }
3371
3372 /*
3373  * Misc
3374  */
3375
3376 static void si_set_tess_state(struct pipe_context *ctx,
3377                               const float default_outer_level[4],
3378                               const float default_inner_level[2])
3379 {
3380         struct si_context *sctx = (struct si_context *)ctx;
3381         struct pipe_constant_buffer cb;
3382         float array[8];
3383
3384         memcpy(array, default_outer_level, sizeof(float) * 4);
3385         memcpy(array+4, default_inner_level, sizeof(float) * 2);
3386
3387         cb.buffer = NULL;
3388         cb.user_buffer = NULL;
3389         cb.buffer_size = sizeof(array);
3390
3391         si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3392                                (void*)array, sizeof(array),
3393                                &cb.buffer_offset);
3394
3395         si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3396         pipe_resource_reference(&cb.buffer, NULL);
3397 }
3398
3399 static void si_texture_barrier(struct pipe_context *ctx)
3400 {
3401         struct si_context *sctx = (struct si_context *)ctx;
3402
3403         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3404                          SI_CONTEXT_INV_GLOBAL_L2 |
3405                          SI_CONTEXT_FLUSH_AND_INV_CB |
3406                          SI_CONTEXT_CS_PARTIAL_FLUSH;
3407 }
3408
3409 /* This only ensures coherency for shader image/buffer stores. */
3410 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3411 {
3412         struct si_context *sctx = (struct si_context *)ctx;
3413
3414         /* Subsequent commands must wait for all shader invocations to
3415          * complete. */
3416         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3417                          SI_CONTEXT_CS_PARTIAL_FLUSH;
3418
3419         if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3420                 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3421                                  SI_CONTEXT_INV_VMEM_L1;
3422
3423         if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3424                      PIPE_BARRIER_SHADER_BUFFER |
3425                      PIPE_BARRIER_TEXTURE |
3426                      PIPE_BARRIER_IMAGE |
3427                      PIPE_BARRIER_STREAMOUT_BUFFER |
3428                      PIPE_BARRIER_GLOBAL_BUFFER)) {
3429                 /* As far as I can tell, L1 contents are written back to L2
3430                  * automatically at end of shader, but the contents of other
3431                  * L1 caches might still be stale. */
3432                 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3433         }
3434
3435         if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3436                 /* Indices are read through TC L2 since VI.
3437                  * L1 isn't used.
3438                  */
3439                 if (sctx->screen->b.chip_class <= CIK)
3440                         sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3441         }
3442
3443         if (flags & PIPE_BARRIER_FRAMEBUFFER)
3444                 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3445
3446         if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3447                      PIPE_BARRIER_INDIRECT_BUFFER))
3448                 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3449 }
3450
3451 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3452 {
3453         struct pipe_blend_state blend;
3454
3455         memset(&blend, 0, sizeof(blend));
3456         blend.independent_blend_enable = true;
3457         blend.rt[0].colormask = 0xf;
3458         return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3459 }
3460
3461 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3462                                  bool include_draw_vbo)
3463 {
3464         si_need_cs_space((struct si_context*)ctx);
3465 }
3466
3467 static void si_init_config(struct si_context *sctx);
3468
3469 void si_init_state_functions(struct si_context *sctx)
3470 {
3471         si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3472         si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3473         si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3474         si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3475         si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3476
3477         si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3478         si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3479         si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3480         si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3481         si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3482         si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3483         si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3484         si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3485         si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3486         si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3487
3488         sctx->b.b.create_blend_state = si_create_blend_state;
3489         sctx->b.b.bind_blend_state = si_bind_blend_state;
3490         sctx->b.b.delete_blend_state = si_delete_blend_state;
3491         sctx->b.b.set_blend_color = si_set_blend_color;
3492
3493         sctx->b.b.create_rasterizer_state = si_create_rs_state;
3494         sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3495         sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3496
3497         sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3498         sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3499         sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3500
3501         sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3502         sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3503         sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3504         sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3505         sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3506
3507         sctx->b.b.set_clip_state = si_set_clip_state;
3508         sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3509
3510         sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3511         sctx->b.b.get_sample_position = cayman_get_sample_position;
3512
3513         sctx->b.b.create_sampler_state = si_create_sampler_state;
3514         sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3515
3516         sctx->b.b.create_sampler_view = si_create_sampler_view;
3517         sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3518
3519         sctx->b.b.set_sample_mask = si_set_sample_mask;
3520
3521         sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3522         sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3523         sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3524         sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3525         sctx->b.b.set_index_buffer = si_set_index_buffer;
3526
3527         sctx->b.b.texture_barrier = si_texture_barrier;
3528         sctx->b.b.memory_barrier = si_memory_barrier;
3529         sctx->b.b.set_min_samples = si_set_min_samples;
3530         sctx->b.b.set_tess_state = si_set_tess_state;
3531
3532         sctx->b.b.set_active_query_state = si_set_active_query_state;
3533         sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3534         sctx->b.save_qbo_state = si_save_qbo_state;
3535         sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3536
3537         sctx->b.b.draw_vbo = si_draw_vbo;
3538
3539         si_init_config(sctx);
3540 }
3541
3542 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3543 {
3544         return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3545 }
3546
3547 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3548                                      struct r600_texture *rtex,
3549                                      struct radeon_bo_metadata *md)
3550 {
3551         struct si_screen *sscreen = (struct si_screen*)rscreen;
3552         struct pipe_resource *res = &rtex->resource.b.b;
3553         static const unsigned char swizzle[] = {
3554                 PIPE_SWIZZLE_X,
3555                 PIPE_SWIZZLE_Y,
3556                 PIPE_SWIZZLE_Z,
3557                 PIPE_SWIZZLE_W
3558         };
3559         uint32_t desc[8], i;
3560         bool is_array = util_resource_is_array_texture(res);
3561
3562         /* DRM 2.x.x doesn't support this. */
3563         if (rscreen->info.drm_major != 3)
3564                 return;
3565
3566         assert(rtex->dcc_separate_buffer == NULL);
3567         assert(rtex->fmask.size == 0);
3568
3569         /* Metadata image format format version 1:
3570          * [0] = 1 (metadata format identifier)
3571          * [1] = (VENDOR_ID << 16) | PCI_ID
3572          * [2:9] = image descriptor for the whole resource
3573          *         [2] is always 0, because the base address is cleared
3574          *         [9] is the DCC offset bits [39:8] from the beginning of
3575          *             the buffer
3576          * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3577          */
3578
3579         md->metadata[0] = 1; /* metadata image format version 1 */
3580
3581         /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3582         md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3583
3584         si_make_texture_descriptor(sscreen, rtex, true,
3585                                    res->target, res->format,
3586                                    swizzle, 0, res->last_level, 0,
3587                                    is_array ? res->array_size - 1 : 0,
3588                                    res->width0, res->height0, res->depth0,
3589                                    desc, NULL);
3590
3591         si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3592                                        rtex->surface.blk_w, false, desc);
3593
3594         /* Clear the base address and set the relative DCC offset. */
3595         desc[0] = 0;
3596         desc[1] &= C_008F14_BASE_ADDRESS_HI;
3597         desc[7] = rtex->dcc_offset >> 8;
3598
3599         /* Dwords [2:9] contain the image descriptor. */
3600         memcpy(&md->metadata[2], desc, sizeof(desc));
3601
3602         /* Dwords [10:..] contain the mipmap level offsets. */
3603         for (i = 0; i <= res->last_level; i++)
3604                 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3605
3606         md->size_metadata = (11 + res->last_level) * 4;
3607 }
3608
3609 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3610                                      struct r600_texture *rtex,
3611                                      struct radeon_bo_metadata *md)
3612 {
3613         uint32_t *desc = &md->metadata[2];
3614
3615         if (rscreen->chip_class < VI)
3616                 return;
3617
3618         /* Return if DCC is enabled. The texture should be set up with it
3619          * already.
3620          */
3621         if (md->size_metadata >= 11 * 4 &&
3622             md->metadata[0] != 0 &&
3623             md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3624             G_008F28_COMPRESSION_EN(desc[6])) {
3625                 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3626                 return;
3627         }
3628
3629         /* Disable DCC. These are always set by texture_from_handle and must
3630          * be cleared here.
3631          */
3632         rtex->dcc_offset = 0;
3633 }
3634
3635 void si_init_screen_state_functions(struct si_screen *sscreen)
3636 {
3637         sscreen->b.b.is_format_supported = si_is_format_supported;
3638         sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3639         sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3640 }
3641
3642 static void
3643 si_write_harvested_raster_configs(struct si_context *sctx,
3644                                   struct si_pm4_state *pm4,
3645                                   unsigned raster_config,
3646                                   unsigned raster_config_1)
3647 {
3648         unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3649         unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3650         unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3651         unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3652         unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3653         unsigned rb_per_se = num_rb / num_se;
3654         unsigned se_mask[4];
3655         unsigned se;
3656
3657         se_mask[0] = ((1 << rb_per_se) - 1);
3658         se_mask[1] = (se_mask[0] << rb_per_se);
3659         se_mask[2] = (se_mask[1] << rb_per_se);
3660         se_mask[3] = (se_mask[2] << rb_per_se);
3661
3662         se_mask[0] &= rb_mask;
3663         se_mask[1] &= rb_mask;
3664         se_mask[2] &= rb_mask;
3665         se_mask[3] &= rb_mask;
3666
3667         assert(num_se == 1 || num_se == 2 || num_se == 4);
3668         assert(sh_per_se == 1 || sh_per_se == 2);
3669         assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3670
3671         /* XXX: I can't figure out what the *_XSEL and *_YSEL
3672          * fields are for, so I'm leaving them as their default
3673          * values. */
3674
3675         for (se = 0; se < num_se; se++) {
3676                 unsigned raster_config_se = raster_config;
3677                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3678                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3679                 int idx = (se / 2) * 2;
3680
3681                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3682                         raster_config_se &= C_028350_SE_MAP;
3683
3684                         if (!se_mask[idx]) {
3685                                 raster_config_se |=
3686                                         S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3687                         } else {
3688                                 raster_config_se |=
3689                                         S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3690                         }
3691                 }
3692
3693                 pkr0_mask &= rb_mask;
3694                 pkr1_mask &= rb_mask;
3695                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3696                         raster_config_se &= C_028350_PKR_MAP;
3697
3698                         if (!pkr0_mask) {
3699                                 raster_config_se |=
3700                                         S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3701                         } else {
3702                                 raster_config_se |=
3703                                         S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3704                         }
3705                 }
3706
3707                 if (rb_per_se >= 2) {
3708                         unsigned rb0_mask = 1 << (se * rb_per_se);
3709                         unsigned rb1_mask = rb0_mask << 1;
3710
3711                         rb0_mask &= rb_mask;
3712                         rb1_mask &= rb_mask;
3713                         if (!rb0_mask || !rb1_mask) {
3714                                 raster_config_se &= C_028350_RB_MAP_PKR0;
3715
3716                                 if (!rb0_mask) {
3717                                         raster_config_se |=
3718                                                 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3719                                 } else {
3720                                         raster_config_se |=
3721                                                 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3722                                 }
3723                         }
3724
3725                         if (rb_per_se > 2) {
3726                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3727                                 rb1_mask = rb0_mask << 1;
3728                                 rb0_mask &= rb_mask;
3729                                 rb1_mask &= rb_mask;
3730                                 if (!rb0_mask || !rb1_mask) {
3731                                         raster_config_se &= C_028350_RB_MAP_PKR1;
3732
3733                                         if (!rb0_mask) {
3734                                                 raster_config_se |=
3735                                                         S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3736                                         } else {
3737                                                 raster_config_se |=
3738                                                         S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3739                                         }
3740                                 }
3741                         }
3742                 }
3743
3744                 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3745                 if (sctx->b.chip_class < CIK)
3746                         si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3747                                        SE_INDEX(se) | SH_BROADCAST_WRITES |
3748                                        INSTANCE_BROADCAST_WRITES);
3749                 else
3750                         si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3751                                        S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3752                                        S_030800_INSTANCE_BROADCAST_WRITES(1));
3753                 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3754         }
3755
3756         /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3757         if (sctx->b.chip_class < CIK)
3758                 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3759                                SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3760                                INSTANCE_BROADCAST_WRITES);
3761         else {
3762                 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3763                                S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3764                                S_030800_INSTANCE_BROADCAST_WRITES(1));
3765
3766                 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3767                                      (!se_mask[2] && !se_mask[3]))) {
3768                         raster_config_1 &= C_028354_SE_PAIR_MAP;
3769
3770                         if (!se_mask[0] && !se_mask[1]) {
3771                                 raster_config_1 |=
3772                                         S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3773                         } else {
3774                                 raster_config_1 |=
3775                                         S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3776                         }
3777                 }
3778
3779                 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3780         }
3781 }
3782
3783 static void si_init_config(struct si_context *sctx)
3784 {
3785         struct si_screen *sscreen = sctx->screen;
3786         unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3787         unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3788         unsigned raster_config, raster_config_1;
3789         uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3790         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3791
3792         if (!pm4)
3793                 return;
3794
3795         si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3796         si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3797         si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3798         si_pm4_cmd_end(pm4, false);
3799
3800         si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3801         si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3802
3803         /* FIXME calculate these values somehow ??? */
3804         si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3805         si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3806         si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3807
3808         si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3809         si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3810
3811         si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3812         si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3813         if (sctx->b.chip_class < CIK)
3814                 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3815                                S_008A14_CLIP_VTX_REORDER_ENA(1));
3816
3817         si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3818         si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3819
3820         si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3821
3822         switch (sctx->screen->b.family) {
3823         case CHIP_TAHITI:
3824         case CHIP_PITCAIRN:
3825                 raster_config = 0x2a00126a;
3826                 raster_config_1 = 0x00000000;
3827                 break;
3828         case CHIP_VERDE:
3829                 raster_config = 0x0000124a;
3830                 raster_config_1 = 0x00000000;
3831                 break;
3832         case CHIP_OLAND:
3833                 raster_config = 0x00000082;
3834                 raster_config_1 = 0x00000000;
3835                 break;
3836         case CHIP_HAINAN:
3837                 raster_config = 0x00000000;
3838                 raster_config_1 = 0x00000000;
3839                 break;
3840         case CHIP_BONAIRE:
3841                 raster_config = 0x16000012;
3842                 raster_config_1 = 0x00000000;
3843                 break;
3844         case CHIP_HAWAII:
3845                 raster_config = 0x3a00161a;
3846                 raster_config_1 = 0x0000002e;
3847                 break;
3848         case CHIP_FIJI:
3849                 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3850                         /* old kernels with old tiling config */
3851                         raster_config = 0x16000012;
3852                         raster_config_1 = 0x0000002a;
3853                 } else {
3854                         raster_config = 0x3a00161a;
3855                         raster_config_1 = 0x0000002e;
3856                 }
3857                 break;
3858         case CHIP_POLARIS10:
3859                 raster_config = 0x16000012;
3860                 raster_config_1 = 0x0000002a;
3861                 break;
3862         case CHIP_POLARIS11:
3863                 raster_config = 0x16000012;
3864                 raster_config_1 = 0x00000000;
3865                 break;
3866         case CHIP_TONGA:
3867                 raster_config = 0x16000012;
3868                 raster_config_1 = 0x0000002a;
3869                 break;
3870         case CHIP_ICELAND:
3871                 if (num_rb == 1)
3872                         raster_config = 0x00000000;
3873                 else
3874                         raster_config = 0x00000002;
3875                 raster_config_1 = 0x00000000;
3876                 break;
3877         case CHIP_CARRIZO:
3878                 raster_config = 0x00000002;
3879                 raster_config_1 = 0x00000000;
3880                 break;
3881         case CHIP_KAVERI:
3882                 /* KV should be 0x00000002, but that causes problems with radeon */
3883                 raster_config = 0x00000000; /* 0x00000002 */
3884                 raster_config_1 = 0x00000000;
3885                 break;
3886         case CHIP_KABINI:
3887         case CHIP_MULLINS:
3888         case CHIP_STONEY:
3889                 raster_config = 0x00000000;
3890                 raster_config_1 = 0x00000000;
3891                 break;
3892         default:
3893                 fprintf(stderr,
3894                         "radeonsi: Unknown GPU, using 0 for raster_config\n");
3895                 raster_config = 0x00000000;
3896                 raster_config_1 = 0x00000000;
3897                 break;
3898         }
3899
3900         /* Always use the default config when all backends are enabled
3901          * (or when we failed to determine the enabled backends).
3902          */
3903         if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3904                 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3905                                raster_config);
3906                 if (sctx->b.chip_class >= CIK)
3907                         si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3908                                        raster_config_1);
3909         } else {
3910                 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3911         }
3912
3913         si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3914         si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3915         si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3916                        S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3917         si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3918         si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3919                        S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3920
3921         si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3922         si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3923                        S_028230_ER_TRI(0xA) |
3924                        S_028230_ER_POINT(0xA) |
3925                        S_028230_ER_RECT(0xA) |
3926                        /* Required by DX10_DIAMOND_TEST_ENA: */
3927                        S_028230_ER_LINE_LR(0x1A) |
3928                        S_028230_ER_LINE_RL(0x26) |
3929                        S_028230_ER_LINE_TB(0xA) |
3930                        S_028230_ER_LINE_BT(0xA));
3931         /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3932         si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3933         si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3934         si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3935         si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3936         si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3937         si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
3938
3939         si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3940         si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3941         si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3942
3943         if (sctx->b.chip_class >= CIK) {
3944                 /* If this is 0, Bonaire can hang even if GS isn't being used.
3945                  * Other chips are unaffected. These are suboptimal values,
3946                  * but we don't use on-chip GS.
3947                  */
3948                 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
3949                                S_028A44_ES_VERTS_PER_SUBGRP(64) |
3950                                S_028A44_GS_PRIMS_PER_SUBGRP(4));
3951
3952                 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3953                 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3954                 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3955                 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3956
3957                 if (sscreen->b.info.num_good_compute_units /
3958                     (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3959                         /* Too few available compute units per SH. Disallowing
3960                          * VS to run on CU0 could hurt us more than late VS
3961                          * allocation would help.
3962                          *
3963                          * LATE_ALLOC_VS = 2 is the highest safe number.
3964                          */
3965                         si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3966                         si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3967                 } else {
3968                         /* Set LATE_ALLOC_VS == 31. It should be less than
3969                          * the number of scratch waves. Limitations:
3970                          * - VS can't execute on CU0.
3971                          * - If HS writes outputs to LDS, LS can't execute on CU0.
3972                          */
3973                         si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3974                         si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3975                 }
3976
3977                 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3978         }
3979
3980         if (sctx->b.chip_class >= VI) {
3981                 unsigned vgt_tess_distribution;
3982
3983                 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3984                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3985                                S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3986                 if (sctx->b.family < CHIP_POLARIS10)
3987                         si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3988                 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3989
3990                 vgt_tess_distribution =
3991                         S_028B50_ACCUM_ISOLINE(32) |
3992                         S_028B50_ACCUM_TRI(11) |
3993                         S_028B50_ACCUM_QUAD(11) |
3994                         S_028B50_DONUT_SPLIT(16);
3995
3996                 /* Testing with Unigine Heaven extreme tesselation yielded best results
3997                  * with TRAP_SPLIT = 3.
3998                  */
3999                 if (sctx->b.family == CHIP_FIJI ||
4000                     sctx->b.family >= CHIP_POLARIS10)
4001                         vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4002
4003                 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4004         } else {
4005                 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4006                 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4007         }
4008
4009         if (sctx->b.family == CHIP_STONEY)
4010                 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4011
4012         si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4013         if (sctx->b.chip_class >= CIK)
4014                 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4015         si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4016                       RADEON_PRIO_BORDER_COLORS);
4017
4018         si_pm4_upload_indirect_buffer(sctx, pm4);
4019         sctx->init_config = pm4;
4020 }