src/gallium/drivers/radeonsi/si_state.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "si_shader.h"
  29 #include "sid.h"
  30 #include "radeon/r600_cs.h"
  31
  32 #include "util/u_dual_blend.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_pstipple.h"
  37 #include "util/u_resource.h"
  38
  39 /* Initialize an external atom (owned by ../radeon). */
  40 static void
  41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
  42                       struct r600_atom **list_elem)
  43 {
  44         atom->id = list_elem - sctx->atoms.array + 1;
  45         *list_elem = atom;
  46 }
  47
  48 /* Initialize an atom owned by radeonsi.  */
  49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
  50                   struct r600_atom **list_elem,
  51                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
  52 {
  53         atom->emit = (void*)emit_func;
  54         atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
  55         *list_elem = atom;
  56 }
  57
  58 static unsigned si_map_swizzle(unsigned swizzle)
  59 {
  60         switch (swizzle) {
  61         case PIPE_SWIZZLE_Y:
  62                 return V_008F0C_SQ_SEL_Y;
  63         case PIPE_SWIZZLE_Z:
  64                 return V_008F0C_SQ_SEL_Z;
  65         case PIPE_SWIZZLE_W:
  66                 return V_008F0C_SQ_SEL_W;
  67         case PIPE_SWIZZLE_0:
  68                 return V_008F0C_SQ_SEL_0;
  69         case PIPE_SWIZZLE_1:
  70                 return V_008F0C_SQ_SEL_1;
  71         default: /* PIPE_SWIZZLE_X */
  72                 return V_008F0C_SQ_SEL_X;
  73         }
  74 }
  75
  76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
  77 {
  78         return value * (1 << frac_bits);
  79 }
  80
  81 /* 12.4 fixed-point */
  82 static unsigned si_pack_float_12p4(float x)
  83 {
  84         return x <= 0    ? 0 :
  85                x >= 4096 ? 0xffff : x * 16;
  86 }
  87
  88 /*
  89  * Inferred framebuffer and blender state.
  90  *
  91  * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
  92  * is that:
  93  * - The blend state mask is 0xf most of the time.
  94  * - The COLOR1 format isn't INVALID because of possible dual-source blending,
  95  *   so COLOR1 is enabled pretty much all the time.
  96  * So CB_TARGET_MASK is the only register that can disable COLOR1.
  97  *
  98  * Another reason is to avoid a hang with dual source blending.
  99  */
 100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
 101 {
 102         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 103         struct si_state_blend *blend = sctx->queued.named.blend;
 104         uint32_t cb_target_mask = 0, i;
 105
 106         for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
 107                 if (sctx->framebuffer.state.cbufs[i])
 108                         cb_target_mask |= 0xf << (4*i);
 109
 110         if (blend)
 111                 cb_target_mask &= blend->cb_target_mask;
 112
 113         /* Avoid a hang that happens when dual source blending is enabled
 114          * but there is not enough color outputs. This is undefined behavior,
 115          * so disable color writes completely.
 116          *
 117          * Reproducible with Unigine Heaven 4.0 and drirc missing.
 118          */
 119         if (blend && blend->dual_src_blend &&
 120             sctx->ps_shader.cso &&
 121             (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
 122                 cb_target_mask = 0;
 123
 124         radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
 125
 126         /* STONEY-specific register settings. */
 127         if (sctx->b.family == CHIP_STONEY) {
 128                 unsigned spi_shader_col_format =
 129                         sctx->ps_shader.cso ?
 130                         sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
 131                 unsigned sx_ps_downconvert = 0;
 132                 unsigned sx_blend_opt_epsilon = 0;
 133                 unsigned sx_blend_opt_control = 0;
 134
 135                 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
 136                         struct r600_surface *surf =
 137                                 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
 138                         unsigned format, swap, spi_format, colormask;
 139                         bool has_alpha, has_rgb;
 140
 141                         if (!surf)
 142                                 continue;
 143
 144                         format = G_028C70_FORMAT(surf->cb_color_info);
 145                         swap = G_028C70_COMP_SWAP(surf->cb_color_info);
 146                         spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
 147                         colormask = (cb_target_mask >> (i * 4)) & 0xf;
 148
 149                         /* Set if RGB and A are present. */
 150                         has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
 151
 152                         if (format == V_028C70_COLOR_8 ||
 153                             format == V_028C70_COLOR_16 ||
 154                             format == V_028C70_COLOR_32)
 155                                 has_rgb = !has_alpha;
 156                         else
 157                                 has_rgb = true;
 158
 159                         /* Check the colormask and export format. */
 160                         if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
 161                                 has_rgb = false;
 162                         if (!(colormask & PIPE_MASK_A))
 163                                 has_alpha = false;
 164
 165                         if (spi_format == V_028714_SPI_SHADER_ZERO) {
 166                                 has_rgb = false;
 167                                 has_alpha = false;
 168                         }
 169
 170                         /* Disable value checking for disabled channels. */
 171                         if (!has_rgb)
 172                                 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 173                         if (!has_alpha)
 174                                 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 175
 176                         /* Enable down-conversion for 32bpp and smaller formats. */
 177                         switch (format) {
 178                         case V_028C70_COLOR_8:
 179                         case V_028C70_COLOR_8_8:
 180                         case V_028C70_COLOR_8_8_8_8:
 181                                 /* For 1 and 2-channel formats, use the superset thereof. */
 182                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 183                                     spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 184                                     spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 185                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 186                                         sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 187                                 }
 188                                 break;
 189
 190                         case V_028C70_COLOR_5_6_5:
 191                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 192                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 193                                         sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 194                                 }
 195                                 break;
 196
 197                         case V_028C70_COLOR_1_5_5_5:
 198                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 199                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 200                                         sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 201                                 }
 202                                 break;
 203
 204                         case V_028C70_COLOR_4_4_4_4:
 205                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 206                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 207                                         sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 208                                 }
 209                                 break;
 210
 211                         case V_028C70_COLOR_32:
 212                                 if (swap == V_0280A0_SWAP_STD &&
 213                                     spi_format == V_028714_SPI_SHADER_32_R)
 214                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 215                                 else if (swap == V_0280A0_SWAP_ALT_REV &&
 216                                          spi_format == V_028714_SPI_SHADER_32_AR)
 217                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 218                                 break;
 219
 220                         case V_028C70_COLOR_16:
 221                         case V_028C70_COLOR_16_16:
 222                                 /* For 1-channel formats, use the superset thereof. */
 223                                 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 224                                     spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 225                                     spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 226                                     spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 227                                         if (swap == V_0280A0_SWAP_STD ||
 228                                             swap == V_0280A0_SWAP_STD_REV)
 229                                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 230                                         else
 231                                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 232                                 }
 233                                 break;
 234
 235                         case V_028C70_COLOR_10_11_11:
 236                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 237                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 238                                         sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 239                                 }
 240                                 break;
 241
 242                         case V_028C70_COLOR_2_10_10_10:
 243                                 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 244                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 245                                         sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 246                                 }
 247                                 break;
 248                         }
 249                 }
 250
 251                 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
 252                         sx_ps_downconvert = 0;
 253                         sx_blend_opt_epsilon = 0;
 254                         sx_blend_opt_control = 0;
 255                 }
 256
 257                 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
 258                 radeon_emit(cs, sx_ps_downconvert);     /* R_028754_SX_PS_DOWNCONVERT */
 259                 radeon_emit(cs, sx_blend_opt_epsilon);  /* R_028758_SX_BLEND_OPT_EPSILON */
 260                 radeon_emit(cs, sx_blend_opt_control);  /* R_02875C_SX_BLEND_OPT_CONTROL */
 261         }
 262 }
 263
 264 /*
 265  * Blender functions
 266  */
 267
 268 static uint32_t si_translate_blend_function(int blend_func)
 269 {
 270         switch (blend_func) {
 271         case PIPE_BLEND_ADD:
 272                 return V_028780_COMB_DST_PLUS_SRC;
 273         case PIPE_BLEND_SUBTRACT:
 274                 return V_028780_COMB_SRC_MINUS_DST;
 275         case PIPE_BLEND_REVERSE_SUBTRACT:
 276                 return V_028780_COMB_DST_MINUS_SRC;
 277         case PIPE_BLEND_MIN:
 278                 return V_028780_COMB_MIN_DST_SRC;
 279         case PIPE_BLEND_MAX:
 280                 return V_028780_COMB_MAX_DST_SRC;
 281         default:
 282                 R600_ERR("Unknown blend function %d\n", blend_func);
 283                 assert(0);
 284                 break;
 285         }
 286         return 0;
 287 }
 288
 289 static uint32_t si_translate_blend_factor(int blend_fact)
 290 {
 291         switch (blend_fact) {
 292         case PIPE_BLENDFACTOR_ONE:
 293                 return V_028780_BLEND_ONE;
 294         case PIPE_BLENDFACTOR_SRC_COLOR:
 295                 return V_028780_BLEND_SRC_COLOR;
 296         case PIPE_BLENDFACTOR_SRC_ALPHA:
 297                 return V_028780_BLEND_SRC_ALPHA;
 298         case PIPE_BLENDFACTOR_DST_ALPHA:
 299                 return V_028780_BLEND_DST_ALPHA;
 300         case PIPE_BLENDFACTOR_DST_COLOR:
 301                 return V_028780_BLEND_DST_COLOR;
 302         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 303                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 304         case PIPE_BLENDFACTOR_CONST_COLOR:
 305                 return V_028780_BLEND_CONSTANT_COLOR;
 306         case PIPE_BLENDFACTOR_CONST_ALPHA:
 307                 return V_028780_BLEND_CONSTANT_ALPHA;
 308         case PIPE_BLENDFACTOR_ZERO:
 309                 return V_028780_BLEND_ZERO;
 310         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 311                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 312         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 313                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 314         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 315                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 316         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 317                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 318         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 319                 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
 320         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 321                 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
 322         case PIPE_BLENDFACTOR_SRC1_COLOR:
 323                 return V_028780_BLEND_SRC1_COLOR;
 324         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 325                 return V_028780_BLEND_SRC1_ALPHA;
 326         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 327                 return V_028780_BLEND_INV_SRC1_COLOR;
 328         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 329                 return V_028780_BLEND_INV_SRC1_ALPHA;
 330         default:
 331                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 332                 assert(0);
 333                 break;
 334         }
 335         return 0;
 336 }
 337
 338 static uint32_t si_translate_blend_opt_function(int blend_func)
 339 {
 340         switch (blend_func) {
 341         case PIPE_BLEND_ADD:
 342                 return V_028760_OPT_COMB_ADD;
 343         case PIPE_BLEND_SUBTRACT:
 344                 return V_028760_OPT_COMB_SUBTRACT;
 345         case PIPE_BLEND_REVERSE_SUBTRACT:
 346                 return V_028760_OPT_COMB_REVSUBTRACT;
 347         case PIPE_BLEND_MIN:
 348                 return V_028760_OPT_COMB_MIN;
 349         case PIPE_BLEND_MAX:
 350                 return V_028760_OPT_COMB_MAX;
 351         default:
 352                 return V_028760_OPT_COMB_BLEND_DISABLED;
 353         }
 354 }
 355
 356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
 357 {
 358         switch (blend_fact) {
 359         case PIPE_BLENDFACTOR_ZERO:
 360                 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
 361         case PIPE_BLENDFACTOR_ONE:
 362                 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
 363         case PIPE_BLENDFACTOR_SRC_COLOR:
 364                 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
 365                                 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
 366         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 367                 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
 368                                 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
 369         case PIPE_BLENDFACTOR_SRC_ALPHA:
 370                 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
 371         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 372                 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
 373         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 374                 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
 375                                 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
 376         default:
 377                 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
 378         }
 379 }
 380
 381 /**
 382  * Get rid of DST in the blend factors by commuting the operands:
 383  *    func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
 384  */
 385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
 386                                 unsigned *dst_factor, unsigned expected_dst,
 387                                 unsigned replacement_src)
 388 {
 389         if (*src_factor == expected_dst &&
 390             *dst_factor == PIPE_BLENDFACTOR_ZERO) {
 391                 *src_factor = PIPE_BLENDFACTOR_ZERO;
 392                 *dst_factor = replacement_src;
 393
 394                 /* Commuting the operands requires reversing subtractions. */
 395                 if (*func == PIPE_BLEND_SUBTRACT)
 396                         *func = PIPE_BLEND_REVERSE_SUBTRACT;
 397                 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
 398                         *func = PIPE_BLEND_SUBTRACT;
 399         }
 400 }
 401
 402 static bool si_blend_factor_uses_dst(unsigned factor)
 403 {
 404         return factor == PIPE_BLENDFACTOR_DST_COLOR ||
 405                 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
 406                 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
 407                 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
 408                 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
 409 }
 410
 411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
 412                                         const struct pipe_blend_state *state,
 413                                         unsigned mode)
 414 {
 415         struct si_context *sctx = (struct si_context*)ctx;
 416         struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
 417         struct si_pm4_state *pm4 = &blend->pm4;
 418         uint32_t sx_mrt_blend_opt[8] = {0};
 419         uint32_t color_control = 0;
 420
 421         if (!blend)
 422                 return NULL;
 423
 424         blend->alpha_to_coverage = state->alpha_to_coverage;
 425         blend->alpha_to_one = state->alpha_to_one;
 426         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 427
 428         if (state->logicop_enable) {
 429                 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
 430         } else {
 431                 color_control |= S_028808_ROP3(0xcc);
 432         }
 433
 434         si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
 435                        S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 436                        S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
 437                        S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
 438                        S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
 439                        S_028B70_ALPHA_TO_MASK_OFFSET3(2));
 440
 441         if (state->alpha_to_coverage)
 442                 blend->need_src_alpha_4bit |= 0xf;
 443
 444         blend->cb_target_mask = 0;
 445         for (int i = 0; i < 8; i++) {
 446                 /* state->rt entries > 0 only written if independent blending */
 447                 const int j = state->independent_blend_enable ? i : 0;
 448
 449                 unsigned eqRGB = state->rt[j].rgb_func;
 450                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 451                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 452                 unsigned eqA = state->rt[j].alpha_func;
 453                 unsigned srcA = state->rt[j].alpha_src_factor;
 454                 unsigned dstA = state->rt[j].alpha_dst_factor;
 455
 456                 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
 457                 unsigned blend_cntl = 0;
 458
 459                 sx_mrt_blend_opt[i] =
 460                         S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
 461                         S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
 462
 463                 if (!state->rt[j].colormask)
 464                         continue;
 465
 466                 /* cb_render_state will disable unused ones */
 467                 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
 468
 469                 if (!state->rt[j].blend_enable) {
 470                         si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
 471                         continue;
 472                 }
 473
 474                 /* Blending optimizations for Stoney.
 475                  * These transformations don't change the behavior.
 476                  *
 477                  * First, get rid of DST in the blend factors:
 478                  *    func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
 479                  */
 480                 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
 481                                     PIPE_BLENDFACTOR_DST_COLOR,
 482                                     PIPE_BLENDFACTOR_SRC_COLOR);
 483                 si_blend_remove_dst(&eqA, &srcA, &dstA,
 484                                     PIPE_BLENDFACTOR_DST_COLOR,
 485                                     PIPE_BLENDFACTOR_SRC_COLOR);
 486                 si_blend_remove_dst(&eqA, &srcA, &dstA,
 487                                     PIPE_BLENDFACTOR_DST_ALPHA,
 488                                     PIPE_BLENDFACTOR_SRC_ALPHA);
 489
 490                 /* Look up the ideal settings from tables. */
 491                 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
 492                 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
 493                 srcA_opt = si_translate_blend_opt_factor(srcA, true);
 494                 dstA_opt = si_translate_blend_opt_factor(dstA, true);
 495
 496                 /* Handle interdependencies. */
 497                 if (si_blend_factor_uses_dst(srcRGB))
 498                         dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
 499                 if (si_blend_factor_uses_dst(srcA))
 500                         dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
 501
 502                 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
 503                     (dstRGB == PIPE_BLENDFACTOR_ZERO ||
 504                      dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
 505                      dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
 506                         dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
 507
 508                 /* Set the final value. */
 509                 sx_mrt_blend_opt[i] =
 510                         S_028760_COLOR_SRC_OPT(srcRGB_opt) |
 511                         S_028760_COLOR_DST_OPT(dstRGB_opt) |
 512                         S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
 513                         S_028760_ALPHA_SRC_OPT(srcA_opt) |
 514                         S_028760_ALPHA_DST_OPT(dstA_opt) |
 515                         S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
 516
 517                 /* Set blend state. */
 518                 blend_cntl |= S_028780_ENABLE(1);
 519                 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
 520                 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
 521                 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
 522
 523                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 524                         blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
 525                         blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
 526                         blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
 527                         blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
 528                 }
 529                 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
 530
 531                 blend->blend_enable_4bit |= 0xfu << (i * 4);
 532
 533                 /* This is only important for formats without alpha. */
 534                 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
 535                     dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
 536                     srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
 537                     dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
 538                     srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
 539                     dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
 540                         blend->need_src_alpha_4bit |= 0xfu << (i * 4);
 541         }
 542
 543         if (blend->cb_target_mask) {
 544                 color_control |= S_028808_MODE(mode);
 545         } else {
 546                 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 547         }
 548
 549         if (sctx->b.family == CHIP_STONEY) {
 550                 for (int i = 0; i < 8; i++)
 551                         si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
 552                                        sx_mrt_blend_opt[i]);
 553
 554                 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
 555                 if (blend->dual_src_blend || state->logicop_enable ||
 556                     mode == V_028808_CB_RESOLVE)
 557                         color_control |= S_028808_DISABLE_DUAL_QUAD(1);
 558         }
 559
 560         si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
 561         return blend;
 562 }
 563
 564 static void *si_create_blend_state(struct pipe_context *ctx,
 565                                    const struct pipe_blend_state *state)
 566 {
 567         return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
 568 }
 569
 570 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
 571 {
 572         struct si_context *sctx = (struct si_context *)ctx;
 573         si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
 574         si_mark_atom_dirty(sctx, &sctx->cb_render_state);
 575 }
 576
 577 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
 578 {
 579         struct si_context *sctx = (struct si_context *)ctx;
 580         si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
 581 }
 582
 583 static void si_set_blend_color(struct pipe_context *ctx,
 584                                const struct pipe_blend_color *state)
 585 {
 586         struct si_context *sctx = (struct si_context *)ctx;
 587
 588         if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
 589                 return;
 590
 591         sctx->blend_color.state = *state;
 592         si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
 593 }
 594
 595 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
 596 {
 597         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 598
 599         radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 600         radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
 601 }
 602
 603 /*
 604  * Clipping
 605  */
 606
 607 static void si_set_clip_state(struct pipe_context *ctx,
 608                               const struct pipe_clip_state *state)
 609 {
 610         struct si_context *sctx = (struct si_context *)ctx;
 611         struct pipe_constant_buffer cb;
 612
 613         if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
 614                 return;
 615
 616         sctx->clip_state.state = *state;
 617         si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
 618
 619         cb.buffer = NULL;
 620         cb.user_buffer = state->ucp;
 621         cb.buffer_offset = 0;
 622         cb.buffer_size = 4*4*8;
 623         si_set_constant_buffer(sctx, &sctx->rw_buffers,
 624                                SI_VS_CONST_CLIP_PLANES, &cb);
 625         pipe_resource_reference(&cb.buffer, NULL);
 626 }
 627
 628 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
 629 {
 630         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 631
 632         radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
 633         radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
 634 }
 635
 636 #define SIX_BITS 0x3F
 637
 638 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
 639 {
 640         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 641         struct tgsi_shader_info *info = si_get_vs_info(sctx);
 642         unsigned window_space =
 643            info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 644         unsigned clipdist_mask =
 645                 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
 646
 647         radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
 648                 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
 649                 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
 650                 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
 651                 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
 652                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
 653                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
 654                 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
 655                                             info->writes_edgeflag ||
 656                                             info->writes_layer ||
 657                                              info->writes_viewport_index) |
 658                 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
 659                 (sctx->queued.named.rasterizer->clip_plane_enable &
 660                  clipdist_mask));
 661         radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
 662                 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
 663                 (clipdist_mask ? 0 :
 664                  sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
 665                 S_028810_CLIP_DISABLE(window_space));
 666
 667         /* reuse needs to be set off if we write oViewport */
 668         radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
 669                                S_028AB4_REUSE_OFF(info->writes_viewport_index));
 670 }
 671
 672 /*
 673  * inferred state between framebuffer and rasterizer
 674  */
 675 static void si_update_poly_offset_state(struct si_context *sctx)
 676 {
 677         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
 678
 679         if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
 680                 return;
 681
 682         switch (sctx->framebuffer.state.zsbuf->texture->format) {
 683         case PIPE_FORMAT_Z16_UNORM:
 684                 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
 685                 break;
 686         default: /* 24-bit */
 687                 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
 688                 break;
 689         case PIPE_FORMAT_Z32_FLOAT:
 690         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 691                 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
 692                 break;
 693         }
 694 }
 695
 696 /*
 697  * Rasterizer
 698  */
 699
 700 static uint32_t si_translate_fill(uint32_t func)
 701 {
 702         switch(func) {
 703         case PIPE_POLYGON_MODE_FILL:
 704                 return V_028814_X_DRAW_TRIANGLES;
 705         case PIPE_POLYGON_MODE_LINE:
 706                 return V_028814_X_DRAW_LINES;
 707         case PIPE_POLYGON_MODE_POINT:
 708                 return V_028814_X_DRAW_POINTS;
 709         default:
 710                 assert(0);
 711                 return V_028814_X_DRAW_POINTS;
 712         }
 713 }
 714
 715 static void *si_create_rs_state(struct pipe_context *ctx,
 716                                 const struct pipe_rasterizer_state *state)
 717 {
 718         struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
 719         struct si_pm4_state *pm4 = &rs->pm4;
 720         unsigned tmp, i;
 721         float psize_min, psize_max;
 722
 723         if (!rs) {
 724                 return NULL;
 725         }
 726
 727         rs->scissor_enable = state->scissor;
 728         rs->two_side = state->light_twoside;
 729         rs->multisample_enable = state->multisample;
 730         rs->force_persample_interp = state->force_persample_interp;
 731         rs->clip_plane_enable = state->clip_plane_enable;
 732         rs->line_stipple_enable = state->line_stipple_enable;
 733         rs->poly_stipple_enable = state->poly_stipple_enable;
 734         rs->line_smooth = state->line_smooth;
 735         rs->poly_smooth = state->poly_smooth;
 736         rs->uses_poly_offset = state->offset_point || state->offset_line ||
 737                                state->offset_tri;
 738         rs->clamp_fragment_color = state->clamp_fragment_color;
 739         rs->flatshade = state->flatshade;
 740         rs->sprite_coord_enable = state->sprite_coord_enable;
 741         rs->rasterizer_discard = state->rasterizer_discard;
 742         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 743                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 744                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 745         rs->pa_cl_clip_cntl =
 746                 S_028810_PS_UCP_MODE(3) |
 747                 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
 748                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 749                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 750                 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
 751                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 752
 753         si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
 754                 S_0286D4_FLAT_SHADE_ENA(1) |
 755                 S_0286D4_PNT_SPRITE_ENA(1) |
 756                 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
 757                 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
 758                 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
 759                 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
 760                 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
 761
 762         /* point size 12.4 fixed point */
 763         tmp = (unsigned)(state->point_size * 8.0);
 764         si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 765
 766         if (state->point_size_per_vertex) {
 767                 psize_min = util_get_min_point_size(state);
 768                 psize_max = 8192;
 769         } else {
 770                 /* Force the point size to be as if the vertex output was disabled. */
 771                 psize_min = state->point_size;
 772                 psize_max = state->point_size;
 773         }
 774         /* Divide by two, because 0.5 = 1 pixel. */
 775         si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
 776                         S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
 777                         S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
 778
 779         tmp = (unsigned)state->line_width * 8;
 780         si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
 781         si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
 782                        S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
 783                        S_028A48_MSAA_ENABLE(state->multisample ||
 784                                             state->poly_smooth ||
 785                                             state->line_smooth) |
 786                        S_028A48_VPORT_SCISSOR_ENABLE(1));
 787
 788         si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
 789                        S_028BE4_PIX_CENTER(state->half_pixel_center) |
 790                        S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
 791
 792         si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 793         si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
 794                 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 795                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 796                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 797                 S_028814_FACE(!state->front_ccw) |
 798                 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
 799                 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
 800                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
 801                 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
 802                                    state->fill_back != PIPE_POLYGON_MODE_FILL) |
 803                 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
 804                 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
 805         si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
 806                        SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
 807
 808         /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
 809         for (i = 0; i < 3; i++) {
 810                 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
 811                 float offset_units = state->offset_units;
 812                 float offset_scale = state->offset_scale * 16.0f;
 813
 814                 switch (i) {
 815                 case 0: /* 16-bit zbuffer */
 816                         offset_units *= 4.0f;
 817                         break;
 818                 case 1: /* 24-bit zbuffer */
 819                         offset_units *= 2.0f;
 820                         break;
 821                 case 2: /* 32-bit zbuffer */
 822                         offset_units *= 1.0f;
 823                         break;
 824                 }
 825
 826                 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
 827                                fui(offset_scale));
 828                 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 829                                fui(offset_units));
 830                 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
 831                                fui(offset_scale));
 832                 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 833                                fui(offset_units));
 834         }
 835
 836         return rs;
 837 }
 838
 839 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
 840 {
 841         struct si_context *sctx = (struct si_context *)ctx;
 842         struct si_state_rasterizer *old_rs =
 843                 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
 844         struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
 845
 846         if (!state)
 847                 return;
 848
 849         if (sctx->framebuffer.nr_samples > 1 &&
 850             (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
 851                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
 852
 853         r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
 854
 855         si_pm4_bind_state(sctx, rasterizer, rs);
 856         si_update_poly_offset_state(sctx);
 857
 858         si_mark_atom_dirty(sctx, &sctx->clip_regs);
 859 }
 860
 861 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
 862 {
 863         struct si_context *sctx = (struct si_context *)ctx;
 864
 865         if (sctx->queued.named.rasterizer == state)
 866                 si_pm4_bind_state(sctx, poly_offset, NULL);
 867         si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
 868 }
 869
 870 /*
 871  * infeered state between dsa and stencil ref
 872  */
 873 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
 874 {
 875         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 876         struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
 877         struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
 878
 879         radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 880         radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
 881                         S_028430_STENCILMASK(dsa->valuemask[0]) |
 882                         S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
 883                         S_028430_STENCILOPVAL(1));
 884         radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
 885                         S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
 886                         S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
 887                         S_028434_STENCILOPVAL_BF(1));
 888 }
 889
 890 static void si_set_stencil_ref(struct pipe_context *ctx,
 891                                const struct pipe_stencil_ref *state)
 892 {
 893         struct si_context *sctx = (struct si_context *)ctx;
 894
 895         if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
 896                 return;
 897
 898         sctx->stencil_ref.state = *state;
 899         si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
 900 }
 901
 902
 903 /*
 904  * DSA
 905  */
 906
 907 static uint32_t si_translate_stencil_op(int s_op)
 908 {
 909         switch (s_op) {
 910         case PIPE_STENCIL_OP_KEEP:
 911                 return V_02842C_STENCIL_KEEP;
 912         case PIPE_STENCIL_OP_ZERO:
 913                 return V_02842C_STENCIL_ZERO;
 914         case PIPE_STENCIL_OP_REPLACE:
 915                 return V_02842C_STENCIL_REPLACE_TEST;
 916         case PIPE_STENCIL_OP_INCR:
 917                 return V_02842C_STENCIL_ADD_CLAMP;
 918         case PIPE_STENCIL_OP_DECR:
 919                 return V_02842C_STENCIL_SUB_CLAMP;
 920         case PIPE_STENCIL_OP_INCR_WRAP:
 921                 return V_02842C_STENCIL_ADD_WRAP;
 922         case PIPE_STENCIL_OP_DECR_WRAP:
 923                 return V_02842C_STENCIL_SUB_WRAP;
 924         case PIPE_STENCIL_OP_INVERT:
 925                 return V_02842C_STENCIL_INVERT;
 926         default:
 927                 R600_ERR("Unknown stencil op %d", s_op);
 928                 assert(0);
 929                 break;
 930         }
 931         return 0;
 932 }
 933
 934 static void *si_create_dsa_state(struct pipe_context *ctx,
 935                                  const struct pipe_depth_stencil_alpha_state *state)
 936 {
 937         struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
 938         struct si_pm4_state *pm4 = &dsa->pm4;
 939         unsigned db_depth_control;
 940         uint32_t db_stencil_control = 0;
 941
 942         if (!dsa) {
 943                 return NULL;
 944         }
 945
 946         dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
 947         dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
 948         dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
 949         dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
 950
 951         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 952                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 953                 S_028800_ZFUNC(state->depth.func) |
 954                 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
 955
 956         /* stencil */
 957         if (state->stencil[0].enabled) {
 958                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 959                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
 960                 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
 961                 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
 962                 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
 963
 964                 if (state->stencil[1].enabled) {
 965                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 966                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
 967                         db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
 968                         db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
 969                         db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
 970                 }
 971         }
 972
 973         /* alpha */
 974         if (state->alpha.enabled) {
 975                 dsa->alpha_func = state->alpha.func;
 976
 977                 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
 978                                SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
 979         } else {
 980                 dsa->alpha_func = PIPE_FUNC_ALWAYS;
 981         }
 982
 983         si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 984         si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
 985         if (state->depth.bounds_test) {
 986                 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
 987                 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
 988         }
 989
 990         return dsa;
 991 }
 992
 993 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
 994 {
 995         struct si_context *sctx = (struct si_context *)ctx;
 996         struct si_state_dsa *dsa = state;
 997
 998         if (!state)
 999                 return;
1000
1001         si_pm4_bind_state(sctx, dsa, dsa);
1002
1003         if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1004                    sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1005                 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1006                 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1007         }
1008 }
1009
1010 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1011 {
1012         struct si_context *sctx = (struct si_context *)ctx;
1013         si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1014 }
1015
1016 static void *si_create_db_flush_dsa(struct si_context *sctx)
1017 {
1018         struct pipe_depth_stencil_alpha_state dsa = {};
1019
1020         return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1021 }
1022
1023 /* DB RENDER STATE */
1024
1025 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1026 {
1027         struct si_context *sctx = (struct si_context*)ctx;
1028
1029         /* Pipeline stat & streamout queries. */
1030         if (enable) {
1031                 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1032                 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1033         } else {
1034                 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1035                 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1036         }
1037
1038         /* Occlusion queries. */
1039         if (sctx->occlusion_queries_disabled != !enable) {
1040                 sctx->occlusion_queries_disabled = !enable;
1041                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1042         }
1043 }
1044
1045 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1046 {
1047         struct si_context *sctx = (struct si_context*)ctx;
1048
1049         si_mark_atom_dirty(sctx, &sctx->db_render_state);
1050 }
1051
1052 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1053 {
1054         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1055         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1056         unsigned db_shader_control;
1057
1058         radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1059
1060         /* DB_RENDER_CONTROL */
1061         if (sctx->dbcb_depth_copy_enabled ||
1062             sctx->dbcb_stencil_copy_enabled) {
1063                 radeon_emit(cs,
1064                             S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1065                             S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1066                             S_028000_COPY_CENTROID(1) |
1067                             S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1068         } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1069                 radeon_emit(cs,
1070                             S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1071                             S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1072         } else {
1073                 radeon_emit(cs,
1074                             S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1075                             S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1076         }
1077
1078         /* DB_COUNT_CONTROL (occlusion queries) */
1079         if (sctx->b.num_occlusion_queries > 0 &&
1080             !sctx->occlusion_queries_disabled) {
1081                 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1082
1083                 if (sctx->b.chip_class >= CIK) {
1084                         radeon_emit(cs,
1085                                     S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1086                                     S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1087                                     S_028004_ZPASS_ENABLE(1) |
1088                                     S_028004_SLICE_EVEN_ENABLE(1) |
1089                                     S_028004_SLICE_ODD_ENABLE(1));
1090                 } else {
1091                         radeon_emit(cs,
1092                                     S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1093                                     S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1094                 }
1095         } else {
1096                 /* Disable occlusion queries. */
1097                 if (sctx->b.chip_class >= CIK) {
1098                         radeon_emit(cs, 0);
1099                 } else {
1100                         radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1101                 }
1102         }
1103
1104         /* DB_RENDER_OVERRIDE2 */
1105         radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1106                 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1107                 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1108                 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1109
1110         db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1111                             sctx->ps_db_shader_control;
1112
1113         /* Bug workaround for smoothing (overrasterization) on SI. */
1114         if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1115                 db_shader_control &= C_02880C_Z_ORDER;
1116                 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1117         }
1118
1119         /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1120         if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1121                 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1122
1123         if (sctx->b.family == CHIP_STONEY &&
1124             sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1125                 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1126
1127         radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1128                                db_shader_control);
1129 }
1130
1131 /*
1132  * format translation
1133  */
1134 static uint32_t si_translate_colorformat(enum pipe_format format)
1135 {
1136         const struct util_format_description *desc = util_format_description(format);
1137
1138 #define HAS_SIZE(x,y,z,w) \
1139         (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1140          desc->channel[2].size == (z) && desc->channel[3].size == (w))
1141
1142         if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1143                 return V_028C70_COLOR_10_11_11;
1144
1145         if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1146                 return V_028C70_COLOR_INVALID;
1147
1148         /* hw cannot support mixed formats (except depth/stencil, since
1149          * stencil is not written to). */
1150         if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1151                 return V_028C70_COLOR_INVALID;
1152
1153         switch (desc->nr_channels) {
1154         case 1:
1155                 switch (desc->channel[0].size) {
1156                 case 8:
1157                         return V_028C70_COLOR_8;
1158                 case 16:
1159                         return V_028C70_COLOR_16;
1160                 case 32:
1161                         return V_028C70_COLOR_32;
1162                 }
1163                 break;
1164         case 2:
1165                 if (desc->channel[0].size == desc->channel[1].size) {
1166                         switch (desc->channel[0].size) {
1167                         case 8:
1168                                 return V_028C70_COLOR_8_8;
1169                         case 16:
1170                                 return V_028C70_COLOR_16_16;
1171                         case 32:
1172                                 return V_028C70_COLOR_32_32;
1173                         }
1174                 } else if (HAS_SIZE(8,24,0,0)) {
1175                         return V_028C70_COLOR_24_8;
1176                 } else if (HAS_SIZE(24,8,0,0)) {
1177                         return V_028C70_COLOR_8_24;
1178                 }
1179                 break;
1180         case 3:
1181                 if (HAS_SIZE(5,6,5,0)) {
1182                         return V_028C70_COLOR_5_6_5;
1183                 } else if (HAS_SIZE(32,8,24,0)) {
1184                         return V_028C70_COLOR_X24_8_32_FLOAT;
1185                 }
1186                 break;
1187         case 4:
1188                 if (desc->channel[0].size == desc->channel[1].size &&
1189                     desc->channel[0].size == desc->channel[2].size &&
1190                     desc->channel[0].size == desc->channel[3].size) {
1191                         switch (desc->channel[0].size) {
1192                         case 4:
1193                                 return V_028C70_COLOR_4_4_4_4;
1194                         case 8:
1195                                 return V_028C70_COLOR_8_8_8_8;
1196                         case 16:
1197                                 return V_028C70_COLOR_16_16_16_16;
1198                         case 32:
1199                                 return V_028C70_COLOR_32_32_32_32;
1200                         }
1201                 } else if (HAS_SIZE(5,5,5,1)) {
1202                         return V_028C70_COLOR_1_5_5_5;
1203                 } else if (HAS_SIZE(10,10,10,2)) {
1204                         return V_028C70_COLOR_2_10_10_10;
1205                 }
1206                 break;
1207         }
1208         return V_028C70_COLOR_INVALID;
1209 }
1210
1211 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1212 {
1213         if (SI_BIG_ENDIAN) {
1214                 switch(colorformat) {
1215                 /* 8-bit buffers. */
1216                 case V_028C70_COLOR_8:
1217                         return V_028C70_ENDIAN_NONE;
1218
1219                 /* 16-bit buffers. */
1220                 case V_028C70_COLOR_5_6_5:
1221                 case V_028C70_COLOR_1_5_5_5:
1222                 case V_028C70_COLOR_4_4_4_4:
1223                 case V_028C70_COLOR_16:
1224                 case V_028C70_COLOR_8_8:
1225                         return V_028C70_ENDIAN_8IN16;
1226
1227                 /* 32-bit buffers. */
1228                 case V_028C70_COLOR_8_8_8_8:
1229                 case V_028C70_COLOR_2_10_10_10:
1230                 case V_028C70_COLOR_8_24:
1231                 case V_028C70_COLOR_24_8:
1232                 case V_028C70_COLOR_16_16:
1233                         return V_028C70_ENDIAN_8IN32;
1234
1235                 /* 64-bit buffers. */
1236                 case V_028C70_COLOR_16_16_16_16:
1237                         return V_028C70_ENDIAN_8IN16;
1238
1239                 case V_028C70_COLOR_32_32:
1240                         return V_028C70_ENDIAN_8IN32;
1241
1242                 /* 128-bit buffers. */
1243                 case V_028C70_COLOR_32_32_32_32:
1244                         return V_028C70_ENDIAN_8IN32;
1245                 default:
1246                         return V_028C70_ENDIAN_NONE; /* Unsupported. */
1247                 }
1248         } else {
1249                 return V_028C70_ENDIAN_NONE;
1250         }
1251 }
1252
1253 static uint32_t si_translate_dbformat(enum pipe_format format)
1254 {
1255         switch (format) {
1256         case PIPE_FORMAT_Z16_UNORM:
1257                 return V_028040_Z_16;
1258         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1259         case PIPE_FORMAT_X8Z24_UNORM:
1260         case PIPE_FORMAT_Z24X8_UNORM:
1261         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1262                 return V_028040_Z_24; /* deprecated on SI */
1263         case PIPE_FORMAT_Z32_FLOAT:
1264         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1265                 return V_028040_Z_32_FLOAT;
1266         default:
1267                 return V_028040_Z_INVALID;
1268         }
1269 }
1270
1271 /*
1272  * Texture translation
1273  */
1274
1275 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1276                                        enum pipe_format format,
1277                                        const struct util_format_description *desc,
1278                                        int first_non_void)
1279 {
1280         struct si_screen *sscreen = (struct si_screen*)screen;
1281         bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1282                                           sscreen->b.info.drm_minor >= 31) ||
1283                                          sscreen->b.info.drm_major == 3;
1284         boolean uniform = TRUE;
1285         int i;
1286
1287         /* Colorspace (return non-RGB formats directly). */
1288         switch (desc->colorspace) {
1289         /* Depth stencil formats */
1290         case UTIL_FORMAT_COLORSPACE_ZS:
1291                 switch (format) {
1292                 case PIPE_FORMAT_Z16_UNORM:
1293                         return V_008F14_IMG_DATA_FORMAT_16;
1294                 case PIPE_FORMAT_X24S8_UINT:
1295                 case PIPE_FORMAT_Z24X8_UNORM:
1296                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1297                         return V_008F14_IMG_DATA_FORMAT_8_24;
1298                 case PIPE_FORMAT_X8Z24_UNORM:
1299                 case PIPE_FORMAT_S8X24_UINT:
1300                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1301                         return V_008F14_IMG_DATA_FORMAT_24_8;
1302                 case PIPE_FORMAT_S8_UINT:
1303                         return V_008F14_IMG_DATA_FORMAT_8;
1304                 case PIPE_FORMAT_Z32_FLOAT:
1305                         return V_008F14_IMG_DATA_FORMAT_32;
1306                 case PIPE_FORMAT_X32_S8X24_UINT:
1307                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1308                         return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1309                 default:
1310                         goto out_unknown;
1311                 }
1312
1313         case UTIL_FORMAT_COLORSPACE_YUV:
1314                 goto out_unknown; /* TODO */
1315
1316         case UTIL_FORMAT_COLORSPACE_SRGB:
1317                 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1318                         goto out_unknown;
1319                 break;
1320
1321         default:
1322                 break;
1323         }
1324
1325         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1326                 if (!enable_compressed_formats)
1327                         goto out_unknown;
1328
1329                 switch (format) {
1330                 case PIPE_FORMAT_RGTC1_SNORM:
1331                 case PIPE_FORMAT_LATC1_SNORM:
1332                 case PIPE_FORMAT_RGTC1_UNORM:
1333                 case PIPE_FORMAT_LATC1_UNORM:
1334                         return V_008F14_IMG_DATA_FORMAT_BC4;
1335                 case PIPE_FORMAT_RGTC2_SNORM:
1336                 case PIPE_FORMAT_LATC2_SNORM:
1337                 case PIPE_FORMAT_RGTC2_UNORM:
1338                 case PIPE_FORMAT_LATC2_UNORM:
1339                         return V_008F14_IMG_DATA_FORMAT_BC5;
1340                 default:
1341                         goto out_unknown;
1342                 }
1343         }
1344
1345         if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1346             sscreen->b.family == CHIP_STONEY) {
1347                 switch (format) {
1348                 case PIPE_FORMAT_ETC1_RGB8:
1349                 case PIPE_FORMAT_ETC2_RGB8:
1350                 case PIPE_FORMAT_ETC2_SRGB8:
1351                         return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1352                 case PIPE_FORMAT_ETC2_RGB8A1:
1353                 case PIPE_FORMAT_ETC2_SRGB8A1:
1354                         return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1355                 case PIPE_FORMAT_ETC2_RGBA8:
1356                 case PIPE_FORMAT_ETC2_SRGBA8:
1357                         return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1358                 case PIPE_FORMAT_ETC2_R11_UNORM:
1359                 case PIPE_FORMAT_ETC2_R11_SNORM:
1360                         return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1361                 case PIPE_FORMAT_ETC2_RG11_UNORM:
1362                 case PIPE_FORMAT_ETC2_RG11_SNORM:
1363                         return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1364                 default:
1365                         goto out_unknown;
1366                 }
1367         }
1368
1369         if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1370                 if (!enable_compressed_formats)
1371                         goto out_unknown;
1372
1373                 switch (format) {
1374                 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1375                 case PIPE_FORMAT_BPTC_SRGBA:
1376                         return V_008F14_IMG_DATA_FORMAT_BC7;
1377                 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1378                 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1379                         return V_008F14_IMG_DATA_FORMAT_BC6;
1380                 default:
1381                         goto out_unknown;
1382                 }
1383         }
1384
1385         if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1386                 switch (format) {
1387                 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1388                 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1389                         return V_008F14_IMG_DATA_FORMAT_GB_GR;
1390                 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1391                 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1392                         return V_008F14_IMG_DATA_FORMAT_BG_RG;
1393                 default:
1394                         goto out_unknown;
1395                 }
1396         }
1397
1398         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1399                 if (!enable_compressed_formats)
1400                         goto out_unknown;
1401
1402                 if (!util_format_s3tc_enabled) {
1403                         goto out_unknown;
1404                 }
1405
1406                 switch (format) {
1407                 case PIPE_FORMAT_DXT1_RGB:
1408                 case PIPE_FORMAT_DXT1_RGBA:
1409                 case PIPE_FORMAT_DXT1_SRGB:
1410                 case PIPE_FORMAT_DXT1_SRGBA:
1411                         return V_008F14_IMG_DATA_FORMAT_BC1;
1412                 case PIPE_FORMAT_DXT3_RGBA:
1413                 case PIPE_FORMAT_DXT3_SRGBA:
1414                         return V_008F14_IMG_DATA_FORMAT_BC2;
1415                 case PIPE_FORMAT_DXT5_RGBA:
1416                 case PIPE_FORMAT_DXT5_SRGBA:
1417                         return V_008F14_IMG_DATA_FORMAT_BC3;
1418                 default:
1419                         goto out_unknown;
1420                 }
1421         }
1422
1423         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1424                 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1425         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1426                 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1427         }
1428
1429         /* R8G8Bx_SNORM - TODO CxV8U8 */
1430
1431         /* hw cannot support mixed formats (except depth/stencil, since only
1432          * depth is read).*/
1433         if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1434                 goto out_unknown;
1435
1436         /* See whether the components are of the same size. */
1437         for (i = 1; i < desc->nr_channels; i++) {
1438                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1439         }
1440
1441         /* Non-uniform formats. */
1442         if (!uniform) {
1443                 switch(desc->nr_channels) {
1444                 case 3:
1445                         if (desc->channel[0].size == 5 &&
1446                             desc->channel[1].size == 6 &&
1447                             desc->channel[2].size == 5) {
1448                                 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1449                         }
1450                         goto out_unknown;
1451                 case 4:
1452                         if (desc->channel[0].size == 5 &&
1453                             desc->channel[1].size == 5 &&
1454                             desc->channel[2].size == 5 &&
1455                             desc->channel[3].size == 1) {
1456                                 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1457                         }
1458                         if (desc->channel[0].size == 10 &&
1459                             desc->channel[1].size == 10 &&
1460                             desc->channel[2].size == 10 &&
1461                             desc->channel[3].size == 2) {
1462                                 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1463                         }
1464                         goto out_unknown;
1465                 }
1466                 goto out_unknown;
1467         }
1468
1469         if (first_non_void < 0 || first_non_void > 3)
1470                 goto out_unknown;
1471
1472         /* uniform formats */
1473         switch (desc->channel[first_non_void].size) {
1474         case 4:
1475                 switch (desc->nr_channels) {
1476 #if 0 /* Not supported for render targets */
1477                 case 2:
1478                         return V_008F14_IMG_DATA_FORMAT_4_4;
1479 #endif
1480                 case 4:
1481                         return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1482                 }
1483                 break;
1484         case 8:
1485                 switch (desc->nr_channels) {
1486                 case 1:
1487                         return V_008F14_IMG_DATA_FORMAT_8;
1488                 case 2:
1489                         return V_008F14_IMG_DATA_FORMAT_8_8;
1490                 case 4:
1491                         return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1492                 }
1493                 break;
1494         case 16:
1495                 switch (desc->nr_channels) {
1496                 case 1:
1497                         return V_008F14_IMG_DATA_FORMAT_16;
1498                 case 2:
1499                         return V_008F14_IMG_DATA_FORMAT_16_16;
1500                 case 4:
1501                         return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1502                 }
1503                 break;
1504         case 32:
1505                 switch (desc->nr_channels) {
1506                 case 1:
1507                         return V_008F14_IMG_DATA_FORMAT_32;
1508                 case 2:
1509                         return V_008F14_IMG_DATA_FORMAT_32_32;
1510 #if 0 /* Not supported for render targets */
1511                 case 3:
1512                         return V_008F14_IMG_DATA_FORMAT_32_32_32;
1513 #endif
1514                 case 4:
1515                         return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1516                 }
1517         }
1518
1519 out_unknown:
1520         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1521         return ~0;
1522 }
1523
1524 static unsigned si_tex_wrap(unsigned wrap)
1525 {
1526         switch (wrap) {
1527         default:
1528         case PIPE_TEX_WRAP_REPEAT:
1529                 return V_008F30_SQ_TEX_WRAP;
1530         case PIPE_TEX_WRAP_CLAMP:
1531                 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1532         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1533                 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1534         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1535                 return V_008F30_SQ_TEX_CLAMP_BORDER;
1536         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1537                 return V_008F30_SQ_TEX_MIRROR;
1538         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1539                 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1540         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1541                 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1542         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1543                 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1544         }
1545 }
1546
1547 static unsigned si_tex_mipfilter(unsigned filter)
1548 {
1549         switch (filter) {
1550         case PIPE_TEX_MIPFILTER_NEAREST:
1551                 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1552         case PIPE_TEX_MIPFILTER_LINEAR:
1553                 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1554         default:
1555         case PIPE_TEX_MIPFILTER_NONE:
1556                 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1557         }
1558 }
1559
1560 static unsigned si_tex_compare(unsigned compare)
1561 {
1562         switch (compare) {
1563         default:
1564         case PIPE_FUNC_NEVER:
1565                 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1566         case PIPE_FUNC_LESS:
1567                 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1568         case PIPE_FUNC_EQUAL:
1569                 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1570         case PIPE_FUNC_LEQUAL:
1571                 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1572         case PIPE_FUNC_GREATER:
1573                 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1574         case PIPE_FUNC_NOTEQUAL:
1575                 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1576         case PIPE_FUNC_GEQUAL:
1577                 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1578         case PIPE_FUNC_ALWAYS:
1579                 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1580         }
1581 }
1582
1583 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1584                            unsigned nr_samples)
1585 {
1586         if (view_target == PIPE_TEXTURE_CUBE ||
1587             view_target == PIPE_TEXTURE_CUBE_ARRAY)
1588                 res_target = view_target;
1589
1590         switch (res_target) {
1591         default:
1592         case PIPE_TEXTURE_1D:
1593                 return V_008F1C_SQ_RSRC_IMG_1D;
1594         case PIPE_TEXTURE_1D_ARRAY:
1595                 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1596         case PIPE_TEXTURE_2D:
1597         case PIPE_TEXTURE_RECT:
1598                 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1599                                         V_008F1C_SQ_RSRC_IMG_2D;
1600         case PIPE_TEXTURE_2D_ARRAY:
1601                 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1602                                         V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1603         case PIPE_TEXTURE_3D:
1604                 return V_008F1C_SQ_RSRC_IMG_3D;
1605         case PIPE_TEXTURE_CUBE:
1606         case PIPE_TEXTURE_CUBE_ARRAY:
1607                 return V_008F1C_SQ_RSRC_IMG_CUBE;
1608         }
1609 }
1610
1611 /*
1612  * Format support testing
1613  */
1614
1615 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1616 {
1617         return si_translate_texformat(screen, format, util_format_description(format),
1618                                       util_format_get_first_non_void_channel(format)) != ~0U;
1619 }
1620
1621 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1622                                                const struct util_format_description *desc,
1623                                                int first_non_void)
1624 {
1625         unsigned type;
1626         int i;
1627
1628         if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1629                 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1630
1631         assert(first_non_void >= 0);
1632         type = desc->channel[first_non_void].type;
1633
1634         if (type == UTIL_FORMAT_TYPE_FIXED)
1635                 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1636
1637         if (desc->nr_channels == 4 &&
1638             desc->channel[0].size == 10 &&
1639             desc->channel[1].size == 10 &&
1640             desc->channel[2].size == 10 &&
1641             desc->channel[3].size == 2)
1642                 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1643
1644         /* See whether the components are of the same size. */
1645         for (i = 0; i < desc->nr_channels; i++) {
1646                 if (desc->channel[first_non_void].size != desc->channel[i].size)
1647                         return V_008F0C_BUF_DATA_FORMAT_INVALID;
1648         }
1649
1650         switch (desc->channel[first_non_void].size) {
1651         case 8:
1652                 switch (desc->nr_channels) {
1653                 case 1:
1654                         return V_008F0C_BUF_DATA_FORMAT_8;
1655                 case 2:
1656                         return V_008F0C_BUF_DATA_FORMAT_8_8;
1657                 case 3:
1658                 case 4:
1659                         return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1660                 }
1661                 break;
1662         case 16:
1663                 switch (desc->nr_channels) {
1664                 case 1:
1665                         return V_008F0C_BUF_DATA_FORMAT_16;
1666                 case 2:
1667                         return V_008F0C_BUF_DATA_FORMAT_16_16;
1668                 case 3:
1669                 case 4:
1670                         return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1671                 }
1672                 break;
1673         case 32:
1674                 /* From the Southern Islands ISA documentation about MTBUF:
1675                  * 'Memory reads of data in memory that is 32 or 64 bits do not
1676                  * undergo any format conversion.'
1677                  */
1678                 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1679                     !desc->channel[first_non_void].pure_integer)
1680                         return V_008F0C_BUF_DATA_FORMAT_INVALID;
1681
1682                 switch (desc->nr_channels) {
1683                 case 1:
1684                         return V_008F0C_BUF_DATA_FORMAT_32;
1685                 case 2:
1686                         return V_008F0C_BUF_DATA_FORMAT_32_32;
1687                 case 3:
1688                         return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1689                 case 4:
1690                         return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1691                 }
1692                 break;
1693         }
1694
1695         return V_008F0C_BUF_DATA_FORMAT_INVALID;
1696 }
1697
1698 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1699                                               const struct util_format_description *desc,
1700                                               int first_non_void)
1701 {
1702         if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1703                 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1704
1705         assert(first_non_void >= 0);
1706
1707         switch (desc->channel[first_non_void].type) {
1708         case UTIL_FORMAT_TYPE_SIGNED:
1709                 if (desc->channel[first_non_void].normalized)
1710                         return V_008F0C_BUF_NUM_FORMAT_SNORM;
1711                 else if (desc->channel[first_non_void].pure_integer)
1712                         return V_008F0C_BUF_NUM_FORMAT_SINT;
1713                 else
1714                         return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1715                 break;
1716         case UTIL_FORMAT_TYPE_UNSIGNED:
1717                 if (desc->channel[first_non_void].normalized)
1718                         return V_008F0C_BUF_NUM_FORMAT_UNORM;
1719                 else if (desc->channel[first_non_void].pure_integer)
1720                         return V_008F0C_BUF_NUM_FORMAT_UINT;
1721                 else
1722                         return V_008F0C_BUF_NUM_FORMAT_USCALED;
1723                 break;
1724         case UTIL_FORMAT_TYPE_FLOAT:
1725         default:
1726                 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1727         }
1728 }
1729
1730 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1731 {
1732         const struct util_format_description *desc;
1733         int first_non_void;
1734         unsigned data_format;
1735
1736         desc = util_format_description(format);
1737         first_non_void = util_format_get_first_non_void_channel(format);
1738         data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1739         return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1740 }
1741
1742 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1743 {
1744         return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1745                 r600_translate_colorswap(format, FALSE) != ~0U;
1746 }
1747
1748 static bool si_is_zs_format_supported(enum pipe_format format)
1749 {
1750         return si_translate_dbformat(format) != V_028040_Z_INVALID;
1751 }
1752
1753 boolean si_is_format_supported(struct pipe_screen *screen,
1754                                enum pipe_format format,
1755                                enum pipe_texture_target target,
1756                                unsigned sample_count,
1757                                unsigned usage)
1758 {
1759         unsigned retval = 0;
1760
1761         if (target >= PIPE_MAX_TEXTURE_TYPES) {
1762                 R600_ERR("r600: unsupported texture type %d\n", target);
1763                 return FALSE;
1764         }
1765
1766         if (!util_format_is_supported(format, usage))
1767                 return FALSE;
1768
1769         if (sample_count > 1) {
1770                 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1771                         return FALSE;
1772
1773                 switch (sample_count) {
1774                 case 2:
1775                 case 4:
1776                 case 8:
1777                         break;
1778                 case 16:
1779                         if (format == PIPE_FORMAT_NONE)
1780                                 return TRUE;
1781                         else
1782                                 return FALSE;
1783                 default:
1784                         return FALSE;
1785                 }
1786         }
1787
1788         if (usage & PIPE_BIND_SAMPLER_VIEW) {
1789                 if (target == PIPE_BUFFER) {
1790                         if (si_is_vertex_format_supported(screen, format))
1791                                 retval |= PIPE_BIND_SAMPLER_VIEW;
1792                 } else {
1793                         if (si_is_sampler_format_supported(screen, format))
1794                                 retval |= PIPE_BIND_SAMPLER_VIEW;
1795                 }
1796         }
1797
1798         if ((usage & (PIPE_BIND_RENDER_TARGET |
1799                       PIPE_BIND_DISPLAY_TARGET |
1800                       PIPE_BIND_SCANOUT |
1801                       PIPE_BIND_SHARED |
1802                       PIPE_BIND_BLENDABLE)) &&
1803             si_is_colorbuffer_format_supported(format)) {
1804                 retval |= usage &
1805                           (PIPE_BIND_RENDER_TARGET |
1806                            PIPE_BIND_DISPLAY_TARGET |
1807                            PIPE_BIND_SCANOUT |
1808                            PIPE_BIND_SHARED);
1809                 if (!util_format_is_pure_integer(format) &&
1810                     !util_format_is_depth_or_stencil(format))
1811                         retval |= usage & PIPE_BIND_BLENDABLE;
1812         }
1813
1814         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1815             si_is_zs_format_supported(format)) {
1816                 retval |= PIPE_BIND_DEPTH_STENCIL;
1817         }
1818
1819         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1820             si_is_vertex_format_supported(screen, format)) {
1821                 retval |= PIPE_BIND_VERTEX_BUFFER;
1822         }
1823
1824         if (usage & PIPE_BIND_TRANSFER_READ)
1825                 retval |= PIPE_BIND_TRANSFER_READ;
1826         if (usage & PIPE_BIND_TRANSFER_WRITE)
1827                 retval |= PIPE_BIND_TRANSFER_WRITE;
1828
1829         if ((usage & PIPE_BIND_LINEAR) &&
1830             !util_format_is_compressed(format) &&
1831             !(usage & PIPE_BIND_DEPTH_STENCIL))
1832                 retval |= PIPE_BIND_LINEAR;
1833
1834         return retval == usage;
1835 }
1836
1837 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level,
1838                                    bool stencil)
1839 {
1840         unsigned tile_mode_index = 0;
1841
1842         if (stencil) {
1843                 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1844         } else {
1845                 tile_mode_index = rtex->surface.tiling_index[level];
1846         }
1847         return tile_mode_index;
1848 }
1849
1850 /*
1851  * framebuffer handling
1852  */
1853
1854 static void si_choose_spi_color_formats(struct r600_surface *surf,
1855                                         unsigned format, unsigned swap,
1856                                         unsigned ntype, bool is_depth)
1857 {
1858         /* Alpha is needed for alpha-to-coverage.
1859          * Blending may be with or without alpha.
1860          */
1861         unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1862         unsigned alpha = 0; /* exports alpha, but may not support blending */
1863         unsigned blend = 0; /* supports blending, but may not export alpha */
1864         unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1865
1866         /* Choose the SPI color formats. These are required values for Stoney/RB+.
1867          * Other chips have multiple choices, though they are not necessarily better.
1868          */
1869         switch (format) {
1870         case V_028C70_COLOR_5_6_5:
1871         case V_028C70_COLOR_1_5_5_5:
1872         case V_028C70_COLOR_5_5_5_1:
1873         case V_028C70_COLOR_4_4_4_4:
1874         case V_028C70_COLOR_10_11_11:
1875         case V_028C70_COLOR_11_11_10:
1876         case V_028C70_COLOR_8:
1877         case V_028C70_COLOR_8_8:
1878         case V_028C70_COLOR_8_8_8_8:
1879         case V_028C70_COLOR_10_10_10_2:
1880         case V_028C70_COLOR_2_10_10_10:
1881                 if (ntype == V_028C70_NUMBER_UINT)
1882                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1883                 else if (ntype == V_028C70_NUMBER_SINT)
1884                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1885                 else
1886                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1887                 break;
1888
1889         case V_028C70_COLOR_16:
1890         case V_028C70_COLOR_16_16:
1891         case V_028C70_COLOR_16_16_16_16:
1892                 if (ntype == V_028C70_NUMBER_UNORM ||
1893                     ntype == V_028C70_NUMBER_SNORM) {
1894                         /* UNORM16 and SNORM16 don't support blending */
1895                         if (ntype == V_028C70_NUMBER_UNORM)
1896                                 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1897                         else
1898                                 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1899
1900                         /* Use 32 bits per channel for blending. */
1901                         if (format == V_028C70_COLOR_16) {
1902                                 if (swap == V_028C70_SWAP_STD) { /* R */
1903                                         blend = V_028714_SPI_SHADER_32_R;
1904                                         blend_alpha = V_028714_SPI_SHADER_32_AR;
1905                                 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1906                                         blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1907                                 else
1908                                         assert(0);
1909                         } else if (format == V_028C70_COLOR_16_16) {
1910                                 if (swap == V_028C70_SWAP_STD) { /* RG */
1911                                         blend = V_028714_SPI_SHADER_32_GR;
1912                                         blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1913                                 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1914                                         blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1915                                 else
1916                                         assert(0);
1917                         } else /* 16_16_16_16 */
1918                                 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1919                 } else if (ntype == V_028C70_NUMBER_UINT)
1920                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1921                 else if (ntype == V_028C70_NUMBER_SINT)
1922                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1923                 else if (ntype == V_028C70_NUMBER_FLOAT)
1924                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1925                 else
1926                         assert(0);
1927                 break;
1928
1929         case V_028C70_COLOR_32:
1930                 if (swap == V_028C70_SWAP_STD) { /* R */
1931                         blend = normal = V_028714_SPI_SHADER_32_R;
1932                         alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1933                 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1934                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1935                 else
1936                         assert(0);
1937                 break;
1938
1939         case V_028C70_COLOR_32_32:
1940                 if (swap == V_028C70_SWAP_STD) { /* RG */
1941                         blend = normal = V_028714_SPI_SHADER_32_GR;
1942                         alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1943                 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1944                         alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1945                 else
1946                         assert(0);
1947                 break;
1948
1949         case V_028C70_COLOR_32_32_32_32:
1950         case V_028C70_COLOR_8_24:
1951         case V_028C70_COLOR_24_8:
1952         case V_028C70_COLOR_X24_8_32_FLOAT:
1953                 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1954                 break;
1955
1956         default:
1957                 assert(0);
1958                 return;
1959         }
1960
1961         /* The DB->CB copy needs 32_ABGR. */
1962         if (is_depth)
1963                 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1964
1965         surf->spi_shader_col_format = normal;
1966         surf->spi_shader_col_format_alpha = alpha;
1967         surf->spi_shader_col_format_blend = blend;
1968         surf->spi_shader_col_format_blend_alpha = blend_alpha;
1969 }
1970
1971 static void si_initialize_color_surface(struct si_context *sctx,
1972                                         struct r600_surface *surf)
1973 {
1974         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1975         unsigned level = surf->base.u.tex.level;
1976         uint64_t offset = rtex->surface.level[level].offset;
1977         unsigned pitch, slice;
1978         unsigned color_info, color_attrib, color_pitch, color_view;
1979         unsigned tile_mode_index;
1980         unsigned format, swap, ntype, endian;
1981         const struct util_format_description *desc;
1982         int i;
1983         unsigned blend_clamp = 0, blend_bypass = 0;
1984
1985         color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1986                      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1987
1988         pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1989         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1990         if (slice) {
1991                 slice = slice - 1;
1992         }
1993
1994         tile_mode_index = si_tile_mode_index(rtex, level, false);
1995
1996         desc = util_format_description(surf->base.format);
1997         for (i = 0; i < 4; i++) {
1998                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1999                         break;
2000                 }
2001         }
2002         if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2003                 ntype = V_028C70_NUMBER_FLOAT;
2004         } else {
2005                 ntype = V_028C70_NUMBER_UNORM;
2006                 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2007                         ntype = V_028C70_NUMBER_SRGB;
2008                 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2009                         if (desc->channel[i].pure_integer) {
2010                                 ntype = V_028C70_NUMBER_SINT;
2011                         } else {
2012                                 assert(desc->channel[i].normalized);
2013                                 ntype = V_028C70_NUMBER_SNORM;
2014                         }
2015                 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2016                         if (desc->channel[i].pure_integer) {
2017                                 ntype = V_028C70_NUMBER_UINT;
2018                         } else {
2019                                 assert(desc->channel[i].normalized);
2020                                 ntype = V_028C70_NUMBER_UNORM;
2021                         }
2022                 }
2023         }
2024
2025         format = si_translate_colorformat(surf->base.format);
2026         if (format == V_028C70_COLOR_INVALID) {
2027                 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2028         }
2029         assert(format != V_028C70_COLOR_INVALID);
2030         swap = r600_translate_colorswap(surf->base.format, FALSE);
2031         endian = si_colorformat_endian_swap(format);
2032
2033         /* blend clamp should be set for all NORM/SRGB types */
2034         if (ntype == V_028C70_NUMBER_UNORM ||
2035             ntype == V_028C70_NUMBER_SNORM ||
2036             ntype == V_028C70_NUMBER_SRGB)
2037                 blend_clamp = 1;
2038
2039         /* set blend bypass according to docs if SINT/UINT or
2040            8/24 COLOR variants */
2041         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2042             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2043             format == V_028C70_COLOR_X24_8_32_FLOAT) {
2044                 blend_clamp = 0;
2045                 blend_bypass = 1;
2046         }
2047
2048         if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2049             (format == V_028C70_COLOR_8 ||
2050              format == V_028C70_COLOR_8_8 ||
2051              format == V_028C70_COLOR_8_8_8_8))
2052                 surf->color_is_int8 = true;
2053
2054         color_info = S_028C70_FORMAT(format) |
2055                 S_028C70_COMP_SWAP(swap) |
2056                 S_028C70_BLEND_CLAMP(blend_clamp) |
2057                 S_028C70_BLEND_BYPASS(blend_bypass) |
2058                 S_028C70_NUMBER_TYPE(ntype) |
2059                 S_028C70_ENDIAN(endian);
2060
2061         color_pitch = S_028C64_TILE_MAX(pitch);
2062
2063         /* Intensity is implemented as Red, so treat it that way. */
2064         color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2065                 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2066                                            util_format_is_intensity(surf->base.format));
2067
2068         if (rtex->resource.b.b.nr_samples > 1) {
2069                 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2070
2071                 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2072                                 S_028C74_NUM_FRAGMENTS(log_samples);
2073
2074                 if (rtex->fmask.size) {
2075                         color_info |= S_028C70_COMPRESSION(1);
2076                         unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2077
2078                         color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2079
2080                         if (sctx->b.chip_class == SI) {
2081                                 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2082                                 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2083                         }
2084                         if (sctx->b.chip_class >= CIK) {
2085                                 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2086                         }
2087                 }
2088         }
2089
2090         offset += rtex->resource.gpu_address;
2091
2092         surf->cb_color_base = offset >> 8;
2093         surf->cb_color_pitch = color_pitch;
2094         surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2095         surf->cb_color_view = color_view;
2096         surf->cb_color_info = color_info;
2097         surf->cb_color_attrib = color_attrib;
2098
2099         if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2100                 unsigned max_uncompressed_block_size = 2;
2101
2102                 if (rtex->surface.nsamples > 1) {
2103                         if (rtex->surface.bpe == 1)
2104                                 max_uncompressed_block_size = 0;
2105                         else if (rtex->surface.bpe == 2)
2106                                 max_uncompressed_block_size = 1;
2107                 }
2108
2109                 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2110                                        S_028C78_INDEPENDENT_64B_BLOCKS(1);
2111                 surf->cb_dcc_base = (rtex->resource.gpu_address +
2112                                      rtex->dcc_offset +
2113                                      rtex->surface.level[level].dcc_offset) >> 8;
2114         }
2115
2116         if (rtex->fmask.size) {
2117                 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2118                 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2119         } else {
2120                 /* This must be set for fast clear to work without FMASK. */
2121                 surf->cb_color_fmask = surf->cb_color_base;
2122                 surf->cb_color_fmask_slice = surf->cb_color_slice;
2123                 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2124
2125                 if (sctx->b.chip_class == SI) {
2126                         unsigned bankh = util_logbase2(rtex->surface.bankh);
2127                         surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2128                 }
2129
2130                 if (sctx->b.chip_class >= CIK) {
2131                         surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2132                 }
2133         }
2134
2135         /* Determine pixel shader export format */
2136         si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2137
2138         surf->color_initialized = true;
2139 }
2140
2141 static void si_init_depth_surface(struct si_context *sctx,
2142                                   struct r600_surface *surf)
2143 {
2144         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2145         unsigned level = surf->base.u.tex.level;
2146         struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2147         unsigned format;
2148         uint32_t z_info, s_info, db_depth_info;
2149         uint64_t z_offs, s_offs;
2150         uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2151
2152         switch (sctx->framebuffer.state.zsbuf->texture->format) {
2153         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2154         case PIPE_FORMAT_X8Z24_UNORM:
2155         case PIPE_FORMAT_Z24X8_UNORM:
2156         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2157                 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2158                 break;
2159         case PIPE_FORMAT_Z32_FLOAT:
2160         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2161                 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2162                                                 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2163                 break;
2164         case PIPE_FORMAT_Z16_UNORM:
2165                 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2166                 break;
2167         default:
2168                 assert(0);
2169         }
2170
2171         format = si_translate_dbformat(rtex->resource.b.b.format);
2172
2173         if (format == V_028040_Z_INVALID) {
2174                 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2175         }
2176         assert(format != V_028040_Z_INVALID);
2177
2178         s_offs = z_offs = rtex->resource.gpu_address;
2179         z_offs += rtex->surface.level[level].offset;
2180         s_offs += rtex->surface.stencil_level[level].offset;
2181
2182         db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2183
2184         z_info = S_028040_FORMAT(format);
2185         if (rtex->resource.b.b.nr_samples > 1) {
2186                 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2187         }
2188
2189         if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2190                 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2191         else
2192                 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2193
2194         if (sctx->b.chip_class >= CIK) {
2195                 struct radeon_info *info = &sctx->screen->b.info;
2196                 unsigned index = rtex->surface.tiling_index[level];
2197                 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2198                 unsigned macro_index = rtex->surface.macro_tile_index;
2199                 unsigned tile_mode = info->si_tile_mode_array[index];
2200                 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2201                 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2202
2203                 db_depth_info |=
2204                         S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2205                         S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2206                         S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2207                         S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2208                         S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2209                         S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2210                 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2211                 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2212         } else {
2213                 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2214                 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2215                 tile_mode_index = si_tile_mode_index(rtex, level, true);
2216                 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2217         }
2218
2219         /* HiZ aka depth buffer htile */
2220         /* use htile only for first level */
2221         if (rtex->htile_buffer && !level) {
2222                 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2223                           S_028040_ALLOW_EXPCLEAR(1);
2224
2225                 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2226                         /* Workaround: For a not yet understood reason, the
2227                          * combination of MSAA, fast stencil clear and stencil
2228                          * decompress messes with subsequent stencil buffer
2229                          * uses. Problem was reproduced on Verde, Bonaire,
2230                          * Tonga, and Carrizo.
2231                          *
2232                          * Disabling EXPCLEAR works around the problem.
2233                          *
2234                          * Check piglit's arb_texture_multisample-stencil-clear
2235                          * test if you want to try changing this.
2236                          */
2237                         if (rtex->resource.b.b.nr_samples <= 1)
2238                                 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2239                 } else
2240                         /* Use all of the htile_buffer for depth if there's no stencil. */
2241                         s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2242
2243                 uint64_t va = rtex->htile_buffer->gpu_address;
2244                 db_htile_data_base = va >> 8;
2245                 db_htile_surface = S_028ABC_FULL_CACHE(1);
2246         } else {
2247                 db_htile_data_base = 0;
2248                 db_htile_surface = 0;
2249         }
2250
2251         assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2252
2253         surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2254                               S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2255         surf->db_htile_data_base = db_htile_data_base;
2256         surf->db_depth_info = db_depth_info;
2257         surf->db_z_info = z_info;
2258         surf->db_stencil_info = s_info;
2259         surf->db_depth_base = z_offs >> 8;
2260         surf->db_stencil_base = s_offs >> 8;
2261         surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2262                               S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2263         surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2264                                                         levelinfo->nblk_y) / 64 - 1);
2265         surf->db_htile_surface = db_htile_surface;
2266         surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2267
2268         surf->depth_initialized = true;
2269 }
2270
2271 static void si_set_framebuffer_state(struct pipe_context *ctx,
2272                                      const struct pipe_framebuffer_state *state)
2273 {
2274         struct si_context *sctx = (struct si_context *)ctx;
2275         struct pipe_constant_buffer constbuf = {0};
2276         struct r600_surface *surf = NULL;
2277         struct r600_texture *rtex;
2278         bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2279         unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2280         int i;
2281
2282         /* Only flush TC when changing the framebuffer state, because
2283          * the only client not using TC that can change textures is
2284          * the framebuffer.
2285          *
2286          * Flush all CB and DB caches here because all buffers can be used
2287          * for write by both TC (with shader image stores) and CB/DB.
2288          */
2289         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2290                          SI_CONTEXT_INV_GLOBAL_L2 |
2291                          SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2292                          SI_CONTEXT_CS_PARTIAL_FLUSH;
2293
2294         /* Take the maximum of the old and new count. If the new count is lower,
2295          * dirtying is needed to disable the unbound colorbuffers.
2296          */
2297         sctx->framebuffer.dirty_cbufs |=
2298                 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2299         sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2300
2301         util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2302
2303         sctx->framebuffer.spi_shader_col_format = 0;
2304         sctx->framebuffer.spi_shader_col_format_alpha = 0;
2305         sctx->framebuffer.spi_shader_col_format_blend = 0;
2306         sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2307         sctx->framebuffer.color_is_int8 = 0;
2308
2309         sctx->framebuffer.compressed_cb_mask = 0;
2310         sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2311         sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2312         sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2313                                   util_format_is_pure_integer(state->cbufs[0]->format);
2314
2315         if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2316                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2317
2318         for (i = 0; i < state->nr_cbufs; i++) {
2319                 if (!state->cbufs[i])
2320                         continue;
2321
2322                 surf = (struct r600_surface*)state->cbufs[i];
2323                 rtex = (struct r600_texture*)surf->base.texture;
2324
2325                 if (!surf->color_initialized) {
2326                         si_initialize_color_surface(sctx, surf);
2327                 }
2328
2329                 sctx->framebuffer.spi_shader_col_format |=
2330                         surf->spi_shader_col_format << (i * 4);
2331                 sctx->framebuffer.spi_shader_col_format_alpha |=
2332                         surf->spi_shader_col_format_alpha << (i * 4);
2333                 sctx->framebuffer.spi_shader_col_format_blend |=
2334                         surf->spi_shader_col_format_blend << (i * 4);
2335                 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2336                         surf->spi_shader_col_format_blend_alpha << (i * 4);
2337
2338                 if (surf->color_is_int8)
2339                         sctx->framebuffer.color_is_int8 |= 1 << i;
2340
2341                 if (rtex->fmask.size && rtex->cmask.size) {
2342                         sctx->framebuffer.compressed_cb_mask |= 1 << i;
2343                 }
2344                 r600_context_add_resource_size(ctx, surf->base.texture);
2345         }
2346         /* Set the second SPI format for possible dual-src blending. */
2347         if (i == 1 && surf) {
2348                 sctx->framebuffer.spi_shader_col_format |=
2349                         surf->spi_shader_col_format << (i * 4);
2350                 sctx->framebuffer.spi_shader_col_format_alpha |=
2351                         surf->spi_shader_col_format_alpha << (i * 4);
2352                 sctx->framebuffer.spi_shader_col_format_blend |=
2353                         surf->spi_shader_col_format_blend << (i * 4);
2354                 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2355                         surf->spi_shader_col_format_blend_alpha << (i * 4);
2356         }
2357
2358         if (state->zsbuf) {
2359                 surf = (struct r600_surface*)state->zsbuf;
2360
2361                 if (!surf->depth_initialized) {
2362                         si_init_depth_surface(sctx, surf);
2363                 }
2364                 r600_context_add_resource_size(ctx, surf->base.texture);
2365         }
2366
2367         si_update_poly_offset_state(sctx);
2368         si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2369         si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2370
2371         if (sctx->framebuffer.nr_samples != old_nr_samples) {
2372                 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2373                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2374
2375                 /* Set sample locations as fragment shader constants. */
2376                 switch (sctx->framebuffer.nr_samples) {
2377                 case 1:
2378                         constbuf.user_buffer = sctx->b.sample_locations_1x;
2379                         break;
2380                 case 2:
2381                         constbuf.user_buffer = sctx->b.sample_locations_2x;
2382                         break;
2383                 case 4:
2384                         constbuf.user_buffer = sctx->b.sample_locations_4x;
2385                         break;
2386                 case 8:
2387                         constbuf.user_buffer = sctx->b.sample_locations_8x;
2388                         break;
2389                 case 16:
2390                         constbuf.user_buffer = sctx->b.sample_locations_16x;
2391                         break;
2392                 default:
2393                         R600_ERR("Requested an invalid number of samples %i.\n",
2394                                  sctx->framebuffer.nr_samples);
2395                         assert(0);
2396                 }
2397                 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2398                 si_set_constant_buffer(sctx, &sctx->rw_buffers,
2399                                        SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2400
2401                 /* Smoothing (only possible with nr_samples == 1) uses the same
2402                  * sample locations as the MSAA it simulates.
2403                  *
2404                  * Therefore, don't update the sample locations when
2405                  * transitioning from no AA to smoothing-equivalent AA, and
2406                  * vice versa.
2407                  */
2408                 if ((sctx->framebuffer.nr_samples != 1 ||
2409                      old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2410                     (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2411                      old_nr_samples != 1))
2412                         si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2413         }
2414 }
2415
2416 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2417 {
2418         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2419         struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2420         unsigned i, nr_cbufs = state->nr_cbufs;
2421         struct r600_texture *tex = NULL;
2422         struct r600_surface *cb = NULL;
2423
2424         /* Colorbuffers. */
2425         for (i = 0; i < nr_cbufs; i++) {
2426                 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2427                         continue;
2428
2429                 cb = (struct r600_surface*)state->cbufs[i];
2430                 if (!cb) {
2431                         radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2432                                                S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2433                         continue;
2434                 }
2435
2436                 tex = (struct r600_texture *)cb->base.texture;
2437                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2438                                       &tex->resource, RADEON_USAGE_READWRITE,
2439                                       tex->surface.nsamples > 1 ?
2440                                               RADEON_PRIO_COLOR_BUFFER_MSAA :
2441                                               RADEON_PRIO_COLOR_BUFFER);
2442
2443                 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2444                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2445                                 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2446                                 RADEON_PRIO_CMASK);
2447                 }
2448
2449                 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2450                                            sctx->b.chip_class >= VI ? 14 : 13);
2451                 radeon_emit(cs, cb->cb_color_base);     /* R_028C60_CB_COLOR0_BASE */
2452                 radeon_emit(cs, cb->cb_color_pitch);    /* R_028C64_CB_COLOR0_PITCH */
2453                 radeon_emit(cs, cb->cb_color_slice);    /* R_028C68_CB_COLOR0_SLICE */
2454                 radeon_emit(cs, cb->cb_color_view);     /* R_028C6C_CB_COLOR0_VIEW */
2455                 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2456                 radeon_emit(cs, cb->cb_color_attrib);   /* R_028C74_CB_COLOR0_ATTRIB */
2457                 radeon_emit(cs, cb->cb_dcc_control);    /* R_028C78_CB_COLOR0_DCC_CONTROL */
2458                 radeon_emit(cs, tex->cmask.base_address_reg);   /* R_028C7C_CB_COLOR0_CMASK */
2459                 radeon_emit(cs, tex->cmask.slice_tile_max);     /* R_028C80_CB_COLOR0_CMASK_SLICE */
2460                 radeon_emit(cs, cb->cb_color_fmask);            /* R_028C84_CB_COLOR0_FMASK */
2461                 radeon_emit(cs, cb->cb_color_fmask_slice);      /* R_028C88_CB_COLOR0_FMASK_SLICE */
2462                 radeon_emit(cs, tex->color_clear_value[0]);     /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2463                 radeon_emit(cs, tex->color_clear_value[1]);     /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2464
2465                 if (sctx->b.chip_class >= VI)
2466                         radeon_emit(cs, cb->cb_dcc_base);       /* R_028C94_CB_COLOR0_DCC_BASE */
2467         }
2468         /* set CB_COLOR1_INFO for possible dual-src blending */
2469         if (i == 1 && state->cbufs[0] &&
2470             sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2471                 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2472                                        cb->cb_color_info | tex->cb_color_info);
2473                 i++;
2474         }
2475         for (; i < 8 ; i++)
2476                 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2477                         radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2478
2479         /* ZS buffer. */
2480         if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2481                 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2482                 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2483
2484                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2485                                       &rtex->resource, RADEON_USAGE_READWRITE,
2486                                       zb->base.texture->nr_samples > 1 ?
2487                                               RADEON_PRIO_DEPTH_BUFFER_MSAA :
2488                                               RADEON_PRIO_DEPTH_BUFFER);
2489
2490                 if (zb->db_htile_data_base) {
2491                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2492                                               rtex->htile_buffer, RADEON_USAGE_READWRITE,
2493                                               RADEON_PRIO_HTILE);
2494                 }
2495
2496                 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2497                 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2498
2499                 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2500                 radeon_emit(cs, zb->db_depth_info);     /* R_02803C_DB_DEPTH_INFO */
2501                 radeon_emit(cs, zb->db_z_info |         /* R_028040_DB_Z_INFO */
2502                             S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2503                 radeon_emit(cs, zb->db_stencil_info);   /* R_028044_DB_STENCIL_INFO */
2504                 radeon_emit(cs, zb->db_depth_base);     /* R_028048_DB_Z_READ_BASE */
2505                 radeon_emit(cs, zb->db_stencil_base);   /* R_02804C_DB_STENCIL_READ_BASE */
2506                 radeon_emit(cs, zb->db_depth_base);     /* R_028050_DB_Z_WRITE_BASE */
2507                 radeon_emit(cs, zb->db_stencil_base);   /* R_028054_DB_STENCIL_WRITE_BASE */
2508                 radeon_emit(cs, zb->db_depth_size);     /* R_028058_DB_DEPTH_SIZE */
2509                 radeon_emit(cs, zb->db_depth_slice);    /* R_02805C_DB_DEPTH_SLICE */
2510
2511                 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2512                 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2513                 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2514
2515                 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2516                 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2517                                        zb->pa_su_poly_offset_db_fmt_cntl);
2518         } else if (sctx->framebuffer.dirty_zsbuf) {
2519                 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2520                 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2521                 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2522         }
2523
2524         /* Framebuffer dimensions. */
2525         /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2526         radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2527                                S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2528
2529         sctx->framebuffer.dirty_cbufs = 0;
2530         sctx->framebuffer.dirty_zsbuf = false;
2531 }
2532
2533 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2534                                      struct r600_atom *atom)
2535 {
2536         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2537         unsigned nr_samples = sctx->framebuffer.nr_samples;
2538
2539         cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2540                                                 SI_NUM_SMOOTH_AA_SAMPLES);
2541 }
2542
2543 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2544 {
2545         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2546
2547         cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2548                                 sctx->ps_iter_samples,
2549                                 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2550 }
2551
2552
2553 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2554 {
2555         struct si_context *sctx = (struct si_context *)ctx;
2556
2557         if (sctx->ps_iter_samples == min_samples)
2558                 return;
2559
2560         sctx->ps_iter_samples = min_samples;
2561
2562         if (sctx->framebuffer.nr_samples > 1)
2563                 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2564 }
2565
2566 /*
2567  * Samplers
2568  */
2569
2570 /**
2571  * Build the sampler view descriptor for a buffer texture.
2572  * @param state 256-bit descriptor; only the high 128 bits are filled in
2573  */
2574 void
2575 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2576                           enum pipe_format format,
2577                           unsigned first_element, unsigned last_element,
2578                           uint32_t *state)
2579 {
2580         const struct util_format_description *desc;
2581         int first_non_void;
2582         uint64_t va;
2583         unsigned stride;
2584         unsigned num_records;
2585         unsigned num_format, data_format;
2586
2587         desc = util_format_description(format);
2588         first_non_void = util_format_get_first_non_void_channel(format);
2589         stride = desc->block.bits / 8;
2590         va = buf->gpu_address + first_element * stride;
2591         num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2592         data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2593
2594         num_records = last_element + 1 - first_element;
2595         num_records = MIN2(num_records, buf->b.b.width0 / stride);
2596
2597         if (screen->b.chip_class >= VI)
2598                 num_records *= stride;
2599
2600         state[4] = va;
2601         state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2602                    S_008F04_STRIDE(stride);
2603         state[6] = num_records;
2604         state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2605                    S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2606                    S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2607                    S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2608                    S_008F0C_NUM_FORMAT(num_format) |
2609                    S_008F0C_DATA_FORMAT(data_format);
2610 }
2611
2612 /**
2613  * Build the sampler view descriptor for a texture.
2614  */
2615 void
2616 si_make_texture_descriptor(struct si_screen *screen,
2617                            struct r600_texture *tex,
2618                            bool sampler,
2619                            enum pipe_texture_target target,
2620                            enum pipe_format pipe_format,
2621                            const unsigned char state_swizzle[4],
2622                            unsigned base_level, unsigned first_level, unsigned last_level,
2623                            unsigned first_layer, unsigned last_layer,
2624                            unsigned width, unsigned height, unsigned depth,
2625                            uint32_t *state,
2626                            uint32_t *fmask_state)
2627 {
2628         struct pipe_resource *res = &tex->resource.b.b;
2629         const struct radeon_surf_level *surflevel = tex->surface.level;
2630         const struct util_format_description *desc;
2631         unsigned char swizzle[4];
2632         int first_non_void;
2633         unsigned num_format, data_format, type;
2634         uint32_t pitch;
2635         uint64_t va;
2636
2637         /* Texturing with separate depth and stencil. */
2638         if (tex->is_depth && !tex->is_flushing_texture) {
2639                 switch (pipe_format) {
2640                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2641                         pipe_format = PIPE_FORMAT_Z32_FLOAT;
2642                         break;
2643                 case PIPE_FORMAT_X8Z24_UNORM:
2644                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2645                         /* Z24 is always stored like this. */
2646                         pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2647                         break;
2648                 case PIPE_FORMAT_X24S8_UINT:
2649                 case PIPE_FORMAT_S8X24_UINT:
2650                 case PIPE_FORMAT_X32_S8X24_UINT:
2651                         pipe_format = PIPE_FORMAT_S8_UINT;
2652                         surflevel = tex->surface.stencil_level;
2653                         break;
2654                 default:;
2655                 }
2656         }
2657
2658         desc = util_format_description(pipe_format);
2659
2660         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2661                 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2662                 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2663
2664                 switch (pipe_format) {
2665                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2666                 case PIPE_FORMAT_X24S8_UINT:
2667                 case PIPE_FORMAT_X32_S8X24_UINT:
2668                 case PIPE_FORMAT_X8Z24_UNORM:
2669                         util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2670                         break;
2671                 default:
2672                         util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2673                 }
2674         } else {
2675                 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2676         }
2677
2678         first_non_void = util_format_get_first_non_void_channel(pipe_format);
2679
2680         switch (pipe_format) {
2681         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2682                 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2683                 break;
2684         default:
2685                 if (first_non_void < 0) {
2686                         if (util_format_is_compressed(pipe_format)) {
2687                                 switch (pipe_format) {
2688                                 case PIPE_FORMAT_DXT1_SRGB:
2689                                 case PIPE_FORMAT_DXT1_SRGBA:
2690                                 case PIPE_FORMAT_DXT3_SRGBA:
2691                                 case PIPE_FORMAT_DXT5_SRGBA:
2692                                 case PIPE_FORMAT_BPTC_SRGBA:
2693                                 case PIPE_FORMAT_ETC2_SRGB8:
2694                                 case PIPE_FORMAT_ETC2_SRGB8A1:
2695                                 case PIPE_FORMAT_ETC2_SRGBA8:
2696                                         num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2697                                         break;
2698                                 case PIPE_FORMAT_RGTC1_SNORM:
2699                                 case PIPE_FORMAT_LATC1_SNORM:
2700                                 case PIPE_FORMAT_RGTC2_SNORM:
2701                                 case PIPE_FORMAT_LATC2_SNORM:
2702                                 case PIPE_FORMAT_ETC2_R11_SNORM:
2703                                 case PIPE_FORMAT_ETC2_RG11_SNORM:
2704                                 /* implies float, so use SNORM/UNORM to determine
2705                                    whether data is signed or not */
2706                                 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2707                                         num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2708                                         break;
2709                                 default:
2710                                         num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2711                                         break;
2712                                 }
2713                         } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2714                                 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2715                         } else {
2716                                 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2717                         }
2718                 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2719                         num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2720                 } else {
2721                         num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2722
2723                         switch (desc->channel[first_non_void].type) {
2724                         case UTIL_FORMAT_TYPE_FLOAT:
2725                                 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2726                                 break;
2727                         case UTIL_FORMAT_TYPE_SIGNED:
2728                                 if (desc->channel[first_non_void].normalized)
2729                                         num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2730                                 else if (desc->channel[first_non_void].pure_integer)
2731                                         num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2732                                 else
2733                                         num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2734                                 break;
2735                         case UTIL_FORMAT_TYPE_UNSIGNED:
2736                                 if (desc->channel[first_non_void].normalized)
2737                                         num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2738                                 else if (desc->channel[first_non_void].pure_integer)
2739                                         num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2740                                 else
2741                                         num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2742                         }
2743                 }
2744         }
2745
2746         data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2747         if (data_format == ~0) {
2748                 data_format = 0;
2749         }
2750
2751         if (!sampler &&
2752             (res->target == PIPE_TEXTURE_CUBE ||
2753              res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2754              res->target == PIPE_TEXTURE_3D)) {
2755                 /* For the purpose of shader images, treat cube maps and 3D
2756                  * textures as 2D arrays. For 3D textures, the address
2757                  * calculations for mipmaps are different, so we rely on the
2758                  * caller to effectively disable mipmaps.
2759                  */
2760                 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2761
2762                 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2763         } else {
2764                 type = si_tex_dim(res->target, target, res->nr_samples);
2765         }
2766
2767         if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2768                 height = 1;
2769                 depth = res->array_size;
2770         } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2771                    type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2772                 if (sampler || res->target != PIPE_TEXTURE_3D)
2773                         depth = res->array_size;
2774         } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2775                 depth = res->array_size / 6;
2776
2777         pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2778         va = tex->resource.gpu_address + surflevel[base_level].offset;
2779
2780         state[0] = va >> 8;
2781         state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2782                     S_008F14_DATA_FORMAT(data_format) |
2783                     S_008F14_NUM_FORMAT(num_format));
2784         state[2] = (S_008F18_WIDTH(width - 1) |
2785                     S_008F18_HEIGHT(height - 1));
2786         state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2787                     S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2788                     S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2789                     S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2790                     S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2791                                         0 : first_level) |
2792                     S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2793                                         util_logbase2(res->nr_samples) :
2794                                         last_level) |
2795                     S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
2796                     S_008F1C_POW2_PAD(res->last_level > 0) |
2797                     S_008F1C_TYPE(type));
2798         state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2799         state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2800                     S_008F24_LAST_ARRAY(last_layer));
2801
2802         if (tex->dcc_offset) {
2803                 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2804
2805                 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2806                 state[7] = (tex->resource.gpu_address +
2807                             tex->dcc_offset +
2808                             surflevel[base_level].dcc_offset) >> 8;
2809         } else {
2810                 state[6] = 0;
2811                 state[7] = 0;
2812
2813                 /* The last dword is unused by hw. The shader uses it to clear
2814                  * bits in the first dword of sampler state.
2815                  */
2816                 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2817                         if (first_level == last_level)
2818                                 state[7] = C_008F30_MAX_ANISO_RATIO;
2819                         else
2820                                 state[7] = 0xffffffff;
2821                 }
2822         }
2823
2824         /* Initialize the sampler view for FMASK. */
2825         if (tex->fmask.size) {
2826                 uint32_t fmask_format;
2827
2828                 va = tex->resource.gpu_address + tex->fmask.offset;
2829
2830                 switch (res->nr_samples) {
2831                 case 2:
2832                         fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2833                         break;
2834                 case 4:
2835                         fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2836                         break;
2837                 case 8:
2838                         fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2839                         break;
2840                 default:
2841                         assert(0);
2842                         fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2843                 }
2844
2845                 fmask_state[0] = va >> 8;
2846                 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2847                                  S_008F14_DATA_FORMAT(fmask_format) |
2848                                  S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2849                 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2850                                  S_008F18_HEIGHT(height - 1);
2851                 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2852                                  S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2853                                  S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2854                                  S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2855                                  S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2856                                  S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2857                 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2858                                  S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2859                 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2860                                  S_008F24_LAST_ARRAY(last_layer);
2861                 fmask_state[6] = 0;
2862                 fmask_state[7] = 0;
2863         }
2864 }
2865
2866 /**
2867  * Create a sampler view.
2868  *
2869  * @param ctx           context
2870  * @param texture       texture
2871  * @param state         sampler view template
2872  * @param width0        width0 override (for compressed textures as int)
2873  * @param height0       height0 override (for compressed textures as int)
2874  * @param force_level   set the base address to the level (for compressed textures)
2875  */
2876 struct pipe_sampler_view *
2877 si_create_sampler_view_custom(struct pipe_context *ctx,
2878                               struct pipe_resource *texture,
2879                               const struct pipe_sampler_view *state,
2880                               unsigned width0, unsigned height0,
2881                               unsigned force_level)
2882 {
2883         struct si_context *sctx = (struct si_context*)ctx;
2884         struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2885         struct r600_texture *tmp = (struct r600_texture*)texture;
2886         unsigned base_level, first_level, last_level;
2887         unsigned char state_swizzle[4];
2888         unsigned height, depth, width;
2889         unsigned last_layer = state->u.tex.last_layer;
2890
2891         if (!view)
2892                 return NULL;
2893
2894         /* initialize base object */
2895         view->base = *state;
2896         view->base.texture = NULL;
2897         view->base.reference.count = 1;
2898         view->base.context = ctx;
2899
2900         /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2901         if (!texture) {
2902                 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2903                                  S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2904                                  S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2905                                  S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2906                                  S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2907                 return &view->base;
2908         }
2909
2910         pipe_resource_reference(&view->base.texture, texture);
2911
2912         if (state->format == PIPE_FORMAT_X24S8_UINT ||
2913             state->format == PIPE_FORMAT_S8X24_UINT ||
2914             state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2915             state->format == PIPE_FORMAT_S8_UINT)
2916                 view->is_stencil_sampler = true;
2917
2918         /* Buffer resource. */
2919         if (texture->target == PIPE_BUFFER) {
2920                 si_make_buffer_descriptor(sctx->screen,
2921                                           (struct r600_resource *)texture,
2922                                           state->format,
2923                                           state->u.buf.first_element,
2924                                           state->u.buf.last_element,
2925                                           view->state);
2926
2927                 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2928                 return &view->base;
2929         }
2930
2931         state_swizzle[0] = state->swizzle_r;
2932         state_swizzle[1] = state->swizzle_g;
2933         state_swizzle[2] = state->swizzle_b;
2934         state_swizzle[3] = state->swizzle_a;
2935
2936         base_level = 0;
2937         first_level = state->u.tex.first_level;
2938         last_level = state->u.tex.last_level;
2939         width = width0;
2940         height = height0;
2941         depth = texture->depth0;
2942
2943         if (force_level) {
2944                 assert(force_level == first_level &&
2945                        force_level == last_level);
2946                 base_level = force_level;
2947                 first_level = 0;
2948                 last_level = 0;
2949                 width = u_minify(width, force_level);
2950                 height = u_minify(height, force_level);
2951                 depth = u_minify(depth, force_level);
2952         }
2953
2954         /* This is not needed if state trackers set last_layer correctly. */
2955         if (state->target == PIPE_TEXTURE_1D ||
2956             state->target == PIPE_TEXTURE_2D ||
2957             state->target == PIPE_TEXTURE_RECT ||
2958             state->target == PIPE_TEXTURE_CUBE)
2959                 last_layer = state->u.tex.first_layer;
2960
2961         si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
2962                                    state->format, state_swizzle,
2963                                    base_level, first_level, last_level,
2964                                    state->u.tex.first_layer, last_layer,
2965                                    width, height, depth,
2966                                    view->state, view->fmask_state);
2967
2968         return &view->base;
2969 }
2970
2971 static struct pipe_sampler_view *
2972 si_create_sampler_view(struct pipe_context *ctx,
2973                        struct pipe_resource *texture,
2974                        const struct pipe_sampler_view *state)
2975 {
2976         return si_create_sampler_view_custom(ctx, texture, state,
2977                                              texture ? texture->width0 : 0,
2978                                              texture ? texture->height0 : 0, 0);
2979 }
2980
2981 static void si_sampler_view_destroy(struct pipe_context *ctx,
2982                                     struct pipe_sampler_view *state)
2983 {
2984         struct si_sampler_view *view = (struct si_sampler_view *)state;
2985
2986         if (state->texture && state->texture->target == PIPE_BUFFER)
2987                 LIST_DELINIT(&view->list);
2988
2989         pipe_resource_reference(&state->texture, NULL);
2990         FREE(view);
2991 }
2992
2993 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2994 {
2995         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2996                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2997                (linear_filter &&
2998                 (wrap == PIPE_TEX_WRAP_CLAMP ||
2999                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3000 }
3001
3002 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3003 {
3004         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3005                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3006
3007         return (state->border_color.ui[0] || state->border_color.ui[1] ||
3008                 state->border_color.ui[2] || state->border_color.ui[3]) &&
3009                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3010                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3011                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3012 }
3013
3014 static void *si_create_sampler_state(struct pipe_context *ctx,
3015                                      const struct pipe_sampler_state *state)
3016 {
3017         struct si_context *sctx = (struct si_context *)ctx;
3018         struct r600_common_screen *rscreen = sctx->b.screen;
3019         struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3020         unsigned border_color_type, border_color_index = 0;
3021         unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3022                                                        : state->max_anisotropy;
3023         unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3024
3025         if (!rstate) {
3026                 return NULL;
3027         }
3028
3029         if (!sampler_state_needs_border_color(state))
3030                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3031         else if (state->border_color.f[0] == 0 &&
3032                  state->border_color.f[1] == 0 &&
3033                  state->border_color.f[2] == 0 &&
3034                  state->border_color.f[3] == 0)
3035                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3036         else if (state->border_color.f[0] == 0 &&
3037                  state->border_color.f[1] == 0 &&
3038                  state->border_color.f[2] == 0 &&
3039                  state->border_color.f[3] == 1)
3040                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3041         else if (state->border_color.f[0] == 1 &&
3042                  state->border_color.f[1] == 1 &&
3043                  state->border_color.f[2] == 1 &&
3044                  state->border_color.f[3] == 1)
3045                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3046         else {
3047                 int i;
3048
3049                 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3050
3051                 /* Check if the border has been uploaded already. */
3052                 for (i = 0; i < sctx->border_color_count; i++)
3053                         if (memcmp(&sctx->border_color_table[i], &state->border_color,
3054                                    sizeof(state->border_color)) == 0)
3055                                 break;
3056
3057                 if (i >= SI_MAX_BORDER_COLORS) {
3058                         /* Getting 4096 unique border colors is very unlikely. */
3059                         fprintf(stderr, "radeonsi: The border color table is full. "
3060                                 "Any new border colors will be just black. "
3061                                 "Please file a bug.\n");
3062                         border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3063                 } else {
3064                         if (i == sctx->border_color_count) {
3065                                 /* Upload a new border color. */
3066                                 memcpy(&sctx->border_color_table[i], &state->border_color,
3067                                        sizeof(state->border_color));
3068                                 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3069                                                         &state->border_color,
3070                                                         sizeof(state->border_color));
3071                                 sctx->border_color_count++;
3072                         }
3073
3074                         border_color_index = i;
3075                 }
3076         }
3077
3078         rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3079                           S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3080                           S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3081                           S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3082                           S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3083                           S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3084                           S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3085                           S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3086         rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3087                           S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3088         rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3089                           S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3090                           S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3091                           S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3092                           S_008F38_MIP_POINT_PRECLAMP(1) |
3093                           S_008F38_DISABLE_LSB_CEIL(1) |
3094                           S_008F38_FILTER_PREC_FIX(1) |
3095                           S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3096         rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3097                          S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3098         return rstate;
3099 }
3100
3101 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3102 {
3103         struct si_context *sctx = (struct si_context *)ctx;
3104
3105         if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3106                 return;
3107
3108         sctx->sample_mask.sample_mask = sample_mask;
3109         si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3110 }
3111
3112 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3113 {
3114         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3115         unsigned mask = sctx->sample_mask.sample_mask;
3116
3117         radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3118         radeon_emit(cs, mask | (mask << 16));
3119         radeon_emit(cs, mask | (mask << 16));
3120 }
3121
3122 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3123 {
3124         free(state);
3125 }
3126
3127 /*
3128  * Vertex elements & buffers
3129  */
3130
3131 static void *si_create_vertex_elements(struct pipe_context *ctx,
3132                                        unsigned count,
3133                                        const struct pipe_vertex_element *elements)
3134 {
3135         struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3136         int i;
3137
3138         assert(count <= SI_MAX_ATTRIBS);
3139         if (!v)
3140                 return NULL;
3141
3142         v->count = count;
3143         for (i = 0; i < count; ++i) {
3144                 const struct util_format_description *desc;
3145                 unsigned data_format, num_format;
3146                 int first_non_void;
3147
3148                 desc = util_format_description(elements[i].src_format);
3149                 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3150                 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3151                 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3152
3153                 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3154                                    S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3155                                    S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3156                                    S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3157                                    S_008F0C_NUM_FORMAT(num_format) |
3158                                    S_008F0C_DATA_FORMAT(data_format);
3159                 v->format_size[i] = desc->block.bits / 8;
3160         }
3161         memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3162
3163         return v;
3164 }
3165
3166 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3167 {
3168         struct si_context *sctx = (struct si_context *)ctx;
3169         struct si_vertex_element *v = (struct si_vertex_element*)state;
3170
3171         sctx->vertex_elements = v;
3172         sctx->vertex_buffers_dirty = true;
3173 }
3174
3175 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3176 {
3177         struct si_context *sctx = (struct si_context *)ctx;
3178
3179         if (sctx->vertex_elements == state)
3180                 sctx->vertex_elements = NULL;
3181         FREE(state);
3182 }
3183
3184 static void si_set_vertex_buffers(struct pipe_context *ctx,
3185                                   unsigned start_slot, unsigned count,
3186                                   const struct pipe_vertex_buffer *buffers)
3187 {
3188         struct si_context *sctx = (struct si_context *)ctx;
3189         struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3190         int i;
3191
3192         assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3193
3194         if (buffers) {
3195                 for (i = 0; i < count; i++) {
3196                         const struct pipe_vertex_buffer *src = buffers + i;
3197                         struct pipe_vertex_buffer *dsti = dst + i;
3198
3199                         pipe_resource_reference(&dsti->buffer, src->buffer);
3200                         dsti->buffer_offset = src->buffer_offset;
3201                         dsti->stride = src->stride;
3202                         r600_context_add_resource_size(ctx, src->buffer);
3203                 }
3204         } else {
3205                 for (i = 0; i < count; i++) {
3206                         pipe_resource_reference(&dst[i].buffer, NULL);
3207                 }
3208         }
3209         sctx->vertex_buffers_dirty = true;
3210 }
3211
3212 static void si_set_index_buffer(struct pipe_context *ctx,
3213                                 const struct pipe_index_buffer *ib)
3214 {
3215         struct si_context *sctx = (struct si_context *)ctx;
3216
3217         if (ib) {
3218                 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3219                 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3220                 r600_context_add_resource_size(ctx, ib->buffer);
3221         } else {
3222                 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3223         }
3224 }
3225
3226 /*
3227  * Misc
3228  */
3229
3230 static void si_set_tess_state(struct pipe_context *ctx,
3231                               const float default_outer_level[4],
3232                               const float default_inner_level[2])
3233 {
3234         struct si_context *sctx = (struct si_context *)ctx;
3235         struct pipe_constant_buffer cb;
3236         float array[8];
3237
3238         memcpy(array, default_outer_level, sizeof(float) * 4);
3239         memcpy(array+4, default_inner_level, sizeof(float) * 2);
3240
3241         cb.buffer = NULL;
3242         cb.user_buffer = NULL;
3243         cb.buffer_size = sizeof(array);
3244
3245         si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3246                                (void*)array, sizeof(array),
3247                                &cb.buffer_offset);
3248
3249         si_set_constant_buffer(sctx, &sctx->rw_buffers,
3250                                SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3251         pipe_resource_reference(&cb.buffer, NULL);
3252 }
3253
3254 static void si_texture_barrier(struct pipe_context *ctx)
3255 {
3256         struct si_context *sctx = (struct si_context *)ctx;
3257
3258         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3259                          SI_CONTEXT_INV_GLOBAL_L2 |
3260                          SI_CONTEXT_FLUSH_AND_INV_CB |
3261                          SI_CONTEXT_CS_PARTIAL_FLUSH;
3262 }
3263
3264 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3265 {
3266         struct si_context *sctx = (struct si_context *)ctx;
3267
3268         /* Subsequent commands must wait for all shader invocations to
3269          * complete. */
3270         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3271                          SI_CONTEXT_CS_PARTIAL_FLUSH;
3272
3273         if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3274                 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3275                                  SI_CONTEXT_INV_VMEM_L1;
3276
3277         if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3278                      PIPE_BARRIER_SHADER_BUFFER |
3279                      PIPE_BARRIER_TEXTURE |
3280                      PIPE_BARRIER_IMAGE |
3281                      PIPE_BARRIER_STREAMOUT_BUFFER |
3282                      PIPE_BARRIER_GLOBAL_BUFFER)) {
3283                 /* As far as I can tell, L1 contents are written back to L2
3284                  * automatically at end of shader, but the contents of other
3285                  * L1 caches might still be stale. */
3286                 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3287         }
3288
3289         if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3290                 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3291
3292                 /* Indices are read through TC L2 since VI. */
3293                 if (sctx->screen->b.chip_class <= CIK)
3294                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3295         }
3296
3297         if (flags & PIPE_BARRIER_FRAMEBUFFER)
3298                 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3299
3300         if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3301                      PIPE_BARRIER_FRAMEBUFFER |
3302                      PIPE_BARRIER_INDIRECT_BUFFER)) {
3303                 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3304                  *
3305                  * We need to make sure that TC L1 & L2 are written back to
3306                  * memory, because neither CPU accesses nor CB fetches consider
3307                  * TC, but there's no need to invalidate any TC cache lines. */
3308                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3309         }
3310 }
3311
3312 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3313 {
3314         struct pipe_blend_state blend;
3315
3316         memset(&blend, 0, sizeof(blend));
3317         blend.independent_blend_enable = true;
3318         blend.rt[0].colormask = 0xf;
3319         return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3320 }
3321
3322 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3323                                  bool include_draw_vbo)
3324 {
3325         si_need_cs_space((struct si_context*)ctx);
3326 }
3327
3328 static void si_init_config(struct si_context *sctx);
3329
3330 void si_init_state_functions(struct si_context *sctx)
3331 {
3332         si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3333         si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3334         si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3335         si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3336         si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3337
3338         si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3339         si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3340         si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3341         si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3342         si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3343         si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3344         si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3345         si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3346         si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3347         si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3348         si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3349
3350         sctx->b.b.create_blend_state = si_create_blend_state;
3351         sctx->b.b.bind_blend_state = si_bind_blend_state;
3352         sctx->b.b.delete_blend_state = si_delete_blend_state;
3353         sctx->b.b.set_blend_color = si_set_blend_color;
3354
3355         sctx->b.b.create_rasterizer_state = si_create_rs_state;
3356         sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3357         sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3358
3359         sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3360         sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3361         sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3362
3363         sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3364         sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3365         sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3366         sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3367         sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3368
3369         sctx->b.b.set_clip_state = si_set_clip_state;
3370         sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3371
3372         sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3373         sctx->b.b.get_sample_position = cayman_get_sample_position;
3374
3375         sctx->b.b.create_sampler_state = si_create_sampler_state;
3376         sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3377
3378         sctx->b.b.create_sampler_view = si_create_sampler_view;
3379         sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3380
3381         sctx->b.b.set_sample_mask = si_set_sample_mask;
3382
3383         sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3384         sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3385         sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3386         sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3387         sctx->b.b.set_index_buffer = si_set_index_buffer;
3388
3389         sctx->b.b.texture_barrier = si_texture_barrier;
3390         sctx->b.b.memory_barrier = si_memory_barrier;
3391         sctx->b.b.set_min_samples = si_set_min_samples;
3392         sctx->b.b.set_tess_state = si_set_tess_state;
3393
3394         sctx->b.b.set_active_query_state = si_set_active_query_state;
3395         sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3396         sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3397
3398         sctx->b.b.draw_vbo = si_draw_vbo;
3399
3400         si_init_config(sctx);
3401 }
3402
3403 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3404                                      struct r600_texture *rtex,
3405                                      struct radeon_bo_metadata *md)
3406 {
3407         struct si_screen *sscreen = (struct si_screen*)rscreen;
3408         struct pipe_resource *res = &rtex->resource.b.b;
3409         static const unsigned char swizzle[] = {
3410                 PIPE_SWIZZLE_X,
3411                 PIPE_SWIZZLE_Y,
3412                 PIPE_SWIZZLE_Z,
3413                 PIPE_SWIZZLE_W
3414         };
3415         uint32_t desc[8], i;
3416         bool is_array = util_resource_is_array_texture(res);
3417
3418         /* DRM 2.x.x doesn't support this. */
3419         if (rscreen->info.drm_major != 3)
3420                 return;
3421
3422         assert(rtex->fmask.size == 0);
3423
3424         /* Metadata image format format version 1:
3425          * [0] = 1 (metadata format identifier)
3426          * [1] = (VENDOR_ID << 16) | PCI_ID
3427          * [2:9] = image descriptor for the whole resource
3428          *         [2] is always 0, because the base address is cleared
3429          *         [9] is the DCC offset bits [39:8] from the beginning of
3430          *             the buffer
3431          * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3432          */
3433
3434         md->metadata[0] = 1; /* metadata image format version 1 */
3435
3436         /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3437         md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3438
3439         si_make_texture_descriptor(sscreen, rtex, true,
3440                                    res->target, res->format,
3441                                    swizzle, 0, 0, res->last_level, 0,
3442                                    is_array ? res->array_size - 1 : 0,
3443                                    res->width0, res->height0, res->depth0,
3444                                    desc, NULL);
3445
3446         /* Clear the base address and set the relative DCC offset. */
3447         desc[0] = 0;
3448         desc[1] &= C_008F14_BASE_ADDRESS_HI;
3449         desc[7] = rtex->dcc_offset >> 8;
3450
3451         /* Dwords [2:9] contain the image descriptor. */
3452         memcpy(&md->metadata[2], desc, sizeof(desc));
3453
3454         /* Dwords [10:..] contain the mipmap level offsets. */
3455         for (i = 0; i <= res->last_level; i++)
3456                 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3457
3458         md->size_metadata = (11 + res->last_level) * 4;
3459 }
3460
3461 void si_init_screen_state_functions(struct si_screen *sscreen)
3462 {
3463         sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3464 }
3465
3466 static void
3467 si_write_harvested_raster_configs(struct si_context *sctx,
3468                                   struct si_pm4_state *pm4,
3469                                   unsigned raster_config,
3470                                   unsigned raster_config_1)
3471 {
3472         unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3473         unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3474         unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3475         unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3476         unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3477         unsigned rb_per_se = num_rb / num_se;
3478         unsigned se_mask[4];
3479         unsigned se;
3480
3481         se_mask[0] = ((1 << rb_per_se) - 1);
3482         se_mask[1] = (se_mask[0] << rb_per_se);
3483         se_mask[2] = (se_mask[1] << rb_per_se);
3484         se_mask[3] = (se_mask[2] << rb_per_se);
3485
3486         se_mask[0] &= rb_mask;
3487         se_mask[1] &= rb_mask;
3488         se_mask[2] &= rb_mask;
3489         se_mask[3] &= rb_mask;
3490
3491         assert(num_se == 1 || num_se == 2 || num_se == 4);
3492         assert(sh_per_se == 1 || sh_per_se == 2);
3493         assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3494
3495         /* XXX: I can't figure out what the *_XSEL and *_YSEL
3496          * fields are for, so I'm leaving them as their default
3497          * values. */
3498
3499         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3500                              (!se_mask[2] && !se_mask[3]))) {
3501                 raster_config_1 &= C_028354_SE_PAIR_MAP;
3502
3503                 if (!se_mask[0] && !se_mask[1]) {
3504                         raster_config_1 |=
3505                                 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3506                 } else {
3507                         raster_config_1 |=
3508                                 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3509                 }
3510         }
3511
3512         for (se = 0; se < num_se; se++) {
3513                 unsigned raster_config_se = raster_config;
3514                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3515                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3516                 int idx = (se / 2) * 2;
3517
3518                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3519                         raster_config_se &= C_028350_SE_MAP;
3520
3521                         if (!se_mask[idx]) {
3522                                 raster_config_se |=
3523                                         S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3524                         } else {
3525                                 raster_config_se |=
3526                                         S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3527                         }
3528                 }
3529
3530                 pkr0_mask &= rb_mask;
3531                 pkr1_mask &= rb_mask;
3532                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3533                         raster_config_se &= C_028350_PKR_MAP;
3534
3535                         if (!pkr0_mask) {
3536                                 raster_config_se |=
3537                                         S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3538                         } else {
3539                                 raster_config_se |=
3540                                         S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3541                         }
3542                 }
3543
3544                 if (rb_per_se >= 2) {
3545                         unsigned rb0_mask = 1 << (se * rb_per_se);
3546                         unsigned rb1_mask = rb0_mask << 1;
3547
3548                         rb0_mask &= rb_mask;
3549                         rb1_mask &= rb_mask;
3550                         if (!rb0_mask || !rb1_mask) {
3551                                 raster_config_se &= C_028350_RB_MAP_PKR0;
3552
3553                                 if (!rb0_mask) {
3554                                         raster_config_se |=
3555                                                 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3556                                 } else {
3557                                         raster_config_se |=
3558                                                 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3559                                 }
3560                         }
3561
3562                         if (rb_per_se > 2) {
3563                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3564                                 rb1_mask = rb0_mask << 1;
3565                                 rb0_mask &= rb_mask;
3566                                 rb1_mask &= rb_mask;
3567                                 if (!rb0_mask || !rb1_mask) {
3568                                         raster_config_se &= C_028350_RB_MAP_PKR1;
3569
3570                                         if (!rb0_mask) {
3571                                                 raster_config_se |=
3572                                                         S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3573                                         } else {
3574                                                 raster_config_se |=
3575                                                         S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3576                                         }
3577                                 }
3578                         }
3579                 }
3580
3581                 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3582                 if (sctx->b.chip_class < CIK)
3583                         si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3584                                        SE_INDEX(se) | SH_BROADCAST_WRITES |
3585                                        INSTANCE_BROADCAST_WRITES);
3586                 else
3587                         si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3588                                        S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3589                                        S_030800_INSTANCE_BROADCAST_WRITES(1));
3590                 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3591                 if (sctx->b.chip_class >= CIK)
3592                         si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3593         }
3594
3595         /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3596         if (sctx->b.chip_class < CIK)
3597                 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3598                                SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3599                                INSTANCE_BROADCAST_WRITES);
3600         else
3601                 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3602                                S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3603                                S_030800_INSTANCE_BROADCAST_WRITES(1));
3604 }
3605
3606 static void si_init_config(struct si_context *sctx)
3607 {
3608         struct si_screen *sscreen = sctx->screen;
3609         unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3610         unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3611         unsigned raster_config, raster_config_1;
3612         uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3613         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3614         int i;
3615
3616         if (!pm4)
3617                 return;
3618
3619         si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3620         si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3621         si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3622         si_pm4_cmd_end(pm4, false);
3623
3624         si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3625         si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3626
3627         /* FIXME calculate these values somehow ??? */
3628         si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3629         si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3630         si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3631
3632         si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3633         si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3634
3635         si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3636         si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3637         if (sctx->b.chip_class < CIK)
3638                 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3639                                S_008A14_CLIP_VTX_REORDER_ENA(1));
3640
3641         si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3642         si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3643
3644         si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3645
3646         for (i = 0; i < 16; i++) {
3647                 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3648                 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3649         }
3650
3651         switch (sctx->screen->b.family) {
3652         case CHIP_TAHITI:
3653         case CHIP_PITCAIRN:
3654                 raster_config = 0x2a00126a;
3655                 raster_config_1 = 0x00000000;
3656                 break;
3657         case CHIP_VERDE:
3658                 raster_config = 0x0000124a;
3659                 raster_config_1 = 0x00000000;
3660                 break;
3661         case CHIP_OLAND:
3662                 raster_config = 0x00000082;
3663                 raster_config_1 = 0x00000000;
3664                 break;
3665         case CHIP_HAINAN:
3666                 raster_config = 0x00000000;
3667                 raster_config_1 = 0x00000000;
3668                 break;
3669         case CHIP_BONAIRE:
3670                 raster_config = 0x16000012;
3671                 raster_config_1 = 0x00000000;
3672                 break;
3673         case CHIP_HAWAII:
3674                 raster_config = 0x3a00161a;
3675                 raster_config_1 = 0x0000002e;
3676                 break;
3677         case CHIP_FIJI:
3678                 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3679                         /* old kernels with old tiling config */
3680                         raster_config = 0x16000012;
3681                         raster_config_1 = 0x0000002a;
3682                 } else {
3683                         raster_config = 0x3a00161a;
3684                         raster_config_1 = 0x0000002e;
3685                 }
3686                 break;
3687         case CHIP_POLARIS10:
3688                 raster_config = 0x16000012;
3689                 raster_config_1 = 0x0000002a;
3690                 break;
3691         case CHIP_POLARIS11:
3692                 raster_config = 0x16000012;
3693                 raster_config_1 = 0x00000000;
3694                 break;
3695         case CHIP_TONGA:
3696                 raster_config = 0x16000012;
3697                 raster_config_1 = 0x0000002a;
3698                 break;
3699         case CHIP_ICELAND:
3700                 if (num_rb == 1)
3701                         raster_config = 0x00000000;
3702                 else
3703                         raster_config = 0x00000002;
3704                 raster_config_1 = 0x00000000;
3705                 break;
3706         case CHIP_CARRIZO:
3707                 raster_config = 0x00000002;
3708                 raster_config_1 = 0x00000000;
3709                 break;
3710         case CHIP_KAVERI:
3711                 /* KV should be 0x00000002, but that causes problems with radeon */
3712                 raster_config = 0x00000000; /* 0x00000002 */
3713                 raster_config_1 = 0x00000000;
3714                 break;
3715         case CHIP_KABINI:
3716         case CHIP_MULLINS:
3717         case CHIP_STONEY:
3718                 raster_config = 0x00000000;
3719                 raster_config_1 = 0x00000000;
3720                 break;
3721         default:
3722                 fprintf(stderr,
3723                         "radeonsi: Unknown GPU, using 0 for raster_config\n");
3724                 raster_config = 0x00000000;
3725                 raster_config_1 = 0x00000000;
3726                 break;
3727         }
3728
3729         /* Always use the default config when all backends are enabled
3730          * (or when we failed to determine the enabled backends).
3731          */
3732         if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3733                 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3734                                raster_config);
3735                 if (sctx->b.chip_class >= CIK)
3736                         si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3737                                        raster_config_1);
3738         } else {
3739                 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3740         }
3741
3742         si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3743         si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3744         si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3745                        S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3746         si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3747         si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3748                        S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3749
3750         si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3751         si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3752         /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3753         si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3754         si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3755         si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3756         si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3757         si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3758         si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3759                        S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3760                        S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3761
3762         si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3763         si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3764         si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3765
3766         if (sctx->b.chip_class >= CIK) {
3767                 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3768                 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3769                 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3770
3771                 if (sscreen->b.info.num_good_compute_units /
3772                     (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3773                         /* Too few available compute units per SH. Disallowing
3774                          * VS to run on CU0 could hurt us more than late VS
3775                          * allocation would help.
3776                          *
3777                          * LATE_ALLOC_VS = 2 is the highest safe number.
3778                          */
3779                         si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3780                         si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3781                         si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3782                 } else {
3783                         /* Set LATE_ALLOC_VS == 31. It should be less than
3784                          * the number of scratch waves. Limitations:
3785                          * - VS can't execute on CU0.
3786                          * - If HS writes outputs to LDS, LS can't execute on CU0.
3787                          */
3788                         si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3789                         si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3790                         si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3791                 }
3792
3793                 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3794         }
3795
3796         if (sctx->b.chip_class >= VI) {
3797                 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3798                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3799                                S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3800                 if (sctx->b.family < CHIP_POLARIS10)
3801                         si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3802                 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3803                 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
3804                                S_028B50_ACCUM_ISOLINE(32) |
3805                                S_028B50_ACCUM_TRI(11) |
3806                                S_028B50_ACCUM_QUAD(11) |
3807                                S_028B50_DONUT_SPLIT(16));
3808         }
3809
3810         if (sctx->b.family == CHIP_STONEY)
3811                 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3812
3813         if (sctx->b.family >= CHIP_POLARIS10)
3814                 si_pm4_set_reg(pm4, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3815                                S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3816                                S_028830_LINE_FILTER_DISABLE(1)); /* line bug */
3817
3818         si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3819         if (sctx->b.chip_class >= CIK)
3820                 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3821         si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3822                       RADEON_PRIO_BORDER_COLORS);
3823
3824         si_pm4_upload_indirect_buffer(sctx, pm4);
3825         sctx->init_config = pm4;
3826 }