2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
36 #define SI_MAX_ATTRIBS 16
37 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
38 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
39 #define SI_NUM_CONST_BUFFERS 16
40 #define SI_NUM_IMAGES 16
41 #define SI_NUM_SHADER_BUFFERS 16
46 struct si_state_blend {
47 struct si_pm4_state pm4;
48 uint32_t cb_target_mask;
49 bool alpha_to_coverage;
52 /* Set 0xf or 0x0 (4 bits) per render target if the following is
53 * true. ANDed with spi_shader_col_format.
55 unsigned blend_enable_4bit;
56 unsigned need_src_alpha_4bit;
59 struct si_state_rasterizer {
60 struct si_pm4_state pm4;
61 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
62 struct si_pm4_state pm4_poly_offset[3];
65 bool multisample_enable;
66 bool force_persample_interp;
67 bool line_stipple_enable;
68 unsigned sprite_coord_enable;
69 unsigned pa_sc_line_stipple;
70 unsigned pa_cl_clip_cntl;
71 unsigned clip_plane_enable;
72 bool poly_stipple_enable;
75 bool uses_poly_offset;
76 bool clamp_fragment_color;
77 bool rasterizer_discard;
81 struct si_dsa_stencil_ref_part {
87 struct si_pm4_state pm4;
89 struct si_dsa_stencil_ref_part stencil_ref;
92 struct si_stencil_ref {
93 struct r600_atom atom;
94 struct pipe_stencil_ref state;
95 struct si_dsa_stencil_ref_part dsa_part;
98 struct si_vertex_element
101 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
102 uint32_t format_size[SI_MAX_ATTRIBS];
103 struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
108 struct si_state_blend *blend;
109 struct si_state_rasterizer *rasterizer;
110 struct si_state_dsa *dsa;
111 struct si_pm4_state *poly_offset;
112 struct si_pm4_state *ls;
113 struct si_pm4_state *hs;
114 struct si_pm4_state *es;
115 struct si_pm4_state *gs;
116 struct si_pm4_state *vgt_shader_config;
117 struct si_pm4_state *vs;
118 struct si_pm4_state *ps;
120 struct si_pm4_state *array[0];
123 union si_state_atoms {
125 /* The order matters. */
126 struct r600_atom *cache_flush;
127 struct r600_atom *render_cond;
128 struct r600_atom *streamout_begin;
129 struct r600_atom *streamout_enable; /* must be after streamout_begin */
130 struct r600_atom *framebuffer;
131 struct r600_atom *msaa_sample_locs;
132 struct r600_atom *db_render_state;
133 struct r600_atom *msaa_config;
134 struct r600_atom *sample_mask;
135 struct r600_atom *cb_render_state;
136 struct r600_atom *blend_color;
137 struct r600_atom *clip_regs;
138 struct r600_atom *clip_state;
139 struct r600_atom *shader_userdata;
140 struct r600_atom *scissors;
141 struct r600_atom *viewports;
142 struct r600_atom *stencil_ref;
143 struct r600_atom *spi_map;
145 struct r600_atom *array[0];
148 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
150 struct si_shader_data {
151 struct r600_atom atom;
152 uint32_t sh_base[SI_NUM_SHADERS];
155 /* Private read-write buffer slots. */
157 SI_HS_RING_TESS_FACTOR,
168 SI_VS_STREAMOUT_BUF0,
169 SI_VS_STREAMOUT_BUF1,
170 SI_VS_STREAMOUT_BUF2,
171 SI_VS_STREAMOUT_BUF3,
173 SI_HS_CONST_DEFAULT_TESS_LEVELS,
174 SI_VS_CONST_CLIP_PLANES,
175 SI_PS_CONST_POLY_STIPPLE,
176 SI_PS_CONST_SAMPLE_POSITIONS,
181 /* This represents descriptors in memory, such as buffer resources,
182 * image resources, and sampler states.
184 struct si_descriptors {
185 /* The list of descriptors in malloc'd memory. */
187 /* The size of one descriptor. */
188 unsigned element_dw_size;
189 /* The maximum number of descriptors. */
190 unsigned num_elements;
192 /* The buffer where the descriptors have been uploaded. */
193 struct r600_resource *buffer;
194 unsigned buffer_offset;
196 /* Offset in CE RAM */
199 /* The i-th bit is set if that element is enabled (non-NULL resource). */
200 unsigned enabled_mask;
202 /* elements of the list that are changed and need to be uploaded */
205 /* Whether the CE ram is dirty and needs to be reinitialized entirely
206 * before we can do partial updates. */
209 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
210 * array will be stored. */
211 unsigned shader_userdata_offset;
212 /* Whether the pointer should be re-emitted. */
216 struct si_sampler_views {
217 struct si_descriptors desc;
218 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
219 void *sampler_states[SI_NUM_SAMPLERS];
222 struct si_buffer_resources {
223 struct si_descriptors desc;
224 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
225 enum radeon_bo_priority priority;
226 struct pipe_resource **buffers; /* this has num_buffers elements */
229 #define si_pm4_block_idx(member) \
230 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
232 #define si_pm4_state_changed(sctx, member) \
233 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
235 #define si_pm4_bind_state(sctx, member, value) \
237 (sctx)->queued.named.member = (value); \
240 #define si_pm4_delete_state(sctx, member, value) \
242 if ((sctx)->queued.named.member == (value)) { \
243 (sctx)->queued.named.member = NULL; \
245 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
246 si_pm4_block_idx(member)); \
249 /* si_descriptors.c */
250 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
251 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
252 struct pipe_resource *buffer,
253 unsigned stride, unsigned num_records,
254 bool add_tid, bool swizzle,
255 unsigned element_size, unsigned index_stride, uint64_t offset);
256 void si_init_all_descriptors(struct si_context *sctx);
257 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
258 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
259 void si_release_all_descriptors(struct si_context *sctx);
260 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
261 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
262 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
263 void si_shader_change_notify(struct si_context *sctx);
264 void si_update_compressed_colortex_masks(struct si_context *sctx);
265 void si_emit_graphics_shader_userdata(struct si_context *sctx,
266 struct r600_atom *atom);
267 void si_emit_compute_shader_userdata(struct si_context *sctx);
268 void si_set_constant_buffer(struct si_context *sctx,
269 struct si_buffer_resources *buffers,
270 uint slot, struct pipe_constant_buffer *input);
273 struct si_shader_selector;
275 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
276 struct r600_atom **list_elem,
277 void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
278 boolean si_is_format_supported(struct pipe_screen *screen,
279 enum pipe_format format,
280 enum pipe_texture_target target,
281 unsigned sample_count,
283 void si_init_state_functions(struct si_context *sctx);
284 void si_init_screen_state_functions(struct si_screen *sscreen);
285 unsigned cik_bank_wh(unsigned bankwh);
286 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
287 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
288 unsigned cik_tile_split(unsigned tile_split);
289 unsigned si_array_mode(unsigned mode);
290 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
291 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
293 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
294 enum pipe_format format,
295 unsigned first_element, unsigned last_element,
298 si_make_texture_descriptor(struct si_screen *screen,
299 struct r600_texture *tex,
301 enum pipe_texture_target target,
302 enum pipe_format pipe_format,
303 const unsigned char state_swizzle[4],
304 unsigned base_level, unsigned first_level, unsigned last_level,
305 unsigned first_layer, unsigned last_layer,
306 unsigned width, unsigned height, unsigned depth,
308 uint32_t *fmask_state);
309 struct pipe_sampler_view *
310 si_create_sampler_view_custom(struct pipe_context *ctx,
311 struct pipe_resource *texture,
312 const struct pipe_sampler_view *state,
313 unsigned width0, unsigned height0,
314 unsigned force_level);
316 /* si_state_shader.c */
317 bool si_update_shaders(struct si_context *sctx);
318 void si_init_shader_functions(struct si_context *sctx);
319 bool si_init_shader_cache(struct si_screen *sscreen);
320 void si_destroy_shader_cache(struct si_screen *sscreen);
322 /* si_state_draw.c */
323 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
324 void si_ce_pre_draw_synchronization(struct si_context *sctx);
325 void si_ce_post_draw_synchronization(struct si_context *sctx);
326 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
327 void si_trace_emit(struct si_context *sctx);