2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
35 #define SI_MAX_ATTRIBS 16
40 struct si_state_blend {
41 struct si_pm4_state pm4;
42 uint32_t cb_target_mask;
43 bool alpha_to_coverage;
46 /* Set 0xf or 0x0 (4 bits) per render target if the following is
47 * true. ANDed with spi_shader_col_format.
49 unsigned blend_enable_4bit;
50 unsigned need_src_alpha_4bit;
53 struct si_state_rasterizer {
54 struct si_pm4_state pm4;
55 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
56 struct si_pm4_state pm4_poly_offset[3];
59 bool multisample_enable;
60 bool force_persample_interp;
61 bool line_stipple_enable;
62 unsigned sprite_coord_enable;
63 unsigned pa_sc_line_stipple;
64 unsigned pa_cl_clip_cntl;
65 unsigned clip_plane_enable;
66 bool poly_stipple_enable;
69 bool uses_poly_offset;
70 bool clamp_fragment_color;
71 bool rasterizer_discard;
75 struct si_dsa_stencil_ref_part {
81 struct si_pm4_state pm4;
83 struct si_dsa_stencil_ref_part stencil_ref;
86 struct si_stencil_ref {
87 struct r600_atom atom;
88 struct pipe_stencil_ref state;
89 struct si_dsa_stencil_ref_part dsa_part;
92 struct si_vertex_element
95 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
96 uint32_t format_size[SI_MAX_ATTRIBS];
97 struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
102 struct si_state_blend *blend;
103 struct si_state_rasterizer *rasterizer;
104 struct si_state_dsa *dsa;
105 struct si_pm4_state *poly_offset;
106 struct si_pm4_state *ls;
107 struct si_pm4_state *hs;
108 struct si_pm4_state *es;
109 struct si_pm4_state *gs;
110 struct si_pm4_state *vgt_shader_config;
111 struct si_pm4_state *vs;
112 struct si_pm4_state *ps;
114 struct si_pm4_state *array[0];
117 union si_state_atoms {
119 /* The order matters. */
120 struct r600_atom *cache_flush;
121 struct r600_atom *render_cond;
122 struct r600_atom *streamout_begin;
123 struct r600_atom *streamout_enable; /* must be after streamout_begin */
124 struct r600_atom *framebuffer;
125 struct r600_atom *msaa_sample_locs;
126 struct r600_atom *db_render_state;
127 struct r600_atom *msaa_config;
128 struct r600_atom *sample_mask;
129 struct r600_atom *cb_render_state;
130 struct r600_atom *blend_color;
131 struct r600_atom *clip_regs;
132 struct r600_atom *clip_state;
133 struct r600_atom *shader_userdata;
134 struct r600_atom *scissors;
135 struct r600_atom *viewports;
136 struct r600_atom *stencil_ref;
137 struct r600_atom *spi_map;
139 struct r600_atom *array[0];
142 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
144 struct si_shader_data {
145 struct r600_atom atom;
146 uint32_t sh_base[SI_NUM_SHADERS];
149 /* User sampler views: 0..31
150 * Polygon stipple tex: 32
152 #define SI_NUM_USER_SAMPLERS 32 /* AKA OpenGL textures units per shader */
153 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
154 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
156 /* User constant buffers: 0..15
157 * Driver state constants: 16
159 #define SI_NUM_USER_CONST_BUFFERS 16
160 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
161 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
163 #define SI_NUM_IMAGES 16
165 #define SI_NUM_SHADER_BUFFERS 16
167 /* Private read-write buffer slots. */
169 SI_HS_RING_TESS_FACTOR,
180 SI_VS_STREAMOUT_BUF0,
181 SI_VS_STREAMOUT_BUF1,
182 SI_VS_STREAMOUT_BUF2,
183 SI_VS_STREAMOUT_BUF3,
188 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
191 /* This represents descriptors in memory, such as buffer resources,
192 * image resources, and sampler states.
194 struct si_descriptors {
195 /* The list of descriptors in malloc'd memory. */
197 /* The size of one descriptor. */
198 unsigned element_dw_size;
199 /* The maximum number of descriptors. */
200 unsigned num_elements;
202 /* The buffer where the descriptors have been uploaded. */
203 struct r600_resource *buffer;
204 unsigned buffer_offset;
206 /* Offset in CE RAM */
209 /* The i-th bit is set if that element is enabled (non-NULL resource). */
210 uint64_t enabled_mask;
212 /* elements of the list that are changed and need to be uploaded */
215 /* Whether the CE ram is dirty and needs to be reinitialized entirely
216 * before we can do partial updates. */
219 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
220 * array will be stored. */
221 unsigned shader_userdata_offset;
222 /* Whether the pointer should be re-emitted. */
226 struct si_sampler_views {
227 struct si_descriptors desc;
228 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
229 void *sampler_states[SI_NUM_SAMPLERS];
232 struct si_buffer_resources {
233 struct si_descriptors desc;
234 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
235 enum radeon_bo_priority priority;
236 struct pipe_resource **buffers; /* this has num_buffers elements */
239 #define si_pm4_block_idx(member) \
240 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
242 #define si_pm4_state_changed(sctx, member) \
243 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
245 #define si_pm4_bind_state(sctx, member, value) \
247 (sctx)->queued.named.member = (value); \
250 #define si_pm4_delete_state(sctx, member, value) \
252 if ((sctx)->queued.named.member == (value)) { \
253 (sctx)->queued.named.member = NULL; \
255 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
256 si_pm4_block_idx(member)); \
259 /* si_descriptors.c */
260 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
261 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
262 struct pipe_resource *buffer,
263 unsigned stride, unsigned num_records,
264 bool add_tid, bool swizzle,
265 unsigned element_size, unsigned index_stride, uint64_t offset);
266 void si_init_all_descriptors(struct si_context *sctx);
267 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
268 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
269 void si_release_all_descriptors(struct si_context *sctx);
270 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
271 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
272 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
273 void si_shader_change_notify(struct si_context *sctx);
274 void si_update_compressed_colortex_masks(struct si_context *sctx);
275 void si_emit_graphics_shader_userdata(struct si_context *sctx,
276 struct r600_atom *atom);
277 void si_emit_compute_shader_userdata(struct si_context *sctx);
280 struct si_shader_selector;
282 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
283 struct r600_atom **list_elem,
284 void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
285 boolean si_is_format_supported(struct pipe_screen *screen,
286 enum pipe_format format,
287 enum pipe_texture_target target,
288 unsigned sample_count,
290 void si_init_state_functions(struct si_context *sctx);
291 void si_init_screen_state_functions(struct si_screen *sscreen);
292 unsigned cik_bank_wh(unsigned bankwh);
293 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
294 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
295 unsigned cik_tile_split(unsigned tile_split);
296 unsigned si_array_mode(unsigned mode);
297 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
298 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
300 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
301 enum pipe_format format,
302 unsigned first_element, unsigned last_element,
305 si_make_texture_descriptor(struct si_screen *screen,
306 struct r600_texture *tex,
308 enum pipe_texture_target target,
309 enum pipe_format pipe_format,
310 const unsigned char state_swizzle[4],
311 unsigned base_level, unsigned first_level, unsigned last_level,
312 unsigned first_layer, unsigned last_layer,
313 unsigned width, unsigned height, unsigned depth,
315 uint32_t *fmask_state);
316 struct pipe_sampler_view *
317 si_create_sampler_view_custom(struct pipe_context *ctx,
318 struct pipe_resource *texture,
319 const struct pipe_sampler_view *state,
320 unsigned width0, unsigned height0,
321 unsigned force_level);
323 /* si_state_shader.c */
324 bool si_update_shaders(struct si_context *sctx);
325 void si_init_shader_functions(struct si_context *sctx);
326 bool si_init_shader_cache(struct si_screen *sscreen);
327 void si_destroy_shader_cache(struct si_screen *sscreen);
329 /* si_state_draw.c */
330 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
331 void si_ce_pre_draw_synchronization(struct si_context *sctx);
332 void si_ce_post_draw_synchronization(struct si_context *sctx);
333 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
334 void si_trace_emit(struct si_context *sctx);