2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_SHADERS (PIPE_SHADER_GEOMETRY+1)
38 struct si_state_blend {
39 struct si_pm4_state pm4;
40 uint32_t cb_target_mask;
44 struct si_state_sample_mask {
45 struct si_pm4_state pm4;
49 struct si_state_scissor {
50 struct si_pm4_state pm4;
51 struct pipe_scissor_state scissor;
54 struct si_state_viewport {
55 struct si_pm4_state pm4;
56 struct pipe_viewport_state viewport;
59 struct si_state_rasterizer {
60 struct si_pm4_state pm4;
63 bool multisample_enable;
64 bool line_stipple_enable;
65 unsigned sprite_coord_enable;
66 unsigned pa_sc_line_stipple;
67 unsigned pa_cl_clip_cntl;
68 unsigned clip_plane_enable;
71 bool poly_stipple_enable;
77 struct si_pm4_state pm4;
83 struct si_vertex_element
86 uint32_t rsrc_word3[PIPE_MAX_ATTRIBS];
87 uint32_t format_size[PIPE_MAX_ATTRIBS];
88 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
93 struct si_state_blend *blend;
94 struct si_pm4_state *blend_color;
95 struct si_pm4_state *clip;
96 struct si_state_sample_mask *sample_mask;
97 struct si_state_scissor *scissor[16];
98 struct si_state_viewport *viewport[16];
99 struct si_state_rasterizer *rasterizer;
100 struct si_state_dsa *dsa;
101 struct si_pm4_state *fb_rs;
102 struct si_pm4_state *fb_blend;
103 struct si_pm4_state *dsa_stencil_ref;
104 struct si_pm4_state *ta_bordercolor_base;
105 struct si_pm4_state *es;
106 struct si_pm4_state *gs;
107 struct si_pm4_state *gs_rings;
108 struct si_pm4_state *gs_onoff;
109 struct si_pm4_state *vs;
110 struct si_pm4_state *ps;
111 struct si_pm4_state *spi;
113 struct si_pm4_state *array[0];
116 struct si_shader_data {
117 struct r600_atom atom;
118 uint32_t sh_base[SI_NUM_SHADERS];
121 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
122 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
123 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
125 /* User sampler views: 0..15
126 * Polygon stipple tex: 16
127 * FMASK sampler views: 17..33 (no sampler states)
129 #define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
130 #define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
131 #define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
133 /* User constant buffers: 0..15
134 * Driver state constants: 16
136 #define SI_NUM_USER_CONST_BUFFERS 16
137 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
138 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
140 /* Read-write buffer slots.
143 * Streamout buffers: 2..5
145 #define SI_RING_ESGS 0
146 #define SI_RING_GSVS 1
147 #define SI_NUM_RING_BUFFERS 2
148 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
149 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
151 #define SI_NUM_VERTEX_BUFFERS 16
154 /* This represents resource descriptors in memory, such as buffer resources,
155 * image resources, and sampler states.
157 struct si_descriptors {
158 struct r600_atom atom;
160 /* The size of one resource descriptor. */
161 unsigned element_dw_size;
162 /* The maximum number of resource descriptors. */
163 unsigned num_elements;
165 /* The buffer where resource descriptors are stored. */
166 struct r600_resource *buffer;
167 unsigned buffer_offset;
169 /* The i-th bit is set if that element is dirty (changed but not emitted). */
171 /* The i-th bit is set if that element is enabled (non-NULL resource). */
172 uint64_t enabled_mask;
174 /* We can't update descriptors directly because the GPU might be
175 * reading them at the same time, so we have to update them
176 * in a copy-on-write manner. Each such copy is called a context,
177 * which is just another array descriptors in the same buffer. */
178 unsigned current_context_id;
179 /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
180 unsigned context_size;
182 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
183 * array will be stored. */
184 unsigned shader_userdata_offset;
188 struct si_sampler_views {
189 struct si_descriptors desc;
190 struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS];
191 uint32_t *desc_data[SI_NUM_SAMPLER_VIEWS];
194 struct si_sampler_states {
195 struct si_descriptors desc;
196 uint32_t *desc_data[SI_NUM_SAMPLER_STATES];
197 void *saved_states[2]; /* saved for u_blitter */
200 struct si_buffer_resources {
201 struct si_descriptors desc;
202 unsigned num_buffers;
203 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
204 enum radeon_bo_priority priority;
205 struct pipe_resource **buffers; /* this has num_buffers elements */
206 uint32_t *desc_storage; /* this has num_buffers*4 elements */
207 uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
210 #define si_pm4_block_idx(member) \
211 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
213 #define si_pm4_state_changed(sctx, member) \
214 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
216 #define si_pm4_bind_state(sctx, member, value) \
218 (sctx)->queued.named.member = (value); \
221 #define si_pm4_delete_state(sctx, member, value) \
223 if ((sctx)->queued.named.member == (value)) { \
224 (sctx)->queued.named.member = NULL; \
226 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
227 si_pm4_block_idx(member)); \
230 #define si_pm4_set_state(sctx, member, value) \
232 if ((sctx)->queued.named.member != (value)) { \
233 si_pm4_free_state(sctx, \
234 (struct si_pm4_state *)(sctx)->queued.named.member, \
235 si_pm4_block_idx(member)); \
236 (sctx)->queued.named.member = (value); \
240 /* si_descriptors.c */
241 void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
242 unsigned start, unsigned count, void **states);
243 void si_update_vertex_buffers(struct si_context *sctx);
244 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
245 struct pipe_resource *buffer,
246 unsigned stride, unsigned num_records,
247 bool add_tid, bool swizzle,
248 unsigned element_size, unsigned index_stride);
249 void si_init_all_descriptors(struct si_context *sctx);
250 void si_release_all_descriptors(struct si_context *sctx);
251 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
252 void si_copy_buffer(struct si_context *sctx,
253 struct pipe_resource *dst, struct pipe_resource *src,
254 uint64_t dst_offset, uint64_t src_offset, unsigned size, bool is_framebuffer);
255 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
256 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
257 void si_shader_change_notify(struct si_context *sctx);
260 struct si_shader_selector;
262 boolean si_is_format_supported(struct pipe_screen *screen,
263 enum pipe_format format,
264 enum pipe_texture_target target,
265 unsigned sample_count,
267 void si_init_state_functions(struct si_context *sctx);
268 unsigned cik_bank_wh(unsigned bankwh);
269 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
270 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
271 unsigned cik_tile_split(unsigned tile_split);
272 unsigned si_array_mode(unsigned mode);
273 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
274 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
275 struct pipe_sampler_view *
276 si_create_sampler_view_custom(struct pipe_context *ctx,
277 struct pipe_resource *texture,
278 const struct pipe_sampler_view *state,
279 unsigned width0, unsigned height0,
280 unsigned force_level);
282 /* si_state_shader.c */
283 void si_update_shaders(struct si_context *sctx);
284 void si_init_shader_functions(struct si_context *sctx);
286 /* si_state_draw.c */
287 extern const struct r600_atom si_atom_cache_flush;
288 extern const struct r600_atom si_atom_msaa_sample_locs;
289 extern const struct r600_atom si_atom_msaa_config;
290 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
291 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
294 void si_cmd_context_control(struct si_pm4_state *pm4);