2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
36 struct si_state_blend {
37 struct si_pm4_state pm4;
38 uint32_t cb_target_mask;
42 struct si_state_sample_mask {
43 struct si_pm4_state pm4;
47 struct si_state_scissor {
48 struct si_pm4_state pm4;
49 struct pipe_scissor_state scissor;
52 struct si_state_viewport {
53 struct si_pm4_state pm4;
54 struct pipe_viewport_state viewport;
57 struct si_state_rasterizer {
58 struct si_pm4_state pm4;
61 bool multisample_enable;
62 bool line_stipple_enable;
63 unsigned sprite_coord_enable;
64 unsigned pa_sc_line_stipple;
65 unsigned pa_su_sc_mode_cntl;
66 unsigned pa_cl_clip_cntl;
67 unsigned clip_plane_enable;
70 bool poly_stipple_enable;
74 struct si_pm4_state pm4;
80 struct si_vertex_element
83 uint32_t rsrc_word3[PIPE_MAX_ATTRIBS];
84 uint32_t format_size[PIPE_MAX_ATTRIBS];
85 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
90 struct si_state_blend *blend;
91 struct si_pm4_state *blend_color;
92 struct si_pm4_state *clip;
93 struct si_state_sample_mask *sample_mask;
94 struct si_state_scissor *scissor;
95 struct si_state_viewport *viewport;
96 struct si_state_rasterizer *rasterizer;
97 struct si_state_dsa *dsa;
98 struct si_pm4_state *fb_rs;
99 struct si_pm4_state *fb_blend;
100 struct si_pm4_state *dsa_stencil_ref;
101 struct si_pm4_state *ta_bordercolor_base;
102 struct si_pm4_state *es;
103 struct si_pm4_state *gs;
104 struct si_pm4_state *gs_rings;
105 struct si_pm4_state *gs_onoff;
106 struct si_pm4_state *vs;
107 struct si_pm4_state *ps;
108 struct si_pm4_state *spi;
110 struct si_pm4_state *array[0];
113 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
114 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
115 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
117 /* User sampler views: 0..15
118 * Polygon stipple tex: 16
119 * FMASK sampler views: 17..33 (no sampler states)
121 #define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
122 #define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
123 #define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
125 /* User constant buffers: 0..15
126 * Driver state constants: 16
128 #define SI_NUM_USER_CONST_BUFFERS 16
129 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
130 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
132 /* Read-write buffer slots.
135 * Streamout buffers: 2..5
137 #define SI_RING_ESGS 0
138 #define SI_RING_GSVS 1
139 #define SI_NUM_RING_BUFFERS 2
140 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
141 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
143 #define SI_NUM_VERTEX_BUFFERS 16
146 /* This represents resource descriptors in memory, such as buffer resources,
147 * image resources, and sampler states.
149 struct si_descriptors {
150 struct r600_atom atom;
152 /* The size of one resource descriptor. */
153 unsigned element_dw_size;
154 /* The maximum number of resource descriptors. */
155 unsigned num_elements;
157 /* The buffer where resource descriptors are stored. */
158 struct r600_resource *buffer;
159 unsigned buffer_offset;
161 /* The i-th bit is set if that element is dirty (changed but not emitted). */
163 /* The i-th bit is set if that element is enabled (non-NULL resource). */
164 uint64_t enabled_mask;
166 /* We can't update descriptors directly because the GPU might be
167 * reading them at the same time, so we have to update them
168 * in a copy-on-write manner. Each such copy is called a context,
169 * which is just another array descriptors in the same buffer. */
170 unsigned current_context_id;
171 /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
172 unsigned context_size;
174 /* The shader userdata register where the 64-bit pointer to the descriptor
175 * array will be stored. */
176 unsigned shader_userdata_reg;
179 struct si_sampler_views {
180 struct si_descriptors desc;
181 struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS];
182 uint32_t *desc_data[SI_NUM_SAMPLER_VIEWS];
185 struct si_sampler_states {
186 struct si_descriptors desc;
187 uint32_t *desc_data[SI_NUM_SAMPLER_STATES];
188 void *saved_states[2]; /* saved for u_blitter */
191 struct si_buffer_resources {
192 struct si_descriptors desc;
193 unsigned num_buffers;
194 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
195 enum radeon_bo_priority priority;
196 struct pipe_resource **buffers; /* this has num_buffers elements */
197 uint32_t *desc_storage; /* this has num_buffers*4 elements */
198 uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
201 #define si_pm4_block_idx(member) \
202 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
204 #define si_pm4_state_changed(sctx, member) \
205 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
207 #define si_pm4_bind_state(sctx, member, value) \
209 (sctx)->queued.named.member = (value); \
212 #define si_pm4_delete_state(sctx, member, value) \
214 if ((sctx)->queued.named.member == (value)) { \
215 (sctx)->queued.named.member = NULL; \
217 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
218 si_pm4_block_idx(member)); \
221 #define si_pm4_set_state(sctx, member, value) \
223 if ((sctx)->queued.named.member != (value)) { \
224 si_pm4_free_state(sctx, \
225 (struct si_pm4_state *)(sctx)->queued.named.member, \
226 si_pm4_block_idx(member)); \
227 (sctx)->queued.named.member = (value); \
231 /* si_descriptors.c */
232 void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
233 unsigned start, unsigned count, void **states);
234 void si_update_vertex_buffers(struct si_context *sctx);
235 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
236 struct pipe_resource *buffer,
237 unsigned stride, unsigned num_records,
238 bool add_tid, bool swizzle,
239 unsigned element_size, unsigned index_stride);
240 void si_init_all_descriptors(struct si_context *sctx);
241 void si_release_all_descriptors(struct si_context *sctx);
242 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
243 void si_copy_buffer(struct si_context *sctx,
244 struct pipe_resource *dst, struct pipe_resource *src,
245 uint64_t dst_offset, uint64_t src_offset, unsigned size, bool is_framebuffer);
246 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
247 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
250 struct si_shader_selector;
252 boolean si_is_format_supported(struct pipe_screen *screen,
253 enum pipe_format format,
254 enum pipe_texture_target target,
255 unsigned sample_count,
257 void si_init_state_functions(struct si_context *sctx);
258 void si_init_config(struct si_context *sctx);
259 unsigned cik_bank_wh(unsigned bankwh);
260 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
261 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
262 unsigned cik_tile_split(unsigned tile_split);
263 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
264 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
266 /* si_state_shader.c */
267 void si_update_shaders(struct si_context *sctx);
268 void si_init_shader_functions(struct si_context *sctx);
270 /* si_state_draw.c */
271 extern const struct r600_atom si_atom_cache_flush;
272 extern const struct r600_atom si_atom_msaa_sample_locs;
273 extern const struct r600_atom si_atom_msaa_config;
274 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
275 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
278 void si_cmd_context_control(struct si_pm4_state *pm4);