2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_MAX_ATTRIBS 16
39 struct si_state_blend {
40 struct si_pm4_state pm4;
41 uint32_t cb_target_mask;
42 bool alpha_to_coverage;
45 /* Set 0xf or 0x0 (4 bits) per render target if the following is
46 * true. ANDed with spi_shader_col_format.
48 unsigned blend_enable_4bit;
49 unsigned need_src_alpha_4bit;
52 struct si_state_rasterizer {
53 struct si_pm4_state pm4;
54 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
55 struct si_pm4_state pm4_poly_offset[3];
58 bool multisample_enable;
59 bool force_persample_interp;
60 bool line_stipple_enable;
61 unsigned sprite_coord_enable;
62 unsigned pa_sc_line_stipple;
63 unsigned pa_cl_clip_cntl;
64 unsigned clip_plane_enable;
65 bool poly_stipple_enable;
68 bool uses_poly_offset;
69 bool clamp_fragment_color;
70 bool rasterizer_discard;
73 struct si_dsa_stencil_ref_part {
79 struct si_pm4_state pm4;
81 struct si_dsa_stencil_ref_part stencil_ref;
84 struct si_stencil_ref {
85 struct r600_atom atom;
86 struct pipe_stencil_ref state;
87 struct si_dsa_stencil_ref_part dsa_part;
90 struct si_vertex_element
93 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
94 uint32_t format_size[SI_MAX_ATTRIBS];
95 struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
100 struct si_state_blend *blend;
101 struct si_state_rasterizer *rasterizer;
102 struct si_state_dsa *dsa;
103 struct si_pm4_state *poly_offset;
104 struct si_pm4_state *ls;
105 struct si_pm4_state *hs;
106 struct si_pm4_state *es;
107 struct si_pm4_state *gs;
108 struct si_pm4_state *vgt_shader_config;
109 struct si_pm4_state *vs;
110 struct si_pm4_state *ps;
112 struct si_pm4_state *array[0];
115 union si_state_atoms {
117 /* The order matters. */
118 struct r600_atom *cache_flush;
119 struct r600_atom *render_cond;
120 struct r600_atom *streamout_begin;
121 struct r600_atom *streamout_enable; /* must be after streamout_begin */
122 struct r600_atom *framebuffer;
123 struct r600_atom *msaa_sample_locs;
124 struct r600_atom *db_render_state;
125 struct r600_atom *msaa_config;
126 struct r600_atom *sample_mask;
127 struct r600_atom *cb_render_state;
128 struct r600_atom *blend_color;
129 struct r600_atom *clip_regs;
130 struct r600_atom *clip_state;
131 struct r600_atom *shader_userdata;
132 struct r600_atom *scissors;
133 struct r600_atom *viewports;
134 struct r600_atom *stencil_ref;
135 struct r600_atom *spi_map;
137 struct r600_atom *array[0];
140 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
142 struct si_shader_data {
143 struct r600_atom atom;
144 uint32_t sh_base[SI_NUM_SHADERS];
147 /* User sampler views: 0..15
148 * Polygon stipple tex: 16
150 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
151 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
152 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
154 /* User constant buffers: 0..15
155 * Driver state constants: 16
157 #define SI_NUM_USER_CONST_BUFFERS 16
158 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
159 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
161 /* Read-write buffer slots.
164 * Streamout buffers: 2..5
166 #define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */
167 #define SI_RING_ESGS 0 /* for ES, GS */
168 #define SI_RING_GSVS 1 /* for GS, VS */
169 #define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */
170 #define SI_RING_GSVS_2 3
171 #define SI_RING_GSVS_3 4
172 #define SI_NUM_RING_BUFFERS 5
173 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
174 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
176 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
179 /* This represents descriptors in memory, such as buffer resources,
180 * image resources, and sampler states.
182 struct si_descriptors {
183 /* The list of descriptors in malloc'd memory. */
185 /* The size of one descriptor. */
186 unsigned element_dw_size;
187 /* The maximum number of descriptors. */
188 unsigned num_elements;
189 /* Whether the list has been changed and should be re-uploaded. */
192 /* The buffer where the descriptors have been uploaded. */
193 struct r600_resource *buffer;
194 unsigned buffer_offset;
196 /* The i-th bit is set if that element is enabled (non-NULL resource). */
197 uint64_t enabled_mask;
199 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
200 * array will be stored. */
201 unsigned shader_userdata_offset;
202 /* Whether the pointer should be re-emitted. */
206 struct si_sampler_views {
207 struct si_descriptors desc;
208 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
209 void *sampler_states[SI_NUM_SAMPLERS];
212 struct si_buffer_resources {
213 struct si_descriptors desc;
214 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
215 enum radeon_bo_priority priority;
216 struct pipe_resource **buffers; /* this has num_buffers elements */
219 #define si_pm4_block_idx(member) \
220 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
222 #define si_pm4_state_changed(sctx, member) \
223 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
225 #define si_pm4_bind_state(sctx, member, value) \
227 (sctx)->queued.named.member = (value); \
230 #define si_pm4_delete_state(sctx, member, value) \
232 if ((sctx)->queued.named.member == (value)) { \
233 (sctx)->queued.named.member = NULL; \
235 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
236 si_pm4_block_idx(member)); \
239 /* si_descriptors.c */
240 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
241 struct pipe_resource *buffer,
242 unsigned stride, unsigned num_records,
243 bool add_tid, bool swizzle,
244 unsigned element_size, unsigned index_stride, uint64_t offset);
245 void si_init_all_descriptors(struct si_context *sctx);
246 bool si_upload_shader_descriptors(struct si_context *sctx);
247 void si_release_all_descriptors(struct si_context *sctx);
248 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
249 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
250 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
251 void si_shader_change_notify(struct si_context *sctx);
252 void si_update_compressed_colortex_masks(struct si_context *sctx);
253 void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom);
256 struct si_shader_selector;
258 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
259 struct r600_atom **list_elem,
260 void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
261 boolean si_is_format_supported(struct pipe_screen *screen,
262 enum pipe_format format,
263 enum pipe_texture_target target,
264 unsigned sample_count,
266 void si_init_state_functions(struct si_context *sctx);
267 void si_init_screen_state_functions(struct si_screen *sscreen);
268 unsigned cik_bank_wh(unsigned bankwh);
269 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
270 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
271 unsigned cik_tile_split(unsigned tile_split);
272 unsigned si_array_mode(unsigned mode);
273 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
274 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
275 struct pipe_sampler_view *
276 si_create_sampler_view_custom(struct pipe_context *ctx,
277 struct pipe_resource *texture,
278 const struct pipe_sampler_view *state,
279 unsigned width0, unsigned height0,
280 unsigned force_level);
282 /* si_state_shader.c */
283 bool si_update_shaders(struct si_context *sctx);
284 void si_init_shader_functions(struct si_context *sctx);
285 bool si_init_shader_cache(struct si_screen *sscreen);
286 void si_destroy_shader_cache(struct si_screen *sscreen);
288 /* si_state_draw.c */
289 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
290 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
291 void si_trace_emit(struct si_context *sctx);