2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
38 struct si_state_blend {
39 struct si_pm4_state pm4;
40 uint32_t cb_target_mask;
45 struct si_state_sample_mask {
46 struct si_pm4_state pm4;
50 struct si_state_scissor {
51 struct si_pm4_state pm4;
52 struct pipe_scissor_state scissor;
55 struct si_state_viewport {
56 struct si_pm4_state pm4;
57 struct pipe_viewport_state viewport;
60 struct si_state_rasterizer {
61 struct si_pm4_state pm4;
64 bool multisample_enable;
65 bool line_stipple_enable;
66 unsigned sprite_coord_enable;
67 unsigned pa_sc_line_stipple;
68 unsigned pa_cl_clip_cntl;
69 unsigned clip_plane_enable;
72 bool poly_stipple_enable;
78 struct si_pm4_state pm4;
84 struct si_vertex_element
87 uint32_t rsrc_word3[PIPE_MAX_ATTRIBS];
88 uint32_t format_size[PIPE_MAX_ATTRIBS];
89 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
94 struct si_state_blend *blend;
95 struct si_pm4_state *blend_color;
96 struct si_pm4_state *clip;
97 struct si_state_sample_mask *sample_mask;
98 struct si_state_scissor *scissor[16];
99 struct si_state_viewport *viewport[16];
100 struct si_state_rasterizer *rasterizer;
101 struct si_state_dsa *dsa;
102 struct si_pm4_state *fb_rs;
103 struct si_pm4_state *fb_blend;
104 struct si_pm4_state *dsa_stencil_ref;
105 struct si_pm4_state *ta_bordercolor_base;
106 struct si_pm4_state *ls;
107 struct si_pm4_state *hs;
108 struct si_pm4_state *es;
109 struct si_pm4_state *gs;
110 struct si_pm4_state *gs_rings;
111 struct si_pm4_state *tf_ring;
112 struct si_pm4_state *vgt_shader_config;
113 struct si_pm4_state *vs;
114 struct si_pm4_state *ps;
115 struct si_pm4_state *spi;
117 struct si_pm4_state *array[0];
120 struct si_shader_data {
121 struct r600_atom atom;
122 uint32_t sh_base[SI_NUM_SHADERS];
125 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
126 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
127 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
129 /* User sampler views: 0..15
130 * Polygon stipple tex: 16
131 * FMASK sampler views: 17..33 (no sampler states)
133 #define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
134 #define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
135 #define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
137 /* User constant buffers: 0..15
138 * Driver state constants: 16
140 #define SI_NUM_USER_CONST_BUFFERS 16
141 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
142 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
144 /* Read-write buffer slots.
147 * Streamout buffers: 2..5
149 #define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */
150 #define SI_RING_ESGS 0 /* for ES, GS */
151 #define SI_RING_GSVS 1 /* for GS, VS */
152 #define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */
153 #define SI_RING_GSVS_2 3
154 #define SI_RING_GSVS_3 4
155 #define SI_NUM_RING_BUFFERS 5
156 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
157 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
159 #define SI_NUM_VERTEX_BUFFERS 16
162 /* This represents descriptors in memory, such as buffer resources,
163 * image resources, and sampler states.
165 struct si_descriptors {
166 /* The list of descriptors in malloc'd memory. */
168 /* The size of one descriptor. */
169 unsigned element_dw_size;
170 /* The maximum number of descriptors. */
171 unsigned num_elements;
172 /* Whether the list has been changed and should be re-uploaded. */
175 /* The buffer where the descriptors have been uploaded. */
176 struct r600_resource *buffer;
177 unsigned buffer_offset;
179 /* The i-th bit is set if that element is enabled (non-NULL resource). */
180 uint64_t enabled_mask;
182 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
183 * array will be stored. */
184 unsigned shader_userdata_offset;
185 /* Whether the pointer should be re-emitted. */
189 struct si_sampler_views {
190 struct si_descriptors desc;
191 struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS];
194 struct si_sampler_states {
195 struct si_descriptors desc;
196 void *saved_states[2]; /* saved for u_blitter */
199 struct si_buffer_resources {
200 struct si_descriptors desc;
201 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
202 enum radeon_bo_priority priority;
203 struct pipe_resource **buffers; /* this has num_buffers elements */
206 #define si_pm4_block_idx(member) \
207 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
209 #define si_pm4_state_changed(sctx, member) \
210 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
212 #define si_pm4_bind_state(sctx, member, value) \
214 (sctx)->queued.named.member = (value); \
217 #define si_pm4_delete_state(sctx, member, value) \
219 if ((sctx)->queued.named.member == (value)) { \
220 (sctx)->queued.named.member = NULL; \
222 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
223 si_pm4_block_idx(member)); \
226 #define si_pm4_set_state(sctx, member, value) \
228 if ((sctx)->queued.named.member != (value)) { \
229 si_pm4_free_state(sctx, \
230 (struct si_pm4_state *)(sctx)->queued.named.member, \
231 si_pm4_block_idx(member)); \
232 (sctx)->queued.named.member = (value); \
236 /* si_descriptors.c */
237 void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
238 unsigned start, unsigned count, void **states);
239 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
240 struct pipe_resource *buffer,
241 unsigned stride, unsigned num_records,
242 bool add_tid, bool swizzle,
243 unsigned element_size, unsigned index_stride, uint64_t offset);
244 void si_init_all_descriptors(struct si_context *sctx);
245 bool si_upload_shader_descriptors(struct si_context *sctx);
246 void si_release_all_descriptors(struct si_context *sctx);
247 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
248 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
249 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
250 void si_shader_change_notify(struct si_context *sctx);
253 struct si_shader_selector;
255 void si_update_fb_blend_state(struct si_context *sctx);
256 boolean si_is_format_supported(struct pipe_screen *screen,
257 enum pipe_format format,
258 enum pipe_texture_target target,
259 unsigned sample_count,
261 void si_init_state_functions(struct si_context *sctx);
262 unsigned cik_bank_wh(unsigned bankwh);
263 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
264 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
265 unsigned cik_tile_split(unsigned tile_split);
266 unsigned si_array_mode(unsigned mode);
267 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
268 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
269 struct pipe_sampler_view *
270 si_create_sampler_view_custom(struct pipe_context *ctx,
271 struct pipe_resource *texture,
272 const struct pipe_sampler_view *state,
273 unsigned width0, unsigned height0,
274 unsigned force_level);
276 /* si_state_shader.c */
277 void si_update_shaders(struct si_context *sctx);
278 void si_init_shader_functions(struct si_context *sctx);
280 /* si_state_draw.c */
281 extern const struct r600_atom si_atom_cache_flush;
282 extern const struct r600_atom si_atom_msaa_sample_locs;
283 extern const struct r600_atom si_atom_msaa_config;
284 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
285 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
286 void si_trace_emit(struct si_context *sctx);
289 void si_cmd_context_control(struct si_pm4_state *pm4);