src/gallium/drivers/radeonsi/si_state_draw.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "si_shader.h"
  29 #include "radeon/r600_cs.h"
  30 #include "sid.h"
  31
  32 #include "util/u_index_modify.h"
  33 #include "util/u_upload_mgr.h"
  34 #include "util/u_prim.h"
  35 #include "util/u_memory.h"
  36
  37 static unsigned si_conv_pipe_prim(unsigned mode)
  38 {
  39         static const unsigned prim_conv[] = {
  40                 [PIPE_PRIM_POINTS]                      = V_008958_DI_PT_POINTLIST,
  41                 [PIPE_PRIM_LINES]                       = V_008958_DI_PT_LINELIST,
  42                 [PIPE_PRIM_LINE_LOOP]                   = V_008958_DI_PT_LINELOOP,
  43                 [PIPE_PRIM_LINE_STRIP]                  = V_008958_DI_PT_LINESTRIP,
  44                 [PIPE_PRIM_TRIANGLES]                   = V_008958_DI_PT_TRILIST,
  45                 [PIPE_PRIM_TRIANGLE_STRIP]              = V_008958_DI_PT_TRISTRIP,
  46                 [PIPE_PRIM_TRIANGLE_FAN]                = V_008958_DI_PT_TRIFAN,
  47                 [PIPE_PRIM_QUADS]                       = V_008958_DI_PT_QUADLIST,
  48                 [PIPE_PRIM_QUAD_STRIP]                  = V_008958_DI_PT_QUADSTRIP,
  49                 [PIPE_PRIM_POLYGON]                     = V_008958_DI_PT_POLYGON,
  50                 [PIPE_PRIM_LINES_ADJACENCY]             = V_008958_DI_PT_LINELIST_ADJ,
  51                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = V_008958_DI_PT_LINESTRIP_ADJ,
  52                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = V_008958_DI_PT_TRILIST_ADJ,
  53                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = V_008958_DI_PT_TRISTRIP_ADJ,
  54                 [PIPE_PRIM_PATCHES]                     = V_008958_DI_PT_PATCH,
  55                 [R600_PRIM_RECTANGLE_LIST]              = V_008958_DI_PT_RECTLIST
  56         };
  57         assert(mode < ARRAY_SIZE(prim_conv));
  58         return prim_conv[mode];
  59 }
  60
  61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
  62 {
  63         static const int prim_conv[] = {
  64                 [PIPE_PRIM_POINTS]                      = V_028A6C_OUTPRIM_TYPE_POINTLIST,
  65                 [PIPE_PRIM_LINES]                       = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
  66                 [PIPE_PRIM_LINE_LOOP]                   = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
  67                 [PIPE_PRIM_LINE_STRIP]                  = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
  68                 [PIPE_PRIM_TRIANGLES]                   = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  69                 [PIPE_PRIM_TRIANGLE_STRIP]              = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  70                 [PIPE_PRIM_TRIANGLE_FAN]                = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  71                 [PIPE_PRIM_QUADS]                       = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  72                 [PIPE_PRIM_QUAD_STRIP]                  = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  73                 [PIPE_PRIM_POLYGON]                     = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  74                 [PIPE_PRIM_LINES_ADJACENCY]             = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
  75                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
  76                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  77                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
  78                 [PIPE_PRIM_PATCHES]                     = V_028A6C_OUTPRIM_TYPE_POINTLIST,
  79                 [R600_PRIM_RECTANGLE_LIST]              = V_028A6C_OUTPRIM_TYPE_TRISTRIP
  80         };
  81         assert(mode < ARRAY_SIZE(prim_conv));
  82
  83         return prim_conv[mode];
  84 }
  85
  86 /**
  87  * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
  88  * LS.LDS_SIZE is shared by all 3 shader stages.
  89  *
  90  * The information about LDS and other non-compile-time parameters is then
  91  * written to userdata SGPRs.
  92  */
  93 static void si_emit_derived_tess_state(struct si_context *sctx,
  94                                        const struct pipe_draw_info *info,
  95                                        unsigned *num_patches)
  96 {
  97         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  98         struct si_shader_ctx_state *ls = &sctx->vs_shader;
  99         /* The TES pointer will only be used for sctx->last_tcs.
 100          * It would be wrong to think that TCS = TES. */
 101         struct si_shader_selector *tcs =
 102                 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
 103         unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
 104         unsigned num_tcs_input_cp = info->vertices_per_patch;
 105         unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
 106         unsigned num_tcs_patch_outputs;
 107         unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
 108         unsigned input_patch_size, output_patch_size, output_patch0_offset;
 109         unsigned perpatch_output_offset, lds_size, ls_rsrc2;
 110         unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
 111         unsigned offchip_layout, hardware_lds_size;
 112
 113         /* This calculates how shader inputs and outputs among VS, TCS, and TES
 114          * are laid out in LDS. */
 115         num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
 116
 117         if (sctx->tcs_shader.cso) {
 118                 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
 119                 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
 120                 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
 121         } else {
 122                 /* No TCS. Route varyings from LS to TES. */
 123                 num_tcs_outputs = num_tcs_inputs;
 124                 num_tcs_output_cp = num_tcs_input_cp;
 125                 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
 126         }
 127
 128         input_vertex_size = num_tcs_inputs * 16;
 129         output_vertex_size = num_tcs_outputs * 16;
 130
 131         input_patch_size = num_tcs_input_cp * input_vertex_size;
 132
 133         pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
 134         output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
 135
 136         /* Ensure that we only need one wave per SIMD so we don't need to check
 137          * resource usage. Also ensures that the number of tcs in and out
 138          * vertices per threadgroup are at most 256.
 139          */
 140         *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
 141
 142         /* Make sure that the data fits in LDS. This assumes the shaders only
 143          * use LDS for the inputs and outputs.
 144          */
 145         hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
 146         *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
 147                                                                output_patch_size));
 148
 149         /* Make sure the output data fits in the offchip buffer */
 150         *num_patches = MIN2(*num_patches,
 151                             (sctx->screen->tess_offchip_block_dw_size * 4) /
 152                             output_patch_size);
 153
 154         /* Not necessary for correctness, but improves performance. The
 155          * specific value is taken from the proprietary driver.
 156          */
 157         *num_patches = MIN2(*num_patches, 40);
 158
 159         output_patch0_offset = input_patch_size * *num_patches;
 160         perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
 161
 162         lds_size = output_patch0_offset + output_patch_size * *num_patches;
 163         ls_rsrc2 = ls->current->config.rsrc2;
 164
 165         if (sctx->b.chip_class >= CIK) {
 166                 assert(lds_size <= 65536);
 167                 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
 168         } else {
 169                 assert(lds_size <= 32768);
 170                 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
 171         }
 172
 173         if (sctx->last_ls == ls->current &&
 174             sctx->last_tcs == tcs &&
 175             sctx->last_tes_sh_base == tes_sh_base &&
 176             sctx->last_num_tcs_input_cp == num_tcs_input_cp)
 177                 return;
 178
 179         sctx->last_ls = ls->current;
 180         sctx->last_tcs = tcs;
 181         sctx->last_tes_sh_base = tes_sh_base;
 182         sctx->last_num_tcs_input_cp = num_tcs_input_cp;
 183
 184         /* Due to a hw bug, RSRC2_LS must be written twice with another
 185          * LS register written in between. */
 186         if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
 187                 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
 188         radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
 189         radeon_emit(cs, ls->current->config.rsrc1);
 190         radeon_emit(cs, ls_rsrc2);
 191
 192         /* Compute userdata SGPRs. */
 193         assert(((input_vertex_size / 4) & ~0xff) == 0);
 194         assert(((output_vertex_size / 4) & ~0xff) == 0);
 195         assert(((input_patch_size / 4) & ~0x1fff) == 0);
 196         assert(((output_patch_size / 4) & ~0x1fff) == 0);
 197         assert(((output_patch0_offset / 16) & ~0xffff) == 0);
 198         assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
 199         assert(num_tcs_input_cp <= 32);
 200         assert(num_tcs_output_cp <= 32);
 201
 202         tcs_in_layout = (input_patch_size / 4) |
 203                         ((input_vertex_size / 4) << 13);
 204         tcs_out_layout = (output_patch_size / 4) |
 205                          ((output_vertex_size / 4) << 13);
 206         tcs_out_offsets = (output_patch0_offset / 16) |
 207                           ((perpatch_output_offset / 16) << 16);
 208         offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
 209                          (num_tcs_output_cp << 9) | *num_patches;
 210
 211         /* Set them for LS. */
 212         radeon_set_sh_reg(cs,
 213                 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
 214                 tcs_in_layout);
 215
 216         /* Set them for TCS. */
 217         radeon_set_sh_reg_seq(cs,
 218                 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
 219         radeon_emit(cs, offchip_layout);
 220         radeon_emit(cs, tcs_out_offsets);
 221         radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
 222         radeon_emit(cs, tcs_in_layout);
 223
 224         /* Set them for TES. */
 225         radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
 226         radeon_emit(cs, offchip_layout);
 227 }
 228
 229 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
 230 {
 231         switch (info->mode) {
 232         case PIPE_PRIM_PATCHES:
 233                 return info->count / info->vertices_per_patch;
 234         case R600_PRIM_RECTANGLE_LIST:
 235                 return info->count / 3;
 236         default:
 237                 return u_prims_for_vertices(info->mode, info->count);
 238         }
 239 }
 240
 241 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 242                                           const struct pipe_draw_info *info,
 243                                           unsigned num_patches)
 244 {
 245         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
 246         unsigned prim = info->mode;
 247         unsigned primgroup_size = 128; /* recommended without a GS */
 248         unsigned max_primgroup_in_wave = 2;
 249
 250         /* SWITCH_ON_EOP(0) is always preferable. */
 251         bool wd_switch_on_eop = false;
 252         bool ia_switch_on_eop = false;
 253         bool ia_switch_on_eoi = false;
 254         bool partial_vs_wave = false;
 255         bool partial_es_wave = false;
 256
 257         if (sctx->gs_shader.cso)
 258                 primgroup_size = 64; /* recommended with a GS */
 259
 260         if (sctx->tes_shader.cso) {
 261                 /* primgroup_size must be set to a multiple of NUM_PATCHES */
 262                 primgroup_size = num_patches;
 263
 264                 /* SWITCH_ON_EOI must be set if PrimID is used. */
 265                 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
 266                     sctx->tes_shader.cso->info.uses_primid)
 267                         ia_switch_on_eoi = true;
 268
 269                 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
 270                 if ((sctx->b.family == CHIP_TAHITI ||
 271                      sctx->b.family == CHIP_PITCAIRN ||
 272                      sctx->b.family == CHIP_BONAIRE) &&
 273                     sctx->gs_shader.cso)
 274                         partial_vs_wave = true;
 275
 276                 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
 277                 if (sctx->screen->has_distributed_tess) {
 278                         if (sctx->gs_shader.cso)
 279                                 partial_es_wave = true;
 280                         else
 281                                 partial_vs_wave = true;
 282                 }
 283         }
 284
 285         /* This is a hardware requirement. */
 286         if ((rs && rs->line_stipple_enable) ||
 287             (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
 288                 ia_switch_on_eop = true;
 289                 wd_switch_on_eop = true;
 290         }
 291
 292         if (sctx->b.chip_class >= CIK) {
 293                 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
 294                  * 4 shader engines. Set 1 to pass the assertion below.
 295                  * The other cases are hardware requirements.
 296                  *
 297                  * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
 298                  * for points, line strips, and tri strips.
 299                  */
 300                 if (sctx->b.screen->info.max_se < 4 ||
 301                     prim == PIPE_PRIM_POLYGON ||
 302                     prim == PIPE_PRIM_LINE_LOOP ||
 303                     prim == PIPE_PRIM_TRIANGLE_FAN ||
 304                     prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
 305                     (info->primitive_restart &&
 306                      (sctx->b.family < CHIP_POLARIS10 ||
 307                       (prim != PIPE_PRIM_POINTS &&
 308                        prim != PIPE_PRIM_LINE_STRIP &&
 309                        prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
 310                     info->count_from_stream_output)
 311                         wd_switch_on_eop = true;
 312
 313                 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
 314                  * We don't know that for indirect drawing, so treat it as
 315                  * always problematic. */
 316                 if (sctx->b.family == CHIP_HAWAII &&
 317                     (info->indirect || info->instance_count > 1))
 318                         wd_switch_on_eop = true;
 319
 320                 /* Performance recommendation for 4 SE Gfx7-8 parts if
 321                  * instances are smaller than a primgroup. Ignore the fact
 322                  * primgroup_size is a primitive count, not vertex count.
 323                  * Don't do anything for indirect draws.
 324                  */
 325                 if (sctx->b.chip_class <= VI &&
 326                     sctx->b.screen->info.max_se >= 4 &&
 327                     !info->indirect &&
 328                     info->instance_count > 1 && info->count < primgroup_size)
 329                         wd_switch_on_eop = true;
 330
 331                 /* Required on CIK and later. */
 332                 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
 333                         ia_switch_on_eoi = true;
 334
 335                 /* Required by Hawaii and, for some special cases, by VI. */
 336                 if (ia_switch_on_eoi &&
 337                     (sctx->b.family == CHIP_HAWAII ||
 338                      (sctx->b.chip_class == VI &&
 339                       (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
 340                         partial_vs_wave = true;
 341
 342                 /* Instancing bug on Bonaire. */
 343                 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
 344                     (info->indirect || info->instance_count > 1))
 345                         partial_vs_wave = true;
 346
 347                 /* If the WD switch is false, the IA switch must be false too. */
 348                 assert(wd_switch_on_eop || !ia_switch_on_eop);
 349         }
 350
 351         /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
 352         if (ia_switch_on_eoi)
 353                 partial_es_wave = true;
 354
 355         /* GS requirement. */
 356         if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
 357                 partial_es_wave = true;
 358
 359         /* Hw bug with single-primitive instances and SWITCH_ON_EOI
 360          * on multi-SE chips. */
 361         if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
 362             (info->indirect ||
 363              (info->instance_count > 1 &&
 364               si_num_prims_for_vertices(info) <= 1)))
 365                 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
 366
 367         return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
 368                 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
 369                 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
 370                 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
 371                 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
 372                 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
 373                 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
 374                                              max_primgroup_in_wave : 0);
 375 }
 376
 377 static unsigned si_get_ls_hs_config(struct si_context *sctx,
 378                                     const struct pipe_draw_info *info,
 379                                     unsigned num_patches)
 380 {
 381         unsigned num_output_cp;
 382
 383         if (!sctx->tes_shader.cso)
 384                 return 0;
 385
 386         num_output_cp = sctx->tcs_shader.cso ?
 387                 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
 388                 info->vertices_per_patch;
 389
 390         return S_028B58_NUM_PATCHES(num_patches) |
 391                 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
 392                 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
 393 }
 394
 395 static void si_emit_scratch_reloc(struct si_context *sctx)
 396 {
 397         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 398
 399         if (!sctx->emit_scratch_reloc)
 400                 return;
 401
 402         radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
 403                                sctx->spi_tmpring_size);
 404
 405         if (sctx->scratch_buffer) {
 406                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 407                                       sctx->scratch_buffer, RADEON_USAGE_READWRITE,
 408                                       RADEON_PRIO_SCRATCH_BUFFER);
 409
 410         }
 411         sctx->emit_scratch_reloc = false;
 412 }
 413
 414 /* rast_prim is the primitive type after GS. */
 415 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
 416 {
 417         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 418         unsigned rast_prim = sctx->current_rast_prim;
 419         struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
 420
 421         /* Skip this if not rendering lines. */
 422         if (rast_prim != PIPE_PRIM_LINES &&
 423             rast_prim != PIPE_PRIM_LINE_LOOP &&
 424             rast_prim != PIPE_PRIM_LINE_STRIP &&
 425             rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
 426             rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
 427                 return;
 428
 429         if (rast_prim == sctx->last_rast_prim &&
 430             rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
 431                 return;
 432
 433         /* For lines, reset the stipple pattern at each primitive. Otherwise,
 434          * reset the stipple pattern at each packet (line strips, line loops).
 435          */
 436         radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
 437                 rs->pa_sc_line_stipple |
 438                 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
 439
 440         sctx->last_rast_prim = rast_prim;
 441         sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
 442 }
 443
 444 static void si_emit_draw_registers(struct si_context *sctx,
 445                                    const struct pipe_draw_info *info)
 446 {
 447         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 448         unsigned prim = si_conv_pipe_prim(info->mode);
 449         unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
 450         unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
 451
 452         /* Polaris needs different VTX_REUSE_DEPTH settings depending on
 453          * whether the "fractional odd" tessellation spacing is used.
 454          */
 455         if (sctx->b.family >= CHIP_POLARIS10) {
 456                 struct si_shader_selector *tes = sctx->tes_shader.cso;
 457                 unsigned vtx_reuse_depth = 30;
 458
 459                 if (tes &&
 460                     tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
 461                     PIPE_TESS_SPACING_FRACTIONAL_ODD)
 462                         vtx_reuse_depth = 14;
 463
 464                 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
 465                         radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
 466                                                vtx_reuse_depth);
 467                         sctx->last_vtx_reuse_depth = vtx_reuse_depth;
 468                 }
 469         }
 470
 471         if (sctx->tes_shader.cso)
 472                 si_emit_derived_tess_state(sctx, info, &num_patches);
 473
 474         ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
 475         ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
 476
 477         /* Draw state. */
 478         if (prim != sctx->last_prim ||
 479             ia_multi_vgt_param != sctx->last_multi_vgt_param ||
 480             ls_hs_config != sctx->last_ls_hs_config) {
 481                 if (sctx->b.chip_class >= CIK) {
 482                         radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
 483                         radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
 484                         radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
 485                 } else {
 486                         radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
 487                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
 488                         radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
 489                 }
 490
 491                 sctx->last_prim = prim;
 492                 sctx->last_multi_vgt_param = ia_multi_vgt_param;
 493                 sctx->last_ls_hs_config = ls_hs_config;
 494         }
 495
 496         if (gs_out_prim != sctx->last_gs_out_prim) {
 497                 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
 498                 sctx->last_gs_out_prim = gs_out_prim;
 499         }
 500
 501         /* Primitive restart. */
 502         if (info->primitive_restart != sctx->last_primitive_restart_en) {
 503                 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
 504                 sctx->last_primitive_restart_en = info->primitive_restart;
 505
 506                 if (info->primitive_restart &&
 507                     (info->restart_index != sctx->last_restart_index ||
 508                      sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
 509                         radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
 510                                                info->restart_index);
 511                         sctx->last_restart_index = info->restart_index;
 512                 }
 513         }
 514 }
 515
 516 static void si_emit_draw_packets(struct si_context *sctx,
 517                                  const struct pipe_draw_info *info,
 518                                  const struct pipe_index_buffer *ib)
 519 {
 520         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 521         unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
 522         bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
 523         uint32_t index_max_size = 0;
 524         uint64_t index_va = 0;
 525
 526         if (info->count_from_stream_output) {
 527                 struct r600_so_target *t =
 528                         (struct r600_so_target*)info->count_from_stream_output;
 529                 uint64_t va = t->buf_filled_size->gpu_address +
 530                               t->buf_filled_size_offset;
 531
 532                 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
 533                                        t->stride_in_dw);
 534
 535                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 536                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 537                             COPY_DATA_DST_SEL(COPY_DATA_REG) |
 538                             COPY_DATA_WR_CONFIRM);
 539                 radeon_emit(cs, va);     /* src address lo */
 540                 radeon_emit(cs, va >> 32); /* src address hi */
 541                 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
 542                 radeon_emit(cs, 0); /* unused */
 543
 544                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 545                                       t->buf_filled_size, RADEON_USAGE_READ,
 546                                       RADEON_PRIO_SO_FILLED_SIZE);
 547         }
 548
 549         /* draw packet */
 550         if (info->indexed) {
 551                 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
 552
 553                 /* index type */
 554                 switch (ib->index_size) {
 555                 case 1:
 556                         radeon_emit(cs, V_028A7C_VGT_INDEX_8);
 557                         break;
 558                 case 2:
 559                         radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
 560                                     (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
 561                                              V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
 562                         break;
 563                 case 4:
 564                         radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
 565                                     (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
 566                                              V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
 567                         break;
 568                 default:
 569                         assert(!"unreachable");
 570                         return;
 571                 }
 572
 573                 index_max_size = (ib->buffer->width0 - ib->offset) /
 574                                   ib->index_size;
 575                 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
 576
 577                 assert(index_va % 2 == 0);
 578
 579                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 580                                       (struct r600_resource *)ib->buffer,
 581                                       RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
 582         }
 583
 584         if (!info->indirect) {
 585                 int base_vertex;
 586
 587                 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
 588                 radeon_emit(cs, info->instance_count);
 589
 590                 /* Base vertex and start instance. */
 591                 base_vertex = info->indexed ? info->index_bias : info->start;
 592
 593                 if (base_vertex != sctx->last_base_vertex ||
 594                     sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
 595                     info->start_instance != sctx->last_start_instance ||
 596                     sh_base_reg != sctx->last_sh_base_reg) {
 597                         radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
 598                         radeon_emit(cs, base_vertex);
 599                         radeon_emit(cs, info->start_instance);
 600
 601                         sctx->last_base_vertex = base_vertex;
 602                         sctx->last_start_instance = info->start_instance;
 603                         sctx->last_sh_base_reg = sh_base_reg;
 604                 }
 605         } else {
 606                 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
 607
 608                 assert(indirect_va % 8 == 0);
 609
 610                 si_invalidate_draw_sh_constants(sctx);
 611
 612                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
 613                 radeon_emit(cs, 1);
 614                 radeon_emit(cs, indirect_va);
 615                 radeon_emit(cs, indirect_va >> 32);
 616
 617                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 618                                       (struct r600_resource *)info->indirect,
 619                                       RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 620         }
 621
 622         if (info->indirect) {
 623                 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
 624                                                     : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 625
 626                 assert(info->indirect_offset % 4 == 0);
 627
 628                 if (info->indexed) {
 629                         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
 630                         radeon_emit(cs, index_va);
 631                         radeon_emit(cs, index_va >> 32);
 632
 633                         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
 634                         radeon_emit(cs, index_max_size);
 635                 }
 636
 637                 if (!sctx->screen->has_draw_indirect_multi) {
 638                         radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
 639                                                            : PKT3_DRAW_INDIRECT,
 640                                              3, render_cond_bit));
 641                         radeon_emit(cs, info->indirect_offset);
 642                         radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
 643                         radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
 644                         radeon_emit(cs, di_src_sel);
 645                 } else {
 646                         radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
 647                                                              PKT3_DRAW_INDIRECT_MULTI,
 648                                              8, render_cond_bit));
 649                         radeon_emit(cs, info->indirect_offset);
 650                         radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
 651                         radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
 652                         radeon_emit(cs, 0); /* draw_index */
 653                         radeon_emit(cs, 1); /* count */
 654                         radeon_emit(cs, 0); /* count_addr -- disabled */
 655                         radeon_emit(cs, 0);
 656                         radeon_emit(cs, 16); /* stride */
 657                         radeon_emit(cs, di_src_sel);
 658                 }
 659         } else {
 660                 if (info->indexed) {
 661                         index_va += info->start * ib->index_size;
 662
 663                         radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
 664                         radeon_emit(cs, index_max_size);
 665                         radeon_emit(cs, index_va);
 666                         radeon_emit(cs, (index_va >> 32UL) & 0xFF);
 667                         radeon_emit(cs, info->count);
 668                         radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
 669                 } else {
 670                         radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
 671                         radeon_emit(cs, info->count);
 672                         radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
 673                                         S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
 674                 }
 675         }
 676 }
 677
 678 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
 679 {
 680         struct r600_common_context *sctx = &si_ctx->b;
 681         struct radeon_winsys_cs *cs = sctx->gfx.cs;
 682         uint32_t cp_coher_cntl = 0;
 683
 684         /* SI has a bug that it always flushes ICACHE and KCACHE if either
 685          * bit is set. An alternative way is to write SQC_CACHES, but that
 686          * doesn't seem to work reliably. Since the bug doesn't affect
 687          * correctness (it only does more work than necessary) and
 688          * the performance impact is likely negligible, there is no plan
 689          * to add a workaround for it.
 690          */
 691
 692         if (sctx->flags & SI_CONTEXT_INV_ICACHE)
 693                 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
 694         if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
 695                 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
 696
 697         if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
 698                 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
 699         if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
 700                 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
 701
 702                 if (sctx->chip_class >= VI)
 703                         cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
 704         }
 705
 706         if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
 707                 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
 708                                  S_0085F0_CB0_DEST_BASE_ENA(1) |
 709                                  S_0085F0_CB1_DEST_BASE_ENA(1) |
 710                                  S_0085F0_CB2_DEST_BASE_ENA(1) |
 711                                  S_0085F0_CB3_DEST_BASE_ENA(1) |
 712                                  S_0085F0_CB4_DEST_BASE_ENA(1) |
 713                                  S_0085F0_CB5_DEST_BASE_ENA(1) |
 714                                  S_0085F0_CB6_DEST_BASE_ENA(1) |
 715                                  S_0085F0_CB7_DEST_BASE_ENA(1);
 716
 717                 /* Necessary for DCC */
 718                 if (sctx->chip_class >= VI) {
 719                         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
 720                         radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
 721                                         EVENT_INDEX(5));
 722                         radeon_emit(cs, 0);
 723                         radeon_emit(cs, 0);
 724                         radeon_emit(cs, 0);
 725                         radeon_emit(cs, 0);
 726                 }
 727         }
 728         if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
 729                 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
 730                                  S_0085F0_DB_DEST_BASE_ENA(1);
 731         }
 732
 733         if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
 734                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 735                 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
 736                 /* needed for wait for idle in SURFACE_SYNC */
 737                 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
 738         }
 739         if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
 740                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 741                 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
 742                 /* needed for wait for idle in SURFACE_SYNC */
 743                 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
 744         }
 745
 746         /* Wait for shader engines to go idle.
 747          * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
 748          * for everything including CB/DB cache flushes.
 749          */
 750         if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
 751                              SI_CONTEXT_FLUSH_AND_INV_DB))) {
 752                 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
 753                         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 754                         radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
 755                 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
 756                         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 757                         radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
 758                 }
 759         }
 760         if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
 761                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 762                 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
 763         }
 764
 765         /* VGT state synchronization. */
 766         if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
 767                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 768                 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
 769         }
 770         if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
 771                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 772                 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
 773         }
 774
 775         /* Make sure ME is idle (it executes most packets) before continuing.
 776          * This prevents read-after-write hazards between PFP and ME.
 777          */
 778         if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
 779                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 780                 radeon_emit(cs, 0);
 781         }
 782
 783         /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
 784          * Therefore, it should be last. Done in PFP.
 785          */
 786         if (cp_coher_cntl) {
 787                 /* ACQUIRE_MEM is only required on a compute ring. */
 788                 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
 789                 radeon_emit(cs, cp_coher_cntl);   /* CP_COHER_CNTL */
 790                 radeon_emit(cs, 0xffffffff);      /* CP_COHER_SIZE */
 791                 radeon_emit(cs, 0);               /* CP_COHER_BASE */
 792                 radeon_emit(cs, 0x0000000A);      /* POLL_INTERVAL */
 793         }
 794
 795         if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
 796                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 797                 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
 798                                 EVENT_INDEX(0));
 799         } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
 800                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 801                 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
 802                                 EVENT_INDEX(0));
 803         }
 804
 805         sctx->flags = 0;
 806 }
 807
 808 static void si_get_draw_start_count(struct si_context *sctx,
 809                                     const struct pipe_draw_info *info,
 810                                     unsigned *start, unsigned *count)
 811 {
 812         if (info->indirect) {
 813                 struct r600_resource *indirect =
 814                         (struct r600_resource*)info->indirect;
 815                 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
 816                                         indirect, PIPE_TRANSFER_READ);
 817                 data += info->indirect_offset/sizeof(int);
 818                 *start = data[2];
 819                 *count = data[0];
 820         } else {
 821                 *start = info->start;
 822                 *count = info->count;
 823         }
 824 }
 825
 826 void si_ce_pre_draw_synchronization(struct si_context *sctx)
 827 {
 828         if (sctx->ce_need_synchronization) {
 829                 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
 830                 radeon_emit(sctx->ce_ib, 1);
 831
 832                 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
 833                 radeon_emit(sctx->b.gfx.cs, 1);
 834         }
 835 }
 836
 837 void si_ce_post_draw_synchronization(struct si_context *sctx)
 838 {
 839         if (sctx->ce_need_synchronization) {
 840                 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
 841                 radeon_emit(sctx->b.gfx.cs, 0);
 842
 843                 sctx->ce_need_synchronization = false;
 844         }
 845 }
 846
 847 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 848 {
 849         struct si_context *sctx = (struct si_context *)ctx;
 850         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
 851         struct pipe_index_buffer ib = {};
 852         unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
 853
 854         if (!info->count && !info->indirect &&
 855             (info->indexed || !info->count_from_stream_output))
 856                 return;
 857
 858         if (!sctx->vs_shader.cso) {
 859                 assert(0);
 860                 return;
 861         }
 862         if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
 863                 assert(0);
 864                 return;
 865         }
 866         if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
 867                 assert(0);
 868                 return;
 869         }
 870
 871         /* Re-emit the framebuffer state if needed. */
 872         dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
 873         if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
 874                 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
 875                 sctx->framebuffer.dirty_cbufs |=
 876                         ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
 877                 sctx->framebuffer.dirty_zsbuf = true;
 878                 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
 879         }
 880
 881         /* Invalidate & recompute texture descriptors if needed. */
 882         dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
 883         if (dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter) {
 884                 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
 885                 si_update_all_texture_descriptors(sctx);
 886         }
 887
 888         si_decompress_graphics_textures(sctx);
 889
 890         /* Set the rasterization primitive type.
 891          *
 892          * This must be done after si_decompress_textures, which can call
 893          * draw_vbo recursively, and before si_update_shaders, which uses
 894          * current_rast_prim for this draw_vbo call. */
 895         if (sctx->gs_shader.cso)
 896                 rast_prim = sctx->gs_shader.cso->gs_output_prim;
 897         else if (sctx->tes_shader.cso)
 898                 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
 899         else
 900                 rast_prim = info->mode;
 901
 902         if (rast_prim != sctx->current_rast_prim) {
 903                 sctx->current_rast_prim = rast_prim;
 904                 sctx->do_update_shaders = true;
 905         }
 906
 907         if (sctx->do_update_shaders && !si_update_shaders(sctx))
 908                 return;
 909
 910         if (!si_upload_graphics_shader_descriptors(sctx))
 911                 return;
 912
 913         if (info->indexed) {
 914                 /* Initialize the index buffer struct. */
 915                 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
 916                 ib.user_buffer = sctx->index_buffer.user_buffer;
 917                 ib.index_size = sctx->index_buffer.index_size;
 918                 ib.offset = sctx->index_buffer.offset;
 919
 920                 /* Translate or upload, if needed. */
 921                 /* 8-bit indices are supported on VI. */
 922                 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
 923                         struct pipe_resource *out_buffer = NULL;
 924                         unsigned out_offset, start, count, start_offset;
 925                         void *ptr;
 926
 927                         si_get_draw_start_count(sctx, info, &start, &count);
 928                         start_offset = start * ib.index_size;
 929
 930                         u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
 931                                        &out_offset, &out_buffer, &ptr);
 932                         if (!out_buffer) {
 933                                 pipe_resource_reference(&ib.buffer, NULL);
 934                                 return;
 935                         }
 936
 937                         util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
 938                                                            ib.offset + start_offset,
 939                                                            count, ptr);
 940
 941                         pipe_resource_reference(&ib.buffer, NULL);
 942                         ib.user_buffer = NULL;
 943                         ib.buffer = out_buffer;
 944                         /* info->start will be added by the drawing code */
 945                         ib.offset = out_offset - start_offset;
 946                         ib.index_size = 2;
 947                 } else if (ib.user_buffer && !ib.buffer) {
 948                         unsigned start, count, start_offset;
 949
 950                         si_get_draw_start_count(sctx, info, &start, &count);
 951                         start_offset = start * ib.index_size;
 952
 953                         u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
 954                                       256, (char*)ib.user_buffer + start_offset,
 955                                       &ib.offset, &ib.buffer);
 956                         if (!ib.buffer)
 957                                 return;
 958                         /* info->start will be added by the drawing code */
 959                         ib.offset -= start_offset;
 960                 }
 961         }
 962
 963         /* VI reads index buffers through TC L2. */
 964         if (info->indexed && sctx->b.chip_class <= CIK &&
 965             r600_resource(ib.buffer)->TC_L2_dirty) {
 966                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 967                 r600_resource(ib.buffer)->TC_L2_dirty = false;
 968         }
 969
 970         /* Check flush flags. */
 971         if (sctx->b.flags)
 972                 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
 973
 974         /* Add buffer sizes for memory checking in need_cs_space. */
 975         if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
 976                 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
 977         if (info->indirect)
 978                 r600_context_add_resource_size(ctx, info->indirect);
 979
 980         si_need_cs_space(sctx);
 981
 982         /* Since we've called r600_context_add_resource_size for vertex buffers,
 983          * this must be called after si_need_cs_space, because we must let
 984          * need_cs_space flush before we add buffers to the buffer list.
 985          */
 986         if (!si_upload_vertex_buffer_descriptors(sctx))
 987                 return;
 988
 989         /* Emit states. */
 990         mask = sctx->dirty_atoms;
 991         while (mask) {
 992                 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
 993
 994                 atom->emit(&sctx->b, atom);
 995         }
 996         sctx->dirty_atoms = 0;
 997
 998         si_pm4_emit_dirty(sctx);
 999         si_emit_scratch_reloc(sctx);
1000         si_emit_rasterizer_prim_state(sctx);
1001         si_emit_draw_registers(sctx, info);
1002
1003         si_ce_pre_draw_synchronization(sctx);
1004
1005         si_emit_draw_packets(sctx, info, &ib);
1006
1007         si_ce_post_draw_synchronization(sctx);
1008
1009         if (sctx->trace_buf)
1010                 si_trace_emit(sctx);
1011
1012         /* Workaround for a VGT hang when streamout is enabled.
1013          * It must be done after drawing. */
1014         if ((sctx->b.family == CHIP_HAWAII ||
1015              sctx->b.family == CHIP_TONGA ||
1016              sctx->b.family == CHIP_FIJI) &&
1017             r600_get_strmout_en(&sctx->b)) {
1018                 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1019         }
1020
1021         /* Set the depth buffer as dirty. */
1022         if (sctx->framebuffer.state.zsbuf) {
1023                 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1024                 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1025
1026                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1027
1028                 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1029                         rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1030         }
1031         if (sctx->framebuffer.compressed_cb_mask) {
1032                 struct pipe_surface *surf;
1033                 struct r600_texture *rtex;
1034                 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1035
1036                 do {
1037                         unsigned i = u_bit_scan(&mask);
1038                         surf = sctx->framebuffer.state.cbufs[i];
1039                         rtex = (struct r600_texture*)surf->texture;
1040
1041                         if (rtex->fmask.size)
1042                                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1043                         if (rtex->dcc_gather_statistics)
1044                                 rtex->separate_dcc_dirty = true;
1045                 } while (mask);
1046         }
1047
1048         pipe_resource_reference(&ib.buffer, NULL);
1049         sctx->b.num_draw_calls++;
1050         if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1051                 sctx->b.num_spill_draw_calls++;
1052 }
1053
1054 void si_trace_emit(struct si_context *sctx)
1055 {
1056         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1057
1058         sctx->trace_id++;
1059         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1060                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1061         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1062         radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1063                     S_370_WR_CONFIRM(1) |
1064                     S_370_ENGINE_SEL(V_370_ME));
1065         radeon_emit(cs, sctx->trace_buf->gpu_address);
1066         radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1067         radeon_emit(cs, sctx->trace_id);
1068         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1069         radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1070 }