src/gallium/drivers/radeonsi/si_state_shaders.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_build_pm4.h"
  26 #include "gfx9d.h"
  27
  28 #include "compiler/nir/nir_serialize.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/hash_table.h"
  31 #include "util/crc32.h"
  32 #include "util/u_async_debug.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_prim.h"
  35
  36 #include "util/disk_cache.h"
  37 #include "util/mesa-sha1.h"
  38 #include "ac_exp_param.h"
  39 #include "ac_shader_util.h"
  40
  41 /* SHADER_CACHE */
  42
  43 /**
  44  * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
  45  * size as integer.
  46  */
  47 void *si_get_ir_binary(struct si_shader_selector *sel)
  48 {
  49         struct blob blob;
  50         unsigned ir_size;
  51         void *ir_binary;
  52
  53         if (sel->tokens) {
  54                 ir_binary = sel->tokens;
  55                 ir_size = tgsi_num_tokens(sel->tokens) *
  56                                           sizeof(struct tgsi_token);
  57         } else {
  58                 assert(sel->nir);
  59
  60                 blob_init(&blob);
  61                 nir_serialize(&blob, sel->nir);
  62                 ir_binary = blob.data;
  63                 ir_size = blob.size;
  64         }
  65
  66         unsigned size = 4 + ir_size + sizeof(sel->so);
  67         char *result = (char*)MALLOC(size);
  68         if (!result)
  69                 return NULL;
  70
  71         *((uint32_t*)result) = size;
  72         memcpy(result + 4, ir_binary, ir_size);
  73         memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
  74
  75         if (sel->nir)
  76                 blob_finish(&blob);
  77
  78         return result;
  79 }
  80
  81 /** Copy "data" to "ptr" and return the next dword following copied data. */
  82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
  83 {
  84         /* data may be NULL if size == 0 */
  85         if (size)
  86                 memcpy(ptr, data, size);
  87         ptr += DIV_ROUND_UP(size, 4);
  88         return ptr;
  89 }
  90
  91 /** Read data from "ptr". Return the next dword following the data. */
  92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
  93 {
  94         memcpy(data, ptr, size);
  95         ptr += DIV_ROUND_UP(size, 4);
  96         return ptr;
  97 }
  98
  99 /**
 100  * Write the size as uint followed by the data. Return the next dword
 101  * following the copied data.
 102  */
 103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
 104 {
 105         *ptr++ = size;
 106         return write_data(ptr, data, size);
 107 }
 108
 109 /**
 110  * Read the size as uint followed by the data. Return both via parameters.
 111  * Return the next dword following the data.
 112  */
 113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
 114 {
 115         *size = *ptr++;
 116         assert(*data == NULL);
 117         if (!*size)
 118                 return ptr;
 119         *data = malloc(*size);
 120         return read_data(ptr, *data, *size);
 121 }
 122
 123 /**
 124  * Return the shader binary in a buffer. The first 4 bytes contain its size
 125  * as integer.
 126  */
 127 static void *si_get_shader_binary(struct si_shader *shader)
 128 {
 129         /* There is always a size of data followed by the data itself. */
 130         unsigned relocs_size = shader->binary.reloc_count *
 131                                sizeof(shader->binary.relocs[0]);
 132         unsigned disasm_size = shader->binary.disasm_string ?
 133                                strlen(shader->binary.disasm_string) + 1 : 0;
 134         unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
 135                                 strlen(shader->binary.llvm_ir_string) + 1 : 0;
 136         unsigned size =
 137                 4 + /* total size */
 138                 4 + /* CRC32 of the data below */
 139                 align(sizeof(shader->config), 4) +
 140                 align(sizeof(shader->info), 4) +
 141                 4 + align(shader->binary.code_size, 4) +
 142                 4 + align(shader->binary.rodata_size, 4) +
 143                 4 + align(relocs_size, 4) +
 144                 4 + align(disasm_size, 4) +
 145                 4 + align(llvm_ir_size, 4);
 146         void *buffer = CALLOC(1, size);
 147         uint32_t *ptr = (uint32_t*)buffer;
 148
 149         if (!buffer)
 150                 return NULL;
 151
 152         *ptr++ = size;
 153         ptr++; /* CRC32 is calculated at the end. */
 154
 155         ptr = write_data(ptr, &shader->config, sizeof(shader->config));
 156         ptr = write_data(ptr, &shader->info, sizeof(shader->info));
 157         ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
 158         ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
 159         ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
 160         ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
 161         ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
 162         assert((char *)ptr - (char *)buffer == size);
 163
 164         /* Compute CRC32. */
 165         ptr = (uint32_t*)buffer;
 166         ptr++;
 167         *ptr = util_hash_crc32(ptr + 1, size - 8);
 168
 169         return buffer;
 170 }
 171
 172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
 173 {
 174         uint32_t *ptr = (uint32_t*)binary;
 175         uint32_t size = *ptr++;
 176         uint32_t crc32 = *ptr++;
 177         unsigned chunk_size;
 178
 179         if (util_hash_crc32(ptr, size - 8) != crc32) {
 180                 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
 181                 return false;
 182         }
 183
 184         ptr = read_data(ptr, &shader->config, sizeof(shader->config));
 185         ptr = read_data(ptr, &shader->info, sizeof(shader->info));
 186         ptr = read_chunk(ptr, (void**)&shader->binary.code,
 187                          &shader->binary.code_size);
 188         ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
 189                          &shader->binary.rodata_size);
 190         ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
 191         shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
 192         ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
 193         ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
 194
 195         return true;
 196 }
 197
 198 /**
 199  * Insert a shader into the cache. It's assumed the shader is not in the cache.
 200  * Use si_shader_cache_load_shader before calling this.
 201  *
 202  * Returns false on failure, in which case the ir_binary should be freed.
 203  */
 204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
 205                                    struct si_shader *shader,
 206                                    bool insert_into_disk_cache)
 207 {
 208         void *hw_binary;
 209         struct hash_entry *entry;
 210         uint8_t key[CACHE_KEY_SIZE];
 211
 212         entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
 213         if (entry)
 214                 return false; /* already added */
 215
 216         hw_binary = si_get_shader_binary(shader);
 217         if (!hw_binary)
 218                 return false;
 219
 220         if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
 221                                     hw_binary) == NULL) {
 222                 FREE(hw_binary);
 223                 return false;
 224         }
 225
 226         if (sscreen->disk_shader_cache && insert_into_disk_cache) {
 227                 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
 228                                        *((uint32_t *)ir_binary), key);
 229                 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
 230                                *((uint32_t *) hw_binary), NULL);
 231         }
 232
 233         return true;
 234 }
 235
 236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
 237                                  struct si_shader *shader)
 238 {
 239         struct hash_entry *entry =
 240                 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
 241         if (!entry) {
 242                 if (sscreen->disk_shader_cache) {
 243                         unsigned char sha1[CACHE_KEY_SIZE];
 244                         size_t tg_size = *((uint32_t *) ir_binary);
 245
 246                         disk_cache_compute_key(sscreen->disk_shader_cache,
 247                                                ir_binary, tg_size, sha1);
 248
 249                         size_t binary_size;
 250                         uint8_t *buffer =
 251                                 disk_cache_get(sscreen->disk_shader_cache,
 252                                                sha1, &binary_size);
 253                         if (!buffer)
 254                                 return false;
 255
 256                         if (binary_size < sizeof(uint32_t) ||
 257                             *((uint32_t*)buffer) != binary_size) {
 258                                  /* Something has gone wrong discard the item
 259                                   * from the cache and rebuild/link from
 260                                   * source.
 261                                   */
 262                                 assert(!"Invalid radeonsi shader disk cache "
 263                                        "item!");
 264
 265                                 disk_cache_remove(sscreen->disk_shader_cache,
 266                                                   sha1);
 267                                 free(buffer);
 268
 269                                 return false;
 270                         }
 271
 272                         if (!si_load_shader_binary(shader, buffer)) {
 273                                 free(buffer);
 274                                 return false;
 275                         }
 276                         free(buffer);
 277
 278                         if (!si_shader_cache_insert_shader(sscreen, ir_binary,
 279                                                            shader, false))
 280                                 FREE(ir_binary);
 281                 } else {
 282                         return false;
 283                 }
 284         } else {
 285                 if (si_load_shader_binary(shader, entry->data))
 286                         FREE(ir_binary);
 287                 else
 288                         return false;
 289         }
 290         p_atomic_inc(&sscreen->num_shader_cache_hits);
 291         return true;
 292 }
 293
 294 static uint32_t si_shader_cache_key_hash(const void *key)
 295 {
 296         /* The first dword is the key size. */
 297         return util_hash_crc32(key, *(uint32_t*)key);
 298 }
 299
 300 static bool si_shader_cache_key_equals(const void *a, const void *b)
 301 {
 302         uint32_t *keya = (uint32_t*)a;
 303         uint32_t *keyb = (uint32_t*)b;
 304
 305         /* The first dword is the key size. */
 306         if (*keya != *keyb)
 307                 return false;
 308
 309         return memcmp(keya, keyb, *keya) == 0;
 310 }
 311
 312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
 313 {
 314         FREE((void*)entry->key);
 315         FREE(entry->data);
 316 }
 317
 318 bool si_init_shader_cache(struct si_screen *sscreen)
 319 {
 320         (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
 321         sscreen->shader_cache =
 322                 _mesa_hash_table_create(NULL,
 323                                         si_shader_cache_key_hash,
 324                                         si_shader_cache_key_equals);
 325
 326         return sscreen->shader_cache != NULL;
 327 }
 328
 329 void si_destroy_shader_cache(struct si_screen *sscreen)
 330 {
 331         if (sscreen->shader_cache)
 332                 _mesa_hash_table_destroy(sscreen->shader_cache,
 333                                          si_destroy_shader_cache_entry);
 334         mtx_destroy(&sscreen->shader_cache_mutex);
 335 }
 336
 337 /* SHADER STATES */
 338
 339 static void si_set_tesseval_regs(struct si_screen *sscreen,
 340                                  struct si_shader_selector *tes,
 341                                  struct si_pm4_state *pm4)
 342 {
 343         struct tgsi_shader_info *info = &tes->info;
 344         unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
 345         unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
 346         bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
 347         bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
 348         unsigned type, partitioning, topology, distribution_mode;
 349
 350         switch (tes_prim_mode) {
 351         case PIPE_PRIM_LINES:
 352                 type = V_028B6C_TESS_ISOLINE;
 353                 break;
 354         case PIPE_PRIM_TRIANGLES:
 355                 type = V_028B6C_TESS_TRIANGLE;
 356                 break;
 357         case PIPE_PRIM_QUADS:
 358                 type = V_028B6C_TESS_QUAD;
 359                 break;
 360         default:
 361                 assert(0);
 362                 return;
 363         }
 364
 365         switch (tes_spacing) {
 366         case PIPE_TESS_SPACING_FRACTIONAL_ODD:
 367                 partitioning = V_028B6C_PART_FRAC_ODD;
 368                 break;
 369         case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
 370                 partitioning = V_028B6C_PART_FRAC_EVEN;
 371                 break;
 372         case PIPE_TESS_SPACING_EQUAL:
 373                 partitioning = V_028B6C_PART_INTEGER;
 374                 break;
 375         default:
 376                 assert(0);
 377                 return;
 378         }
 379
 380         if (tes_point_mode)
 381                 topology = V_028B6C_OUTPUT_POINT;
 382         else if (tes_prim_mode == PIPE_PRIM_LINES)
 383                 topology = V_028B6C_OUTPUT_LINE;
 384         else if (tes_vertex_order_cw)
 385                 /* for some reason, this must be the other way around */
 386                 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
 387         else
 388                 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 389
 390         if (sscreen->has_distributed_tess) {
 391                 if (sscreen->info.family == CHIP_FIJI ||
 392                     sscreen->info.family >= CHIP_POLARIS10)
 393                         distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
 394                 else
 395                         distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
 396         } else
 397                 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
 398
 399         assert(pm4->shader);
 400         pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
 401                                     S_028B6C_PARTITIONING(partitioning) |
 402                                     S_028B6C_TOPOLOGY(topology) |
 403                                     S_028B6C_DISTRIBUTION_MODE(distribution_mode);
 404 }
 405
 406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
 407  * whether the "fractional odd" tessellation spacing is used.
 408  *
 409  * Possible VGT configurations and which state should set the register:
 410  *
 411  *   Reg set in | VGT shader configuration   | Value
 412  * ------------------------------------------------------
 413  *     VS as VS | VS                         | 30
 414  *     VS as ES | ES -> GS -> VS             | 30
 415  *    TES as VS | LS -> HS -> VS             | 14 or 30
 416  *    TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
 417  *
 418  * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
 419  */
 420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
 421                                          struct si_shader_selector *sel,
 422                                          struct si_shader *shader,
 423                                          struct si_pm4_state *pm4)
 424 {
 425         unsigned type = sel->type;
 426
 427         if (sscreen->info.family < CHIP_POLARIS10)
 428                 return;
 429
 430         /* VS as VS, or VS as ES: */
 431         if ((type == PIPE_SHADER_VERTEX &&
 432              (!shader ||
 433               (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
 434             /* TES as VS, or TES as ES: */
 435             type == PIPE_SHADER_TESS_EVAL) {
 436                 unsigned vtx_reuse_depth = 30;
 437
 438                 if (type == PIPE_SHADER_TESS_EVAL &&
 439                     sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
 440                     PIPE_TESS_SPACING_FRACTIONAL_ODD)
 441                         vtx_reuse_depth = 14;
 442
 443                 assert(pm4->shader);
 444                 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
 445         }
 446 }
 447
 448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
 449 {
 450         if (shader->pm4)
 451                 si_pm4_clear_state(shader->pm4);
 452         else
 453                 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
 454
 455         if (shader->pm4) {
 456                 shader->pm4->shader = shader;
 457                 return shader->pm4;
 458         } else {
 459                 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
 460                 return NULL;
 461         }
 462 }
 463
 464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
 465 {
 466         /* Add the pointer to VBO descriptors. */
 467         if (HAVE_32BIT_POINTERS) {
 468                 return num_always_on_user_sgprs + 1;
 469         } else {
 470                 assert(num_always_on_user_sgprs % 2 == 0);
 471                 return num_always_on_user_sgprs + 2;
 472         }
 473 }
 474
 475 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
 476 {
 477         struct si_pm4_state *pm4;
 478         unsigned vgpr_comp_cnt;
 479         uint64_t va;
 480
 481         assert(sscreen->info.chip_class <= VI);
 482
 483         pm4 = si_get_shader_pm4_state(shader);
 484         if (!pm4)
 485                 return;
 486
 487         va = shader->bo->gpu_address;
 488         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 489
 490         /* We need at least 2 components for LS.
 491          * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
 492          * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
 493          */
 494         vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
 495
 496         si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
 497         si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
 498
 499         shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
 500                            S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
 501                            S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
 502                            S_00B528_DX10_CLAMP(1) |
 503                            S_00B528_FLOAT_MODE(shader->config.float_mode);
 504         shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
 505                            S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
 506 }
 507
 508 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
 509 {
 510         struct si_pm4_state *pm4;
 511         uint64_t va;
 512         unsigned ls_vgpr_comp_cnt = 0;
 513
 514         pm4 = si_get_shader_pm4_state(shader);
 515         if (!pm4)
 516                 return;
 517
 518         va = shader->bo->gpu_address;
 519         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 520
 521         if (sscreen->info.chip_class >= GFX9) {
 522                 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
 523                 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
 524
 525                 /* We need at least 2 components for LS.
 526                  * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
 527                  * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
 528                  */
 529                 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
 530
 531                 unsigned num_user_sgprs =
 532                         si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
 533
 534                 shader->config.rsrc2 =
 535                         S_00B42C_USER_SGPR(num_user_sgprs) |
 536                         S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
 537                         S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
 538         } else {
 539                 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
 540                 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
 541
 542                 shader->config.rsrc2 =
 543                         S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
 544                         S_00B42C_OC_LDS_EN(1) |
 545                         S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
 546         }
 547
 548         si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
 549                        S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
 550                        S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
 551                        S_00B428_DX10_CLAMP(1) |
 552                        S_00B428_FLOAT_MODE(shader->config.float_mode) |
 553                        S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
 554
 555         if (sscreen->info.chip_class <= VI) {
 556                 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
 557                                shader->config.rsrc2);
 558         }
 559 }
 560
 561 static void si_emit_shader_es(struct si_context *sctx)
 562 {
 563         struct si_shader *shader = sctx->queued.named.es->shader;
 564         unsigned initial_cdw = sctx->gfx_cs->current.cdw;
 565
 566         if (!shader)
 567                 return;
 568
 569         radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
 570                                    SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
 571                                    shader->selector->esgs_itemsize / 4);
 572
 573         if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 574                 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
 575                                            SI_TRACKED_VGT_TF_PARAM,
 576                                            shader->vgt_tf_param);
 577
 578         if (shader->vgt_vertex_reuse_block_cntl)
 579                 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
 580                                            SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
 581                                            shader->vgt_vertex_reuse_block_cntl);
 582
 583         if (initial_cdw != sctx->gfx_cs->current.cdw)
 584                 sctx->context_roll_counter++;
 585 }
 586
 587 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
 588 {
 589         struct si_pm4_state *pm4;
 590         unsigned num_user_sgprs;
 591         unsigned vgpr_comp_cnt;
 592         uint64_t va;
 593         unsigned oc_lds_en;
 594
 595         assert(sscreen->info.chip_class <= VI);
 596
 597         pm4 = si_get_shader_pm4_state(shader);
 598         if (!pm4)
 599                 return;
 600
 601         pm4->atom.emit = si_emit_shader_es;
 602         va = shader->bo->gpu_address;
 603         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 604
 605         if (shader->selector->type == PIPE_SHADER_VERTEX) {
 606                 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
 607                 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
 608                 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
 609         } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
 610                 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
 611                 num_user_sgprs = SI_TES_NUM_USER_SGPR;
 612         } else
 613                 unreachable("invalid shader selector type");
 614
 615         oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
 616
 617         si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
 618         si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
 619         si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
 620                        S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
 621                        S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
 622                        S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
 623                        S_00B328_DX10_CLAMP(1) |
 624                        S_00B328_FLOAT_MODE(shader->config.float_mode));
 625         si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
 626                        S_00B32C_USER_SGPR(num_user_sgprs) |
 627                        S_00B32C_OC_LDS_EN(oc_lds_en) |
 628                        S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
 629
 630         if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 631                 si_set_tesseval_regs(sscreen, shader->selector, pm4);
 632
 633         polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
 634 }
 635
 636 static unsigned si_conv_prim_to_gs_out(unsigned mode)
 637 {
 638         static const int prim_conv[] = {
 639                 [PIPE_PRIM_POINTS]                      = V_028A6C_OUTPRIM_TYPE_POINTLIST,
 640                 [PIPE_PRIM_LINES]                       = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 641                 [PIPE_PRIM_LINE_LOOP]                   = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 642                 [PIPE_PRIM_LINE_STRIP]                  = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 643                 [PIPE_PRIM_TRIANGLES]                   = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 644                 [PIPE_PRIM_TRIANGLE_STRIP]              = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 645                 [PIPE_PRIM_TRIANGLE_FAN]                = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 646                 [PIPE_PRIM_QUADS]                       = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 647                 [PIPE_PRIM_QUAD_STRIP]                  = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 648                 [PIPE_PRIM_POLYGON]                     = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 649                 [PIPE_PRIM_LINES_ADJACENCY]             = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 650                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 651                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 652                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 653                 [PIPE_PRIM_PATCHES]                     = V_028A6C_OUTPRIM_TYPE_POINTLIST,
 654         };
 655         assert(mode < ARRAY_SIZE(prim_conv));
 656
 657         return prim_conv[mode];
 658 }
 659
 660 struct gfx9_gs_info {
 661         unsigned es_verts_per_subgroup;
 662         unsigned gs_prims_per_subgroup;
 663         unsigned gs_inst_prims_in_subgroup;
 664         unsigned max_prims_per_subgroup;
 665         unsigned lds_size;
 666 };
 667
 668 static void gfx9_get_gs_info(struct si_shader_selector *es,
 669                                    struct si_shader_selector *gs,
 670                                    struct gfx9_gs_info *out)
 671 {
 672         unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
 673         unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
 674         bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
 675                               input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
 676
 677         /* All these are in dwords: */
 678         /* We can't allow using the whole LDS, because GS waves compete with
 679          * other shader stages for LDS space. */
 680         const unsigned max_lds_size = 8 * 1024;
 681         const unsigned esgs_itemsize = es->esgs_itemsize / 4;
 682         unsigned esgs_lds_size;
 683
 684         /* All these are per subgroup: */
 685         const unsigned max_out_prims = 32 * 1024;
 686         const unsigned max_es_verts = 255;
 687         const unsigned ideal_gs_prims = 64;
 688         unsigned max_gs_prims, gs_prims;
 689         unsigned min_es_verts, es_verts, worst_case_es_verts;
 690
 691         if (uses_adjacency || gs_num_invocations > 1)
 692                 max_gs_prims = 127 / gs_num_invocations;
 693         else
 694                 max_gs_prims = 255;
 695
 696         /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
 697          * Make sure we don't go over the maximum value.
 698          */
 699         if (gs->gs_max_out_vertices > 0) {
 700                 max_gs_prims = MIN2(max_gs_prims,
 701                                     max_out_prims /
 702                                     (gs->gs_max_out_vertices * gs_num_invocations));
 703         }
 704         assert(max_gs_prims > 0);
 705
 706         /* If the primitive has adjacency, halve the number of vertices
 707          * that will be reused in multiple primitives.
 708          */
 709         min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
 710
 711         gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
 712         worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
 713
 714         /* Compute ESGS LDS size based on the worst case number of ES vertices
 715          * needed to create the target number of GS prims per subgroup.
 716          */
 717         esgs_lds_size = esgs_itemsize * worst_case_es_verts;
 718
 719         /* If total LDS usage is too big, refactor partitions based on ratio
 720          * of ESGS item sizes.
 721          */
 722         if (esgs_lds_size > max_lds_size) {
 723                 /* Our target GS Prims Per Subgroup was too large. Calculate
 724                  * the maximum number of GS Prims Per Subgroup that will fit
 725                  * into LDS, capped by the maximum that the hardware can support.
 726                  */
 727                 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
 728                                 max_gs_prims);
 729                 assert(gs_prims > 0);
 730                 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
 731                                            max_es_verts);
 732
 733                 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
 734                 assert(esgs_lds_size <= max_lds_size);
 735         }
 736
 737         /* Now calculate remaining ESGS information. */
 738         if (esgs_lds_size)
 739                 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
 740         else
 741                 es_verts = max_es_verts;
 742
 743         /* Vertices for adjacency primitives are not always reused, so restore
 744          * it for ES_VERTS_PER_SUBGRP.
 745          */
 746         min_es_verts = gs->gs_input_verts_per_prim;
 747
 748         /* For normal primitives, the VGT only checks if they are past the ES
 749          * verts per subgroup after allocating a full GS primitive and if they
 750          * are, kick off a new subgroup.  But if those additional ES verts are
 751          * unique (e.g. not reused) we need to make sure there is enough LDS
 752          * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
 753          */
 754         es_verts -= min_es_verts - 1;
 755
 756         out->es_verts_per_subgroup = es_verts;
 757         out->gs_prims_per_subgroup = gs_prims;
 758         out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
 759         out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
 760                                       gs->gs_max_out_vertices;
 761         out->lds_size = align(esgs_lds_size, 128) / 128;
 762
 763         assert(out->max_prims_per_subgroup <= max_out_prims);
 764 }
 765
 766 static void si_emit_shader_gs(struct si_context *sctx)
 767 {
 768         struct si_shader *shader = sctx->queued.named.gs->shader;
 769         unsigned initial_cdw = sctx->gfx_cs->current.cdw;
 770
 771         if (!shader)
 772                 return;
 773
 774         /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
 775          * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
 776         radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
 777                                     SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
 778                                     shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
 779                                     shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
 780                                     shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
 781                                     shader->ctx_reg.gs.vgt_gs_out_prim_type);
 782
 783
 784         /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
 785         radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
 786                                    SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
 787                                    shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
 788
 789         /* R_028B38_VGT_GS_MAX_VERT_OUT */
 790         radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
 791                                    SI_TRACKED_VGT_GS_MAX_VERT_OUT,
 792                                    shader->ctx_reg.gs.vgt_gs_max_vert_out);
 793
 794         /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
 795          * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
 796         radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
 797                                     SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
 798                                     shader->ctx_reg.gs.vgt_gs_vert_itemsize,
 799                                     shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
 800                                     shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
 801                                     shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
 802
 803         /* R_028B90_VGT_GS_INSTANCE_CNT */
 804         radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
 805                                    SI_TRACKED_VGT_GS_INSTANCE_CNT,
 806                                    shader->ctx_reg.gs.vgt_gs_instance_cnt);
 807
 808         if (sctx->chip_class >= GFX9) {
 809                 /* R_028A44_VGT_GS_ONCHIP_CNTL */
 810                 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
 811                                            SI_TRACKED_VGT_GS_ONCHIP_CNTL,
 812                                            shader->ctx_reg.gs.vgt_gs_onchip_cntl);
 813                 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
 814                 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
 815                                            SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
 816                                            shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
 817                 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
 818                 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
 819                                            SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
 820                                            shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
 821
 822                 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
 823                         radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
 824                                                    SI_TRACKED_VGT_TF_PARAM,
 825                                                    shader->vgt_tf_param);
 826                 if (shader->vgt_vertex_reuse_block_cntl)
 827                         radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
 828                                                    SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
 829                                                    shader->vgt_vertex_reuse_block_cntl);
 830         }
 831
 832         if (initial_cdw != sctx->gfx_cs->current.cdw)
 833                 sctx->context_roll_counter++;
 834 }
 835
 836 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
 837 {
 838         struct si_shader_selector *sel = shader->selector;
 839         const ubyte *num_components = sel->info.num_stream_output_components;
 840         unsigned gs_num_invocations = sel->gs_num_invocations;
 841         struct si_pm4_state *pm4;
 842         uint64_t va;
 843         unsigned max_stream = sel->max_gs_stream;
 844         unsigned offset;
 845
 846         pm4 = si_get_shader_pm4_state(shader);
 847         if (!pm4)
 848                 return;
 849
 850         pm4->atom.emit = si_emit_shader_gs;
 851
 852         offset = num_components[0] * sel->gs_max_out_vertices;
 853         shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
 854
 855         if (max_stream >= 1)
 856                 offset += num_components[1] * sel->gs_max_out_vertices;
 857         shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
 858
 859         if (max_stream >= 2)
 860                 offset += num_components[2] * sel->gs_max_out_vertices;
 861         shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
 862
 863         shader->ctx_reg.gs.vgt_gs_out_prim_type =
 864                 si_conv_prim_to_gs_out(sel->gs_output_prim);
 865
 866         if (max_stream >= 3)
 867                 offset += num_components[3] * sel->gs_max_out_vertices;
 868         shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
 869
 870         /* The GSVS_RING_ITEMSIZE register takes 15 bits */
 871         assert(offset < (1 << 15));
 872
 873         shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
 874
 875         shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
 876         shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
 877         shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
 878         shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
 879
 880         shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
 881                                                  S_028B90_ENABLE(gs_num_invocations > 0);
 882
 883         va = shader->bo->gpu_address;
 884         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 885
 886         if (sscreen->info.chip_class >= GFX9) {
 887                 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
 888                 unsigned es_type = shader->key.part.gs.es->type;
 889                 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
 890                 struct gfx9_gs_info gs_info;
 891
 892                 if (es_type == PIPE_SHADER_VERTEX)
 893                         /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
 894                         es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
 895                 else if (es_type == PIPE_SHADER_TESS_EVAL)
 896                         es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
 897                 else
 898                         unreachable("invalid shader selector type");
 899
 900                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 901                  * VGPR[0:4] are always loaded.
 902                  */
 903                 if (sel->info.uses_invocationid)
 904                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 905                 else if (sel->info.uses_primid)
 906                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 907                 else if (input_prim >= PIPE_PRIM_TRIANGLES)
 908                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 909                 else
 910                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 911
 912                 unsigned num_user_sgprs;
 913                 if (es_type == PIPE_SHADER_VERTEX)
 914                         num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
 915                 else
 916                         num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
 917
 918                 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
 919
 920                 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
 921                 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
 922
 923                 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
 924                                S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
 925                                S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
 926                                S_00B228_DX10_CLAMP(1) |
 927                                S_00B228_FLOAT_MODE(shader->config.float_mode) |
 928                                S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
 929                 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
 930                                S_00B22C_USER_SGPR(num_user_sgprs) |
 931                                S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
 932                                S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 933                                S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
 934                                S_00B22C_LDS_SIZE(gs_info.lds_size) |
 935                                S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
 936
 937                 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
 938                         S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
 939                         S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
 940                         S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup);
 941                 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
 942                         S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup);
 943                 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
 944                         shader->key.part.gs.es->esgs_itemsize / 4;
 945
 946                 if (es_type == PIPE_SHADER_TESS_EVAL)
 947                         si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
 948
 949                 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
 950                                              NULL, pm4);
 951         } else {
 952                 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
 953                 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
 954
 955                 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
 956                                S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
 957                                S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
 958                                S_00B228_DX10_CLAMP(1) |
 959                                S_00B228_FLOAT_MODE(shader->config.float_mode));
 960                 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
 961                                S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
 962                                S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
 963         }
 964 }
 965
 966 static void si_emit_shader_vs(struct si_context *sctx)
 967 {
 968         struct si_shader *shader = sctx->queued.named.vs->shader;
 969         unsigned initial_cdw = sctx->gfx_cs->current.cdw;
 970
 971         if (!shader)
 972                 return;
 973
 974         radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
 975                                    SI_TRACKED_VGT_GS_MODE,
 976                                    shader->ctx_reg.vs.vgt_gs_mode);
 977         radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
 978                                    SI_TRACKED_VGT_PRIMITIVEID_EN,
 979                                    shader->ctx_reg.vs.vgt_primitiveid_en);
 980
 981         if (sctx->chip_class <= VI) {
 982                 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
 983                                            SI_TRACKED_VGT_REUSE_OFF,
 984                                            shader->ctx_reg.vs.vgt_reuse_off);
 985         }
 986
 987         radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
 988                                    SI_TRACKED_SPI_VS_OUT_CONFIG,
 989                                    shader->ctx_reg.vs.spi_vs_out_config);
 990
 991         radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
 992                                    SI_TRACKED_SPI_SHADER_POS_FORMAT,
 993                                    shader->ctx_reg.vs.spi_shader_pos_format);
 994
 995         radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
 996                                    SI_TRACKED_PA_CL_VTE_CNTL,
 997                                    shader->ctx_reg.vs.pa_cl_vte_cntl);
 998
 999         if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1000                 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1001                                            SI_TRACKED_VGT_TF_PARAM,
1002                                            shader->vgt_tf_param);
1003
1004         if (shader->vgt_vertex_reuse_block_cntl)
1005                 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1006                                            SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1007                                            shader->vgt_vertex_reuse_block_cntl);
1008
1009         if (initial_cdw != sctx->gfx_cs->current.cdw)
1010                 sctx->context_roll_counter++;
1011 }
1012
1013 /**
1014  * Compute the state for \p shader, which will run as a vertex shader on the
1015  * hardware.
1016  *
1017  * If \p gs is non-NULL, it points to the geometry shader for which this shader
1018  * is the copy shader.
1019  */
1020 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1021                          struct si_shader_selector *gs)
1022 {
1023         const struct tgsi_shader_info *info = &shader->selector->info;
1024         struct si_pm4_state *pm4;
1025         unsigned num_user_sgprs, vgpr_comp_cnt;
1026         uint64_t va;
1027         unsigned nparams, oc_lds_en;
1028         unsigned window_space =
1029                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1030         bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1031
1032         pm4 = si_get_shader_pm4_state(shader);
1033         if (!pm4)
1034                 return;
1035
1036         pm4->atom.emit = si_emit_shader_vs;
1037
1038         /* We always write VGT_GS_MODE in the VS state, because every switch
1039          * between different shader pipelines involving a different GS or no
1040          * GS at all involves a switch of the VS (different GS use different
1041          * copy shaders). On the other hand, when the API switches from a GS to
1042          * no GS and then back to the same GS used originally, the GS state is
1043          * not sent again.
1044          */
1045         if (!gs) {
1046                 unsigned mode = V_028A40_GS_OFF;
1047
1048                 /* PrimID needs GS scenario A. */
1049                 if (enable_prim_id)
1050                         mode = V_028A40_GS_SCENARIO_A;
1051
1052                 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1053                 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1054         } else {
1055                 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1056                                                                 sscreen->info.chip_class);
1057                 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1058         }
1059
1060         if (sscreen->info.chip_class <= VI) {
1061                 /* Reuse needs to be set off if we write oViewport. */
1062                 shader->ctx_reg.vs.vgt_reuse_off =
1063                                 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1064         }
1065
1066         va = shader->bo->gpu_address;
1067         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1068
1069         if (gs) {
1070                 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1071                 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1072         } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1073                 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1074                  * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1075                  * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1076                  */
1077                 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1078
1079                 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1080                         num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1081                                          info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1082                 } else {
1083                         num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1084                 }
1085         } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1086                 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1087                 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1088         } else
1089                 unreachable("invalid shader selector type");
1090
1091         /* VS is required to export at least one param. */
1092         nparams = MAX2(shader->info.nr_param_exports, 1);
1093         shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1094
1095         shader->ctx_reg.vs.spi_shader_pos_format =
1096                         S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1097                         S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1098                                                     V_02870C_SPI_SHADER_4COMP :
1099                                                     V_02870C_SPI_SHADER_NONE) |
1100                         S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1101                                                     V_02870C_SPI_SHADER_4COMP :
1102                                                     V_02870C_SPI_SHADER_NONE) |
1103                         S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1104                                                     V_02870C_SPI_SHADER_4COMP :
1105                                                     V_02870C_SPI_SHADER_NONE);
1106
1107         oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1108
1109         si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1110         si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1111         si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1112                        S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1113                        S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1114                        S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1115                        S_00B128_DX10_CLAMP(1) |
1116                        S_00B128_FLOAT_MODE(shader->config.float_mode));
1117         si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1118                        S_00B12C_USER_SGPR(num_user_sgprs) |
1119                        S_00B12C_OC_LDS_EN(oc_lds_en) |
1120                        S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1121                        S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1122                        S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1123                        S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1124                        S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1125                        S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1126
1127         if (window_space)
1128                 shader->ctx_reg.vs.pa_cl_vte_cntl =
1129                                 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1130         else
1131                 shader->ctx_reg.vs.pa_cl_vte_cntl =
1132                                 S_028818_VTX_W0_FMT(1) |
1133                                 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1134                                 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1135                                 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1136
1137         if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1138                 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1139
1140         polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1141 }
1142
1143 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1144 {
1145         struct tgsi_shader_info *info = &ps->selector->info;
1146         unsigned num_colors = !!(info->colors_read & 0x0f) +
1147                               !!(info->colors_read & 0xf0);
1148         unsigned num_interp = ps->selector->info.num_inputs +
1149                               (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1150
1151         assert(num_interp <= 32);
1152         return MIN2(num_interp, 32);
1153 }
1154
1155 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1156 {
1157         unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1158         unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1159
1160         /* If the i-th target format is set, all previous target formats must
1161          * be non-zero to avoid hangs.
1162          */
1163         for (i = 0; i < num_targets; i++)
1164                 if (!(value & (0xf << (i * 4))))
1165                         value |= V_028714_SPI_SHADER_32_R << (i * 4);
1166
1167         return value;
1168 }
1169
1170 static void si_emit_shader_ps(struct si_context *sctx)
1171 {
1172         struct si_shader *shader = sctx->queued.named.ps->shader;
1173         unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1174
1175         if (!shader)
1176                 return;
1177
1178         /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1179         radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1180                                     SI_TRACKED_SPI_PS_INPUT_ENA,
1181                                     shader->ctx_reg.ps.spi_ps_input_ena,
1182                                     shader->ctx_reg.ps.spi_ps_input_addr);
1183
1184         radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1185                                    SI_TRACKED_SPI_BARYC_CNTL,
1186                                    shader->ctx_reg.ps.spi_baryc_cntl);
1187         radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1188                                    SI_TRACKED_SPI_PS_IN_CONTROL,
1189                                    shader->ctx_reg.ps.spi_ps_in_control);
1190
1191         /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1192         radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1193                                     SI_TRACKED_SPI_SHADER_Z_FORMAT,
1194                                     shader->ctx_reg.ps.spi_shader_z_format,
1195                                     shader->ctx_reg.ps.spi_shader_col_format);
1196
1197         radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1198                                    SI_TRACKED_CB_SHADER_MASK,
1199                                    shader->ctx_reg.ps.cb_shader_mask);
1200
1201         if (initial_cdw != sctx->gfx_cs->current.cdw)
1202                 sctx->context_roll_counter++;
1203 }
1204
1205 static void si_shader_ps(struct si_shader *shader)
1206 {
1207         struct tgsi_shader_info *info = &shader->selector->info;
1208         struct si_pm4_state *pm4;
1209         unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1210         unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1211         uint64_t va;
1212         unsigned input_ena = shader->config.spi_ps_input_ena;
1213
1214         /* we need to enable at least one of them, otherwise we hang the GPU */
1215         assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1216                G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1217                G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1218                G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1219                G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1220                G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1221                G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1222                G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1223         /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1224         assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1225                G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1226                G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1227                G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1228                G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1229
1230         /* Validate interpolation optimization flags (read as implications). */
1231         assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1232                (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1233                 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1234         assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1235                (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1236                 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1237         assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1238                (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1239                 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1240         assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1241                (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1242                 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1243         assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1244                (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1245                 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1246         assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1247                (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1248                 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1249
1250         /* Validate cases when the optimizations are off (read as implications). */
1251         assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1252                !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1253                !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1254         assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1255                !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1256                !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1257
1258         pm4 = si_get_shader_pm4_state(shader);
1259         if (!pm4)
1260                 return;
1261
1262         pm4->atom.emit = si_emit_shader_ps;
1263
1264         /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1265          * Possible vaules:
1266          * 0 -> Position = pixel center
1267          * 1 -> Position = pixel centroid
1268          * 2 -> Position = at sample position
1269          *
1270          * From GLSL 4.5 specification, section 7.1:
1271          *   "The variable gl_FragCoord is available as an input variable from
1272          *    within fragment shaders and it holds the window relative coordinates
1273          *    (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1274          *    value can be for any location within the pixel, or one of the
1275          *    fragment samples. The use of centroid does not further restrict
1276          *    this value to be inside the current primitive."
1277          *
1278          * Meaning that centroid has no effect and we can return anything within
1279          * the pixel. Thus, return the value at sample position, because that's
1280          * the most accurate one shaders can get.
1281          */
1282         spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1283
1284         if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1285             TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1286                 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1287
1288         spi_shader_col_format = si_get_spi_shader_col_format(shader);
1289         cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1290
1291         /* Ensure that some export memory is always allocated, for two reasons:
1292          *
1293          * 1) Correctness: The hardware ignores the EXEC mask if no export
1294          *    memory is allocated, so KILL and alpha test do not work correctly
1295          *    without this.
1296          * 2) Performance: Every shader needs at least a NULL export, even when
1297          *    it writes no color/depth output. The NULL export instruction
1298          *    stalls without this setting.
1299          *
1300          * Don't add this to CB_SHADER_MASK.
1301          */
1302         if (!spi_shader_col_format &&
1303             !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1304                 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1305
1306         shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1307         shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1308
1309         /* Set interpolation controls. */
1310         spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1311
1312         shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1313         shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1314         shader->ctx_reg.ps.spi_shader_z_format =
1315                         ac_get_spi_shader_z_format(info->writes_z,
1316                                                    info->writes_stencil,
1317                                                    info->writes_samplemask);
1318         shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1319         shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1320
1321         va = shader->bo->gpu_address;
1322         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1323         si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1324         si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1325
1326         si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1327                        S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1328                        S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1329                        S_00B028_DX10_CLAMP(1) |
1330                        S_00B028_FLOAT_MODE(shader->config.float_mode));
1331         si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1332                        S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1333                        S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1334                        S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1335 }
1336
1337 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1338                                      struct si_shader *shader)
1339 {
1340         switch (shader->selector->type) {
1341         case PIPE_SHADER_VERTEX:
1342                 if (shader->key.as_ls)
1343                         si_shader_ls(sscreen, shader);
1344                 else if (shader->key.as_es)
1345                         si_shader_es(sscreen, shader);
1346                 else
1347                         si_shader_vs(sscreen, shader, NULL);
1348                 break;
1349         case PIPE_SHADER_TESS_CTRL:
1350                 si_shader_hs(sscreen, shader);
1351                 break;
1352         case PIPE_SHADER_TESS_EVAL:
1353                 if (shader->key.as_es)
1354                         si_shader_es(sscreen, shader);
1355                 else
1356                         si_shader_vs(sscreen, shader, NULL);
1357                 break;
1358         case PIPE_SHADER_GEOMETRY:
1359                 si_shader_gs(sscreen, shader);
1360                 break;
1361         case PIPE_SHADER_FRAGMENT:
1362                 si_shader_ps(shader);
1363                 break;
1364         default:
1365                 assert(0);
1366         }
1367 }
1368
1369 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1370 {
1371         /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1372         if (sctx->queued.named.dsa)
1373                 return sctx->queued.named.dsa->alpha_func;
1374
1375         return PIPE_FUNC_ALWAYS;
1376 }
1377
1378 static void si_shader_selector_key_vs(struct si_context *sctx,
1379                                       struct si_shader_selector *vs,
1380                                       struct si_shader_key *key,
1381                                       struct si_vs_prolog_bits *prolog_key)
1382 {
1383         if (!sctx->vertex_elements ||
1384             vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1385                 return;
1386
1387         prolog_key->instance_divisor_is_one =
1388                 sctx->vertex_elements->instance_divisor_is_one;
1389         prolog_key->instance_divisor_is_fetched =
1390                 sctx->vertex_elements->instance_divisor_is_fetched;
1391
1392         /* Prefer a monolithic shader to allow scheduling divisions around
1393          * VBO loads. */
1394         if (prolog_key->instance_divisor_is_fetched)
1395                 key->opt.prefer_mono = 1;
1396
1397         unsigned count = MIN2(vs->info.num_inputs,
1398                               sctx->vertex_elements->count);
1399         memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1400 }
1401
1402 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1403                                          struct si_shader_selector *vs,
1404                                          struct si_shader_key *key)
1405 {
1406         struct si_shader_selector *ps = sctx->ps_shader.cso;
1407
1408         key->opt.clip_disable =
1409                 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1410                 (vs->info.clipdist_writemask ||
1411                  vs->info.writes_clipvertex) &&
1412                 !vs->info.culldist_writemask;
1413
1414         /* Find out if PS is disabled. */
1415         bool ps_disabled = true;
1416         if (ps) {
1417                 const struct si_state_blend *blend = sctx->queued.named.blend;
1418                 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1419                 bool ps_modifies_zs = ps->info.uses_kill ||
1420                                       ps->info.writes_z ||
1421                                       ps->info.writes_stencil ||
1422                                       ps->info.writes_samplemask ||
1423                                       alpha_to_coverage ||
1424                                       si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1425                 unsigned ps_colormask = si_get_total_colormask(sctx);
1426
1427                 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1428                               (!ps_colormask &&
1429                                !ps_modifies_zs &&
1430                                !ps->info.writes_memory);
1431         }
1432
1433         /* Find out which VS outputs aren't used by the PS. */
1434         uint64_t outputs_written = vs->outputs_written_before_ps;
1435         uint64_t inputs_read = 0;
1436
1437         /* Ignore outputs that are not passed from VS to PS. */
1438         outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1439                              (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1440                              (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1441
1442         if (!ps_disabled) {
1443                 inputs_read = ps->inputs_read;
1444         }
1445
1446         uint64_t linked = outputs_written & inputs_read;
1447
1448         key->opt.kill_outputs = ~linked & outputs_written;
1449 }
1450
1451 /* Compute the key for the hw shader variant */
1452 static inline void si_shader_selector_key(struct pipe_context *ctx,
1453                                           struct si_shader_selector *sel,
1454                                           struct si_shader_key *key)
1455 {
1456         struct si_context *sctx = (struct si_context *)ctx;
1457
1458         memset(key, 0, sizeof(*key));
1459
1460         switch (sel->type) {
1461         case PIPE_SHADER_VERTEX:
1462                 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1463
1464                 if (sctx->tes_shader.cso)
1465                         key->as_ls = 1;
1466                 else if (sctx->gs_shader.cso)
1467                         key->as_es = 1;
1468                 else {
1469                         si_shader_selector_key_hw_vs(sctx, sel, key);
1470
1471                         if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1472                                 key->mono.u.vs_export_prim_id = 1;
1473                 }
1474                 break;
1475         case PIPE_SHADER_TESS_CTRL:
1476                 if (sctx->chip_class >= GFX9) {
1477                         si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1478                                                   key, &key->part.tcs.ls_prolog);
1479                         key->part.tcs.ls = sctx->vs_shader.cso;
1480
1481                         /* When the LS VGPR fix is needed, monolithic shaders
1482                          * can:
1483                          *  - avoid initializing EXEC in both the LS prolog
1484                          *    and the LS main part when !vs_needs_prolog
1485                          *  - remove the fixup for unused input VGPRs
1486                          */
1487                         key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1488
1489                         /* The LS output / HS input layout can be communicated
1490                          * directly instead of via user SGPRs for merged LS-HS.
1491                          * The LS VGPR fix prefers this too.
1492                          */
1493                         key->opt.prefer_mono = 1;
1494                 }
1495
1496                 key->part.tcs.epilog.prim_mode =
1497                         sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1498                 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1499                         sel->tcs_info.tessfactors_are_def_in_all_invocs;
1500                 key->part.tcs.epilog.tes_reads_tess_factors =
1501                         sctx->tes_shader.cso->info.reads_tess_factors;
1502
1503                 if (sel == sctx->fixed_func_tcs_shader.cso)
1504                         key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1505                 break;
1506         case PIPE_SHADER_TESS_EVAL:
1507                 if (sctx->gs_shader.cso)
1508                         key->as_es = 1;
1509                 else {
1510                         si_shader_selector_key_hw_vs(sctx, sel, key);
1511
1512                         if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1513                                 key->mono.u.vs_export_prim_id = 1;
1514                 }
1515                 break;
1516         case PIPE_SHADER_GEOMETRY:
1517                 if (sctx->chip_class >= GFX9) {
1518                         if (sctx->tes_shader.cso) {
1519                                 key->part.gs.es = sctx->tes_shader.cso;
1520                         } else {
1521                                 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1522                                                           key, &key->part.gs.vs_prolog);
1523                                 key->part.gs.es = sctx->vs_shader.cso;
1524                                 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1525                         }
1526
1527                         /* Merged ES-GS can have unbalanced wave usage.
1528                          *
1529                          * ES threads are per-vertex, while GS threads are
1530                          * per-primitive. So without any amplification, there
1531                          * are fewer GS threads than ES threads, which can result
1532                          * in empty (no-op) GS waves. With too much amplification,
1533                          * there are more GS threads than ES threads, which
1534                          * can result in empty (no-op) ES waves.
1535                          *
1536                          * Non-monolithic shaders are implemented by setting EXEC
1537                          * at the beginning of shader parts, and don't jump to
1538                          * the end if EXEC is 0.
1539                          *
1540                          * Monolithic shaders use conditional blocks, so they can
1541                          * jump and skip empty waves of ES or GS. So set this to
1542                          * always use optimized variants, which are monolithic.
1543                          */
1544                         key->opt.prefer_mono = 1;
1545                 }
1546                 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1547                 break;
1548         case PIPE_SHADER_FRAGMENT: {
1549                 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1550                 struct si_state_blend *blend = sctx->queued.named.blend;
1551
1552                 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1553                     sel->info.colors_written == 0x1)
1554                         key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1555
1556                 if (blend) {
1557                         /* Select the shader color format based on whether
1558                          * blending or alpha are needed.
1559                          */
1560                         key->part.ps.epilog.spi_shader_col_format =
1561                                 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1562                                  sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1563                                 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1564                                  sctx->framebuffer.spi_shader_col_format_blend) |
1565                                 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1566                                  sctx->framebuffer.spi_shader_col_format_alpha) |
1567                                 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1568                                  sctx->framebuffer.spi_shader_col_format);
1569                         key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1570
1571                         /* The output for dual source blending should have
1572                          * the same format as the first output.
1573                          */
1574                         if (blend->dual_src_blend)
1575                                 key->part.ps.epilog.spi_shader_col_format |=
1576                                         (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1577                 } else
1578                         key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1579
1580                 /* If alpha-to-coverage is enabled, we have to export alpha
1581                  * even if there is no color buffer.
1582                  */
1583                 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1584                     blend && blend->alpha_to_coverage)
1585                         key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1586
1587                 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1588                  * to the range supported by the type if a channel has less
1589                  * than 16 bits and the export format is 16_ABGR.
1590                  */
1591                 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1592                         key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1593                         key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1594                 }
1595
1596                 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1597                 if (!key->part.ps.epilog.last_cbuf) {
1598                         key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1599                         key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1600                         key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1601                 }
1602
1603                 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1604                 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1605
1606                 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1607                 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1608
1609                 if (sctx->queued.named.blend) {
1610                         key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1611                                                            rs->multisample_enable;
1612                 }
1613
1614                 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1615                 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1616                                                            (is_line && rs->line_smooth)) &&
1617                                                           sctx->framebuffer.nr_samples <= 1;
1618                 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1619
1620                 if (sctx->ps_iter_samples > 1 &&
1621                     sel->info.reads_samplemask) {
1622                         key->part.ps.prolog.samplemask_log_ps_iter =
1623                                 util_logbase2(sctx->ps_iter_samples);
1624                 }
1625
1626                 if (rs->force_persample_interp &&
1627                     rs->multisample_enable &&
1628                     sctx->framebuffer.nr_samples > 1 &&
1629                     sctx->ps_iter_samples > 1) {
1630                         key->part.ps.prolog.force_persp_sample_interp =
1631                                 sel->info.uses_persp_center ||
1632                                 sel->info.uses_persp_centroid;
1633
1634                         key->part.ps.prolog.force_linear_sample_interp =
1635                                 sel->info.uses_linear_center ||
1636                                 sel->info.uses_linear_centroid;
1637                 } else if (rs->multisample_enable &&
1638                            sctx->framebuffer.nr_samples > 1) {
1639                         key->part.ps.prolog.bc_optimize_for_persp =
1640                                 sel->info.uses_persp_center &&
1641                                 sel->info.uses_persp_centroid;
1642                         key->part.ps.prolog.bc_optimize_for_linear =
1643                                 sel->info.uses_linear_center &&
1644                                 sel->info.uses_linear_centroid;
1645                 } else {
1646                         /* Make sure SPI doesn't compute more than 1 pair
1647                          * of (i,j), which is the optimization here. */
1648                         key->part.ps.prolog.force_persp_center_interp =
1649                                 sel->info.uses_persp_center +
1650                                 sel->info.uses_persp_centroid +
1651                                 sel->info.uses_persp_sample > 1;
1652
1653                         key->part.ps.prolog.force_linear_center_interp =
1654                                 sel->info.uses_linear_center +
1655                                 sel->info.uses_linear_centroid +
1656                                 sel->info.uses_linear_sample > 1;
1657
1658                         if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1659                                 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1660                 }
1661
1662                 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1663
1664                 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1665                 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1666                         struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1667                         struct pipe_resource *tex = cb0->texture;
1668
1669                         /* 1D textures are allocated and used as 2D on GFX9. */
1670                         key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1671                         key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1672                                                        (tex->target == PIPE_TEXTURE_1D ||
1673                                                         tex->target == PIPE_TEXTURE_1D_ARRAY);
1674                         key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1675                                                          tex->target == PIPE_TEXTURE_2D_ARRAY ||
1676                                                          tex->target == PIPE_TEXTURE_CUBE ||
1677                                                          tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1678                                                          tex->target == PIPE_TEXTURE_3D;
1679                 }
1680                 break;
1681         }
1682         default:
1683                 assert(0);
1684         }
1685
1686         if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1687                 memset(&key->opt, 0, sizeof(key->opt));
1688 }
1689
1690 static void si_build_shader_variant(struct si_shader *shader,
1691                                     int thread_index,
1692                                     bool low_priority)
1693 {
1694         struct si_shader_selector *sel = shader->selector;
1695         struct si_screen *sscreen = sel->screen;
1696         struct ac_llvm_compiler *compiler;
1697         struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1698         int r;
1699
1700         if (thread_index >= 0) {
1701                 if (low_priority) {
1702                         assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1703                         compiler = &sscreen->compiler_lowp[thread_index];
1704                 } else {
1705                         assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1706                         compiler = &sscreen->compiler[thread_index];
1707                 }
1708                 if (!debug->async)
1709                         debug = NULL;
1710         } else {
1711                 assert(!low_priority);
1712                 compiler = shader->compiler_ctx_state.compiler;
1713         }
1714
1715         r = si_shader_create(sscreen, compiler, shader, debug);
1716         if (unlikely(r)) {
1717                 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1718                          sel->type, r);
1719                 shader->compilation_failed = true;
1720                 return;
1721         }
1722
1723         if (shader->compiler_ctx_state.is_debug_context) {
1724                 FILE *f = open_memstream(&shader->shader_log,
1725                                          &shader->shader_log_size);
1726                 if (f) {
1727                         si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1728                         fclose(f);
1729                 }
1730         }
1731
1732         si_shader_init_pm4_state(sscreen, shader);
1733 }
1734
1735 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1736 {
1737         struct si_shader *shader = (struct si_shader *)job;
1738
1739         assert(thread_index >= 0);
1740
1741         si_build_shader_variant(shader, thread_index, true);
1742 }
1743
1744 static const struct si_shader_key zeroed;
1745
1746 static bool si_check_missing_main_part(struct si_screen *sscreen,
1747                                        struct si_shader_selector *sel,
1748                                        struct si_compiler_ctx_state *compiler_state,
1749                                        struct si_shader_key *key)
1750 {
1751         struct si_shader **mainp = si_get_main_shader_part(sel, key);
1752
1753         if (!*mainp) {
1754                 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1755
1756                 if (!main_part)
1757                         return false;
1758
1759                 /* We can leave the fence as permanently signaled because the
1760                  * main part becomes visible globally only after it has been
1761                  * compiled. */
1762                 util_queue_fence_init(&main_part->ready);
1763
1764                 main_part->selector = sel;
1765                 main_part->key.as_es = key->as_es;
1766                 main_part->key.as_ls = key->as_ls;
1767                 main_part->is_monolithic = false;
1768
1769                 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1770                                            main_part, &compiler_state->debug) != 0) {
1771                         FREE(main_part);
1772                         return false;
1773                 }
1774                 *mainp = main_part;
1775         }
1776         return true;
1777 }
1778
1779 /* Select the hw shader variant depending on the current state. */
1780 static int si_shader_select_with_key(struct si_screen *sscreen,
1781                                      struct si_shader_ctx_state *state,
1782                                      struct si_compiler_ctx_state *compiler_state,
1783                                      struct si_shader_key *key,
1784                                      int thread_index)
1785 {
1786         struct si_shader_selector *sel = state->cso;
1787         struct si_shader_selector *previous_stage_sel = NULL;
1788         struct si_shader *current = state->current;
1789         struct si_shader *iter, *shader = NULL;
1790
1791 again:
1792         /* Check if we don't need to change anything.
1793          * This path is also used for most shaders that don't need multiple
1794          * variants, it will cost just a computation of the key and this
1795          * test. */
1796         if (likely(current &&
1797                    memcmp(&current->key, key, sizeof(*key)) == 0)) {
1798                 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1799                         if (current->is_optimized) {
1800                                 memset(&key->opt, 0, sizeof(key->opt));
1801                                 goto current_not_ready;
1802                         }
1803
1804                         util_queue_fence_wait(&current->ready);
1805                 }
1806
1807                 return current->compilation_failed ? -1 : 0;
1808         }
1809 current_not_ready:
1810
1811         /* This must be done before the mutex is locked, because async GS
1812          * compilation calls this function too, and therefore must enter
1813          * the mutex first.
1814          *
1815          * Only wait if we are in a draw call. Don't wait if we are
1816          * in a compiler thread.
1817          */
1818         if (thread_index < 0)
1819                 util_queue_fence_wait(&sel->ready);
1820
1821         mtx_lock(&sel->mutex);
1822
1823         /* Find the shader variant. */
1824         for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1825                 /* Don't check the "current" shader. We checked it above. */
1826                 if (current != iter &&
1827                     memcmp(&iter->key, key, sizeof(*key)) == 0) {
1828                         mtx_unlock(&sel->mutex);
1829
1830                         if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1831                                 /* If it's an optimized shader and its compilation has
1832                                  * been started but isn't done, use the unoptimized
1833                                  * shader so as not to cause a stall due to compilation.
1834                                  */
1835                                 if (iter->is_optimized) {
1836                                         memset(&key->opt, 0, sizeof(key->opt));
1837                                         goto again;
1838                                 }
1839
1840                                 util_queue_fence_wait(&iter->ready);
1841                         }
1842
1843                         if (iter->compilation_failed) {
1844                                 return -1; /* skip the draw call */
1845                         }
1846
1847                         state->current = iter;
1848                         return 0;
1849                 }
1850         }
1851
1852         /* Build a new shader. */
1853         shader = CALLOC_STRUCT(si_shader);
1854         if (!shader) {
1855                 mtx_unlock(&sel->mutex);
1856                 return -ENOMEM;
1857         }
1858
1859         util_queue_fence_init(&shader->ready);
1860
1861         shader->selector = sel;
1862         shader->key = *key;
1863         shader->compiler_ctx_state = *compiler_state;
1864
1865         /* If this is a merged shader, get the first shader's selector. */
1866         if (sscreen->info.chip_class >= GFX9) {
1867                 if (sel->type == PIPE_SHADER_TESS_CTRL)
1868                         previous_stage_sel = key->part.tcs.ls;
1869                 else if (sel->type == PIPE_SHADER_GEOMETRY)
1870                         previous_stage_sel = key->part.gs.es;
1871
1872                 /* We need to wait for the previous shader. */
1873                 if (previous_stage_sel && thread_index < 0)
1874                         util_queue_fence_wait(&previous_stage_sel->ready);
1875         }
1876
1877         /* Compile the main shader part if it doesn't exist. This can happen
1878          * if the initial guess was wrong. */
1879         bool is_pure_monolithic =
1880                 sscreen->use_monolithic_shaders ||
1881                 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1882
1883         if (!is_pure_monolithic) {
1884                 bool ok;
1885
1886                 /* Make sure the main shader part is present. This is needed
1887                  * for shaders that can be compiled as VS, LS, or ES, and only
1888                  * one of them is compiled at creation.
1889                  *
1890                  * For merged shaders, check that the starting shader's main
1891                  * part is present.
1892                  */
1893                 if (previous_stage_sel) {
1894                         struct si_shader_key shader1_key = zeroed;
1895
1896                         if (sel->type == PIPE_SHADER_TESS_CTRL)
1897                                 shader1_key.as_ls = 1;
1898                         else if (sel->type == PIPE_SHADER_GEOMETRY)
1899                                 shader1_key.as_es = 1;
1900                         else
1901                                 assert(0);
1902
1903                         mtx_lock(&previous_stage_sel->mutex);
1904                         ok = si_check_missing_main_part(sscreen,
1905                                                         previous_stage_sel,
1906                                                         compiler_state, &shader1_key);
1907                         mtx_unlock(&previous_stage_sel->mutex);
1908                 } else {
1909                         ok = si_check_missing_main_part(sscreen, sel,
1910                                                         compiler_state, key);
1911                 }
1912                 if (!ok) {
1913                         FREE(shader);
1914                         mtx_unlock(&sel->mutex);
1915                         return -ENOMEM; /* skip the draw call */
1916                 }
1917         }
1918
1919         /* Keep the reference to the 1st shader of merged shaders, so that
1920          * Gallium can't destroy it before we destroy the 2nd shader.
1921          *
1922          * Set sctx = NULL, because it's unused if we're not releasing
1923          * the shader, and we don't have any sctx here.
1924          */
1925         si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1926                                      previous_stage_sel);
1927
1928         /* Monolithic-only shaders don't make a distinction between optimized
1929          * and unoptimized. */
1930         shader->is_monolithic =
1931                 is_pure_monolithic ||
1932                 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1933
1934         shader->is_optimized =
1935                 !is_pure_monolithic &&
1936                 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1937
1938         /* If it's an optimized shader, compile it asynchronously. */
1939         if (shader->is_optimized &&
1940             !is_pure_monolithic &&
1941             thread_index < 0) {
1942                 /* Compile it asynchronously. */
1943                 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1944                                    shader, &shader->ready,
1945                                    si_build_shader_variant_low_priority, NULL);
1946
1947                 /* Add only after the ready fence was reset, to guard against a
1948                  * race with si_bind_XX_shader. */
1949                 if (!sel->last_variant) {
1950                         sel->first_variant = shader;
1951                         sel->last_variant = shader;
1952                 } else {
1953                         sel->last_variant->next_variant = shader;
1954                         sel->last_variant = shader;
1955                 }
1956
1957                 /* Use the default (unoptimized) shader for now. */
1958                 memset(&key->opt, 0, sizeof(key->opt));
1959                 mtx_unlock(&sel->mutex);
1960                 goto again;
1961         }
1962
1963         /* Reset the fence before adding to the variant list. */
1964         util_queue_fence_reset(&shader->ready);
1965
1966         if (!sel->last_variant) {
1967                 sel->first_variant = shader;
1968                 sel->last_variant = shader;
1969         } else {
1970                 sel->last_variant->next_variant = shader;
1971                 sel->last_variant = shader;
1972         }
1973
1974         mtx_unlock(&sel->mutex);
1975
1976         assert(!shader->is_optimized);
1977         si_build_shader_variant(shader, thread_index, false);
1978
1979         util_queue_fence_signal(&shader->ready);
1980
1981         if (!shader->compilation_failed)
1982                 state->current = shader;
1983
1984         return shader->compilation_failed ? -1 : 0;
1985 }
1986
1987 static int si_shader_select(struct pipe_context *ctx,
1988                             struct si_shader_ctx_state *state,
1989                             struct si_compiler_ctx_state *compiler_state)
1990 {
1991         struct si_context *sctx = (struct si_context *)ctx;
1992         struct si_shader_key key;
1993
1994         si_shader_selector_key(ctx, state->cso, &key);
1995         return si_shader_select_with_key(sctx->screen, state, compiler_state,
1996                                          &key, -1);
1997 }
1998
1999 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2000                                           bool streamout,
2001                                           struct si_shader_key *key)
2002 {
2003         unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2004
2005         switch (info->processor) {
2006         case PIPE_SHADER_VERTEX:
2007                 switch (next_shader) {
2008                 case PIPE_SHADER_GEOMETRY:
2009                         key->as_es = 1;
2010                         break;
2011                 case PIPE_SHADER_TESS_CTRL:
2012                 case PIPE_SHADER_TESS_EVAL:
2013                         key->as_ls = 1;
2014                         break;
2015                 default:
2016                         /* If POSITION isn't written, it can only be a HW VS
2017                          * if streamout is used. If streamout isn't used,
2018                          * assume that it's a HW LS. (the next shader is TCS)
2019                          * This heuristic is needed for separate shader objects.
2020                          */
2021                         if (!info->writes_position && !streamout)
2022                                 key->as_ls = 1;
2023                 }
2024                 break;
2025
2026         case PIPE_SHADER_TESS_EVAL:
2027                 if (next_shader == PIPE_SHADER_GEOMETRY ||
2028                     !info->writes_position)
2029                         key->as_es = 1;
2030                 break;
2031         }
2032 }
2033
2034 /**
2035  * Compile the main shader part or the monolithic shader as part of
2036  * si_shader_selector initialization. Since it can be done asynchronously,
2037  * there is no way to report compile failures to applications.
2038  */
2039 static void si_init_shader_selector_async(void *job, int thread_index)
2040 {
2041         struct si_shader_selector *sel = (struct si_shader_selector *)job;
2042         struct si_screen *sscreen = sel->screen;
2043         struct ac_llvm_compiler *compiler;
2044         struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2045
2046         assert(!debug->debug_message || debug->async);
2047         assert(thread_index >= 0);
2048         assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2049         compiler = &sscreen->compiler[thread_index];
2050
2051         /* Compile the main shader part for use with a prolog and/or epilog.
2052          * If this fails, the driver will try to compile a monolithic shader
2053          * on demand.
2054          */
2055         if (!sscreen->use_monolithic_shaders) {
2056                 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2057                 void *ir_binary = NULL;
2058
2059                 if (!shader) {
2060                         fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2061                         return;
2062                 }
2063
2064                 /* We can leave the fence signaled because use of the default
2065                  * main part is guarded by the selector's ready fence. */
2066                 util_queue_fence_init(&shader->ready);
2067
2068                 shader->selector = sel;
2069                 shader->is_monolithic = false;
2070                 si_parse_next_shader_property(&sel->info,
2071                                               sel->so.num_outputs != 0,
2072                                               &shader->key);
2073
2074                 if (sel->tokens || sel->nir)
2075                         ir_binary = si_get_ir_binary(sel);
2076
2077                 /* Try to load the shader from the shader cache. */
2078                 mtx_lock(&sscreen->shader_cache_mutex);
2079
2080                 if (ir_binary &&
2081                     si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2082                         mtx_unlock(&sscreen->shader_cache_mutex);
2083                         si_shader_dump_stats_for_shader_db(shader, debug);
2084                 } else {
2085                         mtx_unlock(&sscreen->shader_cache_mutex);
2086
2087                         /* Compile the shader if it hasn't been loaded from the cache. */
2088                         if (si_compile_tgsi_shader(sscreen, compiler, shader,
2089                                                    debug) != 0) {
2090                                 FREE(shader);
2091                                 FREE(ir_binary);
2092                                 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2093                                 return;
2094                         }
2095
2096                         if (ir_binary) {
2097                                 mtx_lock(&sscreen->shader_cache_mutex);
2098                                 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2099                                         FREE(ir_binary);
2100                                 mtx_unlock(&sscreen->shader_cache_mutex);
2101                         }
2102                 }
2103
2104                 *si_get_main_shader_part(sel, &shader->key) = shader;
2105
2106                 /* Unset "outputs_written" flags for outputs converted to
2107                  * DEFAULT_VAL, so that later inter-shader optimizations don't
2108                  * try to eliminate outputs that don't exist in the final
2109                  * shader.
2110                  *
2111                  * This is only done if non-monolithic shaders are enabled.
2112                  */
2113                 if ((sel->type == PIPE_SHADER_VERTEX ||
2114                      sel->type == PIPE_SHADER_TESS_EVAL) &&
2115                     !shader->key.as_ls &&
2116                     !shader->key.as_es) {
2117                         unsigned i;
2118
2119                         for (i = 0; i < sel->info.num_outputs; i++) {
2120                                 unsigned offset = shader->info.vs_output_param_offset[i];
2121
2122                                 if (offset <= AC_EXP_PARAM_OFFSET_31)
2123                                         continue;
2124
2125                                 unsigned name = sel->info.output_semantic_name[i];
2126                                 unsigned index = sel->info.output_semantic_index[i];
2127                                 unsigned id;
2128
2129                                 switch (name) {
2130                                 case TGSI_SEMANTIC_GENERIC:
2131                                         /* don't process indices the function can't handle */
2132                                         if (index >= SI_MAX_IO_GENERIC)
2133                                                 break;
2134                                         /* fall through */
2135                                 default:
2136                                         id = si_shader_io_get_unique_index(name, index, true);
2137                                         sel->outputs_written_before_ps &= ~(1ull << id);
2138                                         break;
2139                                 case TGSI_SEMANTIC_POSITION: /* ignore these */
2140                                 case TGSI_SEMANTIC_PSIZE:
2141                                 case TGSI_SEMANTIC_CLIPVERTEX:
2142                                 case TGSI_SEMANTIC_EDGEFLAG:
2143                                         break;
2144                                 }
2145                         }
2146                 }
2147         }
2148
2149         /* The GS copy shader is always pre-compiled. */
2150         if (sel->type == PIPE_SHADER_GEOMETRY) {
2151                 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2152                 if (!sel->gs_copy_shader) {
2153                         fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2154                         return;
2155                 }
2156
2157                 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2158         }
2159 }
2160
2161 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2162                                  struct util_queue_fence *ready_fence,
2163                                  struct si_compiler_ctx_state *compiler_ctx_state,
2164                                  void *job, util_queue_execute_func execute)
2165 {
2166         util_queue_fence_init(ready_fence);
2167
2168         struct util_async_debug_callback async_debug;
2169         bool wait =
2170                 (sctx->debug.debug_message && !sctx->debug.async) ||
2171                 sctx->is_debug ||
2172                 si_can_dump_shader(sctx->screen, processor);
2173
2174         if (wait) {
2175                 u_async_debug_init(&async_debug);
2176                 compiler_ctx_state->debug = async_debug.base;
2177         }
2178
2179         util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2180                            ready_fence, execute, NULL);
2181
2182         if (wait) {
2183                 util_queue_fence_wait(ready_fence);
2184                 u_async_debug_drain(&async_debug, &sctx->debug);
2185                 u_async_debug_cleanup(&async_debug);
2186         }
2187 }
2188
2189 /* Return descriptor slot usage masks from the given shader info. */
2190 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2191                               uint32_t *const_and_shader_buffers,
2192                               uint64_t *samplers_and_images)
2193 {
2194         unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2195
2196         num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2197         num_constbufs = util_last_bit(info->const_buffers_declared);
2198         /* two 8-byte images share one 16-byte slot */
2199         num_images = align(util_last_bit(info->images_declared), 2);
2200         num_samplers = util_last_bit(info->samplers_declared);
2201
2202         /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2203         start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2204         *const_and_shader_buffers =
2205                 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2206
2207         /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2208         start = si_get_image_slot(num_images - 1) / 2;
2209         *samplers_and_images =
2210                 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2211 }
2212
2213 static void *si_create_shader_selector(struct pipe_context *ctx,
2214                                        const struct pipe_shader_state *state)
2215 {
2216         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2217         struct si_context *sctx = (struct si_context*)ctx;
2218         struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2219         int i;
2220
2221         if (!sel)
2222                 return NULL;
2223
2224         pipe_reference_init(&sel->reference, 1);
2225         sel->screen = sscreen;
2226         sel->compiler_ctx_state.debug = sctx->debug;
2227         sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2228
2229         sel->so = state->stream_output;
2230
2231         if (state->type == PIPE_SHADER_IR_TGSI) {
2232                 sel->tokens = tgsi_dup_tokens(state->tokens);
2233                 if (!sel->tokens) {
2234                         FREE(sel);
2235                         return NULL;
2236                 }
2237
2238                 tgsi_scan_shader(state->tokens, &sel->info);
2239                 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2240         } else {
2241                 assert(state->type == PIPE_SHADER_IR_NIR);
2242
2243                 sel->nir = state->ir.nir;
2244
2245                 si_nir_scan_shader(sel->nir, &sel->info);
2246                 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2247
2248                 si_lower_nir(sel);
2249         }
2250
2251         sel->type = sel->info.processor;
2252         p_atomic_inc(&sscreen->num_shaders_created);
2253         si_get_active_slot_masks(&sel->info,
2254                                  &sel->active_const_and_shader_buffers,
2255                                  &sel->active_samplers_and_images);
2256
2257         /* Record which streamout buffers are enabled. */
2258         for (i = 0; i < sel->so.num_outputs; i++) {
2259                 sel->enabled_streamout_buffer_mask |=
2260                         (1 << sel->so.output[i].output_buffer) <<
2261                         (sel->so.output[i].stream * 4);
2262         }
2263
2264         /* The prolog is a no-op if there are no inputs. */
2265         sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2266                                sel->info.num_inputs &&
2267                                !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2268
2269         sel->force_correct_derivs_after_kill =
2270                 sel->type == PIPE_SHADER_FRAGMENT &&
2271                 sel->info.uses_derivatives &&
2272                 sel->info.uses_kill &&
2273                 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2274
2275         /* Set which opcode uses which (i,j) pair. */
2276         if (sel->info.uses_persp_opcode_interp_centroid)
2277                 sel->info.uses_persp_centroid = true;
2278
2279         if (sel->info.uses_linear_opcode_interp_centroid)
2280                 sel->info.uses_linear_centroid = true;
2281
2282         if (sel->info.uses_persp_opcode_interp_offset ||
2283             sel->info.uses_persp_opcode_interp_sample)
2284                 sel->info.uses_persp_center = true;
2285
2286         if (sel->info.uses_linear_opcode_interp_offset ||
2287             sel->info.uses_linear_opcode_interp_sample)
2288                 sel->info.uses_linear_center = true;
2289
2290         switch (sel->type) {
2291         case PIPE_SHADER_GEOMETRY:
2292                 sel->gs_output_prim =
2293                         sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2294                 sel->gs_max_out_vertices =
2295                         sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2296                 sel->gs_num_invocations =
2297                         sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2298                 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2299                 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2300                                           sel->gs_max_out_vertices;
2301
2302                 sel->max_gs_stream = 0;
2303                 for (i = 0; i < sel->so.num_outputs; i++)
2304                         sel->max_gs_stream = MAX2(sel->max_gs_stream,
2305                                                   sel->so.output[i].stream);
2306
2307                 sel->gs_input_verts_per_prim =
2308                         u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2309                 break;
2310
2311         case PIPE_SHADER_TESS_CTRL:
2312                 /* Always reserve space for these. */
2313                 sel->patch_outputs_written |=
2314                         (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2315                         (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2316                 /* fall through */
2317         case PIPE_SHADER_VERTEX:
2318         case PIPE_SHADER_TESS_EVAL:
2319                 for (i = 0; i < sel->info.num_outputs; i++) {
2320                         unsigned name = sel->info.output_semantic_name[i];
2321                         unsigned index = sel->info.output_semantic_index[i];
2322
2323                         switch (name) {
2324                         case TGSI_SEMANTIC_TESSINNER:
2325                         case TGSI_SEMANTIC_TESSOUTER:
2326                         case TGSI_SEMANTIC_PATCH:
2327                                 sel->patch_outputs_written |=
2328                                         1ull << si_shader_io_get_unique_index_patch(name, index);
2329                                 break;
2330
2331                         case TGSI_SEMANTIC_GENERIC:
2332                                 /* don't process indices the function can't handle */
2333                                 if (index >= SI_MAX_IO_GENERIC)
2334                                         break;
2335                                 /* fall through */
2336                         default:
2337                                 sel->outputs_written |=
2338                                         1ull << si_shader_io_get_unique_index(name, index, false);
2339                                 sel->outputs_written_before_ps |=
2340                                         1ull << si_shader_io_get_unique_index(name, index, true);
2341                                 break;
2342                         case TGSI_SEMANTIC_EDGEFLAG:
2343                                 break;
2344                         }
2345                 }
2346                 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2347                 sel->lshs_vertex_stride = sel->esgs_itemsize;
2348
2349                 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2350                  * will start on a different bank. (except for the maximum 32*16).
2351                  */
2352                 if (sel->lshs_vertex_stride < 32*16)
2353                         sel->lshs_vertex_stride += 4;
2354
2355                 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2356                  * conflicts, i.e. each vertex will start at a different bank.
2357                  */
2358                 if (sctx->chip_class >= GFX9)
2359                         sel->esgs_itemsize += 4;
2360
2361                 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2362                 break;
2363
2364         case PIPE_SHADER_FRAGMENT:
2365                 for (i = 0; i < sel->info.num_inputs; i++) {
2366                         unsigned name = sel->info.input_semantic_name[i];
2367                         unsigned index = sel->info.input_semantic_index[i];
2368
2369                         switch (name) {
2370                         case TGSI_SEMANTIC_GENERIC:
2371                                 /* don't process indices the function can't handle */
2372                                 if (index >= SI_MAX_IO_GENERIC)
2373                                         break;
2374                                 /* fall through */
2375                         default:
2376                                 sel->inputs_read |=
2377                                         1ull << si_shader_io_get_unique_index(name, index, true);
2378                                 break;
2379                         case TGSI_SEMANTIC_PCOORD: /* ignore this */
2380                                 break;
2381                         }
2382                 }
2383
2384                 for (i = 0; i < 8; i++)
2385                         if (sel->info.colors_written & (1 << i))
2386                                 sel->colors_written_4bit |= 0xf << (4 * i);
2387
2388                 for (i = 0; i < sel->info.num_inputs; i++) {
2389                         if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2390                                 int index = sel->info.input_semantic_index[i];
2391                                 sel->color_attr_index[index] = i;
2392                         }
2393                 }
2394                 break;
2395         }
2396
2397         /* PA_CL_VS_OUT_CNTL */
2398         bool misc_vec_ena =
2399                 sel->info.writes_psize || sel->info.writes_edgeflag ||
2400                 sel->info.writes_layer || sel->info.writes_viewport_index;
2401         sel->pa_cl_vs_out_cntl =
2402                 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2403                 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2404                 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2405                 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2406                 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2407                 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2408         sel->clipdist_mask = sel->info.writes_clipvertex ?
2409                                      SIX_BITS : sel->info.clipdist_writemask;
2410         sel->culldist_mask = sel->info.culldist_writemask <<
2411                              sel->info.num_written_clipdistance;
2412
2413         /* DB_SHADER_CONTROL */
2414         sel->db_shader_control =
2415                 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2416                 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2417                 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2418                 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2419
2420         switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2421         case TGSI_FS_DEPTH_LAYOUT_GREATER:
2422                 sel->db_shader_control |=
2423                         S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2424                 break;
2425         case TGSI_FS_DEPTH_LAYOUT_LESS:
2426                 sel->db_shader_control |=
2427                         S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2428                 break;
2429         }
2430
2431         /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2432          *
2433          *   | early Z/S | writes_mem | allow_ReZ? |      Z_ORDER       | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2434          * --|-----------|------------|------------|--------------------|-------------------|-------------
2435          * 1a|   false   |   false    |   true     | EarlyZ_Then_ReZ    |         0         |     0
2436          * 1b|   false   |   false    |   false    | EarlyZ_Then_LateZ  |         0         |     0
2437          * 2 |   false   |   true     |   n/a      |       LateZ        |         1         |     0
2438          * 3 |   true    |   false    |   n/a      | EarlyZ_Then_LateZ  |         0         |     0
2439          * 4 |   true    |   true     |   n/a      | EarlyZ_Then_LateZ  |         0         |     1
2440          *
2441          * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2442          * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2443          *
2444          * Don't use ReZ without profiling !!!
2445          *
2446          * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2447          * shaders.
2448          */
2449         if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2450                 /* Cases 3, 4. */
2451                 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2452                                           S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2453                                           S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2454         } else if (sel->info.writes_memory) {
2455                 /* Case 2. */
2456                 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2457                                           S_02880C_EXEC_ON_HIER_FAIL(1);
2458         } else {
2459                 /* Case 1. */
2460                 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2461         }
2462
2463         (void) mtx_init(&sel->mutex, mtx_plain);
2464
2465         si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2466                                     &sel->compiler_ctx_state, sel,
2467                                     si_init_shader_selector_async);
2468         return sel;
2469 }
2470
2471 static void si_update_streamout_state(struct si_context *sctx)
2472 {
2473         struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2474
2475         if (!shader_with_so)
2476                 return;
2477
2478         sctx->streamout.enabled_stream_buffers_mask =
2479                 shader_with_so->enabled_streamout_buffer_mask;
2480         sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2481 }
2482
2483 static void si_update_clip_regs(struct si_context *sctx,
2484                                 struct si_shader_selector *old_hw_vs,
2485                                 struct si_shader *old_hw_vs_variant,
2486                                 struct si_shader_selector *next_hw_vs,
2487                                 struct si_shader *next_hw_vs_variant)
2488 {
2489         if (next_hw_vs &&
2490             (!old_hw_vs ||
2491              old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2492              next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2493              old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2494              old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2495              old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2496              !old_hw_vs_variant ||
2497              !next_hw_vs_variant ||
2498              old_hw_vs_variant->key.opt.clip_disable !=
2499              next_hw_vs_variant->key.opt.clip_disable))
2500                 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2501 }
2502
2503 static void si_update_common_shader_state(struct si_context *sctx)
2504 {
2505         sctx->uses_bindless_samplers =
2506                 si_shader_uses_bindless_samplers(sctx->vs_shader.cso)  ||
2507                 si_shader_uses_bindless_samplers(sctx->gs_shader.cso)  ||
2508                 si_shader_uses_bindless_samplers(sctx->ps_shader.cso)  ||
2509                 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2510                 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2511         sctx->uses_bindless_images =
2512                 si_shader_uses_bindless_images(sctx->vs_shader.cso)  ||
2513                 si_shader_uses_bindless_images(sctx->gs_shader.cso)  ||
2514                 si_shader_uses_bindless_images(sctx->ps_shader.cso)  ||
2515                 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2516                 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2517         sctx->do_update_shaders = true;
2518 }
2519
2520 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2521 {
2522         struct si_context *sctx = (struct si_context *)ctx;
2523         struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2524         struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2525         struct si_shader_selector *sel = state;
2526
2527         if (sctx->vs_shader.cso == sel)
2528                 return;
2529
2530         sctx->vs_shader.cso = sel;
2531         sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2532         sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2533
2534         si_update_common_shader_state(sctx);
2535         si_update_vs_viewport_state(sctx);
2536         si_set_active_descriptors_for_shader(sctx, sel);
2537         si_update_streamout_state(sctx);
2538         si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2539                             si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2540 }
2541
2542 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2543 {
2544         sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2545                 (sctx->tes_shader.cso &&
2546                  sctx->tes_shader.cso->info.uses_primid) ||
2547                 (sctx->tcs_shader.cso &&
2548                  sctx->tcs_shader.cso->info.uses_primid) ||
2549                 (sctx->gs_shader.cso &&
2550                  sctx->gs_shader.cso->info.uses_primid) ||
2551                 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2552                  sctx->ps_shader.cso->info.uses_primid);
2553 }
2554
2555 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2556 {
2557         struct si_context *sctx = (struct si_context *)ctx;
2558         struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2559         struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2560         struct si_shader_selector *sel = state;
2561         bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2562
2563         if (sctx->gs_shader.cso == sel)
2564                 return;
2565
2566         sctx->gs_shader.cso = sel;
2567         sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2568         sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2569
2570         si_update_common_shader_state(sctx);
2571         sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2572
2573         if (enable_changed) {
2574                 si_shader_change_notify(sctx);
2575                 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2576                         si_update_tess_uses_prim_id(sctx);
2577         }
2578         si_update_vs_viewport_state(sctx);
2579         si_set_active_descriptors_for_shader(sctx, sel);
2580         si_update_streamout_state(sctx);
2581         si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2582                             si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2583 }
2584
2585 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2586 {
2587         struct si_context *sctx = (struct si_context *)ctx;
2588         struct si_shader_selector *sel = state;
2589         bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2590
2591         if (sctx->tcs_shader.cso == sel)
2592                 return;
2593
2594         sctx->tcs_shader.cso = sel;
2595         sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2596         si_update_tess_uses_prim_id(sctx);
2597
2598         si_update_common_shader_state(sctx);
2599
2600         if (enable_changed)
2601                 sctx->last_tcs = NULL; /* invalidate derived tess state */
2602
2603         si_set_active_descriptors_for_shader(sctx, sel);
2604 }
2605
2606 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2607 {
2608         struct si_context *sctx = (struct si_context *)ctx;
2609         struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2610         struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2611         struct si_shader_selector *sel = state;
2612         bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2613
2614         if (sctx->tes_shader.cso == sel)
2615                 return;
2616
2617         sctx->tes_shader.cso = sel;
2618         sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2619         sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2620         si_update_tess_uses_prim_id(sctx);
2621
2622         si_update_common_shader_state(sctx);
2623         sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2624
2625         if (enable_changed) {
2626                 si_shader_change_notify(sctx);
2627                 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2628         }
2629         si_update_vs_viewport_state(sctx);
2630         si_set_active_descriptors_for_shader(sctx, sel);
2631         si_update_streamout_state(sctx);
2632         si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2633                             si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2634 }
2635
2636 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2637 {
2638         struct si_context *sctx = (struct si_context *)ctx;
2639         struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2640         struct si_shader_selector *sel = state;
2641
2642         /* skip if supplied shader is one already in use */
2643         if (old_sel == sel)
2644                 return;
2645
2646         sctx->ps_shader.cso = sel;
2647         sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2648
2649         si_update_common_shader_state(sctx);
2650         if (sel) {
2651                 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2652                         si_update_tess_uses_prim_id(sctx);
2653
2654                 if (!old_sel ||
2655                     old_sel->info.colors_written != sel->info.colors_written)
2656                         si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2657
2658                 if (sctx->screen->has_out_of_order_rast &&
2659                     (!old_sel ||
2660                      old_sel->info.writes_memory != sel->info.writes_memory ||
2661                      old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2662                      sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2663                         si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2664         }
2665         si_set_active_descriptors_for_shader(sctx, sel);
2666         si_update_ps_colorbuf0_slot(sctx);
2667 }
2668
2669 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2670 {
2671         if (shader->is_optimized) {
2672                 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2673                                     &shader->ready);
2674         }
2675
2676         util_queue_fence_destroy(&shader->ready);
2677
2678         if (shader->pm4) {
2679                 switch (shader->selector->type) {
2680                 case PIPE_SHADER_VERTEX:
2681                         if (shader->key.as_ls) {
2682                                 assert(sctx->chip_class <= VI);
2683                                 si_pm4_delete_state(sctx, ls, shader->pm4);
2684                         } else if (shader->key.as_es) {
2685                                 assert(sctx->chip_class <= VI);
2686                                 si_pm4_delete_state(sctx, es, shader->pm4);
2687                         } else {
2688                                 si_pm4_delete_state(sctx, vs, shader->pm4);
2689                         }
2690                         break;
2691                 case PIPE_SHADER_TESS_CTRL:
2692                         si_pm4_delete_state(sctx, hs, shader->pm4);
2693                         break;
2694                 case PIPE_SHADER_TESS_EVAL:
2695                         if (shader->key.as_es) {
2696                                 assert(sctx->chip_class <= VI);
2697                                 si_pm4_delete_state(sctx, es, shader->pm4);
2698                         } else {
2699                                 si_pm4_delete_state(sctx, vs, shader->pm4);
2700                         }
2701                         break;
2702                 case PIPE_SHADER_GEOMETRY:
2703                         if (shader->is_gs_copy_shader)
2704                                 si_pm4_delete_state(sctx, vs, shader->pm4);
2705                         else
2706                                 si_pm4_delete_state(sctx, gs, shader->pm4);
2707                         break;
2708                 case PIPE_SHADER_FRAGMENT:
2709                         si_pm4_delete_state(sctx, ps, shader->pm4);
2710                         break;
2711                 }
2712         }
2713
2714         si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2715         si_shader_destroy(shader);
2716         free(shader);
2717 }
2718
2719 void si_destroy_shader_selector(struct si_context *sctx,
2720                                 struct si_shader_selector *sel)
2721 {
2722         struct si_shader *p = sel->first_variant, *c;
2723         struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2724                 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2725                 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2726                 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2727                 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2728                 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2729         };
2730
2731         util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2732
2733         if (current_shader[sel->type]->cso == sel) {
2734                 current_shader[sel->type]->cso = NULL;
2735                 current_shader[sel->type]->current = NULL;
2736         }
2737
2738         while (p) {
2739                 c = p->next_variant;
2740                 si_delete_shader(sctx, p);
2741                 p = c;
2742         }
2743
2744         if (sel->main_shader_part)
2745                 si_delete_shader(sctx, sel->main_shader_part);
2746         if (sel->main_shader_part_ls)
2747                 si_delete_shader(sctx, sel->main_shader_part_ls);
2748         if (sel->main_shader_part_es)
2749                 si_delete_shader(sctx, sel->main_shader_part_es);
2750         if (sel->gs_copy_shader)
2751                 si_delete_shader(sctx, sel->gs_copy_shader);
2752
2753         util_queue_fence_destroy(&sel->ready);
2754         mtx_destroy(&sel->mutex);
2755         free(sel->tokens);
2756         ralloc_free(sel->nir);
2757         free(sel);
2758 }
2759
2760 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2761 {
2762         struct si_context *sctx = (struct si_context *)ctx;
2763         struct si_shader_selector *sel = (struct si_shader_selector *)state;
2764
2765         si_shader_selector_reference(sctx, &sel, NULL);
2766 }
2767
2768 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2769                                      struct si_shader *vs, unsigned name,
2770                                      unsigned index, unsigned interpolate)
2771 {
2772         struct tgsi_shader_info *vsinfo = &vs->selector->info;
2773         unsigned j, offset, ps_input_cntl = 0;
2774
2775         if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2776             (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2777                 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2778
2779         if (name == TGSI_SEMANTIC_PCOORD ||
2780             (name == TGSI_SEMANTIC_TEXCOORD &&
2781              sctx->sprite_coord_enable & (1 << index))) {
2782                 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2783         }
2784
2785         for (j = 0; j < vsinfo->num_outputs; j++) {
2786                 if (name == vsinfo->output_semantic_name[j] &&
2787                     index == vsinfo->output_semantic_index[j]) {
2788                         offset = vs->info.vs_output_param_offset[j];
2789
2790                         if (offset <= AC_EXP_PARAM_OFFSET_31) {
2791                                 /* The input is loaded from parameter memory. */
2792                                 ps_input_cntl |= S_028644_OFFSET(offset);
2793                         } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2794                                 if (offset == AC_EXP_PARAM_UNDEFINED) {
2795                                         /* This can happen with depth-only rendering. */
2796                                         offset = 0;
2797                                 } else {
2798                                         /* The input is a DEFAULT_VAL constant. */
2799                                         assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2800                                                offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2801                                         offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2802                                 }
2803
2804                                 ps_input_cntl = S_028644_OFFSET(0x20) |
2805                                                 S_028644_DEFAULT_VAL(offset);
2806                         }
2807                         break;
2808                 }
2809         }
2810
2811         if (name == TGSI_SEMANTIC_PRIMID)
2812                 /* PrimID is written after the last output. */
2813                 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2814         else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2815                 /* No corresponding output found, load defaults into input.
2816                  * Don't set any other bits.
2817                  * (FLAT_SHADE=1 completely changes behavior) */
2818                 ps_input_cntl = S_028644_OFFSET(0x20);
2819                 /* D3D 9 behaviour. GL is undefined */
2820                 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2821                         ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2822         }
2823         return ps_input_cntl;
2824 }
2825
2826 static void si_emit_spi_map(struct si_context *sctx)
2827 {
2828         struct si_shader *ps = sctx->ps_shader.current;
2829         struct si_shader *vs = si_get_vs_state(sctx);
2830         struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2831         unsigned i, num_interp, num_written = 0, bcol_interp[2];
2832         unsigned spi_ps_input_cntl[32];
2833
2834         if (!ps || !ps->selector->info.num_inputs)
2835                 return;
2836
2837         num_interp = si_get_ps_num_interp(ps);
2838         assert(num_interp > 0);
2839
2840         for (i = 0; i < psinfo->num_inputs; i++) {
2841                 unsigned name = psinfo->input_semantic_name[i];
2842                 unsigned index = psinfo->input_semantic_index[i];
2843                 unsigned interpolate = psinfo->input_interpolate[i];
2844
2845                 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2846                                                             index, interpolate);
2847
2848                 if (name == TGSI_SEMANTIC_COLOR) {
2849                         assert(index < ARRAY_SIZE(bcol_interp));
2850                         bcol_interp[index] = interpolate;
2851                 }
2852         }
2853
2854         if (ps->key.part.ps.prolog.color_two_side) {
2855                 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2856
2857                 for (i = 0; i < 2; i++) {
2858                         if (!(psinfo->colors_read & (0xf << (i * 4))))
2859                                 continue;
2860
2861                         spi_ps_input_cntl[num_written++] =
2862                           si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2863
2864                 }
2865         }
2866         assert(num_interp == num_written);
2867
2868         /* R_028644_SPI_PS_INPUT_CNTL_0 */
2869         /* Dota 2: Only ~16% of SPI map updates set different values. */
2870         /* Talos: Only ~9% of SPI map updates set different values. */
2871         unsigned initial_cdw = sctx->gfx_cs->current.cdw;
2872         radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2873                                     spi_ps_input_cntl,
2874                                     sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2875
2876         if (initial_cdw != sctx->gfx_cs->current.cdw)
2877                 sctx->context_roll_counter++;
2878 }
2879
2880 /**
2881  * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2882  */
2883 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2884 {
2885         if (sctx->init_config_has_vgt_flush)
2886                 return;
2887
2888         /* Done by Vulkan before VGT_FLUSH. */
2889         si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2890         si_pm4_cmd_add(sctx->init_config,
2891                        EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2892         si_pm4_cmd_end(sctx->init_config, false);
2893
2894         /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2895         si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2896         si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2897         si_pm4_cmd_end(sctx->init_config, false);
2898         sctx->init_config_has_vgt_flush = true;
2899 }
2900
2901 /* Initialize state related to ESGS / GSVS ring buffers */
2902 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2903 {
2904         struct si_shader_selector *es =
2905                 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2906         struct si_shader_selector *gs = sctx->gs_shader.cso;
2907         struct si_pm4_state *pm4;
2908
2909         /* Chip constants. */
2910         unsigned num_se = sctx->screen->info.max_se;
2911         unsigned wave_size = 64;
2912         unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2913         /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2914          * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2915          */
2916         unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2917         unsigned alignment = 256 * num_se;
2918         /* The maximum size is 63.999 MB per SE. */
2919         unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2920
2921         /* Calculate the minimum size. */
2922         unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2923                                             wave_size, alignment);
2924
2925         /* These are recommended sizes, not minimum sizes. */
2926         unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2927                                   es->esgs_itemsize * gs->gs_input_verts_per_prim;
2928         unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2929                                   gs->max_gsvs_emit_size;
2930
2931         min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2932         esgs_ring_size = align(esgs_ring_size, alignment);
2933         gsvs_ring_size = align(gsvs_ring_size, alignment);
2934
2935         esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2936         gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2937
2938         /* Some rings don't have to be allocated if shaders don't use them.
2939          * (e.g. no varyings between ES and GS or GS and VS)
2940          *
2941          * GFX9 doesn't have the ESGS ring.
2942          */
2943         bool update_esgs = sctx->chip_class <= VI &&
2944                            esgs_ring_size &&
2945                            (!sctx->esgs_ring ||
2946                             sctx->esgs_ring->width0 < esgs_ring_size);
2947         bool update_gsvs = gsvs_ring_size &&
2948                            (!sctx->gsvs_ring ||
2949                             sctx->gsvs_ring->width0 < gsvs_ring_size);
2950
2951         if (!update_esgs && !update_gsvs)
2952                 return true;
2953
2954         if (update_esgs) {
2955                 pipe_resource_reference(&sctx->esgs_ring, NULL);
2956                 sctx->esgs_ring =
2957                         pipe_aligned_buffer_create(sctx->b.screen,
2958                                                    SI_RESOURCE_FLAG_UNMAPPABLE,
2959                                                    PIPE_USAGE_DEFAULT,
2960                                                    esgs_ring_size, alignment);
2961                 if (!sctx->esgs_ring)
2962                         return false;
2963         }
2964
2965         if (update_gsvs) {
2966                 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2967                 sctx->gsvs_ring =
2968                         pipe_aligned_buffer_create(sctx->b.screen,
2969                                                    SI_RESOURCE_FLAG_UNMAPPABLE,
2970                                                    PIPE_USAGE_DEFAULT,
2971                                                    gsvs_ring_size, alignment);
2972                 if (!sctx->gsvs_ring)
2973                         return false;
2974         }
2975
2976         /* Create the "init_config_gs_rings" state. */
2977         pm4 = CALLOC_STRUCT(si_pm4_state);
2978         if (!pm4)
2979                 return false;
2980
2981         if (sctx->chip_class >= CIK) {
2982                 if (sctx->esgs_ring) {
2983                         assert(sctx->chip_class <= VI);
2984                         si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2985                                        sctx->esgs_ring->width0 / 256);
2986                 }
2987                 if (sctx->gsvs_ring)
2988                         si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2989                                        sctx->gsvs_ring->width0 / 256);
2990         } else {
2991                 if (sctx->esgs_ring)
2992                         si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2993                                        sctx->esgs_ring->width0 / 256);
2994                 if (sctx->gsvs_ring)
2995                         si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2996                                        sctx->gsvs_ring->width0 / 256);
2997         }
2998
2999         /* Set the state. */
3000         if (sctx->init_config_gs_rings)
3001                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3002         sctx->init_config_gs_rings = pm4;
3003
3004         if (!sctx->init_config_has_vgt_flush) {
3005                 si_init_config_add_vgt_flush(sctx);
3006                 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3007         }
3008
3009         /* Flush the context to re-emit both init_config states. */
3010         sctx->initial_gfx_cs_size = 0; /* force flush */
3011         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3012
3013         /* Set ring bindings. */
3014         if (sctx->esgs_ring) {
3015                 assert(sctx->chip_class <= VI);
3016                 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3017                                    sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3018                                    true, true, 4, 64, 0);
3019                 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3020                                    sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3021                                    false, false, 0, 0, 0);
3022         }
3023         if (sctx->gsvs_ring) {
3024                 si_set_ring_buffer(sctx, SI_RING_GSVS,
3025                                    sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3026                                    false, false, 0, 0, 0);
3027         }
3028
3029         return true;
3030 }
3031
3032 static void si_shader_lock(struct si_shader *shader)
3033 {
3034         mtx_lock(&shader->selector->mutex);
3035         if (shader->previous_stage_sel) {
3036                 assert(shader->previous_stage_sel != shader->selector);
3037                 mtx_lock(&shader->previous_stage_sel->mutex);
3038         }
3039 }
3040
3041 static void si_shader_unlock(struct si_shader *shader)
3042 {
3043         if (shader->previous_stage_sel)
3044                 mtx_unlock(&shader->previous_stage_sel->mutex);
3045         mtx_unlock(&shader->selector->mutex);
3046 }
3047
3048 /**
3049  * @returns 1 if \p sel has been updated to use a new scratch buffer
3050  *          0 if not
3051  *          < 0 if there was a failure
3052  */
3053 static int si_update_scratch_buffer(struct si_context *sctx,
3054                                     struct si_shader *shader)
3055 {
3056         uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3057         int r;
3058
3059         if (!shader)
3060                 return 0;
3061
3062         /* This shader doesn't need a scratch buffer */
3063         if (shader->config.scratch_bytes_per_wave == 0)
3064                 return 0;
3065
3066         /* Prevent race conditions when updating:
3067          * - si_shader::scratch_bo
3068          * - si_shader::binary::code
3069          * - si_shader::previous_stage::binary::code.
3070          */
3071         si_shader_lock(shader);
3072
3073         /* This shader is already configured to use the current
3074          * scratch buffer. */
3075         if (shader->scratch_bo == sctx->scratch_buffer) {
3076                 si_shader_unlock(shader);
3077                 return 0;
3078         }
3079
3080         assert(sctx->scratch_buffer);
3081
3082         if (shader->previous_stage)
3083                 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
3084
3085         si_shader_apply_scratch_relocs(shader, scratch_va);
3086
3087         /* Replace the shader bo with a new bo that has the relocs applied. */
3088         r = si_shader_binary_upload(sctx->screen, shader);
3089         if (r) {
3090                 si_shader_unlock(shader);
3091                 return r;
3092         }
3093
3094         /* Update the shader state to use the new shader bo. */
3095         si_shader_init_pm4_state(sctx->screen, shader);
3096
3097         r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3098
3099         si_shader_unlock(shader);
3100         return 1;
3101 }
3102
3103 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3104 {
3105         return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3106 }
3107
3108 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3109 {
3110         return shader ? shader->config.scratch_bytes_per_wave : 0;
3111 }
3112
3113 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3114 {
3115         if (!sctx->tes_shader.cso)
3116                 return NULL; /* tessellation disabled */
3117
3118         return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3119                                       sctx->fixed_func_tcs_shader.current;
3120 }
3121
3122 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3123 {
3124         unsigned bytes = 0;
3125
3126         bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3127         bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3128         bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3129         bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3130
3131         if (sctx->tes_shader.cso) {
3132                 struct si_shader *tcs = si_get_tcs_current(sctx);
3133
3134                 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3135         }
3136         return bytes;
3137 }
3138
3139 static bool si_update_scratch_relocs(struct si_context *sctx)
3140 {
3141         struct si_shader *tcs = si_get_tcs_current(sctx);
3142         int r;
3143
3144         /* Update the shaders, so that they are using the latest scratch.
3145          * The scratch buffer may have been changed since these shaders were
3146          * last used, so we still need to try to update them, even if they
3147          * require scratch buffers smaller than the current size.
3148          */
3149         r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3150         if (r < 0)
3151                 return false;
3152         if (r == 1)
3153                 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3154
3155         r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3156         if (r < 0)
3157                 return false;
3158         if (r == 1)
3159                 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3160
3161         r = si_update_scratch_buffer(sctx, tcs);
3162         if (r < 0)
3163                 return false;
3164         if (r == 1)
3165                 si_pm4_bind_state(sctx, hs, tcs->pm4);
3166
3167         /* VS can be bound as LS, ES, or VS. */
3168         r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3169         if (r < 0)
3170                 return false;
3171         if (r == 1) {
3172                 if (sctx->tes_shader.current)
3173                         si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3174                 else if (sctx->gs_shader.current)
3175                         si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3176                 else
3177                         si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3178         }
3179
3180         /* TES can be bound as ES or VS. */
3181         r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3182         if (r < 0)
3183                 return false;
3184         if (r == 1) {
3185                 if (sctx->gs_shader.current)
3186                         si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3187                 else
3188                         si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3189         }
3190
3191         return true;
3192 }
3193
3194 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3195 {
3196         unsigned current_scratch_buffer_size =
3197                 si_get_current_scratch_buffer_size(sctx);
3198         unsigned scratch_bytes_per_wave =
3199                 si_get_max_scratch_bytes_per_wave(sctx);
3200         unsigned scratch_needed_size = scratch_bytes_per_wave *
3201                 sctx->scratch_waves;
3202         unsigned spi_tmpring_size;
3203
3204         if (scratch_needed_size > 0) {
3205                 if (scratch_needed_size > current_scratch_buffer_size) {
3206                         /* Create a bigger scratch buffer */
3207                         r600_resource_reference(&sctx->scratch_buffer, NULL);
3208
3209                         sctx->scratch_buffer =
3210                                 si_aligned_buffer_create(&sctx->screen->b,
3211                                                            SI_RESOURCE_FLAG_UNMAPPABLE,
3212                                                            PIPE_USAGE_DEFAULT,
3213                                                            scratch_needed_size, 256);
3214                         if (!sctx->scratch_buffer)
3215                                 return false;
3216
3217                         si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3218                         si_context_add_resource_size(sctx,
3219                                                      &sctx->scratch_buffer->b.b);
3220                 }
3221
3222                 if (!si_update_scratch_relocs(sctx))
3223                         return false;
3224         }
3225
3226         /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3227         assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3228                 "scratch size should already be aligned correctly.");
3229
3230         spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3231                            S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3232         if (spi_tmpring_size != sctx->spi_tmpring_size) {
3233                 sctx->spi_tmpring_size = spi_tmpring_size;
3234                 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3235         }
3236         return true;
3237 }
3238
3239 static void si_init_tess_factor_ring(struct si_context *sctx)
3240 {
3241         assert(!sctx->tess_rings);
3242
3243         /* The address must be aligned to 2^19, because the shader only
3244          * receives the high 13 bits.
3245          */
3246         sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3247                                                     SI_RESOURCE_FLAG_32BIT,
3248                                                     PIPE_USAGE_DEFAULT,
3249                                                     sctx->screen->tess_offchip_ring_size +
3250                                                     sctx->screen->tess_factor_ring_size,
3251                                                     1 << 19);
3252         if (!sctx->tess_rings)
3253                 return;
3254
3255         si_init_config_add_vgt_flush(sctx);
3256
3257         si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3258                       RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3259
3260         uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3261                              sctx->screen->tess_offchip_ring_size;
3262
3263         /* Append these registers to the init config state. */
3264         if (sctx->chip_class >= CIK) {
3265                 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3266                                S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3267                 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3268                                factor_va >> 8);
3269                 if (sctx->chip_class >= GFX9)
3270                         si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3271                                        S_030944_BASE_HI(factor_va >> 40));
3272                 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3273                                sctx->screen->vgt_hs_offchip_param);
3274         } else {
3275                 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3276                                S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3277                 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3278                                factor_va >> 8);
3279                 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3280                                sctx->screen->vgt_hs_offchip_param);
3281         }
3282
3283         /* Flush the context to re-emit the init_config state.
3284          * This is done only once in a lifetime of a context.
3285          */
3286         si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3287         sctx->initial_gfx_cs_size = 0; /* force flush */
3288         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3289 }
3290
3291 static void si_update_vgt_shader_config(struct si_context *sctx)
3292 {
3293         /* Calculate the index of the config.
3294          * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3295         unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3296         struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3297
3298         if (!*pm4) {
3299                 uint32_t stages = 0;
3300
3301                 *pm4 = CALLOC_STRUCT(si_pm4_state);
3302
3303                 if (sctx->tes_shader.cso) {
3304                         stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3305                                   S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3306
3307                         if (sctx->gs_shader.cso)
3308                                 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3309                                           S_028B54_GS_EN(1) |
3310                                           S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3311                         else
3312                                 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3313                 } else if (sctx->gs_shader.cso) {
3314                         stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3315                                   S_028B54_GS_EN(1) |
3316                                   S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3317                 }
3318
3319                 if (sctx->chip_class >= GFX9)
3320                         stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3321
3322                 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3323         }
3324         si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3325 }
3326
3327 bool si_update_shaders(struct si_context *sctx)
3328 {
3329         struct pipe_context *ctx = (struct pipe_context*)sctx;
3330         struct si_compiler_ctx_state compiler_state;
3331         struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3332         struct si_shader *old_vs = si_get_vs_state(sctx);
3333         bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3334         struct si_shader *old_ps = sctx->ps_shader.current;
3335         unsigned old_spi_shader_col_format =
3336                 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3337         int r;
3338
3339         compiler_state.compiler = &sctx->compiler;
3340         compiler_state.debug = sctx->debug;
3341         compiler_state.is_debug_context = sctx->is_debug;
3342
3343         /* Update stages before GS. */
3344         if (sctx->tes_shader.cso) {
3345                 if (!sctx->tess_rings) {
3346                         si_init_tess_factor_ring(sctx);
3347                         if (!sctx->tess_rings)
3348                                 return false;
3349                 }
3350
3351                 /* VS as LS */
3352                 if (sctx->chip_class <= VI) {
3353                         r = si_shader_select(ctx, &sctx->vs_shader,
3354                                              &compiler_state);
3355                         if (r)
3356                                 return false;
3357                         si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3358                 }
3359
3360                 if (sctx->tcs_shader.cso) {
3361                         r = si_shader_select(ctx, &sctx->tcs_shader,
3362                                              &compiler_state);
3363                         if (r)
3364                                 return false;
3365                         si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3366                 } else {
3367                         if (!sctx->fixed_func_tcs_shader.cso) {
3368                                 sctx->fixed_func_tcs_shader.cso =
3369                                         si_create_fixed_func_tcs(sctx);
3370                                 if (!sctx->fixed_func_tcs_shader.cso)
3371                                         return false;
3372                         }
3373
3374                         r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3375                                              &compiler_state);
3376                         if (r)
3377                                 return false;
3378                         si_pm4_bind_state(sctx, hs,
3379                                           sctx->fixed_func_tcs_shader.current->pm4);
3380                 }
3381
3382                 if (sctx->gs_shader.cso) {
3383                         /* TES as ES */
3384                         if (sctx->chip_class <= VI) {
3385                                 r = si_shader_select(ctx, &sctx->tes_shader,
3386                                                      &compiler_state);
3387                                 if (r)
3388                                         return false;
3389                                 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3390                         }
3391                 } else {
3392                         /* TES as VS */
3393                         r = si_shader_select(ctx, &sctx->tes_shader,
3394                                              &compiler_state);
3395                         if (r)
3396                                 return false;
3397                         si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3398                 }
3399         } else if (sctx->gs_shader.cso) {
3400                 if (sctx->chip_class <= VI) {
3401                         /* VS as ES */
3402                         r = si_shader_select(ctx, &sctx->vs_shader,
3403                                              &compiler_state);
3404                         if (r)
3405                                 return false;
3406                         si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3407
3408                         si_pm4_bind_state(sctx, ls, NULL);
3409                         si_pm4_bind_state(sctx, hs, NULL);
3410                 }
3411         } else {
3412                 /* VS as VS */
3413                 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3414                 if (r)
3415                         return false;
3416                 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3417                 si_pm4_bind_state(sctx, ls, NULL);
3418                 si_pm4_bind_state(sctx, hs, NULL);
3419         }
3420
3421         /* Update GS. */
3422         if (sctx->gs_shader.cso) {
3423                 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3424                 if (r)
3425                         return false;
3426                 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3427                 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3428
3429                 if (!si_update_gs_ring_buffers(sctx))
3430                         return false;
3431         } else {
3432                 si_pm4_bind_state(sctx, gs, NULL);
3433                 if (sctx->chip_class <= VI)
3434                         si_pm4_bind_state(sctx, es, NULL);
3435         }
3436
3437         si_update_vgt_shader_config(sctx);
3438
3439         if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3440                 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3441
3442         if (sctx->ps_shader.cso) {
3443                 unsigned db_shader_control;
3444
3445                 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3446                 if (r)
3447                         return false;
3448                 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3449
3450                 db_shader_control =
3451                         sctx->ps_shader.cso->db_shader_control |
3452                         S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3453
3454                 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3455                     sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3456                     sctx->flatshade != rs->flatshade) {
3457                         sctx->sprite_coord_enable = rs->sprite_coord_enable;
3458                         sctx->flatshade = rs->flatshade;
3459                         si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3460                 }
3461
3462                 if (sctx->screen->rbplus_allowed &&
3463                     si_pm4_state_changed(sctx, ps) &&
3464                     (!old_ps ||
3465                      old_spi_shader_col_format !=
3466                      sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3467                         si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3468
3469                 if (sctx->ps_db_shader_control != db_shader_control) {
3470                         sctx->ps_db_shader_control = db_shader_control;
3471                         si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3472                         if (sctx->screen->dpbb_allowed)
3473                                 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3474                 }
3475
3476                 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3477                         sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3478                         si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3479
3480                         if (sctx->chip_class == SI)
3481                                 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3482
3483                         if (sctx->framebuffer.nr_samples <= 1)
3484                                 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3485                 }
3486         }
3487
3488         if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3489             si_pm4_state_enabled_and_changed(sctx, hs) ||
3490             si_pm4_state_enabled_and_changed(sctx, es) ||
3491             si_pm4_state_enabled_and_changed(sctx, gs) ||
3492             si_pm4_state_enabled_and_changed(sctx, vs) ||
3493             si_pm4_state_enabled_and_changed(sctx, ps)) {
3494                 if (!si_update_spi_tmpring_size(sctx))
3495                         return false;
3496         }
3497
3498         if (sctx->chip_class >= CIK) {
3499                 if (si_pm4_state_enabled_and_changed(sctx, ls))
3500                         sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3501                 else if (!sctx->queued.named.ls)
3502                         sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3503
3504                 if (si_pm4_state_enabled_and_changed(sctx, hs))
3505                         sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3506                 else if (!sctx->queued.named.hs)
3507                         sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3508
3509                 if (si_pm4_state_enabled_and_changed(sctx, es))
3510                         sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3511                 else if (!sctx->queued.named.es)
3512                         sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3513
3514                 if (si_pm4_state_enabled_and_changed(sctx, gs))
3515                         sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3516                 else if (!sctx->queued.named.gs)
3517                         sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3518
3519                 if (si_pm4_state_enabled_and_changed(sctx, vs))
3520                         sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3521                 else if (!sctx->queued.named.vs)
3522                         sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3523
3524                 if (si_pm4_state_enabled_and_changed(sctx, ps))
3525                         sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3526                 else if (!sctx->queued.named.ps)
3527                         sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3528         }
3529
3530         sctx->do_update_shaders = false;
3531         return true;
3532 }
3533
3534 static void si_emit_scratch_state(struct si_context *sctx)
3535 {
3536         struct radeon_cmdbuf *cs = sctx->gfx_cs;
3537
3538         radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3539                                sctx->spi_tmpring_size);
3540
3541         if (sctx->scratch_buffer) {
3542                 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3543                                       sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3544                                       RADEON_PRIO_SCRATCH_BUFFER);
3545         }
3546 }
3547
3548 void si_init_shader_functions(struct si_context *sctx)
3549 {
3550         sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3551         sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3552
3553         sctx->b.create_vs_state = si_create_shader_selector;
3554         sctx->b.create_tcs_state = si_create_shader_selector;
3555         sctx->b.create_tes_state = si_create_shader_selector;
3556         sctx->b.create_gs_state = si_create_shader_selector;
3557         sctx->b.create_fs_state = si_create_shader_selector;
3558
3559         sctx->b.bind_vs_state = si_bind_vs_shader;
3560         sctx->b.bind_tcs_state = si_bind_tcs_shader;
3561         sctx->b.bind_tes_state = si_bind_tes_shader;
3562         sctx->b.bind_gs_state = si_bind_gs_shader;
3563         sctx->b.bind_fs_state = si_bind_ps_shader;
3564
3565         sctx->b.delete_vs_state = si_delete_shader_selector;
3566         sctx->b.delete_tcs_state = si_delete_shader_selector;
3567         sctx->b.delete_tes_state = si_delete_shader_selector;
3568         sctx->b.delete_gs_state = si_delete_shader_selector;
3569         sctx->b.delete_fs_state = si_delete_shader_selector;
3570 }