2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
26 #include "util/u_viewport.h"
27 #include "tgsi/tgsi_scan.h"
29 #define SI_MAX_SCISSOR 16384
31 static void si_set_scissor_states(struct pipe_context *pctx,
33 unsigned num_scissors,
34 const struct pipe_scissor_state *state)
36 struct si_context *ctx = (struct si_context *)pctx;
39 for (i = 0; i < num_scissors; i++)
40 ctx->scissors.states[start_slot + i] = state[i];
42 if (!ctx->queued.named.rasterizer ||
43 !ctx->queued.named.rasterizer->scissor_enable)
46 ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
47 si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
50 /* Since the guard band disables clipping, we have to clip per-pixel
53 static void si_get_scissor_from_viewport(struct si_context *ctx,
54 const struct pipe_viewport_state *vp,
55 struct si_signed_scissor *scissor)
57 float tmp, minx, miny, maxx, maxy;
59 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
60 minx = -vp->scale[0] + vp->translate[0];
61 miny = -vp->scale[1] + vp->translate[1];
62 maxx = vp->scale[0] + vp->translate[0];
63 maxy = vp->scale[1] + vp->translate[1];
65 /* Handle inverted viewports. */
77 /* Convert to integer and round up the max bounds. */
80 scissor->maxx = ceilf(maxx);
81 scissor->maxy = ceilf(maxy);
84 static void si_clamp_scissor(struct si_context *ctx,
85 struct pipe_scissor_state *out,
86 struct si_signed_scissor *scissor)
88 out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
89 out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
90 out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
91 out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
94 static void si_clip_scissor(struct pipe_scissor_state *out,
95 struct pipe_scissor_state *clip)
97 out->minx = MAX2(out->minx, clip->minx);
98 out->miny = MAX2(out->miny, clip->miny);
99 out->maxx = MIN2(out->maxx, clip->maxx);
100 out->maxy = MIN2(out->maxy, clip->maxy);
103 static void si_scissor_make_union(struct si_signed_scissor *out,
104 struct si_signed_scissor *in)
106 out->minx = MIN2(out->minx, in->minx);
107 out->miny = MIN2(out->miny, in->miny);
108 out->maxx = MAX2(out->maxx, in->maxx);
109 out->maxy = MAX2(out->maxy, in->maxy);
110 out->quant_mode = MIN2(out->quant_mode, in->quant_mode);
113 static void si_emit_one_scissor(struct si_context *ctx,
114 struct radeon_cmdbuf *cs,
115 struct si_signed_scissor *vp_scissor,
116 struct pipe_scissor_state *scissor)
118 struct pipe_scissor_state final;
120 if (ctx->vs_disables_clipping_viewport) {
121 final.minx = final.miny = 0;
122 final.maxx = final.maxy = SI_MAX_SCISSOR;
124 si_clamp_scissor(ctx, &final, vp_scissor);
128 si_clip_scissor(&final, scissor);
130 /* Workaround for a hw bug on SI that occurs when PA_SU_HARDWARE_-
131 * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
133 if (ctx->chip_class == SI && (final.maxx == 0 || final.maxy == 0)) {
134 radeon_emit(cs, S_028250_TL_X(1) |
136 S_028250_WINDOW_OFFSET_DISABLE(1));
137 radeon_emit(cs, S_028254_BR_X(1) |
142 radeon_emit(cs, S_028250_TL_X(final.minx) |
143 S_028250_TL_Y(final.miny) |
144 S_028250_WINDOW_OFFSET_DISABLE(1));
145 radeon_emit(cs, S_028254_BR_X(final.maxx) |
146 S_028254_BR_Y(final.maxy));
149 #define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176
151 static void si_emit_guardband(struct si_context *ctx)
153 const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
154 struct si_signed_scissor vp_as_scissor;
155 struct pipe_viewport_state vp;
156 float left, top, right, bottom, max_range, guardband_x, guardband_y;
157 float discard_x, discard_y;
159 if (ctx->vs_writes_viewport_index) {
160 /* Shaders can draw to any viewport. Make a union of all
162 vp_as_scissor = ctx->viewports.as_scissor[0];
163 for (unsigned i = 1; i < SI_MAX_VIEWPORTS; i++) {
164 si_scissor_make_union(&vp_as_scissor,
165 &ctx->viewports.as_scissor[i]);
168 vp_as_scissor = ctx->viewports.as_scissor[0];
171 /* Blits don't set the viewport state. The vertex shader determines
172 * the viewport size by scaling the coordinates, so we don't know
173 * how large the viewport is. Assume the worst case.
175 if (ctx->vs_disables_clipping_viewport)
176 vp_as_scissor.quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
178 /* Determine the optimal hardware screen offset to center the viewport
179 * within the viewport range in order to maximize the guardband size.
181 int hw_screen_offset_x = (vp_as_scissor.maxx + vp_as_scissor.minx) / 2;
182 int hw_screen_offset_y = (vp_as_scissor.maxy + vp_as_scissor.miny) / 2;
184 /* SI-CI need to align the offset to an ubertile consisting of all SEs. */
185 const unsigned hw_screen_offset_alignment =
186 ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
188 /* Indexed by quantization modes */
189 static unsigned max_viewport_size[] = {65535, 16383, 4095};
191 /* Ensure that the whole viewport stays representable in
192 * absolute coordinates.
193 * See comment in si_set_viewport_states.
195 assert(vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode] &&
196 vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]);
198 hw_screen_offset_x = CLAMP(hw_screen_offset_x, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
199 hw_screen_offset_y = CLAMP(hw_screen_offset_y, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
201 /* Align the screen offset by dropping the low bits. */
202 hw_screen_offset_x &= ~(hw_screen_offset_alignment - 1);
203 hw_screen_offset_y &= ~(hw_screen_offset_alignment - 1);
205 /* Apply the offset to center the viewport and maximize the guardband. */
206 vp_as_scissor.minx -= hw_screen_offset_x;
207 vp_as_scissor.maxx -= hw_screen_offset_x;
208 vp_as_scissor.miny -= hw_screen_offset_y;
209 vp_as_scissor.maxy -= hw_screen_offset_y;
211 /* Reconstruct the viewport transformation from the scissor. */
212 vp.translate[0] = (vp_as_scissor.minx + vp_as_scissor.maxx) / 2.0;
213 vp.translate[1] = (vp_as_scissor.miny + vp_as_scissor.maxy) / 2.0;
214 vp.scale[0] = vp_as_scissor.maxx - vp.translate[0];
215 vp.scale[1] = vp_as_scissor.maxy - vp.translate[1];
217 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
218 if (vp_as_scissor.minx == vp_as_scissor.maxx)
220 if (vp_as_scissor.miny == vp_as_scissor.maxy)
223 /* Find the biggest guard band that is inside the supported viewport
224 * range. The guard band is specified as a horizontal and vertical
225 * distance from (0,0) in clip space.
227 * This is done by applying the inverse viewport transformation
228 * on the viewport limits to get those limits in clip space.
230 * The viewport range is [-max_viewport_size/2, max_viewport_size/2].
232 assert(vp_as_scissor.quant_mode < ARRAY_SIZE(max_viewport_size));
233 max_range = max_viewport_size[vp_as_scissor.quant_mode] / 2;
234 left = (-max_range - vp.translate[0]) / vp.scale[0];
235 right = ( max_range - vp.translate[0]) / vp.scale[0];
236 top = (-max_range - vp.translate[1]) / vp.scale[1];
237 bottom = ( max_range - vp.translate[1]) / vp.scale[1];
239 assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
241 guardband_x = MIN2(-left, right);
242 guardband_y = MIN2(-top, bottom);
247 if (unlikely(util_prim_is_points_or_lines(ctx->current_rast_prim))) {
248 /* When rendering wide points or lines, we need to be more
249 * conservative about when to discard them entirely. */
252 if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
253 pixels = rs->max_point_size;
255 pixels = rs->line_width;
257 /* Add half the point size / line width */
258 discard_x += pixels / (2.0 * vp.scale[0]);
259 discard_y += pixels / (2.0 * vp.scale[1]);
261 /* Discard primitives that would lie entirely outside the clip
263 discard_x = MIN2(discard_x, guardband_x);
264 discard_y = MIN2(discard_y, guardband_y);
267 /* If any of the GB registers is updated, all of them must be updated.
268 * R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
269 * R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
271 unsigned initial_cdw = ctx->gfx_cs->current.cdw;
272 radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
273 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ,
274 fui(guardband_y), fui(discard_y),
275 fui(guardband_x), fui(discard_x));
276 radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
277 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
278 S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x >> 4) |
279 S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
280 radeon_opt_set_context_reg(ctx, R_028BE4_PA_SU_VTX_CNTL,
281 SI_TRACKED_PA_SU_VTX_CNTL,
282 S_028BE4_PIX_CENTER(rs->half_pixel_center) |
283 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
284 vp_as_scissor.quant_mode));
285 if (initial_cdw != ctx->gfx_cs->current.cdw)
286 ctx->context_roll_counter++;
289 static void si_emit_scissors(struct si_context *ctx)
291 struct radeon_cmdbuf *cs = ctx->gfx_cs;
292 struct pipe_scissor_state *states = ctx->scissors.states;
293 unsigned mask = ctx->scissors.dirty_mask;
294 bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
296 /* The simple case: Only 1 viewport is active. */
297 if (!ctx->vs_writes_viewport_index) {
298 struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
303 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
304 si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
305 ctx->scissors.dirty_mask &= ~1; /* clear one bit */
312 u_bit_scan_consecutive_range(&mask, &start, &count);
314 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
315 start * 4 * 2, count * 2);
316 for (i = start; i < start+count; i++) {
317 si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
318 scissor_enabled ? &states[i] : NULL);
321 ctx->scissors.dirty_mask = 0;
324 static void si_set_viewport_states(struct pipe_context *pctx,
326 unsigned num_viewports,
327 const struct pipe_viewport_state *state)
329 struct si_context *ctx = (struct si_context *)pctx;
333 for (i = 0; i < num_viewports; i++) {
334 unsigned index = start_slot + i;
335 struct si_signed_scissor *scissor = &ctx->viewports.as_scissor[index];
337 ctx->viewports.states[index] = state[i];
339 si_get_scissor_from_viewport(ctx, &state[i], scissor);
341 unsigned w = scissor->maxx - scissor->minx;
342 unsigned h = scissor->maxy - scissor->miny;
343 unsigned max_extent = MAX2(w, h);
345 int max_corner = MAX2(scissor->maxx, scissor->maxy);
347 unsigned center_x = (scissor->maxx + scissor->minx) / 2;
348 unsigned center_y = (scissor->maxy + scissor->miny) / 2;
349 unsigned max_center = MAX2(center_x, center_y);
351 /* PA_SU_HARDWARE_SCREEN_OFFSET can't center viewports whose
352 * center start farther than MAX_PA_SU_HARDWARE_SCREEN_OFFSET.
353 * (for example, a 1x1 viewport in the lower right corner of
354 * 16Kx16K) Such viewports need a greater guardband, so they
355 * have to use a worse quantization mode.
357 unsigned distance_off_center =
358 MAX2(0, (int)max_center - MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
359 max_extent += distance_off_center;
361 /* Determine the best quantization mode (subpixel precision),
362 * but also leave enough space for the guardband.
364 * Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
365 * and Raven1. What we do depends on the chip:
366 * - Vega10: Never use primitive binning.
367 * - Raven1: Always use QUANT_MODE == 16_8.
369 if (ctx->family == CHIP_RAVEN)
370 max_extent = 16384; /* Use QUANT_MODE == 16_8. */
372 /* Another constraint is that all coordinates in the viewport
373 * are representable in fixed point with respect to the
376 * It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
377 * an offset that would make the upper corner of the viewport
378 * greater than the maximum representable number post
379 * quantization, ie 2^quant_bits.
381 * This does not matter for 14.10 and 16.8 formats since the
382 * offset is already limited at 8k, but it means we can't use
383 * 12.12 if we are drawing to some pixels outside the lower
384 * 4k x 4k of the render target.
387 if (max_extent <= 1024 && max_corner < 4096) /* 4K scanline area for guardband */
388 scissor->quant_mode = SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
389 else if (max_extent <= 4096) /* 16K scanline area for guardband */
390 scissor->quant_mode = SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
391 else /* 64K scanline area for guardband */
392 scissor->quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
395 mask = ((1 << num_viewports) - 1) << start_slot;
396 ctx->viewports.dirty_mask |= mask;
397 ctx->viewports.depth_range_dirty_mask |= mask;
398 ctx->scissors.dirty_mask |= mask;
399 si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
400 si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
401 si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
404 static void si_emit_one_viewport(struct si_context *ctx,
405 struct pipe_viewport_state *state)
407 struct radeon_cmdbuf *cs = ctx->gfx_cs;
409 radeon_emit(cs, fui(state->scale[0]));
410 radeon_emit(cs, fui(state->translate[0]));
411 radeon_emit(cs, fui(state->scale[1]));
412 radeon_emit(cs, fui(state->translate[1]));
413 radeon_emit(cs, fui(state->scale[2]));
414 radeon_emit(cs, fui(state->translate[2]));
417 static void si_emit_viewports(struct si_context *ctx)
419 struct radeon_cmdbuf *cs = ctx->gfx_cs;
420 struct pipe_viewport_state *states = ctx->viewports.states;
421 unsigned mask = ctx->viewports.dirty_mask;
423 /* The simple case: Only 1 viewport is active. */
424 if (!ctx->vs_writes_viewport_index) {
428 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
429 si_emit_one_viewport(ctx, &states[0]);
430 ctx->viewports.dirty_mask &= ~1; /* clear one bit */
437 u_bit_scan_consecutive_range(&mask, &start, &count);
439 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
440 start * 4 * 6, count * 6);
441 for (i = start; i < start+count; i++)
442 si_emit_one_viewport(ctx, &states[i]);
444 ctx->viewports.dirty_mask = 0;
448 si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
449 bool window_space_position, float *zmin, float *zmax)
451 if (window_space_position) {
456 util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
459 static void si_emit_depth_ranges(struct si_context *ctx)
461 struct radeon_cmdbuf *cs = ctx->gfx_cs;
462 struct pipe_viewport_state *states = ctx->viewports.states;
463 unsigned mask = ctx->viewports.depth_range_dirty_mask;
464 bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
465 bool window_space = ctx->vs_disables_clipping_viewport;
468 /* The simple case: Only 1 viewport is active. */
469 if (!ctx->vs_writes_viewport_index) {
473 si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
476 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
477 radeon_emit(cs, fui(zmin));
478 radeon_emit(cs, fui(zmax));
479 ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
486 u_bit_scan_consecutive_range(&mask, &start, &count);
488 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
489 start * 4 * 2, count * 2);
490 for (i = start; i < start+count; i++) {
491 si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
493 radeon_emit(cs, fui(zmin));
494 radeon_emit(cs, fui(zmax));
497 ctx->viewports.depth_range_dirty_mask = 0;
500 static void si_emit_viewport_states(struct si_context *ctx)
502 si_emit_viewports(ctx);
503 si_emit_depth_ranges(ctx);
507 * This reacts to 2 state changes:
508 * - VS.writes_viewport_index
509 * - VS output position in window space (enable/disable)
511 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
512 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
513 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
514 * called to emit the rest.
516 void si_update_vs_viewport_state(struct si_context *ctx)
518 struct tgsi_shader_info *info = si_get_vs_info(ctx);
519 bool vs_window_space;
524 /* When the VS disables clipping and viewport transformation. */
526 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
528 if (ctx->vs_disables_clipping_viewport != vs_window_space) {
529 ctx->vs_disables_clipping_viewport = vs_window_space;
530 ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
531 ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
532 si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
533 si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
536 /* Viewport index handling. */
537 if (ctx->vs_writes_viewport_index == info->writes_viewport_index)
540 /* This changes how the guardband is computed. */
541 ctx->vs_writes_viewport_index = info->writes_viewport_index;
542 si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
544 if (!ctx->vs_writes_viewport_index)
547 if (ctx->scissors.dirty_mask)
548 si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
550 if (ctx->viewports.dirty_mask ||
551 ctx->viewports.depth_range_dirty_mask)
552 si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
555 static void si_emit_window_rectangles(struct si_context *sctx)
557 /* There are four clipping rectangles. Their corner coordinates are inclusive.
558 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
559 * on whether the pixel is inside cliprects 0-3, respectively. For example,
560 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
561 * the number 3 (binary 0011).
563 * If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
565 struct radeon_cmdbuf *cs = sctx->gfx_cs;
566 static const unsigned outside[4] = {
567 /* outside rectangle 0 */
576 /* outside rectangles 0, 1 */
581 /* outside rectangles 0, 1, 2 */
584 /* outside rectangles 0, 1, 2, 3 */
587 const unsigned disabled = 0xffff; /* all inside and outside cases */
588 unsigned num_rectangles = sctx->num_window_rectangles;
589 struct pipe_scissor_state *rects = sctx->window_rectangles;
592 assert(num_rectangles <= 4);
594 if (num_rectangles == 0)
596 else if (sctx->window_rectangles_include)
597 rule = ~outside[num_rectangles - 1];
599 rule = outside[num_rectangles - 1];
601 radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE,
602 SI_TRACKED_PA_SC_CLIPRECT_RULE, rule);
603 if (num_rectangles == 0)
606 radeon_set_context_reg_seq(cs, R_028210_PA_SC_CLIPRECT_0_TL,
608 for (unsigned i = 0; i < num_rectangles; i++) {
609 radeon_emit(cs, S_028210_TL_X(rects[i].minx) |
610 S_028210_TL_Y(rects[i].miny));
611 radeon_emit(cs, S_028214_BR_X(rects[i].maxx) |
612 S_028214_BR_Y(rects[i].maxy));
616 static void si_set_window_rectangles(struct pipe_context *ctx,
618 unsigned num_rectangles,
619 const struct pipe_scissor_state *rects)
621 struct si_context *sctx = (struct si_context *)ctx;
623 sctx->num_window_rectangles = num_rectangles;
624 sctx->window_rectangles_include = include;
625 if (num_rectangles) {
626 memcpy(sctx->window_rectangles, rects,
627 sizeof(*rects) * num_rectangles);
630 si_mark_atom_dirty(sctx, &sctx->atoms.s.window_rectangles);
633 void si_init_viewport_functions(struct si_context *ctx)
635 ctx->atoms.s.guardband.emit = si_emit_guardband;
636 ctx->atoms.s.scissors.emit = si_emit_scissors;
637 ctx->atoms.s.viewports.emit = si_emit_viewport_states;
638 ctx->atoms.s.window_rectangles.emit = si_emit_window_rectangles;
640 ctx->b.set_scissor_states = si_set_scissor_states;
641 ctx->b.set_viewport_states = si_set_viewport_states;
642 ctx->b.set_window_rectangles = si_set_window_rectangles;
644 for (unsigned i = 0; i < 16; i++)
645 ctx->viewports.as_scissor[i].quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;