2 * Southern Islands Register documentation
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define SI_CONFIG_REG_OFFSET 0x00008000
29 #define SI_CONFIG_REG_END 0x0000B000
30 #define SI_SH_REG_OFFSET 0x0000B000
31 #define SI_SH_REG_END 0x0000C000
32 #define SI_CONTEXT_REG_OFFSET 0x00028000
33 #define SI_CONTEXT_REG_END 0x00029000
35 #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
36 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
37 #define EVENT_TYPE_ZPASS_DONE 0x15
38 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
39 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f
40 #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20
41 #define EVENT_TYPE(x) ((x) << 0)
42 #define EVENT_INDEX(x) ((x) << 8)
43 /* 0 - any non-TS event
45 * 2 - SAMPLE_PIPELINESTAT
46 * 3 - SAMPLE_STREAMOUTSTAT*
47 * 4 - *S_PARTIAL_FLUSH
51 #define PREDICATION_OP_CLEAR 0x0
52 #define PREDICATION_OP_ZPASS 0x1
53 #define PREDICATION_OP_PRIMCOUNT 0x2
55 #define PRED_OP(x) ((x) << 16)
57 #define PREDICATION_CONTINUE (1 << 31)
59 #define PREDICATION_HINT_WAIT (0 << 12)
60 #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
62 #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
63 #define PREDICATION_DRAW_VISIBLE (1 << 8)
65 #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
68 #define PKT3_SET_PREDICATION 0x20
69 #define PKT3_COND_EXEC 0x22
70 #define PKT3_PRED_EXEC 0x23
71 #define PKT3_START_3D_CMDBUF 0x24
72 #define PKT3_DRAW_INDEX_2 0x27
73 #define PKT3_CONTEXT_CONTROL 0x28
74 #define PKT3_INDEX_TYPE 0x2A
75 #define PKT3_DRAW_INDEX 0x2B
76 #define PKT3_DRAW_INDEX_AUTO 0x2D
77 #define PKT3_DRAW_INDEX_IMMD 0x2E
78 #define PKT3_NUM_INSTANCES 0x2F
79 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34
80 #define PKT3_MEM_SEMAPHORE 0x39
81 #define PKT3_MPEG_INDEX 0x3A
82 #define PKT3_WAIT_REG_MEM 0x3C
83 #define WAIT_REG_MEM_EQUAL 3
84 #define PKT3_MEM_WRITE 0x3D
85 #define PKT3_INDIRECT_BUFFER 0x32
86 #define PKT3_SURFACE_SYNC 0x43
87 #define PKT3_ME_INITIALIZE 0x44
88 #define PKT3_COND_WRITE 0x45
89 #define PKT3_EVENT_WRITE 0x46
90 #define PKT3_EVENT_WRITE_EOP 0x47
91 #define PKT3_EVENT_WRITE_EOS 0x48
92 #define PKT3_ONE_REG_WRITE 0x57
93 #define PKT3_SET_CONFIG_REG 0x68
94 #define PKT3_SET_CONTEXT_REG 0x69
95 #define PKT3_SET_SH_REG 0x76
97 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
98 #define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
99 #define PKT_TYPE_C 0x3FFFFFFF
100 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
101 #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
102 #define PKT_COUNT_C 0xC000FFFF
103 #define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0)
104 #define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
105 #define PKT0_BASE_INDEX_C 0xFFFF0000
106 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
107 #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
108 #define PKT3_IT_OPCODE_C 0xFFFF00FF
109 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
110 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
111 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate))
113 #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
114 #define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0)
115 #define R_0085F0_CP_COHER_CNTL 0x0085F0
116 #define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
117 #define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
118 #define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
119 #define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
120 #define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
121 #define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
122 #define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6
123 #define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
124 #define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
125 #define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
126 #define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
127 #define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
128 #define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
129 #define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
130 #define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
131 #define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
132 #define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
133 #define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
134 #define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
135 #define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
136 #define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
137 #define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
138 #define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
139 #define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
140 #define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
141 #define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
142 #define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
143 #define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
144 #define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
145 #define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
146 #define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
147 #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
148 #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
149 #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
150 #define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19)
151 #define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1)
152 #define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF
153 #define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21)
154 #define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1)
155 #define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF
156 #define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22)
157 #define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1)
158 #define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF
159 #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
160 #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
161 #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
162 #define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
163 #define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
164 #define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF
165 #define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
166 #define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
167 #define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
168 #define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27)
169 #define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1)
170 #define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF
171 #define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29)
172 #define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
173 #define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
174 #define R_0085F4_CP_COHER_SIZE 0x0085F4
175 #define R_0085F8_CP_COHER_BASE 0x0085F8
176 #define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0
177 #define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0)
178 #define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF)
179 #define C_0088B0_PRIM_COUNT 0xFFFFFC00
180 #define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4
181 #define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5)
182 #define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1)
183 #define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF
184 #define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13)
185 #define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1)
186 #define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF
187 #define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16)
188 #define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F)
189 #define C_0088C4_ES_LIMIT 0xFFE0FFFF
190 #define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8
191 #define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC
192 #define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4
193 #define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0)
194 #define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F)
195 #define C_0088D4_VERT_REUSE 0xFFFFFFE0
196 #define R_008958_VGT_PRIMITIVE_TYPE 0x008958
197 #define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0)
198 #define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
199 #define C_008958_PRIM_TYPE 0xFFFFFFC0
200 #define V_008958_DI_PT_NONE 0x00
201 #define V_008958_DI_PT_POINTLIST 0x01
202 #define V_008958_DI_PT_LINELIST 0x02
203 #define V_008958_DI_PT_LINESTRIP 0x03
204 #define V_008958_DI_PT_TRILIST 0x04
205 #define V_008958_DI_PT_TRIFAN 0x05
206 #define V_008958_DI_PT_TRISTRIP 0x06
207 #define V_008958_DI_PT_UNUSED_0 0x07
208 #define V_008958_DI_PT_UNUSED_1 0x08
209 #define V_008958_DI_PT_PATCH 0x09
210 #define V_008958_DI_PT_LINELIST_ADJ 0x0A
211 #define V_008958_DI_PT_LINESTRIP_ADJ 0x0B
212 #define V_008958_DI_PT_TRILIST_ADJ 0x0C
213 #define V_008958_DI_PT_TRISTRIP_ADJ 0x0D
214 #define V_008958_DI_PT_UNUSED_3 0x0E
215 #define V_008958_DI_PT_UNUSED_4 0x0F
216 #define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10
217 #define V_008958_DI_PT_RECTLIST 0x11
218 #define V_008958_DI_PT_LINELOOP 0x12
219 #define V_008958_DI_PT_QUADLIST 0x13
220 #define V_008958_DI_PT_QUADSTRIP 0x14
221 #define V_008958_DI_PT_POLYGON 0x15
222 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16
223 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17
224 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18
225 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19
226 #define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A
227 #define V_008958_DI_PT_2D_LINE_STRIP 0x1B
228 #define V_008958_DI_PT_2D_TRI_STRIP 0x1C
229 #define R_00895C_VGT_INDEX_TYPE 0x00895C
230 #define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0)
231 #define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
232 #define C_00895C_INDEX_TYPE 0xFFFFFFFC
233 #define V_00895C_DI_INDEX_SIZE_16_BIT 0x00
234 #define V_00895C_DI_INDEX_SIZE_32_BIT 0x01
235 #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960
236 #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964
237 #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968
238 #define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C
239 #define R_008970_VGT_NUM_INDICES 0x008970
240 #define R_008974_VGT_NUM_INSTANCES 0x008974
241 #define R_008988_VGT_TF_RING_SIZE 0x008988
242 #define S_008988_SIZE(x) (((x) & 0xFFFF) << 0)
243 #define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF)
244 #define C_008988_SIZE 0xFFFF0000
245 #define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0
246 #define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0)
247 #define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F)
248 #define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80
249 #define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8
250 #define R_008A14_PA_CL_ENHANCE 0x008A14
251 #define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0)
252 #define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1)
253 #define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE
254 #define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1)
255 #define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03)
256 #define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9
257 #define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3)
258 #define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1)
259 #define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7
260 #define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4)
261 #define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1)
262 #define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF
263 #define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60
264 #define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0)
265 #define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF)
266 #define C_008A60_LINE_STIPPLE_VALUE 0xFF000000
267 #define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10
268 #define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0)
269 #define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F)
270 #define C_008B10_CURRENT_PTR 0xFFFFFFF0
271 #define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8)
272 #define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF)
273 #define C_008B10_CURRENT_COUNT 0xFFFF00FF
274 #define R_008BF0_PA_SC_ENHANCE 0x008BF0
275 #define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0)
276 #define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1)
277 #define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE
278 #define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1)
279 #define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1)
280 #define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD
281 #define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2)
282 #define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1)
283 #define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB
284 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3)
285 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1)
286 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7
287 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4)
288 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1)
289 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF
290 #define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5)
291 #define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1)
292 #define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF
293 #define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6)
294 #define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03)
295 #define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F
296 #define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8)
297 #define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1)
298 #define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF
299 #define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9)
300 #define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1)
301 #define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF
302 #define R_008C08_SQC_CACHES 0x008C08
303 #define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0)
304 #define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1)
305 #define C_008C08_INST_INVALIDATE 0xFFFFFFFE
306 #define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1)
307 #define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1)
308 #define C_008C08_DATA_INVALIDATE 0xFFFFFFFD
309 #define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C
310 #define S_008C0C_RET(x) (((x) & 0x7F) << 0)
311 #define G_008C0C_RET(x) (((x) >> 0) & 0x7F)
312 #define C_008C0C_RET 0xFFFFFF80
313 #define S_008C0C_RUI(x) (((x) & 0x07) << 7)
314 #define G_008C0C_RUI(x) (((x) >> 7) & 0x07)
315 #define C_008C0C_RUI 0xFFFFFC7F
316 #define S_008C0C_RNG(x) (((x) & 0x7FF) << 10)
317 #define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF)
318 #define C_008C0C_RNG 0xFFE003FF
320 #define R_008DFC_SQ_INST 0x008DFC
321 #define R_008DFC_SQ_VOP1 0x008DFC
322 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
323 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
324 #define C_008DFC_SRC0 0xFFFFFE00
325 #define V_008DFC_SQ_SGPR 0x00
326 #define V_008DFC_SQ_VCC_LO 0x6A
327 #define V_008DFC_SQ_VCC_HI 0x6B
328 #define V_008DFC_SQ_TBA_LO 0x6C
329 #define V_008DFC_SQ_TBA_HI 0x6D
330 #define V_008DFC_SQ_TMA_LO 0x6E
331 #define V_008DFC_SQ_TMA_HI 0x6F
332 #define V_008DFC_SQ_TTMP0 0x70
333 #define V_008DFC_SQ_TTMP1 0x71
334 #define V_008DFC_SQ_TTMP2 0x72
335 #define V_008DFC_SQ_TTMP3 0x73
336 #define V_008DFC_SQ_TTMP4 0x74
337 #define V_008DFC_SQ_TTMP5 0x75
338 #define V_008DFC_SQ_TTMP6 0x76
339 #define V_008DFC_SQ_TTMP7 0x77
340 #define V_008DFC_SQ_TTMP8 0x78
341 #define V_008DFC_SQ_TTMP9 0x79
342 #define V_008DFC_SQ_TTMP10 0x7A
343 #define V_008DFC_SQ_TTMP11 0x7B
344 #define V_008DFC_SQ_M0 0x7C
345 #define V_008DFC_SQ_EXEC_LO 0x7E
346 #define V_008DFC_SQ_EXEC_HI 0x7F
347 #define V_008DFC_SQ_SRC_0 0x80
348 #define V_008DFC_SQ_SRC_1_INT 0x81
349 #define V_008DFC_SQ_SRC_2_INT 0x82
350 #define V_008DFC_SQ_SRC_3_INT 0x83
351 #define V_008DFC_SQ_SRC_4_INT 0x84
352 #define V_008DFC_SQ_SRC_5_INT 0x85
353 #define V_008DFC_SQ_SRC_6_INT 0x86
354 #define V_008DFC_SQ_SRC_7_INT 0x87
355 #define V_008DFC_SQ_SRC_8_INT 0x88
356 #define V_008DFC_SQ_SRC_9_INT 0x89
357 #define V_008DFC_SQ_SRC_10_INT 0x8A
358 #define V_008DFC_SQ_SRC_11_INT 0x8B
359 #define V_008DFC_SQ_SRC_12_INT 0x8C
360 #define V_008DFC_SQ_SRC_13_INT 0x8D
361 #define V_008DFC_SQ_SRC_14_INT 0x8E
362 #define V_008DFC_SQ_SRC_15_INT 0x8F
363 #define V_008DFC_SQ_SRC_16_INT 0x90
364 #define V_008DFC_SQ_SRC_17_INT 0x91
365 #define V_008DFC_SQ_SRC_18_INT 0x92
366 #define V_008DFC_SQ_SRC_19_INT 0x93
367 #define V_008DFC_SQ_SRC_20_INT 0x94
368 #define V_008DFC_SQ_SRC_21_INT 0x95
369 #define V_008DFC_SQ_SRC_22_INT 0x96
370 #define V_008DFC_SQ_SRC_23_INT 0x97
371 #define V_008DFC_SQ_SRC_24_INT 0x98
372 #define V_008DFC_SQ_SRC_25_INT 0x99
373 #define V_008DFC_SQ_SRC_26_INT 0x9A
374 #define V_008DFC_SQ_SRC_27_INT 0x9B
375 #define V_008DFC_SQ_SRC_28_INT 0x9C
376 #define V_008DFC_SQ_SRC_29_INT 0x9D
377 #define V_008DFC_SQ_SRC_30_INT 0x9E
378 #define V_008DFC_SQ_SRC_31_INT 0x9F
379 #define V_008DFC_SQ_SRC_32_INT 0xA0
380 #define V_008DFC_SQ_SRC_33_INT 0xA1
381 #define V_008DFC_SQ_SRC_34_INT 0xA2
382 #define V_008DFC_SQ_SRC_35_INT 0xA3
383 #define V_008DFC_SQ_SRC_36_INT 0xA4
384 #define V_008DFC_SQ_SRC_37_INT 0xA5
385 #define V_008DFC_SQ_SRC_38_INT 0xA6
386 #define V_008DFC_SQ_SRC_39_INT 0xA7
387 #define V_008DFC_SQ_SRC_40_INT 0xA8
388 #define V_008DFC_SQ_SRC_41_INT 0xA9
389 #define V_008DFC_SQ_SRC_42_INT 0xAA
390 #define V_008DFC_SQ_SRC_43_INT 0xAB
391 #define V_008DFC_SQ_SRC_44_INT 0xAC
392 #define V_008DFC_SQ_SRC_45_INT 0xAD
393 #define V_008DFC_SQ_SRC_46_INT 0xAE
394 #define V_008DFC_SQ_SRC_47_INT 0xAF
395 #define V_008DFC_SQ_SRC_48_INT 0xB0
396 #define V_008DFC_SQ_SRC_49_INT 0xB1
397 #define V_008DFC_SQ_SRC_50_INT 0xB2
398 #define V_008DFC_SQ_SRC_51_INT 0xB3
399 #define V_008DFC_SQ_SRC_52_INT 0xB4
400 #define V_008DFC_SQ_SRC_53_INT 0xB5
401 #define V_008DFC_SQ_SRC_54_INT 0xB6
402 #define V_008DFC_SQ_SRC_55_INT 0xB7
403 #define V_008DFC_SQ_SRC_56_INT 0xB8
404 #define V_008DFC_SQ_SRC_57_INT 0xB9
405 #define V_008DFC_SQ_SRC_58_INT 0xBA
406 #define V_008DFC_SQ_SRC_59_INT 0xBB
407 #define V_008DFC_SQ_SRC_60_INT 0xBC
408 #define V_008DFC_SQ_SRC_61_INT 0xBD
409 #define V_008DFC_SQ_SRC_62_INT 0xBE
410 #define V_008DFC_SQ_SRC_63_INT 0xBF
411 #define V_008DFC_SQ_SRC_64_INT 0xC0
412 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
413 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
414 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
415 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
416 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
417 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
418 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
419 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
420 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
421 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
422 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
423 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
424 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
425 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
426 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
427 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
428 #define V_008DFC_SQ_SRC_0_5 0xF0
429 #define V_008DFC_SQ_SRC_M_0_5 0xF1
430 #define V_008DFC_SQ_SRC_1 0xF2
431 #define V_008DFC_SQ_SRC_M_1 0xF3
432 #define V_008DFC_SQ_SRC_2 0xF4
433 #define V_008DFC_SQ_SRC_M_2 0xF5
434 #define V_008DFC_SQ_SRC_4 0xF6
435 #define V_008DFC_SQ_SRC_M_4 0xF7
436 #define V_008DFC_SQ_SRC_VCCZ 0xFB
437 #define V_008DFC_SQ_SRC_EXECZ 0xFC
438 #define V_008DFC_SQ_SRC_SCC 0xFD
439 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
440 #define V_008DFC_SQ_SRC_VGPR 0x100
441 #define S_008DFC_OP(x) (((x) & 0xFF) << 9)
442 #define G_008DFC_OP(x) (((x) >> 9) & 0xFF)
443 #define C_008DFC_OP 0xFFFE01FF
444 #define V_008DFC_SQ_V_NOP 0x00
445 #define V_008DFC_SQ_V_MOV_B32 0x01
446 #define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02
447 #define V_008DFC_SQ_V_CVT_I32_F64 0x03
448 #define V_008DFC_SQ_V_CVT_F64_I32 0x04
449 #define V_008DFC_SQ_V_CVT_F32_I32 0x05
450 #define V_008DFC_SQ_V_CVT_F32_U32 0x06
451 #define V_008DFC_SQ_V_CVT_U32_F32 0x07
452 #define V_008DFC_SQ_V_CVT_I32_F32 0x08
453 #define V_008DFC_SQ_V_MOV_FED_B32 0x09
454 #define V_008DFC_SQ_V_CVT_F16_F32 0x0A
455 #define V_008DFC_SQ_V_CVT_F32_F16 0x0B
456 #define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C
457 #define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D
458 #define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E
459 #define V_008DFC_SQ_V_CVT_F32_F64 0x0F
460 #define V_008DFC_SQ_V_CVT_F64_F32 0x10
461 #define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11
462 #define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12
463 #define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13
464 #define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14
465 #define V_008DFC_SQ_V_CVT_U32_F64 0x15
466 #define V_008DFC_SQ_V_CVT_F64_U32 0x16
467 #define V_008DFC_SQ_V_FRACT_F32 0x20
468 #define V_008DFC_SQ_V_TRUNC_F32 0x21
469 #define V_008DFC_SQ_V_CEIL_F32 0x22
470 #define V_008DFC_SQ_V_RNDNE_F32 0x23
471 #define V_008DFC_SQ_V_FLOOR_F32 0x24
472 #define V_008DFC_SQ_V_EXP_F32 0x25
473 #define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26
474 #define V_008DFC_SQ_V_LOG_F32 0x27
475 #define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28
476 #define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29
477 #define V_008DFC_SQ_V_RCP_F32 0x2A
478 #define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B
479 #define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C
480 #define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D
481 #define V_008DFC_SQ_V_RSQ_F32 0x2E
482 #define V_008DFC_SQ_V_RCP_F64 0x2F
483 #define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30
484 #define V_008DFC_SQ_V_RSQ_F64 0x31
485 #define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32
486 #define V_008DFC_SQ_V_SQRT_F32 0x33
487 #define V_008DFC_SQ_V_SQRT_F64 0x34
488 #define V_008DFC_SQ_V_SIN_F32 0x35
489 #define V_008DFC_SQ_V_COS_F32 0x36
490 #define V_008DFC_SQ_V_NOT_B32 0x37
491 #define V_008DFC_SQ_V_BFREV_B32 0x38
492 #define V_008DFC_SQ_V_FFBH_U32 0x39
493 #define V_008DFC_SQ_V_FFBL_B32 0x3A
494 #define V_008DFC_SQ_V_FFBH_I32 0x3B
495 #define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C
496 #define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D
497 #define V_008DFC_SQ_V_FRACT_F64 0x3E
498 #define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F
499 #define V_008DFC_SQ_V_FREXP_MANT_F32 0x40
500 #define V_008DFC_SQ_V_CLREXCP 0x41
501 #define V_008DFC_SQ_V_MOVRELD_B32 0x42
502 #define V_008DFC_SQ_V_MOVRELS_B32 0x43
503 #define V_008DFC_SQ_V_MOVRELSD_B32 0x44
504 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17)
505 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF)
506 #define C_008DFC_VDST 0xFE01FFFF
507 #define V_008DFC_SQ_VGPR 0x00
508 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25)
509 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F)
510 #define C_008DFC_ENCODING 0x01FFFFFF
511 #define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F
512 #define R_008DFC_SQ_MIMG_1 0x008DFC
513 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
514 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
515 #define C_008DFC_VADDR 0xFFFFFF00
516 #define V_008DFC_SQ_VGPR 0x00
517 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
518 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
519 #define C_008DFC_VDATA 0xFFFF00FF
520 #define V_008DFC_SQ_VGPR 0x00
521 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
522 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
523 #define C_008DFC_SRSRC 0xFFE0FFFF
524 #define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21)
525 #define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F)
526 #define C_008DFC_SSAMP 0xFC1FFFFF
527 #define R_008DFC_SQ_VOP3_1 0x008DFC
528 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
529 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
530 #define C_008DFC_SRC0 0xFFFFFE00
531 #define V_008DFC_SQ_SGPR 0x00
532 #define V_008DFC_SQ_VCC_LO 0x6A
533 #define V_008DFC_SQ_VCC_HI 0x6B
534 #define V_008DFC_SQ_TBA_LO 0x6C
535 #define V_008DFC_SQ_TBA_HI 0x6D
536 #define V_008DFC_SQ_TMA_LO 0x6E
537 #define V_008DFC_SQ_TMA_HI 0x6F
538 #define V_008DFC_SQ_TTMP0 0x70
539 #define V_008DFC_SQ_TTMP1 0x71
540 #define V_008DFC_SQ_TTMP2 0x72
541 #define V_008DFC_SQ_TTMP3 0x73
542 #define V_008DFC_SQ_TTMP4 0x74
543 #define V_008DFC_SQ_TTMP5 0x75
544 #define V_008DFC_SQ_TTMP6 0x76
545 #define V_008DFC_SQ_TTMP7 0x77
546 #define V_008DFC_SQ_TTMP8 0x78
547 #define V_008DFC_SQ_TTMP9 0x79
548 #define V_008DFC_SQ_TTMP10 0x7A
549 #define V_008DFC_SQ_TTMP11 0x7B
550 #define V_008DFC_SQ_M0 0x7C
551 #define V_008DFC_SQ_EXEC_LO 0x7E
552 #define V_008DFC_SQ_EXEC_HI 0x7F
553 #define V_008DFC_SQ_SRC_0 0x80
554 #define V_008DFC_SQ_SRC_1_INT 0x81
555 #define V_008DFC_SQ_SRC_2_INT 0x82
556 #define V_008DFC_SQ_SRC_3_INT 0x83
557 #define V_008DFC_SQ_SRC_4_INT 0x84
558 #define V_008DFC_SQ_SRC_5_INT 0x85
559 #define V_008DFC_SQ_SRC_6_INT 0x86
560 #define V_008DFC_SQ_SRC_7_INT 0x87
561 #define V_008DFC_SQ_SRC_8_INT 0x88
562 #define V_008DFC_SQ_SRC_9_INT 0x89
563 #define V_008DFC_SQ_SRC_10_INT 0x8A
564 #define V_008DFC_SQ_SRC_11_INT 0x8B
565 #define V_008DFC_SQ_SRC_12_INT 0x8C
566 #define V_008DFC_SQ_SRC_13_INT 0x8D
567 #define V_008DFC_SQ_SRC_14_INT 0x8E
568 #define V_008DFC_SQ_SRC_15_INT 0x8F
569 #define V_008DFC_SQ_SRC_16_INT 0x90
570 #define V_008DFC_SQ_SRC_17_INT 0x91
571 #define V_008DFC_SQ_SRC_18_INT 0x92
572 #define V_008DFC_SQ_SRC_19_INT 0x93
573 #define V_008DFC_SQ_SRC_20_INT 0x94
574 #define V_008DFC_SQ_SRC_21_INT 0x95
575 #define V_008DFC_SQ_SRC_22_INT 0x96
576 #define V_008DFC_SQ_SRC_23_INT 0x97
577 #define V_008DFC_SQ_SRC_24_INT 0x98
578 #define V_008DFC_SQ_SRC_25_INT 0x99
579 #define V_008DFC_SQ_SRC_26_INT 0x9A
580 #define V_008DFC_SQ_SRC_27_INT 0x9B
581 #define V_008DFC_SQ_SRC_28_INT 0x9C
582 #define V_008DFC_SQ_SRC_29_INT 0x9D
583 #define V_008DFC_SQ_SRC_30_INT 0x9E
584 #define V_008DFC_SQ_SRC_31_INT 0x9F
585 #define V_008DFC_SQ_SRC_32_INT 0xA0
586 #define V_008DFC_SQ_SRC_33_INT 0xA1
587 #define V_008DFC_SQ_SRC_34_INT 0xA2
588 #define V_008DFC_SQ_SRC_35_INT 0xA3
589 #define V_008DFC_SQ_SRC_36_INT 0xA4
590 #define V_008DFC_SQ_SRC_37_INT 0xA5
591 #define V_008DFC_SQ_SRC_38_INT 0xA6
592 #define V_008DFC_SQ_SRC_39_INT 0xA7
593 #define V_008DFC_SQ_SRC_40_INT 0xA8
594 #define V_008DFC_SQ_SRC_41_INT 0xA9
595 #define V_008DFC_SQ_SRC_42_INT 0xAA
596 #define V_008DFC_SQ_SRC_43_INT 0xAB
597 #define V_008DFC_SQ_SRC_44_INT 0xAC
598 #define V_008DFC_SQ_SRC_45_INT 0xAD
599 #define V_008DFC_SQ_SRC_46_INT 0xAE
600 #define V_008DFC_SQ_SRC_47_INT 0xAF
601 #define V_008DFC_SQ_SRC_48_INT 0xB0
602 #define V_008DFC_SQ_SRC_49_INT 0xB1
603 #define V_008DFC_SQ_SRC_50_INT 0xB2
604 #define V_008DFC_SQ_SRC_51_INT 0xB3
605 #define V_008DFC_SQ_SRC_52_INT 0xB4
606 #define V_008DFC_SQ_SRC_53_INT 0xB5
607 #define V_008DFC_SQ_SRC_54_INT 0xB6
608 #define V_008DFC_SQ_SRC_55_INT 0xB7
609 #define V_008DFC_SQ_SRC_56_INT 0xB8
610 #define V_008DFC_SQ_SRC_57_INT 0xB9
611 #define V_008DFC_SQ_SRC_58_INT 0xBA
612 #define V_008DFC_SQ_SRC_59_INT 0xBB
613 #define V_008DFC_SQ_SRC_60_INT 0xBC
614 #define V_008DFC_SQ_SRC_61_INT 0xBD
615 #define V_008DFC_SQ_SRC_62_INT 0xBE
616 #define V_008DFC_SQ_SRC_63_INT 0xBF
617 #define V_008DFC_SQ_SRC_64_INT 0xC0
618 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
619 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
620 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
621 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
622 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
623 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
624 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
625 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
626 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
627 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
628 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
629 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
630 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
631 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
632 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
633 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
634 #define V_008DFC_SQ_SRC_0_5 0xF0
635 #define V_008DFC_SQ_SRC_M_0_5 0xF1
636 #define V_008DFC_SQ_SRC_1 0xF2
637 #define V_008DFC_SQ_SRC_M_1 0xF3
638 #define V_008DFC_SQ_SRC_2 0xF4
639 #define V_008DFC_SQ_SRC_M_2 0xF5
640 #define V_008DFC_SQ_SRC_4 0xF6
641 #define V_008DFC_SQ_SRC_M_4 0xF7
642 #define V_008DFC_SQ_SRC_VCCZ 0xFB
643 #define V_008DFC_SQ_SRC_EXECZ 0xFC
644 #define V_008DFC_SQ_SRC_SCC 0xFD
645 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
646 #define V_008DFC_SQ_SRC_VGPR 0x100
647 #define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9)
648 #define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF)
649 #define C_008DFC_SRC1 0xFFFC01FF
650 #define V_008DFC_SQ_SGPR 0x00
651 #define V_008DFC_SQ_VCC_LO 0x6A
652 #define V_008DFC_SQ_VCC_HI 0x6B
653 #define V_008DFC_SQ_TBA_LO 0x6C
654 #define V_008DFC_SQ_TBA_HI 0x6D
655 #define V_008DFC_SQ_TMA_LO 0x6E
656 #define V_008DFC_SQ_TMA_HI 0x6F
657 #define V_008DFC_SQ_TTMP0 0x70
658 #define V_008DFC_SQ_TTMP1 0x71
659 #define V_008DFC_SQ_TTMP2 0x72
660 #define V_008DFC_SQ_TTMP3 0x73
661 #define V_008DFC_SQ_TTMP4 0x74
662 #define V_008DFC_SQ_TTMP5 0x75
663 #define V_008DFC_SQ_TTMP6 0x76
664 #define V_008DFC_SQ_TTMP7 0x77
665 #define V_008DFC_SQ_TTMP8 0x78
666 #define V_008DFC_SQ_TTMP9 0x79
667 #define V_008DFC_SQ_TTMP10 0x7A
668 #define V_008DFC_SQ_TTMP11 0x7B
669 #define V_008DFC_SQ_M0 0x7C
670 #define V_008DFC_SQ_EXEC_LO 0x7E
671 #define V_008DFC_SQ_EXEC_HI 0x7F
672 #define V_008DFC_SQ_SRC_0 0x80
673 #define V_008DFC_SQ_SRC_1_INT 0x81
674 #define V_008DFC_SQ_SRC_2_INT 0x82
675 #define V_008DFC_SQ_SRC_3_INT 0x83
676 #define V_008DFC_SQ_SRC_4_INT 0x84
677 #define V_008DFC_SQ_SRC_5_INT 0x85
678 #define V_008DFC_SQ_SRC_6_INT 0x86
679 #define V_008DFC_SQ_SRC_7_INT 0x87
680 #define V_008DFC_SQ_SRC_8_INT 0x88
681 #define V_008DFC_SQ_SRC_9_INT 0x89
682 #define V_008DFC_SQ_SRC_10_INT 0x8A
683 #define V_008DFC_SQ_SRC_11_INT 0x8B
684 #define V_008DFC_SQ_SRC_12_INT 0x8C
685 #define V_008DFC_SQ_SRC_13_INT 0x8D
686 #define V_008DFC_SQ_SRC_14_INT 0x8E
687 #define V_008DFC_SQ_SRC_15_INT 0x8F
688 #define V_008DFC_SQ_SRC_16_INT 0x90
689 #define V_008DFC_SQ_SRC_17_INT 0x91
690 #define V_008DFC_SQ_SRC_18_INT 0x92
691 #define V_008DFC_SQ_SRC_19_INT 0x93
692 #define V_008DFC_SQ_SRC_20_INT 0x94
693 #define V_008DFC_SQ_SRC_21_INT 0x95
694 #define V_008DFC_SQ_SRC_22_INT 0x96
695 #define V_008DFC_SQ_SRC_23_INT 0x97
696 #define V_008DFC_SQ_SRC_24_INT 0x98
697 #define V_008DFC_SQ_SRC_25_INT 0x99
698 #define V_008DFC_SQ_SRC_26_INT 0x9A
699 #define V_008DFC_SQ_SRC_27_INT 0x9B
700 #define V_008DFC_SQ_SRC_28_INT 0x9C
701 #define V_008DFC_SQ_SRC_29_INT 0x9D
702 #define V_008DFC_SQ_SRC_30_INT 0x9E
703 #define V_008DFC_SQ_SRC_31_INT 0x9F
704 #define V_008DFC_SQ_SRC_32_INT 0xA0
705 #define V_008DFC_SQ_SRC_33_INT 0xA1
706 #define V_008DFC_SQ_SRC_34_INT 0xA2
707 #define V_008DFC_SQ_SRC_35_INT 0xA3
708 #define V_008DFC_SQ_SRC_36_INT 0xA4
709 #define V_008DFC_SQ_SRC_37_INT 0xA5
710 #define V_008DFC_SQ_SRC_38_INT 0xA6
711 #define V_008DFC_SQ_SRC_39_INT 0xA7
712 #define V_008DFC_SQ_SRC_40_INT 0xA8
713 #define V_008DFC_SQ_SRC_41_INT 0xA9
714 #define V_008DFC_SQ_SRC_42_INT 0xAA
715 #define V_008DFC_SQ_SRC_43_INT 0xAB
716 #define V_008DFC_SQ_SRC_44_INT 0xAC
717 #define V_008DFC_SQ_SRC_45_INT 0xAD
718 #define V_008DFC_SQ_SRC_46_INT 0xAE
719 #define V_008DFC_SQ_SRC_47_INT 0xAF
720 #define V_008DFC_SQ_SRC_48_INT 0xB0
721 #define V_008DFC_SQ_SRC_49_INT 0xB1
722 #define V_008DFC_SQ_SRC_50_INT 0xB2
723 #define V_008DFC_SQ_SRC_51_INT 0xB3
724 #define V_008DFC_SQ_SRC_52_INT 0xB4
725 #define V_008DFC_SQ_SRC_53_INT 0xB5
726 #define V_008DFC_SQ_SRC_54_INT 0xB6
727 #define V_008DFC_SQ_SRC_55_INT 0xB7
728 #define V_008DFC_SQ_SRC_56_INT 0xB8
729 #define V_008DFC_SQ_SRC_57_INT 0xB9
730 #define V_008DFC_SQ_SRC_58_INT 0xBA
731 #define V_008DFC_SQ_SRC_59_INT 0xBB
732 #define V_008DFC_SQ_SRC_60_INT 0xBC
733 #define V_008DFC_SQ_SRC_61_INT 0xBD
734 #define V_008DFC_SQ_SRC_62_INT 0xBE
735 #define V_008DFC_SQ_SRC_63_INT 0xBF
736 #define V_008DFC_SQ_SRC_64_INT 0xC0
737 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
738 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
739 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
740 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
741 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
742 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
743 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
744 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
745 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
746 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
747 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
748 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
749 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
750 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
751 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
752 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
753 #define V_008DFC_SQ_SRC_0_5 0xF0
754 #define V_008DFC_SQ_SRC_M_0_5 0xF1
755 #define V_008DFC_SQ_SRC_1 0xF2
756 #define V_008DFC_SQ_SRC_M_1 0xF3
757 #define V_008DFC_SQ_SRC_2 0xF4
758 #define V_008DFC_SQ_SRC_M_2 0xF5
759 #define V_008DFC_SQ_SRC_4 0xF6
760 #define V_008DFC_SQ_SRC_M_4 0xF7
761 #define V_008DFC_SQ_SRC_VCCZ 0xFB
762 #define V_008DFC_SQ_SRC_EXECZ 0xFC
763 #define V_008DFC_SQ_SRC_SCC 0xFD
764 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
765 #define V_008DFC_SQ_SRC_VGPR 0x100
766 #define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18)
767 #define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF)
768 #define C_008DFC_SRC2 0xF803FFFF
769 #define V_008DFC_SQ_SGPR 0x00
770 #define V_008DFC_SQ_VCC_LO 0x6A
771 #define V_008DFC_SQ_VCC_HI 0x6B
772 #define V_008DFC_SQ_TBA_LO 0x6C
773 #define V_008DFC_SQ_TBA_HI 0x6D
774 #define V_008DFC_SQ_TMA_LO 0x6E
775 #define V_008DFC_SQ_TMA_HI 0x6F
776 #define V_008DFC_SQ_TTMP0 0x70
777 #define V_008DFC_SQ_TTMP1 0x71
778 #define V_008DFC_SQ_TTMP2 0x72
779 #define V_008DFC_SQ_TTMP3 0x73
780 #define V_008DFC_SQ_TTMP4 0x74
781 #define V_008DFC_SQ_TTMP5 0x75
782 #define V_008DFC_SQ_TTMP6 0x76
783 #define V_008DFC_SQ_TTMP7 0x77
784 #define V_008DFC_SQ_TTMP8 0x78
785 #define V_008DFC_SQ_TTMP9 0x79
786 #define V_008DFC_SQ_TTMP10 0x7A
787 #define V_008DFC_SQ_TTMP11 0x7B
788 #define V_008DFC_SQ_M0 0x7C
789 #define V_008DFC_SQ_EXEC_LO 0x7E
790 #define V_008DFC_SQ_EXEC_HI 0x7F
791 #define V_008DFC_SQ_SRC_0 0x80
792 #define V_008DFC_SQ_SRC_1_INT 0x81
793 #define V_008DFC_SQ_SRC_2_INT 0x82
794 #define V_008DFC_SQ_SRC_3_INT 0x83
795 #define V_008DFC_SQ_SRC_4_INT 0x84
796 #define V_008DFC_SQ_SRC_5_INT 0x85
797 #define V_008DFC_SQ_SRC_6_INT 0x86
798 #define V_008DFC_SQ_SRC_7_INT 0x87
799 #define V_008DFC_SQ_SRC_8_INT 0x88
800 #define V_008DFC_SQ_SRC_9_INT 0x89
801 #define V_008DFC_SQ_SRC_10_INT 0x8A
802 #define V_008DFC_SQ_SRC_11_INT 0x8B
803 #define V_008DFC_SQ_SRC_12_INT 0x8C
804 #define V_008DFC_SQ_SRC_13_INT 0x8D
805 #define V_008DFC_SQ_SRC_14_INT 0x8E
806 #define V_008DFC_SQ_SRC_15_INT 0x8F
807 #define V_008DFC_SQ_SRC_16_INT 0x90
808 #define V_008DFC_SQ_SRC_17_INT 0x91
809 #define V_008DFC_SQ_SRC_18_INT 0x92
810 #define V_008DFC_SQ_SRC_19_INT 0x93
811 #define V_008DFC_SQ_SRC_20_INT 0x94
812 #define V_008DFC_SQ_SRC_21_INT 0x95
813 #define V_008DFC_SQ_SRC_22_INT 0x96
814 #define V_008DFC_SQ_SRC_23_INT 0x97
815 #define V_008DFC_SQ_SRC_24_INT 0x98
816 #define V_008DFC_SQ_SRC_25_INT 0x99
817 #define V_008DFC_SQ_SRC_26_INT 0x9A
818 #define V_008DFC_SQ_SRC_27_INT 0x9B
819 #define V_008DFC_SQ_SRC_28_INT 0x9C
820 #define V_008DFC_SQ_SRC_29_INT 0x9D
821 #define V_008DFC_SQ_SRC_30_INT 0x9E
822 #define V_008DFC_SQ_SRC_31_INT 0x9F
823 #define V_008DFC_SQ_SRC_32_INT 0xA0
824 #define V_008DFC_SQ_SRC_33_INT 0xA1
825 #define V_008DFC_SQ_SRC_34_INT 0xA2
826 #define V_008DFC_SQ_SRC_35_INT 0xA3
827 #define V_008DFC_SQ_SRC_36_INT 0xA4
828 #define V_008DFC_SQ_SRC_37_INT 0xA5
829 #define V_008DFC_SQ_SRC_38_INT 0xA6
830 #define V_008DFC_SQ_SRC_39_INT 0xA7
831 #define V_008DFC_SQ_SRC_40_INT 0xA8
832 #define V_008DFC_SQ_SRC_41_INT 0xA9
833 #define V_008DFC_SQ_SRC_42_INT 0xAA
834 #define V_008DFC_SQ_SRC_43_INT 0xAB
835 #define V_008DFC_SQ_SRC_44_INT 0xAC
836 #define V_008DFC_SQ_SRC_45_INT 0xAD
837 #define V_008DFC_SQ_SRC_46_INT 0xAE
838 #define V_008DFC_SQ_SRC_47_INT 0xAF
839 #define V_008DFC_SQ_SRC_48_INT 0xB0
840 #define V_008DFC_SQ_SRC_49_INT 0xB1
841 #define V_008DFC_SQ_SRC_50_INT 0xB2
842 #define V_008DFC_SQ_SRC_51_INT 0xB3
843 #define V_008DFC_SQ_SRC_52_INT 0xB4
844 #define V_008DFC_SQ_SRC_53_INT 0xB5
845 #define V_008DFC_SQ_SRC_54_INT 0xB6
846 #define V_008DFC_SQ_SRC_55_INT 0xB7
847 #define V_008DFC_SQ_SRC_56_INT 0xB8
848 #define V_008DFC_SQ_SRC_57_INT 0xB9
849 #define V_008DFC_SQ_SRC_58_INT 0xBA
850 #define V_008DFC_SQ_SRC_59_INT 0xBB
851 #define V_008DFC_SQ_SRC_60_INT 0xBC
852 #define V_008DFC_SQ_SRC_61_INT 0xBD
853 #define V_008DFC_SQ_SRC_62_INT 0xBE
854 #define V_008DFC_SQ_SRC_63_INT 0xBF
855 #define V_008DFC_SQ_SRC_64_INT 0xC0
856 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
857 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
858 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
859 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
860 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
861 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
862 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
863 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
864 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
865 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
866 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
867 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
868 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
869 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
870 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
871 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
872 #define V_008DFC_SQ_SRC_0_5 0xF0
873 #define V_008DFC_SQ_SRC_M_0_5 0xF1
874 #define V_008DFC_SQ_SRC_1 0xF2
875 #define V_008DFC_SQ_SRC_M_1 0xF3
876 #define V_008DFC_SQ_SRC_2 0xF4
877 #define V_008DFC_SQ_SRC_M_2 0xF5
878 #define V_008DFC_SQ_SRC_4 0xF6
879 #define V_008DFC_SQ_SRC_M_4 0xF7
880 #define V_008DFC_SQ_SRC_VCCZ 0xFB
881 #define V_008DFC_SQ_SRC_EXECZ 0xFC
882 #define V_008DFC_SQ_SRC_SCC 0xFD
883 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
884 #define V_008DFC_SQ_SRC_VGPR 0x100
885 #define S_008DFC_OMOD(x) (((x) & 0x03) << 27)
886 #define G_008DFC_OMOD(x) (((x) >> 27) & 0x03)
887 #define C_008DFC_OMOD 0xE7FFFFFF
888 #define V_008DFC_SQ_OMOD_OFF 0x00
889 #define V_008DFC_SQ_OMOD_M2 0x01
890 #define V_008DFC_SQ_OMOD_M4 0x02
891 #define V_008DFC_SQ_OMOD_D2 0x03
892 #define S_008DFC_NEG(x) (((x) & 0x07) << 29)
893 #define G_008DFC_NEG(x) (((x) >> 29) & 0x07)
894 #define C_008DFC_NEG 0x1FFFFFFF
895 #define R_008DFC_SQ_MUBUF_1 0x008DFC
896 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
897 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
898 #define C_008DFC_VADDR 0xFFFFFF00
899 #define V_008DFC_SQ_VGPR 0x00
900 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
901 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
902 #define C_008DFC_VDATA 0xFFFF00FF
903 #define V_008DFC_SQ_VGPR 0x00
904 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
905 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
906 #define C_008DFC_SRSRC 0xFFE0FFFF
907 #define S_008DFC_SLC(x) (((x) & 0x1) << 22)
908 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1)
909 #define C_008DFC_SLC 0xFFBFFFFF
910 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
911 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
912 #define C_008DFC_TFE 0xFF7FFFFF
913 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24)
914 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF)
915 #define C_008DFC_SOFFSET 0x00FFFFFF
916 #define V_008DFC_SQ_SGPR 0x00
917 #define V_008DFC_SQ_VCC_LO 0x6A
918 #define V_008DFC_SQ_VCC_HI 0x6B
919 #define V_008DFC_SQ_TBA_LO 0x6C
920 #define V_008DFC_SQ_TBA_HI 0x6D
921 #define V_008DFC_SQ_TMA_LO 0x6E
922 #define V_008DFC_SQ_TMA_HI 0x6F
923 #define V_008DFC_SQ_TTMP0 0x70
924 #define V_008DFC_SQ_TTMP1 0x71
925 #define V_008DFC_SQ_TTMP2 0x72
926 #define V_008DFC_SQ_TTMP3 0x73
927 #define V_008DFC_SQ_TTMP4 0x74
928 #define V_008DFC_SQ_TTMP5 0x75
929 #define V_008DFC_SQ_TTMP6 0x76
930 #define V_008DFC_SQ_TTMP7 0x77
931 #define V_008DFC_SQ_TTMP8 0x78
932 #define V_008DFC_SQ_TTMP9 0x79
933 #define V_008DFC_SQ_TTMP10 0x7A
934 #define V_008DFC_SQ_TTMP11 0x7B
935 #define V_008DFC_SQ_M0 0x7C
936 #define V_008DFC_SQ_EXEC_LO 0x7E
937 #define V_008DFC_SQ_EXEC_HI 0x7F
938 #define V_008DFC_SQ_SRC_0 0x80
939 #define V_008DFC_SQ_SRC_1_INT 0x81
940 #define V_008DFC_SQ_SRC_2_INT 0x82
941 #define V_008DFC_SQ_SRC_3_INT 0x83
942 #define V_008DFC_SQ_SRC_4_INT 0x84
943 #define V_008DFC_SQ_SRC_5_INT 0x85
944 #define V_008DFC_SQ_SRC_6_INT 0x86
945 #define V_008DFC_SQ_SRC_7_INT 0x87
946 #define V_008DFC_SQ_SRC_8_INT 0x88
947 #define V_008DFC_SQ_SRC_9_INT 0x89
948 #define V_008DFC_SQ_SRC_10_INT 0x8A
949 #define V_008DFC_SQ_SRC_11_INT 0x8B
950 #define V_008DFC_SQ_SRC_12_INT 0x8C
951 #define V_008DFC_SQ_SRC_13_INT 0x8D
952 #define V_008DFC_SQ_SRC_14_INT 0x8E
953 #define V_008DFC_SQ_SRC_15_INT 0x8F
954 #define V_008DFC_SQ_SRC_16_INT 0x90
955 #define V_008DFC_SQ_SRC_17_INT 0x91
956 #define V_008DFC_SQ_SRC_18_INT 0x92
957 #define V_008DFC_SQ_SRC_19_INT 0x93
958 #define V_008DFC_SQ_SRC_20_INT 0x94
959 #define V_008DFC_SQ_SRC_21_INT 0x95
960 #define V_008DFC_SQ_SRC_22_INT 0x96
961 #define V_008DFC_SQ_SRC_23_INT 0x97
962 #define V_008DFC_SQ_SRC_24_INT 0x98
963 #define V_008DFC_SQ_SRC_25_INT 0x99
964 #define V_008DFC_SQ_SRC_26_INT 0x9A
965 #define V_008DFC_SQ_SRC_27_INT 0x9B
966 #define V_008DFC_SQ_SRC_28_INT 0x9C
967 #define V_008DFC_SQ_SRC_29_INT 0x9D
968 #define V_008DFC_SQ_SRC_30_INT 0x9E
969 #define V_008DFC_SQ_SRC_31_INT 0x9F
970 #define V_008DFC_SQ_SRC_32_INT 0xA0
971 #define V_008DFC_SQ_SRC_33_INT 0xA1
972 #define V_008DFC_SQ_SRC_34_INT 0xA2
973 #define V_008DFC_SQ_SRC_35_INT 0xA3
974 #define V_008DFC_SQ_SRC_36_INT 0xA4
975 #define V_008DFC_SQ_SRC_37_INT 0xA5
976 #define V_008DFC_SQ_SRC_38_INT 0xA6
977 #define V_008DFC_SQ_SRC_39_INT 0xA7
978 #define V_008DFC_SQ_SRC_40_INT 0xA8
979 #define V_008DFC_SQ_SRC_41_INT 0xA9
980 #define V_008DFC_SQ_SRC_42_INT 0xAA
981 #define V_008DFC_SQ_SRC_43_INT 0xAB
982 #define V_008DFC_SQ_SRC_44_INT 0xAC
983 #define V_008DFC_SQ_SRC_45_INT 0xAD
984 #define V_008DFC_SQ_SRC_46_INT 0xAE
985 #define V_008DFC_SQ_SRC_47_INT 0xAF
986 #define V_008DFC_SQ_SRC_48_INT 0xB0
987 #define V_008DFC_SQ_SRC_49_INT 0xB1
988 #define V_008DFC_SQ_SRC_50_INT 0xB2
989 #define V_008DFC_SQ_SRC_51_INT 0xB3
990 #define V_008DFC_SQ_SRC_52_INT 0xB4
991 #define V_008DFC_SQ_SRC_53_INT 0xB5
992 #define V_008DFC_SQ_SRC_54_INT 0xB6
993 #define V_008DFC_SQ_SRC_55_INT 0xB7
994 #define V_008DFC_SQ_SRC_56_INT 0xB8
995 #define V_008DFC_SQ_SRC_57_INT 0xB9
996 #define V_008DFC_SQ_SRC_58_INT 0xBA
997 #define V_008DFC_SQ_SRC_59_INT 0xBB
998 #define V_008DFC_SQ_SRC_60_INT 0xBC
999 #define V_008DFC_SQ_SRC_61_INT 0xBD
1000 #define V_008DFC_SQ_SRC_62_INT 0xBE
1001 #define V_008DFC_SQ_SRC_63_INT 0xBF
1002 #define V_008DFC_SQ_SRC_64_INT 0xC0
1003 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1004 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1005 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1006 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1007 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1008 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1009 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1010 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1011 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1012 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1013 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1014 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1015 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1016 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1017 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1018 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1019 #define V_008DFC_SQ_SRC_0_5 0xF0
1020 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1021 #define V_008DFC_SQ_SRC_1 0xF2
1022 #define V_008DFC_SQ_SRC_M_1 0xF3
1023 #define V_008DFC_SQ_SRC_2 0xF4
1024 #define V_008DFC_SQ_SRC_M_2 0xF5
1025 #define V_008DFC_SQ_SRC_4 0xF6
1026 #define V_008DFC_SQ_SRC_M_4 0xF7
1027 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1028 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1029 #define V_008DFC_SQ_SRC_SCC 0xFD
1030 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1031 #define R_008DFC_SQ_DS_0 0x008DFC
1032 #define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0)
1033 #define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF)
1034 #define C_008DFC_OFFSET0 0xFFFFFF00
1035 #define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8)
1036 #define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF)
1037 #define C_008DFC_OFFSET1 0xFFFF00FF
1038 #define S_008DFC_GDS(x) (((x) & 0x1) << 17)
1039 #define G_008DFC_GDS(x) (((x) >> 17) & 0x1)
1040 #define C_008DFC_GDS 0xFFFDFFFF
1041 #define S_008DFC_OP(x) (((x) & 0xFF) << 18)
1042 #define G_008DFC_OP(x) (((x) >> 18) & 0xFF)
1043 #define C_008DFC_OP 0xFC03FFFF
1044 #define V_008DFC_SQ_DS_ADD_U32 0x00
1045 #define V_008DFC_SQ_DS_SUB_U32 0x01
1046 #define V_008DFC_SQ_DS_RSUB_U32 0x02
1047 #define V_008DFC_SQ_DS_INC_U32 0x03
1048 #define V_008DFC_SQ_DS_DEC_U32 0x04
1049 #define V_008DFC_SQ_DS_MIN_I32 0x05
1050 #define V_008DFC_SQ_DS_MAX_I32 0x06
1051 #define V_008DFC_SQ_DS_MIN_U32 0x07
1052 #define V_008DFC_SQ_DS_MAX_U32 0x08
1053 #define V_008DFC_SQ_DS_AND_B32 0x09
1054 #define V_008DFC_SQ_DS_OR_B32 0x0A
1055 #define V_008DFC_SQ_DS_XOR_B32 0x0B
1056 #define V_008DFC_SQ_DS_MSKOR_B32 0x0C
1057 #define V_008DFC_SQ_DS_WRITE_B32 0x0D
1058 #define V_008DFC_SQ_DS_WRITE2_B32 0x0E
1059 #define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F
1060 #define V_008DFC_SQ_DS_CMPST_B32 0x10
1061 #define V_008DFC_SQ_DS_CMPST_F32 0x11
1062 #define V_008DFC_SQ_DS_MIN_F32 0x12
1063 #define V_008DFC_SQ_DS_MAX_F32 0x13
1064 #define V_008DFC_SQ_DS_GWS_INIT 0x19
1065 #define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A
1066 #define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B
1067 #define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C
1068 #define V_008DFC_SQ_DS_GWS_BARRIER 0x1D
1069 #define V_008DFC_SQ_DS_WRITE_B8 0x1E
1070 #define V_008DFC_SQ_DS_WRITE_B16 0x1F
1071 #define V_008DFC_SQ_DS_ADD_RTN_U32 0x20
1072 #define V_008DFC_SQ_DS_SUB_RTN_U32 0x21
1073 #define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22
1074 #define V_008DFC_SQ_DS_INC_RTN_U32 0x23
1075 #define V_008DFC_SQ_DS_DEC_RTN_U32 0x24
1076 #define V_008DFC_SQ_DS_MIN_RTN_I32 0x25
1077 #define V_008DFC_SQ_DS_MAX_RTN_I32 0x26
1078 #define V_008DFC_SQ_DS_MIN_RTN_U32 0x27
1079 #define V_008DFC_SQ_DS_MAX_RTN_U32 0x28
1080 #define V_008DFC_SQ_DS_AND_RTN_B32 0x29
1081 #define V_008DFC_SQ_DS_OR_RTN_B32 0x2A
1082 #define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B
1083 #define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C
1084 #define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D
1085 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E
1086 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F
1087 #define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30
1088 #define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31
1089 #define V_008DFC_SQ_DS_MIN_RTN_F32 0x32
1090 #define V_008DFC_SQ_DS_MAX_RTN_F32 0x33
1091 #define V_008DFC_SQ_DS_SWIZZLE_B32 0x35
1092 #define V_008DFC_SQ_DS_READ_B32 0x36
1093 #define V_008DFC_SQ_DS_READ2_B32 0x37
1094 #define V_008DFC_SQ_DS_READ2ST64_B32 0x38
1095 #define V_008DFC_SQ_DS_READ_I8 0x39
1096 #define V_008DFC_SQ_DS_READ_U8 0x3A
1097 #define V_008DFC_SQ_DS_READ_I16 0x3B
1098 #define V_008DFC_SQ_DS_READ_U16 0x3C
1099 #define V_008DFC_SQ_DS_CONSUME 0x3D
1100 #define V_008DFC_SQ_DS_APPEND 0x3E
1101 #define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F
1102 #define V_008DFC_SQ_DS_ADD_U64 0x40
1103 #define V_008DFC_SQ_DS_SUB_U64 0x41
1104 #define V_008DFC_SQ_DS_RSUB_U64 0x42
1105 #define V_008DFC_SQ_DS_INC_U64 0x43
1106 #define V_008DFC_SQ_DS_DEC_U64 0x44
1107 #define V_008DFC_SQ_DS_MIN_I64 0x45
1108 #define V_008DFC_SQ_DS_MAX_I64 0x46
1109 #define V_008DFC_SQ_DS_MIN_U64 0x47
1110 #define V_008DFC_SQ_DS_MAX_U64 0x48
1111 #define V_008DFC_SQ_DS_AND_B64 0x49
1112 #define V_008DFC_SQ_DS_OR_B64 0x4A
1113 #define V_008DFC_SQ_DS_XOR_B64 0x4B
1114 #define V_008DFC_SQ_DS_MSKOR_B64 0x4C
1115 #define V_008DFC_SQ_DS_WRITE_B64 0x4D
1116 #define V_008DFC_SQ_DS_WRITE2_B64 0x4E
1117 #define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F
1118 #define V_008DFC_SQ_DS_CMPST_B64 0x50
1119 #define V_008DFC_SQ_DS_CMPST_F64 0x51
1120 #define V_008DFC_SQ_DS_MIN_F64 0x52
1121 #define V_008DFC_SQ_DS_MAX_F64 0x53
1122 #define V_008DFC_SQ_DS_ADD_RTN_U64 0x60
1123 #define V_008DFC_SQ_DS_SUB_RTN_U64 0x61
1124 #define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62
1125 #define V_008DFC_SQ_DS_INC_RTN_U64 0x63
1126 #define V_008DFC_SQ_DS_DEC_RTN_U64 0x64
1127 #define V_008DFC_SQ_DS_MIN_RTN_I64 0x65
1128 #define V_008DFC_SQ_DS_MAX_RTN_I64 0x66
1129 #define V_008DFC_SQ_DS_MIN_RTN_U64 0x67
1130 #define V_008DFC_SQ_DS_MAX_RTN_U64 0x68
1131 #define V_008DFC_SQ_DS_AND_RTN_B64 0x69
1132 #define V_008DFC_SQ_DS_OR_RTN_B64 0x6A
1133 #define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B
1134 #define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C
1135 #define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D
1136 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E
1137 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F
1138 #define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70
1139 #define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71
1140 #define V_008DFC_SQ_DS_MIN_RTN_F64 0x72
1141 #define V_008DFC_SQ_DS_MAX_RTN_F64 0x73
1142 #define V_008DFC_SQ_DS_READ_B64 0x76
1143 #define V_008DFC_SQ_DS_READ2_B64 0x77
1144 #define V_008DFC_SQ_DS_READ2ST64_B64 0x78
1145 #define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80
1146 #define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81
1147 #define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82
1148 #define V_008DFC_SQ_DS_INC_SRC2_U32 0x83
1149 #define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84
1150 #define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85
1151 #define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86
1152 #define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87
1153 #define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88
1154 #define V_008DFC_SQ_DS_AND_SRC2_B32 0x89
1155 #define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A
1156 #define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B
1157 #define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D
1158 #define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92
1159 #define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93
1160 #define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0
1161 #define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1
1162 #define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2
1163 #define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3
1164 #define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4
1165 #define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5
1166 #define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6
1167 #define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7
1168 #define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8
1169 #define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9
1170 #define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA
1171 #define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB
1172 #define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD
1173 #define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2
1174 #define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3
1175 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1176 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1177 #define C_008DFC_ENCODING 0x03FFFFFF
1178 #define V_008DFC_SQ_ENC_DS_FIELD 0x36
1179 #define R_008DFC_SQ_SOPC 0x008DFC
1180 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
1181 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
1182 #define C_008DFC_SSRC0 0xFFFFFF00
1183 #define V_008DFC_SQ_SGPR 0x00
1184 #define V_008DFC_SQ_VCC_LO 0x6A
1185 #define V_008DFC_SQ_VCC_HI 0x6B
1186 #define V_008DFC_SQ_TBA_LO 0x6C
1187 #define V_008DFC_SQ_TBA_HI 0x6D
1188 #define V_008DFC_SQ_TMA_LO 0x6E
1189 #define V_008DFC_SQ_TMA_HI 0x6F
1190 #define V_008DFC_SQ_TTMP0 0x70
1191 #define V_008DFC_SQ_TTMP1 0x71
1192 #define V_008DFC_SQ_TTMP2 0x72
1193 #define V_008DFC_SQ_TTMP3 0x73
1194 #define V_008DFC_SQ_TTMP4 0x74
1195 #define V_008DFC_SQ_TTMP5 0x75
1196 #define V_008DFC_SQ_TTMP6 0x76
1197 #define V_008DFC_SQ_TTMP7 0x77
1198 #define V_008DFC_SQ_TTMP8 0x78
1199 #define V_008DFC_SQ_TTMP9 0x79
1200 #define V_008DFC_SQ_TTMP10 0x7A
1201 #define V_008DFC_SQ_TTMP11 0x7B
1202 #define V_008DFC_SQ_M0 0x7C
1203 #define V_008DFC_SQ_EXEC_LO 0x7E
1204 #define V_008DFC_SQ_EXEC_HI 0x7F
1205 #define V_008DFC_SQ_SRC_0 0x80
1206 #define V_008DFC_SQ_SRC_1_INT 0x81
1207 #define V_008DFC_SQ_SRC_2_INT 0x82
1208 #define V_008DFC_SQ_SRC_3_INT 0x83
1209 #define V_008DFC_SQ_SRC_4_INT 0x84
1210 #define V_008DFC_SQ_SRC_5_INT 0x85
1211 #define V_008DFC_SQ_SRC_6_INT 0x86
1212 #define V_008DFC_SQ_SRC_7_INT 0x87
1213 #define V_008DFC_SQ_SRC_8_INT 0x88
1214 #define V_008DFC_SQ_SRC_9_INT 0x89
1215 #define V_008DFC_SQ_SRC_10_INT 0x8A
1216 #define V_008DFC_SQ_SRC_11_INT 0x8B
1217 #define V_008DFC_SQ_SRC_12_INT 0x8C
1218 #define V_008DFC_SQ_SRC_13_INT 0x8D
1219 #define V_008DFC_SQ_SRC_14_INT 0x8E
1220 #define V_008DFC_SQ_SRC_15_INT 0x8F
1221 #define V_008DFC_SQ_SRC_16_INT 0x90
1222 #define V_008DFC_SQ_SRC_17_INT 0x91
1223 #define V_008DFC_SQ_SRC_18_INT 0x92
1224 #define V_008DFC_SQ_SRC_19_INT 0x93
1225 #define V_008DFC_SQ_SRC_20_INT 0x94
1226 #define V_008DFC_SQ_SRC_21_INT 0x95
1227 #define V_008DFC_SQ_SRC_22_INT 0x96
1228 #define V_008DFC_SQ_SRC_23_INT 0x97
1229 #define V_008DFC_SQ_SRC_24_INT 0x98
1230 #define V_008DFC_SQ_SRC_25_INT 0x99
1231 #define V_008DFC_SQ_SRC_26_INT 0x9A
1232 #define V_008DFC_SQ_SRC_27_INT 0x9B
1233 #define V_008DFC_SQ_SRC_28_INT 0x9C
1234 #define V_008DFC_SQ_SRC_29_INT 0x9D
1235 #define V_008DFC_SQ_SRC_30_INT 0x9E
1236 #define V_008DFC_SQ_SRC_31_INT 0x9F
1237 #define V_008DFC_SQ_SRC_32_INT 0xA0
1238 #define V_008DFC_SQ_SRC_33_INT 0xA1
1239 #define V_008DFC_SQ_SRC_34_INT 0xA2
1240 #define V_008DFC_SQ_SRC_35_INT 0xA3
1241 #define V_008DFC_SQ_SRC_36_INT 0xA4
1242 #define V_008DFC_SQ_SRC_37_INT 0xA5
1243 #define V_008DFC_SQ_SRC_38_INT 0xA6
1244 #define V_008DFC_SQ_SRC_39_INT 0xA7
1245 #define V_008DFC_SQ_SRC_40_INT 0xA8
1246 #define V_008DFC_SQ_SRC_41_INT 0xA9
1247 #define V_008DFC_SQ_SRC_42_INT 0xAA
1248 #define V_008DFC_SQ_SRC_43_INT 0xAB
1249 #define V_008DFC_SQ_SRC_44_INT 0xAC
1250 #define V_008DFC_SQ_SRC_45_INT 0xAD
1251 #define V_008DFC_SQ_SRC_46_INT 0xAE
1252 #define V_008DFC_SQ_SRC_47_INT 0xAF
1253 #define V_008DFC_SQ_SRC_48_INT 0xB0
1254 #define V_008DFC_SQ_SRC_49_INT 0xB1
1255 #define V_008DFC_SQ_SRC_50_INT 0xB2
1256 #define V_008DFC_SQ_SRC_51_INT 0xB3
1257 #define V_008DFC_SQ_SRC_52_INT 0xB4
1258 #define V_008DFC_SQ_SRC_53_INT 0xB5
1259 #define V_008DFC_SQ_SRC_54_INT 0xB6
1260 #define V_008DFC_SQ_SRC_55_INT 0xB7
1261 #define V_008DFC_SQ_SRC_56_INT 0xB8
1262 #define V_008DFC_SQ_SRC_57_INT 0xB9
1263 #define V_008DFC_SQ_SRC_58_INT 0xBA
1264 #define V_008DFC_SQ_SRC_59_INT 0xBB
1265 #define V_008DFC_SQ_SRC_60_INT 0xBC
1266 #define V_008DFC_SQ_SRC_61_INT 0xBD
1267 #define V_008DFC_SQ_SRC_62_INT 0xBE
1268 #define V_008DFC_SQ_SRC_63_INT 0xBF
1269 #define V_008DFC_SQ_SRC_64_INT 0xC0
1270 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1271 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1272 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1273 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1274 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1275 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1276 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1277 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1278 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1279 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1280 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1281 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1282 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1283 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1284 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1285 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1286 #define V_008DFC_SQ_SRC_0_5 0xF0
1287 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1288 #define V_008DFC_SQ_SRC_1 0xF2
1289 #define V_008DFC_SQ_SRC_M_1 0xF3
1290 #define V_008DFC_SQ_SRC_2 0xF4
1291 #define V_008DFC_SQ_SRC_M_2 0xF5
1292 #define V_008DFC_SQ_SRC_4 0xF6
1293 #define V_008DFC_SQ_SRC_M_4 0xF7
1294 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1295 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1296 #define V_008DFC_SQ_SRC_SCC 0xFD
1297 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1298 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8)
1299 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF)
1300 #define C_008DFC_SSRC1 0xFFFF00FF
1301 #define V_008DFC_SQ_SGPR 0x00
1302 #define V_008DFC_SQ_VCC_LO 0x6A
1303 #define V_008DFC_SQ_VCC_HI 0x6B
1304 #define V_008DFC_SQ_TBA_LO 0x6C
1305 #define V_008DFC_SQ_TBA_HI 0x6D
1306 #define V_008DFC_SQ_TMA_LO 0x6E
1307 #define V_008DFC_SQ_TMA_HI 0x6F
1308 #define V_008DFC_SQ_TTMP0 0x70
1309 #define V_008DFC_SQ_TTMP1 0x71
1310 #define V_008DFC_SQ_TTMP2 0x72
1311 #define V_008DFC_SQ_TTMP3 0x73
1312 #define V_008DFC_SQ_TTMP4 0x74
1313 #define V_008DFC_SQ_TTMP5 0x75
1314 #define V_008DFC_SQ_TTMP6 0x76
1315 #define V_008DFC_SQ_TTMP7 0x77
1316 #define V_008DFC_SQ_TTMP8 0x78
1317 #define V_008DFC_SQ_TTMP9 0x79
1318 #define V_008DFC_SQ_TTMP10 0x7A
1319 #define V_008DFC_SQ_TTMP11 0x7B
1320 #define V_008DFC_SQ_M0 0x7C
1321 #define V_008DFC_SQ_EXEC_LO 0x7E
1322 #define V_008DFC_SQ_EXEC_HI 0x7F
1323 #define V_008DFC_SQ_SRC_0 0x80
1324 #define V_008DFC_SQ_SRC_1_INT 0x81
1325 #define V_008DFC_SQ_SRC_2_INT 0x82
1326 #define V_008DFC_SQ_SRC_3_INT 0x83
1327 #define V_008DFC_SQ_SRC_4_INT 0x84
1328 #define V_008DFC_SQ_SRC_5_INT 0x85
1329 #define V_008DFC_SQ_SRC_6_INT 0x86
1330 #define V_008DFC_SQ_SRC_7_INT 0x87
1331 #define V_008DFC_SQ_SRC_8_INT 0x88
1332 #define V_008DFC_SQ_SRC_9_INT 0x89
1333 #define V_008DFC_SQ_SRC_10_INT 0x8A
1334 #define V_008DFC_SQ_SRC_11_INT 0x8B
1335 #define V_008DFC_SQ_SRC_12_INT 0x8C
1336 #define V_008DFC_SQ_SRC_13_INT 0x8D
1337 #define V_008DFC_SQ_SRC_14_INT 0x8E
1338 #define V_008DFC_SQ_SRC_15_INT 0x8F
1339 #define V_008DFC_SQ_SRC_16_INT 0x90
1340 #define V_008DFC_SQ_SRC_17_INT 0x91
1341 #define V_008DFC_SQ_SRC_18_INT 0x92
1342 #define V_008DFC_SQ_SRC_19_INT 0x93
1343 #define V_008DFC_SQ_SRC_20_INT 0x94
1344 #define V_008DFC_SQ_SRC_21_INT 0x95
1345 #define V_008DFC_SQ_SRC_22_INT 0x96
1346 #define V_008DFC_SQ_SRC_23_INT 0x97
1347 #define V_008DFC_SQ_SRC_24_INT 0x98
1348 #define V_008DFC_SQ_SRC_25_INT 0x99
1349 #define V_008DFC_SQ_SRC_26_INT 0x9A
1350 #define V_008DFC_SQ_SRC_27_INT 0x9B
1351 #define V_008DFC_SQ_SRC_28_INT 0x9C
1352 #define V_008DFC_SQ_SRC_29_INT 0x9D
1353 #define V_008DFC_SQ_SRC_30_INT 0x9E
1354 #define V_008DFC_SQ_SRC_31_INT 0x9F
1355 #define V_008DFC_SQ_SRC_32_INT 0xA0
1356 #define V_008DFC_SQ_SRC_33_INT 0xA1
1357 #define V_008DFC_SQ_SRC_34_INT 0xA2
1358 #define V_008DFC_SQ_SRC_35_INT 0xA3
1359 #define V_008DFC_SQ_SRC_36_INT 0xA4
1360 #define V_008DFC_SQ_SRC_37_INT 0xA5
1361 #define V_008DFC_SQ_SRC_38_INT 0xA6
1362 #define V_008DFC_SQ_SRC_39_INT 0xA7
1363 #define V_008DFC_SQ_SRC_40_INT 0xA8
1364 #define V_008DFC_SQ_SRC_41_INT 0xA9
1365 #define V_008DFC_SQ_SRC_42_INT 0xAA
1366 #define V_008DFC_SQ_SRC_43_INT 0xAB
1367 #define V_008DFC_SQ_SRC_44_INT 0xAC
1368 #define V_008DFC_SQ_SRC_45_INT 0xAD
1369 #define V_008DFC_SQ_SRC_46_INT 0xAE
1370 #define V_008DFC_SQ_SRC_47_INT 0xAF
1371 #define V_008DFC_SQ_SRC_48_INT 0xB0
1372 #define V_008DFC_SQ_SRC_49_INT 0xB1
1373 #define V_008DFC_SQ_SRC_50_INT 0xB2
1374 #define V_008DFC_SQ_SRC_51_INT 0xB3
1375 #define V_008DFC_SQ_SRC_52_INT 0xB4
1376 #define V_008DFC_SQ_SRC_53_INT 0xB5
1377 #define V_008DFC_SQ_SRC_54_INT 0xB6
1378 #define V_008DFC_SQ_SRC_55_INT 0xB7
1379 #define V_008DFC_SQ_SRC_56_INT 0xB8
1380 #define V_008DFC_SQ_SRC_57_INT 0xB9
1381 #define V_008DFC_SQ_SRC_58_INT 0xBA
1382 #define V_008DFC_SQ_SRC_59_INT 0xBB
1383 #define V_008DFC_SQ_SRC_60_INT 0xBC
1384 #define V_008DFC_SQ_SRC_61_INT 0xBD
1385 #define V_008DFC_SQ_SRC_62_INT 0xBE
1386 #define V_008DFC_SQ_SRC_63_INT 0xBF
1387 #define V_008DFC_SQ_SRC_64_INT 0xC0
1388 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1389 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1390 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1391 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1392 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1393 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1394 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1395 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1396 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1397 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1398 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1399 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1400 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1401 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1402 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1403 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1404 #define V_008DFC_SQ_SRC_0_5 0xF0
1405 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1406 #define V_008DFC_SQ_SRC_1 0xF2
1407 #define V_008DFC_SQ_SRC_M_1 0xF3
1408 #define V_008DFC_SQ_SRC_2 0xF4
1409 #define V_008DFC_SQ_SRC_M_2 0xF5
1410 #define V_008DFC_SQ_SRC_4 0xF6
1411 #define V_008DFC_SQ_SRC_M_4 0xF7
1412 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1413 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1414 #define V_008DFC_SQ_SRC_SCC 0xFD
1415 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1416 #define S_008DFC_OP(x) (((x) & 0x7F) << 16)
1417 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F)
1418 #define C_008DFC_OP 0xFF80FFFF
1419 #define V_008DFC_SQ_S_CMP_EQ_I32 0x00
1420 #define V_008DFC_SQ_S_CMP_LG_I32 0x01
1421 #define V_008DFC_SQ_S_CMP_GT_I32 0x02
1422 #define V_008DFC_SQ_S_CMP_GE_I32 0x03
1423 #define V_008DFC_SQ_S_CMP_LT_I32 0x04
1424 #define V_008DFC_SQ_S_CMP_LE_I32 0x05
1425 #define V_008DFC_SQ_S_CMP_EQ_U32 0x06
1426 #define V_008DFC_SQ_S_CMP_LG_U32 0x07
1427 #define V_008DFC_SQ_S_CMP_GT_U32 0x08
1428 #define V_008DFC_SQ_S_CMP_GE_U32 0x09
1429 #define V_008DFC_SQ_S_CMP_LT_U32 0x0A
1430 #define V_008DFC_SQ_S_CMP_LE_U32 0x0B
1431 #define V_008DFC_SQ_S_BITCMP0_B32 0x0C
1432 #define V_008DFC_SQ_S_BITCMP1_B32 0x0D
1433 #define V_008DFC_SQ_S_BITCMP0_B64 0x0E
1434 #define V_008DFC_SQ_S_BITCMP1_B64 0x0F
1435 #define V_008DFC_SQ_S_SETVSKIP 0x10
1436 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
1437 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
1438 #define C_008DFC_ENCODING 0x007FFFFF
1439 #define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E
1441 #define R_008DFC_SQ_EXP_0 0x008DFC
1442 #define S_008DFC_EN(x) (((x) & 0x0F) << 0)
1443 #define G_008DFC_EN(x) (((x) >> 0) & 0x0F)
1444 #define C_008DFC_EN 0xFFFFFFF0
1445 #define S_008DFC_TGT(x) (((x) & 0x3F) << 4)
1446 #define G_008DFC_TGT(x) (((x) >> 4) & 0x3F)
1447 #define C_008DFC_TGT 0xFFFFFC0F
1448 #define V_008DFC_SQ_EXP_MRT 0x00
1449 #define V_008DFC_SQ_EXP_MRTZ 0x08
1450 #define V_008DFC_SQ_EXP_NULL 0x09
1451 #define V_008DFC_SQ_EXP_POS 0x0C
1452 #define V_008DFC_SQ_EXP_PARAM 0x20
1453 #define S_008DFC_COMPR(x) (((x) & 0x1) << 10)
1454 #define G_008DFC_COMPR(x) (((x) >> 10) & 0x1)
1455 #define C_008DFC_COMPR 0xFFFFFBFF
1456 #define S_008DFC_DONE(x) (((x) & 0x1) << 11)
1457 #define G_008DFC_DONE(x) (((x) >> 11) & 0x1)
1458 #define C_008DFC_DONE 0xFFFFF7FF
1459 #define S_008DFC_VM(x) (((x) & 0x1) << 12)
1460 #define G_008DFC_VM(x) (((x) >> 12) & 0x1)
1461 #define C_008DFC_VM 0xFFFFEFFF
1462 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1463 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1464 #define C_008DFC_ENCODING 0x03FFFFFF
1465 #define V_008DFC_SQ_ENC_EXP_FIELD 0x3E
1467 #define R_008DFC_SQ_MIMG_0 0x008DFC
1468 #define S_008DFC_DMASK(x) (((x) & 0x0F) << 8)
1469 #define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F)
1470 #define C_008DFC_DMASK 0xFFFFF0FF
1471 #define S_008DFC_UNORM(x) (((x) & 0x1) << 12)
1472 #define G_008DFC_UNORM(x) (((x) >> 12) & 0x1)
1473 #define C_008DFC_UNORM 0xFFFFEFFF
1474 #define S_008DFC_GLC(x) (((x) & 0x1) << 13)
1475 #define G_008DFC_GLC(x) (((x) >> 13) & 0x1)
1476 #define C_008DFC_GLC 0xFFFFDFFF
1477 #define S_008DFC_DA(x) (((x) & 0x1) << 14)
1478 #define G_008DFC_DA(x) (((x) >> 14) & 0x1)
1479 #define C_008DFC_DA 0xFFFFBFFF
1480 #define S_008DFC_R128(x) (((x) & 0x1) << 15)
1481 #define G_008DFC_R128(x) (((x) >> 15) & 0x1)
1482 #define C_008DFC_R128 0xFFFF7FFF
1483 #define S_008DFC_TFE(x) (((x) & 0x1) << 16)
1484 #define G_008DFC_TFE(x) (((x) >> 16) & 0x1)
1485 #define C_008DFC_TFE 0xFFFEFFFF
1486 #define S_008DFC_LWE(x) (((x) & 0x1) << 17)
1487 #define G_008DFC_LWE(x) (((x) >> 17) & 0x1)
1488 #define C_008DFC_LWE 0xFFFDFFFF
1489 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
1490 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
1491 #define C_008DFC_OP 0xFE03FFFF
1492 #define V_008DFC_SQ_IMAGE_LOAD 0x00
1493 #define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01
1494 #define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02
1495 #define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03
1496 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04
1497 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05
1498 #define V_008DFC_SQ_IMAGE_STORE 0x08
1499 #define V_008DFC_SQ_IMAGE_STORE_MIP 0x09
1500 #define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A
1501 #define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B
1502 #define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E
1503 #define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F
1504 #define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10
1505 #define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11
1506 #define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12
1507 #define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13
1508 #define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14
1509 #define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15
1510 #define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16
1511 #define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17
1512 #define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18
1513 #define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19
1514 #define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A
1515 #define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B
1516 #define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C
1517 #define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D
1518 #define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E
1519 #define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F
1520 #define V_008DFC_SQ_IMAGE_SAMPLE 0x20
1521 #define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21
1522 #define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22
1523 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23
1524 #define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24
1525 #define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25
1526 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26
1527 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27
1528 #define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28
1529 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29
1530 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A
1531 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B
1532 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C
1533 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D
1534 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E
1535 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F
1536 #define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30
1537 #define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31
1538 #define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32
1539 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33
1540 #define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34
1541 #define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35
1542 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36
1543 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37
1544 #define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38
1545 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39
1546 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A
1547 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B
1548 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C
1549 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D
1550 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E
1551 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F
1552 #define V_008DFC_SQ_IMAGE_GATHER4 0x40
1553 #define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41
1554 #define V_008DFC_SQ_IMAGE_GATHER4_L 0x44
1555 #define V_008DFC_SQ_IMAGE_GATHER4_B 0x45
1556 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46
1557 #define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47
1558 #define V_008DFC_SQ_IMAGE_GATHER4_C 0x48
1559 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49
1560 #define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C
1561 #define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D
1562 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E
1563 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F
1564 #define V_008DFC_SQ_IMAGE_GATHER4_O 0x50
1565 #define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51
1566 #define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54
1567 #define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55
1568 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56
1569 #define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57
1570 #define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58
1571 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59
1572 #define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C
1573 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D
1574 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E
1575 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F
1576 #define V_008DFC_SQ_IMAGE_GET_LOD 0x60
1577 #define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68
1578 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69
1579 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A
1580 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B
1581 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C
1582 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D
1583 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E
1584 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F
1585 #define V_008DFC_SQ_IMAGE_RSRC256 0x7E
1586 #define V_008DFC_SQ_IMAGE_SAMPLER 0x7F
1587 #define S_008DFC_SLC(x) (((x) & 0x1) << 25)
1588 #define G_008DFC_SLC(x) (((x) >> 25) & 0x1)
1589 #define C_008DFC_SLC 0xFDFFFFFF
1590 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1591 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1592 #define C_008DFC_ENCODING 0x03FFFFFF
1593 #define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C
1594 #define R_008DFC_SQ_SOPP 0x008DFC
1595 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0)
1596 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF)
1597 #define C_008DFC_SIMM16 0xFFFF0000
1598 #define S_008DFC_OP(x) (((x) & 0x7F) << 16)
1599 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F)
1600 #define C_008DFC_OP 0xFF80FFFF
1601 #define V_008DFC_SQ_S_NOP 0x00
1602 #define V_008DFC_SQ_S_ENDPGM 0x01
1603 #define V_008DFC_SQ_S_BRANCH 0x02
1604 #define V_008DFC_SQ_S_CBRANCH_SCC0 0x04
1605 #define V_008DFC_SQ_S_CBRANCH_SCC1 0x05
1606 #define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06
1607 #define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07
1608 #define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08
1609 #define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09
1610 #define V_008DFC_SQ_S_BARRIER 0x0A
1611 #define V_008DFC_SQ_S_WAITCNT 0x0C
1612 #define V_008DFC_SQ_S_SETHALT 0x0D
1613 #define V_008DFC_SQ_S_SLEEP 0x0E
1614 #define V_008DFC_SQ_S_SETPRIO 0x0F
1615 #define V_008DFC_SQ_S_SENDMSG 0x10
1616 #define V_008DFC_SQ_S_SENDMSGHALT 0x11
1617 #define V_008DFC_SQ_S_TRAP 0x12
1618 #define V_008DFC_SQ_S_ICACHE_INV 0x13
1619 #define V_008DFC_SQ_S_INCPERFLEVEL 0x14
1620 #define V_008DFC_SQ_S_DECPERFLEVEL 0x15
1621 #define V_008DFC_SQ_S_TTRACEDATA 0x16
1622 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
1623 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
1624 #define C_008DFC_ENCODING 0x007FFFFF
1625 #define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F
1626 #define R_008DFC_SQ_VINTRP 0x008DFC
1627 #define S_008DFC_VSRC(x) (((x) & 0xFF) << 0)
1628 #define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF)
1629 #define C_008DFC_VSRC 0xFFFFFF00
1630 #define V_008DFC_SQ_VGPR 0x00
1631 #define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8)
1632 #define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03)
1633 #define C_008DFC_ATTRCHAN 0xFFFFFCFF
1634 #define V_008DFC_SQ_CHAN_X 0x00
1635 #define V_008DFC_SQ_CHAN_Y 0x01
1636 #define V_008DFC_SQ_CHAN_Z 0x02
1637 #define V_008DFC_SQ_CHAN_W 0x03
1638 #define S_008DFC_ATTR(x) (((x) & 0x3F) << 10)
1639 #define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F)
1640 #define C_008DFC_ATTR 0xFFFF03FF
1641 #define V_008DFC_SQ_ATTR 0x00
1642 #define S_008DFC_OP(x) (((x) & 0x03) << 16)
1643 #define G_008DFC_OP(x) (((x) >> 16) & 0x03)
1644 #define C_008DFC_OP 0xFFFCFFFF
1645 #define V_008DFC_SQ_V_INTERP_P1_F32 0x00
1646 #define V_008DFC_SQ_V_INTERP_P2_F32 0x01
1647 #define V_008DFC_SQ_V_INTERP_MOV_F32 0x02
1648 #define S_008DFC_VDST(x) (((x) & 0xFF) << 18)
1649 #define G_008DFC_VDST(x) (((x) >> 18) & 0xFF)
1650 #define C_008DFC_VDST 0xFC03FFFF
1651 #define V_008DFC_SQ_VGPR 0x00
1652 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1653 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1654 #define C_008DFC_ENCODING 0x03FFFFFF
1655 #define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32
1656 #define R_008DFC_SQ_MTBUF_0 0x008DFC
1657 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0)
1658 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF)
1659 #define C_008DFC_OFFSET 0xFFFFF000
1660 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12)
1661 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1)
1662 #define C_008DFC_OFFEN 0xFFFFEFFF
1663 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13)
1664 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1)
1665 #define C_008DFC_IDXEN 0xFFFFDFFF
1666 #define S_008DFC_GLC(x) (((x) & 0x1) << 14)
1667 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1)
1668 #define C_008DFC_GLC 0xFFFFBFFF
1669 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15)
1670 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1)
1671 #define C_008DFC_ADDR64 0xFFFF7FFF
1672 #define S_008DFC_OP(x) (((x) & 0x07) << 16)
1673 #define G_008DFC_OP(x) (((x) >> 16) & 0x07)
1674 #define C_008DFC_OP 0xFFF8FFFF
1675 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00
1676 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01
1677 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02
1678 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03
1679 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04
1680 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05
1681 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06
1682 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07
1683 #define S_008DFC_DFMT(x) (((x) & 0x0F) << 19)
1684 #define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F)
1685 #define C_008DFC_DFMT 0xFF87FFFF
1686 #define S_008DFC_NFMT(x) (((x) & 0x07) << 23)
1687 #define G_008DFC_NFMT(x) (((x) >> 23) & 0x07)
1688 #define C_008DFC_NFMT 0xFC7FFFFF
1689 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1690 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1691 #define C_008DFC_ENCODING 0x03FFFFFF
1692 #define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A
1693 #define R_008DFC_SQ_SMRD 0x008DFC
1694 #define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0)
1695 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF)
1696 #define C_008DFC_OFFSET 0xFFFFFF00
1697 #define V_008DFC_SQ_SGPR 0x00
1698 #define V_008DFC_SQ_VCC_LO 0x6A
1699 #define V_008DFC_SQ_VCC_HI 0x6B
1700 #define V_008DFC_SQ_TBA_LO 0x6C
1701 #define V_008DFC_SQ_TBA_HI 0x6D
1702 #define V_008DFC_SQ_TMA_LO 0x6E
1703 #define V_008DFC_SQ_TMA_HI 0x6F
1704 #define V_008DFC_SQ_TTMP0 0x70
1705 #define V_008DFC_SQ_TTMP1 0x71
1706 #define V_008DFC_SQ_TTMP2 0x72
1707 #define V_008DFC_SQ_TTMP3 0x73
1708 #define V_008DFC_SQ_TTMP4 0x74
1709 #define V_008DFC_SQ_TTMP5 0x75
1710 #define V_008DFC_SQ_TTMP6 0x76
1711 #define V_008DFC_SQ_TTMP7 0x77
1712 #define V_008DFC_SQ_TTMP8 0x78
1713 #define V_008DFC_SQ_TTMP9 0x79
1714 #define V_008DFC_SQ_TTMP10 0x7A
1715 #define V_008DFC_SQ_TTMP11 0x7B
1716 #define S_008DFC_IMM(x) (((x) & 0x1) << 8)
1717 #define G_008DFC_IMM(x) (((x) >> 8) & 0x1)
1718 #define C_008DFC_IMM 0xFFFFFEFF
1719 #define S_008DFC_SBASE(x) (((x) & 0x3F) << 9)
1720 #define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F)
1721 #define C_008DFC_SBASE 0xFFFF81FF
1722 #define S_008DFC_SDST(x) (((x) & 0x7F) << 15)
1723 #define G_008DFC_SDST(x) (((x) >> 15) & 0x7F)
1724 #define C_008DFC_SDST 0xFFC07FFF
1725 #define V_008DFC_SQ_SGPR 0x00
1726 #define V_008DFC_SQ_VCC_LO 0x6A
1727 #define V_008DFC_SQ_VCC_HI 0x6B
1728 #define V_008DFC_SQ_TBA_LO 0x6C
1729 #define V_008DFC_SQ_TBA_HI 0x6D
1730 #define V_008DFC_SQ_TMA_LO 0x6E
1731 #define V_008DFC_SQ_TMA_HI 0x6F
1732 #define V_008DFC_SQ_TTMP0 0x70
1733 #define V_008DFC_SQ_TTMP1 0x71
1734 #define V_008DFC_SQ_TTMP2 0x72
1735 #define V_008DFC_SQ_TTMP3 0x73
1736 #define V_008DFC_SQ_TTMP4 0x74
1737 #define V_008DFC_SQ_TTMP5 0x75
1738 #define V_008DFC_SQ_TTMP6 0x76
1739 #define V_008DFC_SQ_TTMP7 0x77
1740 #define V_008DFC_SQ_TTMP8 0x78
1741 #define V_008DFC_SQ_TTMP9 0x79
1742 #define V_008DFC_SQ_TTMP10 0x7A
1743 #define V_008DFC_SQ_TTMP11 0x7B
1744 #define V_008DFC_SQ_M0 0x7C
1745 #define V_008DFC_SQ_EXEC_LO 0x7E
1746 #define V_008DFC_SQ_EXEC_HI 0x7F
1747 #define S_008DFC_OP(x) (((x) & 0x1F) << 22)
1748 #define G_008DFC_OP(x) (((x) >> 22) & 0x1F)
1749 #define C_008DFC_OP 0xF83FFFFF
1750 #define V_008DFC_SQ_S_LOAD_DWORD 0x00
1751 #define V_008DFC_SQ_S_LOAD_DWORDX2 0x01
1752 #define V_008DFC_SQ_S_LOAD_DWORDX4 0x02
1753 #define V_008DFC_SQ_S_LOAD_DWORDX8 0x03
1754 #define V_008DFC_SQ_S_LOAD_DWORDX16 0x04
1755 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08
1756 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09
1757 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A
1758 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B
1759 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C
1760 #define V_008DFC_SQ_S_MEMTIME 0x1E
1761 #define V_008DFC_SQ_S_DCACHE_INV 0x1F
1762 #define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27)
1763 #define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F)
1764 #define C_008DFC_ENCODING 0x07FFFFFF
1765 #define V_008DFC_SQ_ENC_SMRD_FIELD 0x18
1766 #define R_008DFC_SQ_EXP_1 0x008DFC
1767 #define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0)
1768 #define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF)
1769 #define C_008DFC_VSRC0 0xFFFFFF00
1770 #define V_008DFC_SQ_VGPR 0x00
1771 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8)
1772 #define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF)
1773 #define C_008DFC_VSRC1 0xFFFF00FF
1774 #define V_008DFC_SQ_VGPR 0x00
1775 #define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16)
1776 #define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF)
1777 #define C_008DFC_VSRC2 0xFF00FFFF
1778 #define V_008DFC_SQ_VGPR 0x00
1779 #define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24)
1780 #define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF)
1781 #define C_008DFC_VSRC3 0x00FFFFFF
1782 #define V_008DFC_SQ_VGPR 0x00
1783 #define R_008DFC_SQ_DS_1 0x008DFC
1784 #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0)
1785 #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF)
1786 #define C_008DFC_ADDR 0xFFFFFF00
1787 #define V_008DFC_SQ_VGPR 0x00
1788 #define S_008DFC_DATA0(x) (((x) & 0xFF) << 8)
1789 #define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF)
1790 #define C_008DFC_DATA0 0xFFFF00FF
1791 #define V_008DFC_SQ_VGPR 0x00
1792 #define S_008DFC_DATA1(x) (((x) & 0xFF) << 16)
1793 #define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF)
1794 #define C_008DFC_DATA1 0xFF00FFFF
1795 #define V_008DFC_SQ_VGPR 0x00
1796 #define S_008DFC_VDST(x) (((x) & 0xFF) << 24)
1797 #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF)
1798 #define C_008DFC_VDST 0x00FFFFFF
1799 #define V_008DFC_SQ_VGPR 0x00
1800 #define R_008DFC_SQ_VOPC 0x008DFC
1801 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
1802 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
1803 #define C_008DFC_SRC0 0xFFFFFE00
1804 #define V_008DFC_SQ_SGPR 0x00
1805 #define V_008DFC_SQ_VCC_LO 0x6A
1806 #define V_008DFC_SQ_VCC_HI 0x6B
1807 #define V_008DFC_SQ_TBA_LO 0x6C
1808 #define V_008DFC_SQ_TBA_HI 0x6D
1809 #define V_008DFC_SQ_TMA_LO 0x6E
1810 #define V_008DFC_SQ_TMA_HI 0x6F
1811 #define V_008DFC_SQ_TTMP0 0x70
1812 #define V_008DFC_SQ_TTMP1 0x71
1813 #define V_008DFC_SQ_TTMP2 0x72
1814 #define V_008DFC_SQ_TTMP3 0x73
1815 #define V_008DFC_SQ_TTMP4 0x74
1816 #define V_008DFC_SQ_TTMP5 0x75
1817 #define V_008DFC_SQ_TTMP6 0x76
1818 #define V_008DFC_SQ_TTMP7 0x77
1819 #define V_008DFC_SQ_TTMP8 0x78
1820 #define V_008DFC_SQ_TTMP9 0x79
1821 #define V_008DFC_SQ_TTMP10 0x7A
1822 #define V_008DFC_SQ_TTMP11 0x7B
1823 #define V_008DFC_SQ_M0 0x7C
1824 #define V_008DFC_SQ_EXEC_LO 0x7E
1825 #define V_008DFC_SQ_EXEC_HI 0x7F
1826 #define V_008DFC_SQ_SRC_0 0x80
1827 #define V_008DFC_SQ_SRC_1_INT 0x81
1828 #define V_008DFC_SQ_SRC_2_INT 0x82
1829 #define V_008DFC_SQ_SRC_3_INT 0x83
1830 #define V_008DFC_SQ_SRC_4_INT 0x84
1831 #define V_008DFC_SQ_SRC_5_INT 0x85
1832 #define V_008DFC_SQ_SRC_6_INT 0x86
1833 #define V_008DFC_SQ_SRC_7_INT 0x87
1834 #define V_008DFC_SQ_SRC_8_INT 0x88
1835 #define V_008DFC_SQ_SRC_9_INT 0x89
1836 #define V_008DFC_SQ_SRC_10_INT 0x8A
1837 #define V_008DFC_SQ_SRC_11_INT 0x8B
1838 #define V_008DFC_SQ_SRC_12_INT 0x8C
1839 #define V_008DFC_SQ_SRC_13_INT 0x8D
1840 #define V_008DFC_SQ_SRC_14_INT 0x8E
1841 #define V_008DFC_SQ_SRC_15_INT 0x8F
1842 #define V_008DFC_SQ_SRC_16_INT 0x90
1843 #define V_008DFC_SQ_SRC_17_INT 0x91
1844 #define V_008DFC_SQ_SRC_18_INT 0x92
1845 #define V_008DFC_SQ_SRC_19_INT 0x93
1846 #define V_008DFC_SQ_SRC_20_INT 0x94
1847 #define V_008DFC_SQ_SRC_21_INT 0x95
1848 #define V_008DFC_SQ_SRC_22_INT 0x96
1849 #define V_008DFC_SQ_SRC_23_INT 0x97
1850 #define V_008DFC_SQ_SRC_24_INT 0x98
1851 #define V_008DFC_SQ_SRC_25_INT 0x99
1852 #define V_008DFC_SQ_SRC_26_INT 0x9A
1853 #define V_008DFC_SQ_SRC_27_INT 0x9B
1854 #define V_008DFC_SQ_SRC_28_INT 0x9C
1855 #define V_008DFC_SQ_SRC_29_INT 0x9D
1856 #define V_008DFC_SQ_SRC_30_INT 0x9E
1857 #define V_008DFC_SQ_SRC_31_INT 0x9F
1858 #define V_008DFC_SQ_SRC_32_INT 0xA0
1859 #define V_008DFC_SQ_SRC_33_INT 0xA1
1860 #define V_008DFC_SQ_SRC_34_INT 0xA2
1861 #define V_008DFC_SQ_SRC_35_INT 0xA3
1862 #define V_008DFC_SQ_SRC_36_INT 0xA4
1863 #define V_008DFC_SQ_SRC_37_INT 0xA5
1864 #define V_008DFC_SQ_SRC_38_INT 0xA6
1865 #define V_008DFC_SQ_SRC_39_INT 0xA7
1866 #define V_008DFC_SQ_SRC_40_INT 0xA8
1867 #define V_008DFC_SQ_SRC_41_INT 0xA9
1868 #define V_008DFC_SQ_SRC_42_INT 0xAA
1869 #define V_008DFC_SQ_SRC_43_INT 0xAB
1870 #define V_008DFC_SQ_SRC_44_INT 0xAC
1871 #define V_008DFC_SQ_SRC_45_INT 0xAD
1872 #define V_008DFC_SQ_SRC_46_INT 0xAE
1873 #define V_008DFC_SQ_SRC_47_INT 0xAF
1874 #define V_008DFC_SQ_SRC_48_INT 0xB0
1875 #define V_008DFC_SQ_SRC_49_INT 0xB1
1876 #define V_008DFC_SQ_SRC_50_INT 0xB2
1877 #define V_008DFC_SQ_SRC_51_INT 0xB3
1878 #define V_008DFC_SQ_SRC_52_INT 0xB4
1879 #define V_008DFC_SQ_SRC_53_INT 0xB5
1880 #define V_008DFC_SQ_SRC_54_INT 0xB6
1881 #define V_008DFC_SQ_SRC_55_INT 0xB7
1882 #define V_008DFC_SQ_SRC_56_INT 0xB8
1883 #define V_008DFC_SQ_SRC_57_INT 0xB9
1884 #define V_008DFC_SQ_SRC_58_INT 0xBA
1885 #define V_008DFC_SQ_SRC_59_INT 0xBB
1886 #define V_008DFC_SQ_SRC_60_INT 0xBC
1887 #define V_008DFC_SQ_SRC_61_INT 0xBD
1888 #define V_008DFC_SQ_SRC_62_INT 0xBE
1889 #define V_008DFC_SQ_SRC_63_INT 0xBF
1890 #define V_008DFC_SQ_SRC_64_INT 0xC0
1891 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1892 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1893 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1894 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1895 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1896 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1897 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1898 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1899 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1900 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1901 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1902 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1903 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1904 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1905 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1906 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1907 #define V_008DFC_SQ_SRC_0_5 0xF0
1908 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1909 #define V_008DFC_SQ_SRC_1 0xF2
1910 #define V_008DFC_SQ_SRC_M_1 0xF3
1911 #define V_008DFC_SQ_SRC_2 0xF4
1912 #define V_008DFC_SQ_SRC_M_2 0xF5
1913 #define V_008DFC_SQ_SRC_4 0xF6
1914 #define V_008DFC_SQ_SRC_M_4 0xF7
1915 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1916 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1917 #define V_008DFC_SQ_SRC_SCC 0xFD
1918 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1919 #define V_008DFC_SQ_SRC_VGPR 0x100
1920 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9)
1921 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF)
1922 #define C_008DFC_VSRC1 0xFFFE01FF
1923 #define V_008DFC_SQ_VGPR 0x00
1924 #define S_008DFC_OP(x) (((x) & 0xFF) << 17)
1925 #define G_008DFC_OP(x) (((x) >> 17) & 0xFF)
1926 #define C_008DFC_OP 0xFE01FFFF
1927 #define V_008DFC_SQ_V_CMP_F_F32 0x00
1928 #define V_008DFC_SQ_V_CMP_LT_F32 0x01
1929 #define V_008DFC_SQ_V_CMP_EQ_F32 0x02
1930 #define V_008DFC_SQ_V_CMP_LE_F32 0x03
1931 #define V_008DFC_SQ_V_CMP_GT_F32 0x04
1932 #define V_008DFC_SQ_V_CMP_LG_F32 0x05
1933 #define V_008DFC_SQ_V_CMP_GE_F32 0x06
1934 #define V_008DFC_SQ_V_CMP_O_F32 0x07
1935 #define V_008DFC_SQ_V_CMP_U_F32 0x08
1936 #define V_008DFC_SQ_V_CMP_NGE_F32 0x09
1937 #define V_008DFC_SQ_V_CMP_NLG_F32 0x0A
1938 #define V_008DFC_SQ_V_CMP_NGT_F32 0x0B
1939 #define V_008DFC_SQ_V_CMP_NLE_F32 0x0C
1940 #define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D
1941 #define V_008DFC_SQ_V_CMP_NLT_F32 0x0E
1942 #define V_008DFC_SQ_V_CMP_TRU_F32 0x0F
1943 #define V_008DFC_SQ_V_CMPX_F_F32 0x10
1944 #define V_008DFC_SQ_V_CMPX_LT_F32 0x11
1945 #define V_008DFC_SQ_V_CMPX_EQ_F32 0x12
1946 #define V_008DFC_SQ_V_CMPX_LE_F32 0x13
1947 #define V_008DFC_SQ_V_CMPX_GT_F32 0x14
1948 #define V_008DFC_SQ_V_CMPX_LG_F32 0x15
1949 #define V_008DFC_SQ_V_CMPX_GE_F32 0x16
1950 #define V_008DFC_SQ_V_CMPX_O_F32 0x17
1951 #define V_008DFC_SQ_V_CMPX_U_F32 0x18
1952 #define V_008DFC_SQ_V_CMPX_NGE_F32 0x19
1953 #define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A
1954 #define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B
1955 #define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C
1956 #define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D
1957 #define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E
1958 #define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F
1959 #define V_008DFC_SQ_V_CMP_F_F64 0x20
1960 #define V_008DFC_SQ_V_CMP_LT_F64 0x21
1961 #define V_008DFC_SQ_V_CMP_EQ_F64 0x22
1962 #define V_008DFC_SQ_V_CMP_LE_F64 0x23
1963 #define V_008DFC_SQ_V_CMP_GT_F64 0x24
1964 #define V_008DFC_SQ_V_CMP_LG_F64 0x25
1965 #define V_008DFC_SQ_V_CMP_GE_F64 0x26
1966 #define V_008DFC_SQ_V_CMP_O_F64 0x27
1967 #define V_008DFC_SQ_V_CMP_U_F64 0x28
1968 #define V_008DFC_SQ_V_CMP_NGE_F64 0x29
1969 #define V_008DFC_SQ_V_CMP_NLG_F64 0x2A
1970 #define V_008DFC_SQ_V_CMP_NGT_F64 0x2B
1971 #define V_008DFC_SQ_V_CMP_NLE_F64 0x2C
1972 #define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D
1973 #define V_008DFC_SQ_V_CMP_NLT_F64 0x2E
1974 #define V_008DFC_SQ_V_CMP_TRU_F64 0x2F
1975 #define V_008DFC_SQ_V_CMPX_F_F64 0x30
1976 #define V_008DFC_SQ_V_CMPX_LT_F64 0x31
1977 #define V_008DFC_SQ_V_CMPX_EQ_F64 0x32
1978 #define V_008DFC_SQ_V_CMPX_LE_F64 0x33
1979 #define V_008DFC_SQ_V_CMPX_GT_F64 0x34
1980 #define V_008DFC_SQ_V_CMPX_LG_F64 0x35
1981 #define V_008DFC_SQ_V_CMPX_GE_F64 0x36
1982 #define V_008DFC_SQ_V_CMPX_O_F64 0x37
1983 #define V_008DFC_SQ_V_CMPX_U_F64 0x38
1984 #define V_008DFC_SQ_V_CMPX_NGE_F64 0x39
1985 #define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A
1986 #define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B
1987 #define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C
1988 #define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D
1989 #define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E
1990 #define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F
1991 #define V_008DFC_SQ_V_CMPS_F_F32 0x40
1992 #define V_008DFC_SQ_V_CMPS_LT_F32 0x41
1993 #define V_008DFC_SQ_V_CMPS_EQ_F32 0x42
1994 #define V_008DFC_SQ_V_CMPS_LE_F32 0x43
1995 #define V_008DFC_SQ_V_CMPS_GT_F32 0x44
1996 #define V_008DFC_SQ_V_CMPS_LG_F32 0x45
1997 #define V_008DFC_SQ_V_CMPS_GE_F32 0x46
1998 #define V_008DFC_SQ_V_CMPS_O_F32 0x47
1999 #define V_008DFC_SQ_V_CMPS_U_F32 0x48
2000 #define V_008DFC_SQ_V_CMPS_NGE_F32 0x49
2001 #define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A
2002 #define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B
2003 #define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C
2004 #define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D
2005 #define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E
2006 #define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F
2007 #define V_008DFC_SQ_V_CMPSX_F_F32 0x50
2008 #define V_008DFC_SQ_V_CMPSX_LT_F32 0x51
2009 #define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52
2010 #define V_008DFC_SQ_V_CMPSX_LE_F32 0x53
2011 #define V_008DFC_SQ_V_CMPSX_GT_F32 0x54
2012 #define V_008DFC_SQ_V_CMPSX_LG_F32 0x55
2013 #define V_008DFC_SQ_V_CMPSX_GE_F32 0x56
2014 #define V_008DFC_SQ_V_CMPSX_O_F32 0x57
2015 #define V_008DFC_SQ_V_CMPSX_U_F32 0x58
2016 #define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59
2017 #define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A
2018 #define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B
2019 #define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C
2020 #define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D
2021 #define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E
2022 #define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F
2023 #define V_008DFC_SQ_V_CMPS_F_F64 0x60
2024 #define V_008DFC_SQ_V_CMPS_LT_F64 0x61
2025 #define V_008DFC_SQ_V_CMPS_EQ_F64 0x62
2026 #define V_008DFC_SQ_V_CMPS_LE_F64 0x63
2027 #define V_008DFC_SQ_V_CMPS_GT_F64 0x64
2028 #define V_008DFC_SQ_V_CMPS_LG_F64 0x65
2029 #define V_008DFC_SQ_V_CMPS_GE_F64 0x66
2030 #define V_008DFC_SQ_V_CMPS_O_F64 0x67
2031 #define V_008DFC_SQ_V_CMPS_U_F64 0x68
2032 #define V_008DFC_SQ_V_CMPS_NGE_F64 0x69
2033 #define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A
2034 #define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B
2035 #define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C
2036 #define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D
2037 #define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E
2038 #define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F
2039 #define V_008DFC_SQ_V_CMPSX_F_F64 0x70
2040 #define V_008DFC_SQ_V_CMPSX_LT_F64 0x71
2041 #define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72
2042 #define V_008DFC_SQ_V_CMPSX_LE_F64 0x73
2043 #define V_008DFC_SQ_V_CMPSX_GT_F64 0x74
2044 #define V_008DFC_SQ_V_CMPSX_LG_F64 0x75
2045 #define V_008DFC_SQ_V_CMPSX_GE_F64 0x76
2046 #define V_008DFC_SQ_V_CMPSX_O_F64 0x77
2047 #define V_008DFC_SQ_V_CMPSX_U_F64 0x78
2048 #define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79
2049 #define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A
2050 #define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B
2051 #define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C
2052 #define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D
2053 #define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E
2054 #define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F
2055 #define V_008DFC_SQ_V_CMP_F_I32 0x80
2056 #define V_008DFC_SQ_V_CMP_LT_I32 0x81
2057 #define V_008DFC_SQ_V_CMP_EQ_I32 0x82
2058 #define V_008DFC_SQ_V_CMP_LE_I32 0x83
2059 #define V_008DFC_SQ_V_CMP_GT_I32 0x84
2060 #define V_008DFC_SQ_V_CMP_NE_I32 0x85
2061 #define V_008DFC_SQ_V_CMP_GE_I32 0x86
2062 #define V_008DFC_SQ_V_CMP_T_I32 0x87
2063 #define V_008DFC_SQ_V_CMP_CLASS_F32 0x88
2064 #define V_008DFC_SQ_V_CMPX_F_I32 0x90
2065 #define V_008DFC_SQ_V_CMPX_LT_I32 0x91
2066 #define V_008DFC_SQ_V_CMPX_EQ_I32 0x92
2067 #define V_008DFC_SQ_V_CMPX_LE_I32 0x93
2068 #define V_008DFC_SQ_V_CMPX_GT_I32 0x94
2069 #define V_008DFC_SQ_V_CMPX_NE_I32 0x95
2070 #define V_008DFC_SQ_V_CMPX_GE_I32 0x96
2071 #define V_008DFC_SQ_V_CMPX_T_I32 0x97
2072 #define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98
2073 #define V_008DFC_SQ_V_CMP_F_I64 0xA0
2074 #define V_008DFC_SQ_V_CMP_LT_I64 0xA1
2075 #define V_008DFC_SQ_V_CMP_EQ_I64 0xA2
2076 #define V_008DFC_SQ_V_CMP_LE_I64 0xA3
2077 #define V_008DFC_SQ_V_CMP_GT_I64 0xA4
2078 #define V_008DFC_SQ_V_CMP_NE_I64 0xA5
2079 #define V_008DFC_SQ_V_CMP_GE_I64 0xA6
2080 #define V_008DFC_SQ_V_CMP_T_I64 0xA7
2081 #define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8
2082 #define V_008DFC_SQ_V_CMPX_F_I64 0xB0
2083 #define V_008DFC_SQ_V_CMPX_LT_I64 0xB1
2084 #define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2
2085 #define V_008DFC_SQ_V_CMPX_LE_I64 0xB3
2086 #define V_008DFC_SQ_V_CMPX_GT_I64 0xB4
2087 #define V_008DFC_SQ_V_CMPX_NE_I64 0xB5
2088 #define V_008DFC_SQ_V_CMPX_GE_I64 0xB6
2089 #define V_008DFC_SQ_V_CMPX_T_I64 0xB7
2090 #define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8
2091 #define V_008DFC_SQ_V_CMP_F_U32 0xC0
2092 #define V_008DFC_SQ_V_CMP_LT_U32 0xC1
2093 #define V_008DFC_SQ_V_CMP_EQ_U32 0xC2
2094 #define V_008DFC_SQ_V_CMP_LE_U32 0xC3
2095 #define V_008DFC_SQ_V_CMP_GT_U32 0xC4
2096 #define V_008DFC_SQ_V_CMP_NE_U32 0xC5
2097 #define V_008DFC_SQ_V_CMP_GE_U32 0xC6
2098 #define V_008DFC_SQ_V_CMP_T_U32 0xC7
2099 #define V_008DFC_SQ_V_CMPX_F_U32 0xD0
2100 #define V_008DFC_SQ_V_CMPX_LT_U32 0xD1
2101 #define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2
2102 #define V_008DFC_SQ_V_CMPX_LE_U32 0xD3
2103 #define V_008DFC_SQ_V_CMPX_GT_U32 0xD4
2104 #define V_008DFC_SQ_V_CMPX_NE_U32 0xD5
2105 #define V_008DFC_SQ_V_CMPX_GE_U32 0xD6
2106 #define V_008DFC_SQ_V_CMPX_T_U32 0xD7
2107 #define V_008DFC_SQ_V_CMP_F_U64 0xE0
2108 #define V_008DFC_SQ_V_CMP_LT_U64 0xE1
2109 #define V_008DFC_SQ_V_CMP_EQ_U64 0xE2
2110 #define V_008DFC_SQ_V_CMP_LE_U64 0xE3
2111 #define V_008DFC_SQ_V_CMP_GT_U64 0xE4
2112 #define V_008DFC_SQ_V_CMP_NE_U64 0xE5
2113 #define V_008DFC_SQ_V_CMP_GE_U64 0xE6
2114 #define V_008DFC_SQ_V_CMP_T_U64 0xE7
2115 #define V_008DFC_SQ_V_CMPX_F_U64 0xF0
2116 #define V_008DFC_SQ_V_CMPX_LT_U64 0xF1
2117 #define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2
2118 #define V_008DFC_SQ_V_CMPX_LE_U64 0xF3
2119 #define V_008DFC_SQ_V_CMPX_GT_U64 0xF4
2120 #define V_008DFC_SQ_V_CMPX_NE_U64 0xF5
2121 #define V_008DFC_SQ_V_CMPX_GE_U64 0xF6
2122 #define V_008DFC_SQ_V_CMPX_T_U64 0xF7
2123 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25)
2124 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F)
2125 #define C_008DFC_ENCODING 0x01FFFFFF
2126 #define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E
2127 #define R_008DFC_SQ_SOP1 0x008DFC
2128 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
2129 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
2130 #define C_008DFC_SSRC0 0xFFFFFF00
2131 #define V_008DFC_SQ_SGPR 0x00
2132 #define V_008DFC_SQ_VCC_LO 0x6A
2133 #define V_008DFC_SQ_VCC_HI 0x6B
2134 #define V_008DFC_SQ_TBA_LO 0x6C
2135 #define V_008DFC_SQ_TBA_HI 0x6D
2136 #define V_008DFC_SQ_TMA_LO 0x6E
2137 #define V_008DFC_SQ_TMA_HI 0x6F
2138 #define V_008DFC_SQ_TTMP0 0x70
2139 #define V_008DFC_SQ_TTMP1 0x71
2140 #define V_008DFC_SQ_TTMP2 0x72
2141 #define V_008DFC_SQ_TTMP3 0x73
2142 #define V_008DFC_SQ_TTMP4 0x74
2143 #define V_008DFC_SQ_TTMP5 0x75
2144 #define V_008DFC_SQ_TTMP6 0x76
2145 #define V_008DFC_SQ_TTMP7 0x77
2146 #define V_008DFC_SQ_TTMP8 0x78
2147 #define V_008DFC_SQ_TTMP9 0x79
2148 #define V_008DFC_SQ_TTMP10 0x7A
2149 #define V_008DFC_SQ_TTMP11 0x7B
2150 #define V_008DFC_SQ_M0 0x7C
2151 #define V_008DFC_SQ_EXEC_LO 0x7E
2152 #define V_008DFC_SQ_EXEC_HI 0x7F
2153 #define V_008DFC_SQ_SRC_0 0x80
2154 #define V_008DFC_SQ_SRC_1_INT 0x81
2155 #define V_008DFC_SQ_SRC_2_INT 0x82
2156 #define V_008DFC_SQ_SRC_3_INT 0x83
2157 #define V_008DFC_SQ_SRC_4_INT 0x84
2158 #define V_008DFC_SQ_SRC_5_INT 0x85
2159 #define V_008DFC_SQ_SRC_6_INT 0x86
2160 #define V_008DFC_SQ_SRC_7_INT 0x87
2161 #define V_008DFC_SQ_SRC_8_INT 0x88
2162 #define V_008DFC_SQ_SRC_9_INT 0x89
2163 #define V_008DFC_SQ_SRC_10_INT 0x8A
2164 #define V_008DFC_SQ_SRC_11_INT 0x8B
2165 #define V_008DFC_SQ_SRC_12_INT 0x8C
2166 #define V_008DFC_SQ_SRC_13_INT 0x8D
2167 #define V_008DFC_SQ_SRC_14_INT 0x8E
2168 #define V_008DFC_SQ_SRC_15_INT 0x8F
2169 #define V_008DFC_SQ_SRC_16_INT 0x90
2170 #define V_008DFC_SQ_SRC_17_INT 0x91
2171 #define V_008DFC_SQ_SRC_18_INT 0x92
2172 #define V_008DFC_SQ_SRC_19_INT 0x93
2173 #define V_008DFC_SQ_SRC_20_INT 0x94
2174 #define V_008DFC_SQ_SRC_21_INT 0x95
2175 #define V_008DFC_SQ_SRC_22_INT 0x96
2176 #define V_008DFC_SQ_SRC_23_INT 0x97
2177 #define V_008DFC_SQ_SRC_24_INT 0x98
2178 #define V_008DFC_SQ_SRC_25_INT 0x99
2179 #define V_008DFC_SQ_SRC_26_INT 0x9A
2180 #define V_008DFC_SQ_SRC_27_INT 0x9B
2181 #define V_008DFC_SQ_SRC_28_INT 0x9C
2182 #define V_008DFC_SQ_SRC_29_INT 0x9D
2183 #define V_008DFC_SQ_SRC_30_INT 0x9E
2184 #define V_008DFC_SQ_SRC_31_INT 0x9F
2185 #define V_008DFC_SQ_SRC_32_INT 0xA0
2186 #define V_008DFC_SQ_SRC_33_INT 0xA1
2187 #define V_008DFC_SQ_SRC_34_INT 0xA2
2188 #define V_008DFC_SQ_SRC_35_INT 0xA3
2189 #define V_008DFC_SQ_SRC_36_INT 0xA4
2190 #define V_008DFC_SQ_SRC_37_INT 0xA5
2191 #define V_008DFC_SQ_SRC_38_INT 0xA6
2192 #define V_008DFC_SQ_SRC_39_INT 0xA7
2193 #define V_008DFC_SQ_SRC_40_INT 0xA8
2194 #define V_008DFC_SQ_SRC_41_INT 0xA9
2195 #define V_008DFC_SQ_SRC_42_INT 0xAA
2196 #define V_008DFC_SQ_SRC_43_INT 0xAB
2197 #define V_008DFC_SQ_SRC_44_INT 0xAC
2198 #define V_008DFC_SQ_SRC_45_INT 0xAD
2199 #define V_008DFC_SQ_SRC_46_INT 0xAE
2200 #define V_008DFC_SQ_SRC_47_INT 0xAF
2201 #define V_008DFC_SQ_SRC_48_INT 0xB0
2202 #define V_008DFC_SQ_SRC_49_INT 0xB1
2203 #define V_008DFC_SQ_SRC_50_INT 0xB2
2204 #define V_008DFC_SQ_SRC_51_INT 0xB3
2205 #define V_008DFC_SQ_SRC_52_INT 0xB4
2206 #define V_008DFC_SQ_SRC_53_INT 0xB5
2207 #define V_008DFC_SQ_SRC_54_INT 0xB6
2208 #define V_008DFC_SQ_SRC_55_INT 0xB7
2209 #define V_008DFC_SQ_SRC_56_INT 0xB8
2210 #define V_008DFC_SQ_SRC_57_INT 0xB9
2211 #define V_008DFC_SQ_SRC_58_INT 0xBA
2212 #define V_008DFC_SQ_SRC_59_INT 0xBB
2213 #define V_008DFC_SQ_SRC_60_INT 0xBC
2214 #define V_008DFC_SQ_SRC_61_INT 0xBD
2215 #define V_008DFC_SQ_SRC_62_INT 0xBE
2216 #define V_008DFC_SQ_SRC_63_INT 0xBF
2217 #define V_008DFC_SQ_SRC_64_INT 0xC0
2218 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2219 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2220 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2221 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2222 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2223 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2224 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2225 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2226 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2227 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2228 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2229 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2230 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2231 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2232 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2233 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2234 #define V_008DFC_SQ_SRC_0_5 0xF0
2235 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2236 #define V_008DFC_SQ_SRC_1 0xF2
2237 #define V_008DFC_SQ_SRC_M_1 0xF3
2238 #define V_008DFC_SQ_SRC_2 0xF4
2239 #define V_008DFC_SQ_SRC_M_2 0xF5
2240 #define V_008DFC_SQ_SRC_4 0xF6
2241 #define V_008DFC_SQ_SRC_M_4 0xF7
2242 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2243 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2244 #define V_008DFC_SQ_SRC_SCC 0xFD
2245 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2246 #define S_008DFC_OP(x) (((x) & 0xFF) << 8)
2247 #define G_008DFC_OP(x) (((x) >> 8) & 0xFF)
2248 #define C_008DFC_OP 0xFFFF00FF
2249 #define V_008DFC_SQ_S_MOV_B32 0x03
2250 #define V_008DFC_SQ_S_MOV_B64 0x04
2251 #define V_008DFC_SQ_S_CMOV_B32 0x05
2252 #define V_008DFC_SQ_S_CMOV_B64 0x06
2253 #define V_008DFC_SQ_S_NOT_B32 0x07
2254 #define V_008DFC_SQ_S_NOT_B64 0x08
2255 #define V_008DFC_SQ_S_WQM_B32 0x09
2256 #define V_008DFC_SQ_S_WQM_B64 0x0A
2257 #define V_008DFC_SQ_S_BREV_B32 0x0B
2258 #define V_008DFC_SQ_S_BREV_B64 0x0C
2259 #define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D
2260 #define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E
2261 #define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F
2262 #define V_008DFC_SQ_S_BCNT1_I32_B64 0x10
2263 #define V_008DFC_SQ_S_FF0_I32_B32 0x11
2264 #define V_008DFC_SQ_S_FF0_I32_B64 0x12
2265 #define V_008DFC_SQ_S_FF1_I32_B32 0x13
2266 #define V_008DFC_SQ_S_FF1_I32_B64 0x14
2267 #define V_008DFC_SQ_S_FLBIT_I32_B32 0x15
2268 #define V_008DFC_SQ_S_FLBIT_I32_B64 0x16
2269 #define V_008DFC_SQ_S_FLBIT_I32 0x17
2270 #define V_008DFC_SQ_S_FLBIT_I32_I64 0x18
2271 #define V_008DFC_SQ_S_SEXT_I32_I8 0x19
2272 #define V_008DFC_SQ_S_SEXT_I32_I16 0x1A
2273 #define V_008DFC_SQ_S_BITSET0_B32 0x1B
2274 #define V_008DFC_SQ_S_BITSET0_B64 0x1C
2275 #define V_008DFC_SQ_S_BITSET1_B32 0x1D
2276 #define V_008DFC_SQ_S_BITSET1_B64 0x1E
2277 #define V_008DFC_SQ_S_GETPC_B64 0x1F
2278 #define V_008DFC_SQ_S_SETPC_B64 0x20
2279 #define V_008DFC_SQ_S_SWAPPC_B64 0x21
2280 #define V_008DFC_SQ_S_RFE_B64 0x22
2281 #define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24
2282 #define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25
2283 #define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26
2284 #define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27
2285 #define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28
2286 #define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29
2287 #define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A
2288 #define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B
2289 #define V_008DFC_SQ_S_QUADMASK_B32 0x2C
2290 #define V_008DFC_SQ_S_QUADMASK_B64 0x2D
2291 #define V_008DFC_SQ_S_MOVRELS_B32 0x2E
2292 #define V_008DFC_SQ_S_MOVRELS_B64 0x2F
2293 #define V_008DFC_SQ_S_MOVRELD_B32 0x30
2294 #define V_008DFC_SQ_S_MOVRELD_B64 0x31
2295 #define V_008DFC_SQ_S_CBRANCH_JOIN 0x32
2296 #define V_008DFC_SQ_S_MOV_REGRD_B32 0x33
2297 #define V_008DFC_SQ_S_ABS_I32 0x34
2298 #define V_008DFC_SQ_S_MOV_FED_B32 0x35
2299 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
2300 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
2301 #define C_008DFC_SDST 0xFF80FFFF
2302 #define V_008DFC_SQ_SGPR 0x00
2303 #define V_008DFC_SQ_VCC_LO 0x6A
2304 #define V_008DFC_SQ_VCC_HI 0x6B
2305 #define V_008DFC_SQ_TBA_LO 0x6C
2306 #define V_008DFC_SQ_TBA_HI 0x6D
2307 #define V_008DFC_SQ_TMA_LO 0x6E
2308 #define V_008DFC_SQ_TMA_HI 0x6F
2309 #define V_008DFC_SQ_TTMP0 0x70
2310 #define V_008DFC_SQ_TTMP1 0x71
2311 #define V_008DFC_SQ_TTMP2 0x72
2312 #define V_008DFC_SQ_TTMP3 0x73
2313 #define V_008DFC_SQ_TTMP4 0x74
2314 #define V_008DFC_SQ_TTMP5 0x75
2315 #define V_008DFC_SQ_TTMP6 0x76
2316 #define V_008DFC_SQ_TTMP7 0x77
2317 #define V_008DFC_SQ_TTMP8 0x78
2318 #define V_008DFC_SQ_TTMP9 0x79
2319 #define V_008DFC_SQ_TTMP10 0x7A
2320 #define V_008DFC_SQ_TTMP11 0x7B
2321 #define V_008DFC_SQ_M0 0x7C
2322 #define V_008DFC_SQ_EXEC_LO 0x7E
2323 #define V_008DFC_SQ_EXEC_HI 0x7F
2324 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
2325 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
2326 #define C_008DFC_ENCODING 0x007FFFFF
2327 #define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D
2328 #define R_008DFC_SQ_MTBUF_1 0x008DFC
2329 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
2330 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
2331 #define C_008DFC_VADDR 0xFFFFFF00
2332 #define V_008DFC_SQ_VGPR 0x00
2333 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
2334 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
2335 #define C_008DFC_VDATA 0xFFFF00FF
2336 #define V_008DFC_SQ_VGPR 0x00
2337 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
2338 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
2339 #define C_008DFC_SRSRC 0xFFE0FFFF
2340 #define S_008DFC_SLC(x) (((x) & 0x1) << 22)
2341 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1)
2342 #define C_008DFC_SLC 0xFFBFFFFF
2343 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
2344 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
2345 #define C_008DFC_TFE 0xFF7FFFFF
2346 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24)
2347 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF)
2348 #define C_008DFC_SOFFSET 0x00FFFFFF
2349 #define V_008DFC_SQ_SGPR 0x00
2350 #define V_008DFC_SQ_VCC_LO 0x6A
2351 #define V_008DFC_SQ_VCC_HI 0x6B
2352 #define V_008DFC_SQ_TBA_LO 0x6C
2353 #define V_008DFC_SQ_TBA_HI 0x6D
2354 #define V_008DFC_SQ_TMA_LO 0x6E
2355 #define V_008DFC_SQ_TMA_HI 0x6F
2356 #define V_008DFC_SQ_TTMP0 0x70
2357 #define V_008DFC_SQ_TTMP1 0x71
2358 #define V_008DFC_SQ_TTMP2 0x72
2359 #define V_008DFC_SQ_TTMP3 0x73
2360 #define V_008DFC_SQ_TTMP4 0x74
2361 #define V_008DFC_SQ_TTMP5 0x75
2362 #define V_008DFC_SQ_TTMP6 0x76
2363 #define V_008DFC_SQ_TTMP7 0x77
2364 #define V_008DFC_SQ_TTMP8 0x78
2365 #define V_008DFC_SQ_TTMP9 0x79
2366 #define V_008DFC_SQ_TTMP10 0x7A
2367 #define V_008DFC_SQ_TTMP11 0x7B
2368 #define V_008DFC_SQ_M0 0x7C
2369 #define V_008DFC_SQ_EXEC_LO 0x7E
2370 #define V_008DFC_SQ_EXEC_HI 0x7F
2371 #define V_008DFC_SQ_SRC_0 0x80
2372 #define V_008DFC_SQ_SRC_1_INT 0x81
2373 #define V_008DFC_SQ_SRC_2_INT 0x82
2374 #define V_008DFC_SQ_SRC_3_INT 0x83
2375 #define V_008DFC_SQ_SRC_4_INT 0x84
2376 #define V_008DFC_SQ_SRC_5_INT 0x85
2377 #define V_008DFC_SQ_SRC_6_INT 0x86
2378 #define V_008DFC_SQ_SRC_7_INT 0x87
2379 #define V_008DFC_SQ_SRC_8_INT 0x88
2380 #define V_008DFC_SQ_SRC_9_INT 0x89
2381 #define V_008DFC_SQ_SRC_10_INT 0x8A
2382 #define V_008DFC_SQ_SRC_11_INT 0x8B
2383 #define V_008DFC_SQ_SRC_12_INT 0x8C
2384 #define V_008DFC_SQ_SRC_13_INT 0x8D
2385 #define V_008DFC_SQ_SRC_14_INT 0x8E
2386 #define V_008DFC_SQ_SRC_15_INT 0x8F
2387 #define V_008DFC_SQ_SRC_16_INT 0x90
2388 #define V_008DFC_SQ_SRC_17_INT 0x91
2389 #define V_008DFC_SQ_SRC_18_INT 0x92
2390 #define V_008DFC_SQ_SRC_19_INT 0x93
2391 #define V_008DFC_SQ_SRC_20_INT 0x94
2392 #define V_008DFC_SQ_SRC_21_INT 0x95
2393 #define V_008DFC_SQ_SRC_22_INT 0x96
2394 #define V_008DFC_SQ_SRC_23_INT 0x97
2395 #define V_008DFC_SQ_SRC_24_INT 0x98
2396 #define V_008DFC_SQ_SRC_25_INT 0x99
2397 #define V_008DFC_SQ_SRC_26_INT 0x9A
2398 #define V_008DFC_SQ_SRC_27_INT 0x9B
2399 #define V_008DFC_SQ_SRC_28_INT 0x9C
2400 #define V_008DFC_SQ_SRC_29_INT 0x9D
2401 #define V_008DFC_SQ_SRC_30_INT 0x9E
2402 #define V_008DFC_SQ_SRC_31_INT 0x9F
2403 #define V_008DFC_SQ_SRC_32_INT 0xA0
2404 #define V_008DFC_SQ_SRC_33_INT 0xA1
2405 #define V_008DFC_SQ_SRC_34_INT 0xA2
2406 #define V_008DFC_SQ_SRC_35_INT 0xA3
2407 #define V_008DFC_SQ_SRC_36_INT 0xA4
2408 #define V_008DFC_SQ_SRC_37_INT 0xA5
2409 #define V_008DFC_SQ_SRC_38_INT 0xA6
2410 #define V_008DFC_SQ_SRC_39_INT 0xA7
2411 #define V_008DFC_SQ_SRC_40_INT 0xA8
2412 #define V_008DFC_SQ_SRC_41_INT 0xA9
2413 #define V_008DFC_SQ_SRC_42_INT 0xAA
2414 #define V_008DFC_SQ_SRC_43_INT 0xAB
2415 #define V_008DFC_SQ_SRC_44_INT 0xAC
2416 #define V_008DFC_SQ_SRC_45_INT 0xAD
2417 #define V_008DFC_SQ_SRC_46_INT 0xAE
2418 #define V_008DFC_SQ_SRC_47_INT 0xAF
2419 #define V_008DFC_SQ_SRC_48_INT 0xB0
2420 #define V_008DFC_SQ_SRC_49_INT 0xB1
2421 #define V_008DFC_SQ_SRC_50_INT 0xB2
2422 #define V_008DFC_SQ_SRC_51_INT 0xB3
2423 #define V_008DFC_SQ_SRC_52_INT 0xB4
2424 #define V_008DFC_SQ_SRC_53_INT 0xB5
2425 #define V_008DFC_SQ_SRC_54_INT 0xB6
2426 #define V_008DFC_SQ_SRC_55_INT 0xB7
2427 #define V_008DFC_SQ_SRC_56_INT 0xB8
2428 #define V_008DFC_SQ_SRC_57_INT 0xB9
2429 #define V_008DFC_SQ_SRC_58_INT 0xBA
2430 #define V_008DFC_SQ_SRC_59_INT 0xBB
2431 #define V_008DFC_SQ_SRC_60_INT 0xBC
2432 #define V_008DFC_SQ_SRC_61_INT 0xBD
2433 #define V_008DFC_SQ_SRC_62_INT 0xBE
2434 #define V_008DFC_SQ_SRC_63_INT 0xBF
2435 #define V_008DFC_SQ_SRC_64_INT 0xC0
2436 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2437 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2438 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2439 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2440 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2441 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2442 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2443 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2444 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2445 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2446 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2447 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2448 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2449 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2450 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2451 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2452 #define V_008DFC_SQ_SRC_0_5 0xF0
2453 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2454 #define V_008DFC_SQ_SRC_1 0xF2
2455 #define V_008DFC_SQ_SRC_M_1 0xF3
2456 #define V_008DFC_SQ_SRC_2 0xF4
2457 #define V_008DFC_SQ_SRC_M_2 0xF5
2458 #define V_008DFC_SQ_SRC_4 0xF6
2459 #define V_008DFC_SQ_SRC_M_4 0xF7
2460 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2461 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2462 #define V_008DFC_SQ_SRC_SCC 0xFD
2463 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2464 #define R_008DFC_SQ_SOP2 0x008DFC
2465 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
2466 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
2467 #define C_008DFC_SSRC0 0xFFFFFF00
2468 #define V_008DFC_SQ_SGPR 0x00
2469 #define V_008DFC_SQ_VCC_LO 0x6A
2470 #define V_008DFC_SQ_VCC_HI 0x6B
2471 #define V_008DFC_SQ_TBA_LO 0x6C
2472 #define V_008DFC_SQ_TBA_HI 0x6D
2473 #define V_008DFC_SQ_TMA_LO 0x6E
2474 #define V_008DFC_SQ_TMA_HI 0x6F
2475 #define V_008DFC_SQ_TTMP0 0x70
2476 #define V_008DFC_SQ_TTMP1 0x71
2477 #define V_008DFC_SQ_TTMP2 0x72
2478 #define V_008DFC_SQ_TTMP3 0x73
2479 #define V_008DFC_SQ_TTMP4 0x74
2480 #define V_008DFC_SQ_TTMP5 0x75
2481 #define V_008DFC_SQ_TTMP6 0x76
2482 #define V_008DFC_SQ_TTMP7 0x77
2483 #define V_008DFC_SQ_TTMP8 0x78
2484 #define V_008DFC_SQ_TTMP9 0x79
2485 #define V_008DFC_SQ_TTMP10 0x7A
2486 #define V_008DFC_SQ_TTMP11 0x7B
2487 #define V_008DFC_SQ_M0 0x7C
2488 #define V_008DFC_SQ_EXEC_LO 0x7E
2489 #define V_008DFC_SQ_EXEC_HI 0x7F
2490 #define V_008DFC_SQ_SRC_0 0x80
2491 #define V_008DFC_SQ_SRC_1_INT 0x81
2492 #define V_008DFC_SQ_SRC_2_INT 0x82
2493 #define V_008DFC_SQ_SRC_3_INT 0x83
2494 #define V_008DFC_SQ_SRC_4_INT 0x84
2495 #define V_008DFC_SQ_SRC_5_INT 0x85
2496 #define V_008DFC_SQ_SRC_6_INT 0x86
2497 #define V_008DFC_SQ_SRC_7_INT 0x87
2498 #define V_008DFC_SQ_SRC_8_INT 0x88
2499 #define V_008DFC_SQ_SRC_9_INT 0x89
2500 #define V_008DFC_SQ_SRC_10_INT 0x8A
2501 #define V_008DFC_SQ_SRC_11_INT 0x8B
2502 #define V_008DFC_SQ_SRC_12_INT 0x8C
2503 #define V_008DFC_SQ_SRC_13_INT 0x8D
2504 #define V_008DFC_SQ_SRC_14_INT 0x8E
2505 #define V_008DFC_SQ_SRC_15_INT 0x8F
2506 #define V_008DFC_SQ_SRC_16_INT 0x90
2507 #define V_008DFC_SQ_SRC_17_INT 0x91
2508 #define V_008DFC_SQ_SRC_18_INT 0x92
2509 #define V_008DFC_SQ_SRC_19_INT 0x93
2510 #define V_008DFC_SQ_SRC_20_INT 0x94
2511 #define V_008DFC_SQ_SRC_21_INT 0x95
2512 #define V_008DFC_SQ_SRC_22_INT 0x96
2513 #define V_008DFC_SQ_SRC_23_INT 0x97
2514 #define V_008DFC_SQ_SRC_24_INT 0x98
2515 #define V_008DFC_SQ_SRC_25_INT 0x99
2516 #define V_008DFC_SQ_SRC_26_INT 0x9A
2517 #define V_008DFC_SQ_SRC_27_INT 0x9B
2518 #define V_008DFC_SQ_SRC_28_INT 0x9C
2519 #define V_008DFC_SQ_SRC_29_INT 0x9D
2520 #define V_008DFC_SQ_SRC_30_INT 0x9E
2521 #define V_008DFC_SQ_SRC_31_INT 0x9F
2522 #define V_008DFC_SQ_SRC_32_INT 0xA0
2523 #define V_008DFC_SQ_SRC_33_INT 0xA1
2524 #define V_008DFC_SQ_SRC_34_INT 0xA2
2525 #define V_008DFC_SQ_SRC_35_INT 0xA3
2526 #define V_008DFC_SQ_SRC_36_INT 0xA4
2527 #define V_008DFC_SQ_SRC_37_INT 0xA5
2528 #define V_008DFC_SQ_SRC_38_INT 0xA6
2529 #define V_008DFC_SQ_SRC_39_INT 0xA7
2530 #define V_008DFC_SQ_SRC_40_INT 0xA8
2531 #define V_008DFC_SQ_SRC_41_INT 0xA9
2532 #define V_008DFC_SQ_SRC_42_INT 0xAA
2533 #define V_008DFC_SQ_SRC_43_INT 0xAB
2534 #define V_008DFC_SQ_SRC_44_INT 0xAC
2535 #define V_008DFC_SQ_SRC_45_INT 0xAD
2536 #define V_008DFC_SQ_SRC_46_INT 0xAE
2537 #define V_008DFC_SQ_SRC_47_INT 0xAF
2538 #define V_008DFC_SQ_SRC_48_INT 0xB0
2539 #define V_008DFC_SQ_SRC_49_INT 0xB1
2540 #define V_008DFC_SQ_SRC_50_INT 0xB2
2541 #define V_008DFC_SQ_SRC_51_INT 0xB3
2542 #define V_008DFC_SQ_SRC_52_INT 0xB4
2543 #define V_008DFC_SQ_SRC_53_INT 0xB5
2544 #define V_008DFC_SQ_SRC_54_INT 0xB6
2545 #define V_008DFC_SQ_SRC_55_INT 0xB7
2546 #define V_008DFC_SQ_SRC_56_INT 0xB8
2547 #define V_008DFC_SQ_SRC_57_INT 0xB9
2548 #define V_008DFC_SQ_SRC_58_INT 0xBA
2549 #define V_008DFC_SQ_SRC_59_INT 0xBB
2550 #define V_008DFC_SQ_SRC_60_INT 0xBC
2551 #define V_008DFC_SQ_SRC_61_INT 0xBD
2552 #define V_008DFC_SQ_SRC_62_INT 0xBE
2553 #define V_008DFC_SQ_SRC_63_INT 0xBF
2554 #define V_008DFC_SQ_SRC_64_INT 0xC0
2555 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2556 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2557 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2558 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2559 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2560 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2561 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2562 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2563 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2564 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2565 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2566 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2567 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2568 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2569 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2570 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2571 #define V_008DFC_SQ_SRC_0_5 0xF0
2572 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2573 #define V_008DFC_SQ_SRC_1 0xF2
2574 #define V_008DFC_SQ_SRC_M_1 0xF3
2575 #define V_008DFC_SQ_SRC_2 0xF4
2576 #define V_008DFC_SQ_SRC_M_2 0xF5
2577 #define V_008DFC_SQ_SRC_4 0xF6
2578 #define V_008DFC_SQ_SRC_M_4 0xF7
2579 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2580 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2581 #define V_008DFC_SQ_SRC_SCC 0xFD
2582 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2583 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8)
2584 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF)
2585 #define C_008DFC_SSRC1 0xFFFF00FF
2586 #define V_008DFC_SQ_SGPR 0x00
2587 #define V_008DFC_SQ_VCC_LO 0x6A
2588 #define V_008DFC_SQ_VCC_HI 0x6B
2589 #define V_008DFC_SQ_TBA_LO 0x6C
2590 #define V_008DFC_SQ_TBA_HI 0x6D
2591 #define V_008DFC_SQ_TMA_LO 0x6E
2592 #define V_008DFC_SQ_TMA_HI 0x6F
2593 #define V_008DFC_SQ_TTMP0 0x70
2594 #define V_008DFC_SQ_TTMP1 0x71
2595 #define V_008DFC_SQ_TTMP2 0x72
2596 #define V_008DFC_SQ_TTMP3 0x73
2597 #define V_008DFC_SQ_TTMP4 0x74
2598 #define V_008DFC_SQ_TTMP5 0x75
2599 #define V_008DFC_SQ_TTMP6 0x76
2600 #define V_008DFC_SQ_TTMP7 0x77
2601 #define V_008DFC_SQ_TTMP8 0x78
2602 #define V_008DFC_SQ_TTMP9 0x79
2603 #define V_008DFC_SQ_TTMP10 0x7A
2604 #define V_008DFC_SQ_TTMP11 0x7B
2605 #define V_008DFC_SQ_M0 0x7C
2606 #define V_008DFC_SQ_EXEC_LO 0x7E
2607 #define V_008DFC_SQ_EXEC_HI 0x7F
2608 #define V_008DFC_SQ_SRC_0 0x80
2609 #define V_008DFC_SQ_SRC_1_INT 0x81
2610 #define V_008DFC_SQ_SRC_2_INT 0x82
2611 #define V_008DFC_SQ_SRC_3_INT 0x83
2612 #define V_008DFC_SQ_SRC_4_INT 0x84
2613 #define V_008DFC_SQ_SRC_5_INT 0x85
2614 #define V_008DFC_SQ_SRC_6_INT 0x86
2615 #define V_008DFC_SQ_SRC_7_INT 0x87
2616 #define V_008DFC_SQ_SRC_8_INT 0x88
2617 #define V_008DFC_SQ_SRC_9_INT 0x89
2618 #define V_008DFC_SQ_SRC_10_INT 0x8A
2619 #define V_008DFC_SQ_SRC_11_INT 0x8B
2620 #define V_008DFC_SQ_SRC_12_INT 0x8C
2621 #define V_008DFC_SQ_SRC_13_INT 0x8D
2622 #define V_008DFC_SQ_SRC_14_INT 0x8E
2623 #define V_008DFC_SQ_SRC_15_INT 0x8F
2624 #define V_008DFC_SQ_SRC_16_INT 0x90
2625 #define V_008DFC_SQ_SRC_17_INT 0x91
2626 #define V_008DFC_SQ_SRC_18_INT 0x92
2627 #define V_008DFC_SQ_SRC_19_INT 0x93
2628 #define V_008DFC_SQ_SRC_20_INT 0x94
2629 #define V_008DFC_SQ_SRC_21_INT 0x95
2630 #define V_008DFC_SQ_SRC_22_INT 0x96
2631 #define V_008DFC_SQ_SRC_23_INT 0x97
2632 #define V_008DFC_SQ_SRC_24_INT 0x98
2633 #define V_008DFC_SQ_SRC_25_INT 0x99
2634 #define V_008DFC_SQ_SRC_26_INT 0x9A
2635 #define V_008DFC_SQ_SRC_27_INT 0x9B
2636 #define V_008DFC_SQ_SRC_28_INT 0x9C
2637 #define V_008DFC_SQ_SRC_29_INT 0x9D
2638 #define V_008DFC_SQ_SRC_30_INT 0x9E
2639 #define V_008DFC_SQ_SRC_31_INT 0x9F
2640 #define V_008DFC_SQ_SRC_32_INT 0xA0
2641 #define V_008DFC_SQ_SRC_33_INT 0xA1
2642 #define V_008DFC_SQ_SRC_34_INT 0xA2
2643 #define V_008DFC_SQ_SRC_35_INT 0xA3
2644 #define V_008DFC_SQ_SRC_36_INT 0xA4
2645 #define V_008DFC_SQ_SRC_37_INT 0xA5
2646 #define V_008DFC_SQ_SRC_38_INT 0xA6
2647 #define V_008DFC_SQ_SRC_39_INT 0xA7
2648 #define V_008DFC_SQ_SRC_40_INT 0xA8
2649 #define V_008DFC_SQ_SRC_41_INT 0xA9
2650 #define V_008DFC_SQ_SRC_42_INT 0xAA
2651 #define V_008DFC_SQ_SRC_43_INT 0xAB
2652 #define V_008DFC_SQ_SRC_44_INT 0xAC
2653 #define V_008DFC_SQ_SRC_45_INT 0xAD
2654 #define V_008DFC_SQ_SRC_46_INT 0xAE
2655 #define V_008DFC_SQ_SRC_47_INT 0xAF
2656 #define V_008DFC_SQ_SRC_48_INT 0xB0
2657 #define V_008DFC_SQ_SRC_49_INT 0xB1
2658 #define V_008DFC_SQ_SRC_50_INT 0xB2
2659 #define V_008DFC_SQ_SRC_51_INT 0xB3
2660 #define V_008DFC_SQ_SRC_52_INT 0xB4
2661 #define V_008DFC_SQ_SRC_53_INT 0xB5
2662 #define V_008DFC_SQ_SRC_54_INT 0xB6
2663 #define V_008DFC_SQ_SRC_55_INT 0xB7
2664 #define V_008DFC_SQ_SRC_56_INT 0xB8
2665 #define V_008DFC_SQ_SRC_57_INT 0xB9
2666 #define V_008DFC_SQ_SRC_58_INT 0xBA
2667 #define V_008DFC_SQ_SRC_59_INT 0xBB
2668 #define V_008DFC_SQ_SRC_60_INT 0xBC
2669 #define V_008DFC_SQ_SRC_61_INT 0xBD
2670 #define V_008DFC_SQ_SRC_62_INT 0xBE
2671 #define V_008DFC_SQ_SRC_63_INT 0xBF
2672 #define V_008DFC_SQ_SRC_64_INT 0xC0
2673 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2674 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2675 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2676 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2677 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2678 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2679 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2680 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2681 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2682 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2683 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2684 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2685 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2686 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2687 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2688 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2689 #define V_008DFC_SQ_SRC_0_5 0xF0
2690 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2691 #define V_008DFC_SQ_SRC_1 0xF2
2692 #define V_008DFC_SQ_SRC_M_1 0xF3
2693 #define V_008DFC_SQ_SRC_2 0xF4
2694 #define V_008DFC_SQ_SRC_M_2 0xF5
2695 #define V_008DFC_SQ_SRC_4 0xF6
2696 #define V_008DFC_SQ_SRC_M_4 0xF7
2697 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2698 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2699 #define V_008DFC_SQ_SRC_SCC 0xFD
2700 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2701 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
2702 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
2703 #define C_008DFC_SDST 0xFF80FFFF
2704 #define V_008DFC_SQ_SGPR 0x00
2705 #define V_008DFC_SQ_VCC_LO 0x6A
2706 #define V_008DFC_SQ_VCC_HI 0x6B
2707 #define V_008DFC_SQ_TBA_LO 0x6C
2708 #define V_008DFC_SQ_TBA_HI 0x6D
2709 #define V_008DFC_SQ_TMA_LO 0x6E
2710 #define V_008DFC_SQ_TMA_HI 0x6F
2711 #define V_008DFC_SQ_TTMP0 0x70
2712 #define V_008DFC_SQ_TTMP1 0x71
2713 #define V_008DFC_SQ_TTMP2 0x72
2714 #define V_008DFC_SQ_TTMP3 0x73
2715 #define V_008DFC_SQ_TTMP4 0x74
2716 #define V_008DFC_SQ_TTMP5 0x75
2717 #define V_008DFC_SQ_TTMP6 0x76
2718 #define V_008DFC_SQ_TTMP7 0x77
2719 #define V_008DFC_SQ_TTMP8 0x78
2720 #define V_008DFC_SQ_TTMP9 0x79
2721 #define V_008DFC_SQ_TTMP10 0x7A
2722 #define V_008DFC_SQ_TTMP11 0x7B
2723 #define V_008DFC_SQ_M0 0x7C
2724 #define V_008DFC_SQ_EXEC_LO 0x7E
2725 #define V_008DFC_SQ_EXEC_HI 0x7F
2726 #define S_008DFC_OP(x) (((x) & 0x7F) << 23)
2727 #define G_008DFC_OP(x) (((x) >> 23) & 0x7F)
2728 #define C_008DFC_OP 0xC07FFFFF
2729 #define V_008DFC_SQ_S_ADD_U32 0x00
2730 #define V_008DFC_SQ_S_SUB_U32 0x01
2731 #define V_008DFC_SQ_S_ADD_I32 0x02
2732 #define V_008DFC_SQ_S_SUB_I32 0x03
2733 #define V_008DFC_SQ_S_ADDC_U32 0x04
2734 #define V_008DFC_SQ_S_SUBB_U32 0x05
2735 #define V_008DFC_SQ_S_MIN_I32 0x06
2736 #define V_008DFC_SQ_S_MIN_U32 0x07
2737 #define V_008DFC_SQ_S_MAX_I32 0x08
2738 #define V_008DFC_SQ_S_MAX_U32 0x09
2739 #define V_008DFC_SQ_S_CSELECT_B32 0x0A
2740 #define V_008DFC_SQ_S_CSELECT_B64 0x0B
2741 #define V_008DFC_SQ_S_AND_B32 0x0E
2742 #define V_008DFC_SQ_S_AND_B64 0x0F
2743 #define V_008DFC_SQ_S_OR_B32 0x10
2744 #define V_008DFC_SQ_S_OR_B64 0x11
2745 #define V_008DFC_SQ_S_XOR_B32 0x12
2746 #define V_008DFC_SQ_S_XOR_B64 0x13
2747 #define V_008DFC_SQ_S_ANDN2_B32 0x14
2748 #define V_008DFC_SQ_S_ANDN2_B64 0x15
2749 #define V_008DFC_SQ_S_ORN2_B32 0x16
2750 #define V_008DFC_SQ_S_ORN2_B64 0x17
2751 #define V_008DFC_SQ_S_NAND_B32 0x18
2752 #define V_008DFC_SQ_S_NAND_B64 0x19
2753 #define V_008DFC_SQ_S_NOR_B32 0x1A
2754 #define V_008DFC_SQ_S_NOR_B64 0x1B
2755 #define V_008DFC_SQ_S_XNOR_B32 0x1C
2756 #define V_008DFC_SQ_S_XNOR_B64 0x1D
2757 #define V_008DFC_SQ_S_LSHL_B32 0x1E
2758 #define V_008DFC_SQ_S_LSHL_B64 0x1F
2759 #define V_008DFC_SQ_S_LSHR_B32 0x20
2760 #define V_008DFC_SQ_S_LSHR_B64 0x21
2761 #define V_008DFC_SQ_S_ASHR_I32 0x22
2762 #define V_008DFC_SQ_S_ASHR_I64 0x23
2763 #define V_008DFC_SQ_S_BFM_B32 0x24
2764 #define V_008DFC_SQ_S_BFM_B64 0x25
2765 #define V_008DFC_SQ_S_MUL_I32 0x26
2766 #define V_008DFC_SQ_S_BFE_U32 0x27
2767 #define V_008DFC_SQ_S_BFE_I32 0x28
2768 #define V_008DFC_SQ_S_BFE_U64 0x29
2769 #define V_008DFC_SQ_S_BFE_I64 0x2A
2770 #define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B
2771 #define V_008DFC_SQ_S_ABSDIFF_I32 0x2C
2772 #define S_008DFC_ENCODING(x) (((x) & 0x03) << 30)
2773 #define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03)
2774 #define C_008DFC_ENCODING 0x3FFFFFFF
2775 #define V_008DFC_SQ_ENC_SOP2_FIELD 0x02
2776 #define R_008DFC_SQ_SOPK 0x008DFC
2777 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0)
2778 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF)
2779 #define C_008DFC_SIMM16 0xFFFF0000
2780 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
2781 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
2782 #define C_008DFC_SDST 0xFF80FFFF
2783 #define V_008DFC_SQ_SGPR 0x00
2784 #define V_008DFC_SQ_VCC_LO 0x6A
2785 #define V_008DFC_SQ_VCC_HI 0x6B
2786 #define V_008DFC_SQ_TBA_LO 0x6C
2787 #define V_008DFC_SQ_TBA_HI 0x6D
2788 #define V_008DFC_SQ_TMA_LO 0x6E
2789 #define V_008DFC_SQ_TMA_HI 0x6F
2790 #define V_008DFC_SQ_TTMP0 0x70
2791 #define V_008DFC_SQ_TTMP1 0x71
2792 #define V_008DFC_SQ_TTMP2 0x72
2793 #define V_008DFC_SQ_TTMP3 0x73
2794 #define V_008DFC_SQ_TTMP4 0x74
2795 #define V_008DFC_SQ_TTMP5 0x75
2796 #define V_008DFC_SQ_TTMP6 0x76
2797 #define V_008DFC_SQ_TTMP7 0x77
2798 #define V_008DFC_SQ_TTMP8 0x78
2799 #define V_008DFC_SQ_TTMP9 0x79
2800 #define V_008DFC_SQ_TTMP10 0x7A
2801 #define V_008DFC_SQ_TTMP11 0x7B
2802 #define V_008DFC_SQ_M0 0x7C
2803 #define V_008DFC_SQ_EXEC_LO 0x7E
2804 #define V_008DFC_SQ_EXEC_HI 0x7F
2805 #define S_008DFC_OP(x) (((x) & 0x1F) << 23)
2806 #define G_008DFC_OP(x) (((x) >> 23) & 0x1F)
2807 #define C_008DFC_OP 0xF07FFFFF
2808 #define V_008DFC_SQ_S_MOVK_I32 0x00
2809 #define V_008DFC_SQ_S_CMOVK_I32 0x02
2810 #define V_008DFC_SQ_S_CMPK_EQ_I32 0x03
2811 #define V_008DFC_SQ_S_CMPK_LG_I32 0x04
2812 #define V_008DFC_SQ_S_CMPK_GT_I32 0x05
2813 #define V_008DFC_SQ_S_CMPK_GE_I32 0x06
2814 #define V_008DFC_SQ_S_CMPK_LT_I32 0x07
2815 #define V_008DFC_SQ_S_CMPK_LE_I32 0x08
2816 #define V_008DFC_SQ_S_CMPK_EQ_U32 0x09
2817 #define V_008DFC_SQ_S_CMPK_LG_U32 0x0A
2818 #define V_008DFC_SQ_S_CMPK_GT_U32 0x0B
2819 #define V_008DFC_SQ_S_CMPK_GE_U32 0x0C
2820 #define V_008DFC_SQ_S_CMPK_LT_U32 0x0D
2821 #define V_008DFC_SQ_S_CMPK_LE_U32 0x0E
2822 #define V_008DFC_SQ_S_ADDK_I32 0x0F
2823 #define V_008DFC_SQ_S_MULK_I32 0x10
2824 #define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11
2825 #define V_008DFC_SQ_S_GETREG_B32 0x12
2826 #define V_008DFC_SQ_S_SETREG_B32 0x13
2827 #define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14
2828 #define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15
2829 #define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28)
2830 #define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F)
2831 #define C_008DFC_ENCODING 0x0FFFFFFF
2832 #define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B
2833 #define R_008DFC_SQ_VOP3_0 0x008DFC
2834 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0)
2835 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF)
2836 #define C_008DFC_VDST 0xFFFFFF00
2837 #define V_008DFC_SQ_VGPR 0x00
2838 #define S_008DFC_ABS(x) (((x) & 0x07) << 8)
2839 #define G_008DFC_ABS(x) (((x) >> 8) & 0x07)
2840 #define C_008DFC_ABS 0xFFFFF8FF
2841 #define S_008DFC_CLAMP(x) (((x) & 0x1) << 11)
2842 #define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1)
2843 #define C_008DFC_CLAMP 0xFFFFF7FF
2844 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17)
2845 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF)
2846 #define C_008DFC_OP 0xFC01FFFF
2847 #define V_008DFC_SQ_V_OPC_OFFSET 0x00
2848 #define V_008DFC_SQ_V_OP2_OFFSET 0x100
2849 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140
2850 #define V_008DFC_SQ_V_MAD_F32 0x141
2851 #define V_008DFC_SQ_V_MAD_I32_I24 0x142
2852 #define V_008DFC_SQ_V_MAD_U32_U24 0x143
2853 #define V_008DFC_SQ_V_CUBEID_F32 0x144
2854 #define V_008DFC_SQ_V_CUBESC_F32 0x145
2855 #define V_008DFC_SQ_V_CUBETC_F32 0x146
2856 #define V_008DFC_SQ_V_CUBEMA_F32 0x147
2857 #define V_008DFC_SQ_V_BFE_U32 0x148
2858 #define V_008DFC_SQ_V_BFE_I32 0x149
2859 #define V_008DFC_SQ_V_BFI_B32 0x14A
2860 #define V_008DFC_SQ_V_FMA_F32 0x14B
2861 #define V_008DFC_SQ_V_FMA_F64 0x14C
2862 #define V_008DFC_SQ_V_LERP_U8 0x14D
2863 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E
2864 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F
2865 #define V_008DFC_SQ_V_MULLIT_F32 0x150
2866 #define V_008DFC_SQ_V_MIN3_F32 0x151
2867 #define V_008DFC_SQ_V_MIN3_I32 0x152
2868 #define V_008DFC_SQ_V_MIN3_U32 0x153
2869 #define V_008DFC_SQ_V_MAX3_F32 0x154
2870 #define V_008DFC_SQ_V_MAX3_I32 0x155
2871 #define V_008DFC_SQ_V_MAX3_U32 0x156
2872 #define V_008DFC_SQ_V_MED3_F32 0x157
2873 #define V_008DFC_SQ_V_MED3_I32 0x158
2874 #define V_008DFC_SQ_V_MED3_U32 0x159
2875 #define V_008DFC_SQ_V_SAD_U8 0x15A
2876 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B
2877 #define V_008DFC_SQ_V_SAD_U16 0x15C
2878 #define V_008DFC_SQ_V_SAD_U32 0x15D
2879 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E
2880 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F
2881 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160
2882 #define V_008DFC_SQ_V_LSHL_B64 0x161
2883 #define V_008DFC_SQ_V_LSHR_B64 0x162
2884 #define V_008DFC_SQ_V_ASHR_I64 0x163
2885 #define V_008DFC_SQ_V_ADD_F64 0x164
2886 #define V_008DFC_SQ_V_MUL_F64 0x165
2887 #define V_008DFC_SQ_V_MIN_F64 0x166
2888 #define V_008DFC_SQ_V_MAX_F64 0x167
2889 #define V_008DFC_SQ_V_LDEXP_F64 0x168
2890 #define V_008DFC_SQ_V_MUL_LO_U32 0x169
2891 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A
2892 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B
2893 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C
2894 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D
2895 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E
2896 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F
2897 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170
2898 #define V_008DFC_SQ_V_MSAD_U8 0x171
2899 #define V_008DFC_SQ_V_QSAD_U8 0x172
2900 #define V_008DFC_SQ_V_MQSAD_U8 0x173
2901 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174
2902 #define V_008DFC_SQ_V_OP1_OFFSET 0x180
2903 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2904 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2905 #define C_008DFC_ENCODING 0x03FFFFFF
2906 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34
2907 #define R_008DFC_SQ_VOP2 0x008DFC
2908 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
2909 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
2910 #define C_008DFC_SRC0 0xFFFFFE00
2911 #define V_008DFC_SQ_SGPR 0x00
2912 #define V_008DFC_SQ_VCC_LO 0x6A
2913 #define V_008DFC_SQ_VCC_HI 0x6B
2914 #define V_008DFC_SQ_TBA_LO 0x6C
2915 #define V_008DFC_SQ_TBA_HI 0x6D
2916 #define V_008DFC_SQ_TMA_LO 0x6E
2917 #define V_008DFC_SQ_TMA_HI 0x6F
2918 #define V_008DFC_SQ_TTMP0 0x70
2919 #define V_008DFC_SQ_TTMP1 0x71
2920 #define V_008DFC_SQ_TTMP2 0x72
2921 #define V_008DFC_SQ_TTMP3 0x73
2922 #define V_008DFC_SQ_TTMP4 0x74
2923 #define V_008DFC_SQ_TTMP5 0x75
2924 #define V_008DFC_SQ_TTMP6 0x76
2925 #define V_008DFC_SQ_TTMP7 0x77
2926 #define V_008DFC_SQ_TTMP8 0x78
2927 #define V_008DFC_SQ_TTMP9 0x79
2928 #define V_008DFC_SQ_TTMP10 0x7A
2929 #define V_008DFC_SQ_TTMP11 0x7B
2930 #define V_008DFC_SQ_M0 0x7C
2931 #define V_008DFC_SQ_EXEC_LO 0x7E
2932 #define V_008DFC_SQ_EXEC_HI 0x7F
2933 #define V_008DFC_SQ_SRC_0 0x80
2934 #define V_008DFC_SQ_SRC_1_INT 0x81
2935 #define V_008DFC_SQ_SRC_2_INT 0x82
2936 #define V_008DFC_SQ_SRC_3_INT 0x83
2937 #define V_008DFC_SQ_SRC_4_INT 0x84
2938 #define V_008DFC_SQ_SRC_5_INT 0x85
2939 #define V_008DFC_SQ_SRC_6_INT 0x86
2940 #define V_008DFC_SQ_SRC_7_INT 0x87
2941 #define V_008DFC_SQ_SRC_8_INT 0x88
2942 #define V_008DFC_SQ_SRC_9_INT 0x89
2943 #define V_008DFC_SQ_SRC_10_INT 0x8A
2944 #define V_008DFC_SQ_SRC_11_INT 0x8B
2945 #define V_008DFC_SQ_SRC_12_INT 0x8C
2946 #define V_008DFC_SQ_SRC_13_INT 0x8D
2947 #define V_008DFC_SQ_SRC_14_INT 0x8E
2948 #define V_008DFC_SQ_SRC_15_INT 0x8F
2949 #define V_008DFC_SQ_SRC_16_INT 0x90
2950 #define V_008DFC_SQ_SRC_17_INT 0x91
2951 #define V_008DFC_SQ_SRC_18_INT 0x92
2952 #define V_008DFC_SQ_SRC_19_INT 0x93
2953 #define V_008DFC_SQ_SRC_20_INT 0x94
2954 #define V_008DFC_SQ_SRC_21_INT 0x95
2955 #define V_008DFC_SQ_SRC_22_INT 0x96
2956 #define V_008DFC_SQ_SRC_23_INT 0x97
2957 #define V_008DFC_SQ_SRC_24_INT 0x98
2958 #define V_008DFC_SQ_SRC_25_INT 0x99
2959 #define V_008DFC_SQ_SRC_26_INT 0x9A
2960 #define V_008DFC_SQ_SRC_27_INT 0x9B
2961 #define V_008DFC_SQ_SRC_28_INT 0x9C
2962 #define V_008DFC_SQ_SRC_29_INT 0x9D
2963 #define V_008DFC_SQ_SRC_30_INT 0x9E
2964 #define V_008DFC_SQ_SRC_31_INT 0x9F
2965 #define V_008DFC_SQ_SRC_32_INT 0xA0
2966 #define V_008DFC_SQ_SRC_33_INT 0xA1
2967 #define V_008DFC_SQ_SRC_34_INT 0xA2
2968 #define V_008DFC_SQ_SRC_35_INT 0xA3
2969 #define V_008DFC_SQ_SRC_36_INT 0xA4
2970 #define V_008DFC_SQ_SRC_37_INT 0xA5
2971 #define V_008DFC_SQ_SRC_38_INT 0xA6
2972 #define V_008DFC_SQ_SRC_39_INT 0xA7
2973 #define V_008DFC_SQ_SRC_40_INT 0xA8
2974 #define V_008DFC_SQ_SRC_41_INT 0xA9
2975 #define V_008DFC_SQ_SRC_42_INT 0xAA
2976 #define V_008DFC_SQ_SRC_43_INT 0xAB
2977 #define V_008DFC_SQ_SRC_44_INT 0xAC
2978 #define V_008DFC_SQ_SRC_45_INT 0xAD
2979 #define V_008DFC_SQ_SRC_46_INT 0xAE
2980 #define V_008DFC_SQ_SRC_47_INT 0xAF
2981 #define V_008DFC_SQ_SRC_48_INT 0xB0
2982 #define V_008DFC_SQ_SRC_49_INT 0xB1
2983 #define V_008DFC_SQ_SRC_50_INT 0xB2
2984 #define V_008DFC_SQ_SRC_51_INT 0xB3
2985 #define V_008DFC_SQ_SRC_52_INT 0xB4
2986 #define V_008DFC_SQ_SRC_53_INT 0xB5
2987 #define V_008DFC_SQ_SRC_54_INT 0xB6
2988 #define V_008DFC_SQ_SRC_55_INT 0xB7
2989 #define V_008DFC_SQ_SRC_56_INT 0xB8
2990 #define V_008DFC_SQ_SRC_57_INT 0xB9
2991 #define V_008DFC_SQ_SRC_58_INT 0xBA
2992 #define V_008DFC_SQ_SRC_59_INT 0xBB
2993 #define V_008DFC_SQ_SRC_60_INT 0xBC
2994 #define V_008DFC_SQ_SRC_61_INT 0xBD
2995 #define V_008DFC_SQ_SRC_62_INT 0xBE
2996 #define V_008DFC_SQ_SRC_63_INT 0xBF
2997 #define V_008DFC_SQ_SRC_64_INT 0xC0
2998 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2999 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3000 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3001 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3002 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3003 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3004 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3005 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3006 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3007 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3008 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3009 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3010 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3011 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3012 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3013 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3014 #define V_008DFC_SQ_SRC_0_5 0xF0
3015 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3016 #define V_008DFC_SQ_SRC_1 0xF2
3017 #define V_008DFC_SQ_SRC_M_1 0xF3
3018 #define V_008DFC_SQ_SRC_2 0xF4
3019 #define V_008DFC_SQ_SRC_M_2 0xF5
3020 #define V_008DFC_SQ_SRC_4 0xF6
3021 #define V_008DFC_SQ_SRC_M_4 0xF7
3022 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3023 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3024 #define V_008DFC_SQ_SRC_SCC 0xFD
3025 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3026 #define V_008DFC_SQ_SRC_VGPR 0x100
3027 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9)
3028 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF)
3029 #define C_008DFC_VSRC1 0xFFFE01FF
3030 #define V_008DFC_SQ_VGPR 0x00
3031 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17)
3032 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF)
3033 #define C_008DFC_VDST 0xFE01FFFF
3034 #define V_008DFC_SQ_VGPR 0x00
3035 #define S_008DFC_OP(x) (((x) & 0x3F) << 25)
3036 #define G_008DFC_OP(x) (((x) >> 25) & 0x3F)
3037 #define C_008DFC_OP 0x81FFFFFF
3038 #define V_008DFC_SQ_V_CNDMASK_B32 0x00
3039 #define V_008DFC_SQ_V_READLANE_B32 0x01
3040 #define V_008DFC_SQ_V_WRITELANE_B32 0x02
3041 #define V_008DFC_SQ_V_ADD_F32 0x03
3042 #define V_008DFC_SQ_V_SUB_F32 0x04
3043 #define V_008DFC_SQ_V_SUBREV_F32 0x05
3044 #define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06
3045 #define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07
3046 #define V_008DFC_SQ_V_MUL_F32 0x08
3047 #define V_008DFC_SQ_V_MUL_I32_I24 0x09
3048 #define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A
3049 #define V_008DFC_SQ_V_MUL_U32_U24 0x0B
3050 #define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C
3051 #define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D
3052 #define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E
3053 #define V_008DFC_SQ_V_MIN_F32 0x0F
3054 #define V_008DFC_SQ_V_MAX_F32 0x10
3055 #define V_008DFC_SQ_V_MIN_I32 0x11
3056 #define V_008DFC_SQ_V_MAX_I32 0x12
3057 #define V_008DFC_SQ_V_MIN_U32 0x13
3058 #define V_008DFC_SQ_V_MAX_U32 0x14
3059 #define V_008DFC_SQ_V_LSHR_B32 0x15
3060 #define V_008DFC_SQ_V_LSHRREV_B32 0x16
3061 #define V_008DFC_SQ_V_ASHR_I32 0x17
3062 #define V_008DFC_SQ_V_ASHRREV_I32 0x18
3063 #define V_008DFC_SQ_V_LSHL_B32 0x19
3064 #define V_008DFC_SQ_V_LSHLREV_B32 0x1A
3065 #define V_008DFC_SQ_V_AND_B32 0x1B
3066 #define V_008DFC_SQ_V_OR_B32 0x1C
3067 #define V_008DFC_SQ_V_XOR_B32 0x1D
3068 #define V_008DFC_SQ_V_BFM_B32 0x1E
3069 #define V_008DFC_SQ_V_MAC_F32 0x1F
3070 #define V_008DFC_SQ_V_MADMK_F32 0x20
3071 #define V_008DFC_SQ_V_MADAK_F32 0x21
3072 #define V_008DFC_SQ_V_BCNT_U32_B32 0x22
3073 #define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23
3074 #define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24
3075 #define V_008DFC_SQ_V_ADD_I32 0x25
3076 #define V_008DFC_SQ_V_SUB_I32 0x26
3077 #define V_008DFC_SQ_V_SUBREV_I32 0x27
3078 #define V_008DFC_SQ_V_ADDC_U32 0x28
3079 #define V_008DFC_SQ_V_SUBB_U32 0x29
3080 #define V_008DFC_SQ_V_SUBBREV_U32 0x2A
3081 #define V_008DFC_SQ_V_LDEXP_F32 0x2B
3082 #define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C
3083 #define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D
3084 #define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E
3085 #define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F
3086 #define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30
3087 #define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31
3088 #define S_008DFC_ENCODING(x) (((x) & 0x1) << 31)
3089 #define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1)
3090 #define C_008DFC_ENCODING 0x7FFFFFFF
3091 #define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC
3092 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0)
3093 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF)
3094 #define C_008DFC_VDST 0xFFFFFF00
3095 #define V_008DFC_SQ_VGPR 0x00
3096 #define S_008DFC_SDST(x) (((x) & 0x7F) << 8)
3097 #define G_008DFC_SDST(x) (((x) >> 8) & 0x7F)
3098 #define C_008DFC_SDST 0xFFFF80FF
3099 #define V_008DFC_SQ_SGPR 0x00
3100 #define V_008DFC_SQ_VCC_LO 0x6A
3101 #define V_008DFC_SQ_VCC_HI 0x6B
3102 #define V_008DFC_SQ_TBA_LO 0x6C
3103 #define V_008DFC_SQ_TBA_HI 0x6D
3104 #define V_008DFC_SQ_TMA_LO 0x6E
3105 #define V_008DFC_SQ_TMA_HI 0x6F
3106 #define V_008DFC_SQ_TTMP0 0x70
3107 #define V_008DFC_SQ_TTMP1 0x71
3108 #define V_008DFC_SQ_TTMP2 0x72
3109 #define V_008DFC_SQ_TTMP3 0x73
3110 #define V_008DFC_SQ_TTMP4 0x74
3111 #define V_008DFC_SQ_TTMP5 0x75
3112 #define V_008DFC_SQ_TTMP6 0x76
3113 #define V_008DFC_SQ_TTMP7 0x77
3114 #define V_008DFC_SQ_TTMP8 0x78
3115 #define V_008DFC_SQ_TTMP9 0x79
3116 #define V_008DFC_SQ_TTMP10 0x7A
3117 #define V_008DFC_SQ_TTMP11 0x7B
3118 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17)
3119 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF)
3120 #define C_008DFC_OP 0xFC01FFFF
3121 #define V_008DFC_SQ_V_OPC_OFFSET 0x00
3122 #define V_008DFC_SQ_V_OP2_OFFSET 0x100
3123 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140
3124 #define V_008DFC_SQ_V_MAD_F32 0x141
3125 #define V_008DFC_SQ_V_MAD_I32_I24 0x142
3126 #define V_008DFC_SQ_V_MAD_U32_U24 0x143
3127 #define V_008DFC_SQ_V_CUBEID_F32 0x144
3128 #define V_008DFC_SQ_V_CUBESC_F32 0x145
3129 #define V_008DFC_SQ_V_CUBETC_F32 0x146
3130 #define V_008DFC_SQ_V_CUBEMA_F32 0x147
3131 #define V_008DFC_SQ_V_BFE_U32 0x148
3132 #define V_008DFC_SQ_V_BFE_I32 0x149
3133 #define V_008DFC_SQ_V_BFI_B32 0x14A
3134 #define V_008DFC_SQ_V_FMA_F32 0x14B
3135 #define V_008DFC_SQ_V_FMA_F64 0x14C
3136 #define V_008DFC_SQ_V_LERP_U8 0x14D
3137 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E
3138 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F
3139 #define V_008DFC_SQ_V_MULLIT_F32 0x150
3140 #define V_008DFC_SQ_V_MIN3_F32 0x151
3141 #define V_008DFC_SQ_V_MIN3_I32 0x152
3142 #define V_008DFC_SQ_V_MIN3_U32 0x153
3143 #define V_008DFC_SQ_V_MAX3_F32 0x154
3144 #define V_008DFC_SQ_V_MAX3_I32 0x155
3145 #define V_008DFC_SQ_V_MAX3_U32 0x156
3146 #define V_008DFC_SQ_V_MED3_F32 0x157
3147 #define V_008DFC_SQ_V_MED3_I32 0x158
3148 #define V_008DFC_SQ_V_MED3_U32 0x159
3149 #define V_008DFC_SQ_V_SAD_U8 0x15A
3150 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B
3151 #define V_008DFC_SQ_V_SAD_U16 0x15C
3152 #define V_008DFC_SQ_V_SAD_U32 0x15D
3153 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E
3154 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F
3155 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160
3156 #define V_008DFC_SQ_V_LSHL_B64 0x161
3157 #define V_008DFC_SQ_V_LSHR_B64 0x162
3158 #define V_008DFC_SQ_V_ASHR_I64 0x163
3159 #define V_008DFC_SQ_V_ADD_F64 0x164
3160 #define V_008DFC_SQ_V_MUL_F64 0x165
3161 #define V_008DFC_SQ_V_MIN_F64 0x166
3162 #define V_008DFC_SQ_V_MAX_F64 0x167
3163 #define V_008DFC_SQ_V_LDEXP_F64 0x168
3164 #define V_008DFC_SQ_V_MUL_LO_U32 0x169
3165 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A
3166 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B
3167 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C
3168 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D
3169 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E
3170 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F
3171 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170
3172 #define V_008DFC_SQ_V_MSAD_U8 0x171
3173 #define V_008DFC_SQ_V_QSAD_U8 0x172
3174 #define V_008DFC_SQ_V_MQSAD_U8 0x173
3175 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174
3176 #define V_008DFC_SQ_V_OP1_OFFSET 0x180
3177 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3178 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3179 #define C_008DFC_ENCODING 0x03FFFFFF
3180 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34
3181 #define R_008DFC_SQ_MUBUF_0 0x008DFC
3182 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0)
3183 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF)
3184 #define C_008DFC_OFFSET 0xFFFFF000
3185 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12)
3186 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1)
3187 #define C_008DFC_OFFEN 0xFFFFEFFF
3188 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13)
3189 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1)
3190 #define C_008DFC_IDXEN 0xFFFFDFFF
3191 #define S_008DFC_GLC(x) (((x) & 0x1) << 14)
3192 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1)
3193 #define C_008DFC_GLC 0xFFFFBFFF
3194 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15)
3195 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1)
3196 #define C_008DFC_ADDR64 0xFFFF7FFF
3197 #define S_008DFC_LDS(x) (((x) & 0x1) << 16)
3198 #define G_008DFC_LDS(x) (((x) >> 16) & 0x1)
3199 #define C_008DFC_LDS 0xFFFEFFFF
3200 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
3201 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
3202 #define C_008DFC_OP 0xFE03FFFF
3203 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00
3204 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01
3205 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02
3206 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03
3207 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04
3208 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05
3209 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06
3210 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07
3211 #define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08
3212 #define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09
3213 #define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A
3214 #define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B
3215 #define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C
3216 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D
3217 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E
3218 #define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18
3219 #define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A
3220 #define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C
3221 #define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D
3222 #define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E
3223 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30
3224 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31
3225 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32
3226 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33
3227 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34
3228 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35
3229 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36
3230 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37
3231 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38
3232 #define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39
3233 #define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A
3234 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B
3235 #define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C
3236 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D
3237 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E
3238 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F
3239 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40
3240 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50
3241 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51
3242 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52
3243 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53
3244 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54
3245 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55
3246 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56
3247 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57
3248 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58
3249 #define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59
3250 #define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A
3251 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B
3252 #define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C
3253 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D
3254 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E
3255 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F
3256 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60
3257 #define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70
3258 #define V_008DFC_SQ_BUFFER_WBINVL1 0x71
3259 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3260 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3261 #define C_008DFC_ENCODING 0x03FFFFFF
3262 #define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38
3264 #define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00
3265 #define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04
3266 #define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0)
3267 #define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF)
3268 #define C_008F04_BASE_ADDRESS_HI 0xFFFF0000
3269 #define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16)
3270 #define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF)
3271 #define C_008F04_STRIDE 0xC000FFFF
3272 #define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30)
3273 #define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1)
3274 #define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF
3275 #define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31)
3276 #define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1)
3277 #define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF
3278 #define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08
3279 #define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C
3280 #define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0)
3281 #define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07)
3282 #define C_008F0C_DST_SEL_X 0xFFFFFFF8
3283 #define V_008F0C_SQ_SEL_0 0x00
3284 #define V_008F0C_SQ_SEL_1 0x01
3285 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3286 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3287 #define V_008F0C_SQ_SEL_X 0x04
3288 #define V_008F0C_SQ_SEL_Y 0x05
3289 #define V_008F0C_SQ_SEL_Z 0x06
3290 #define V_008F0C_SQ_SEL_W 0x07
3291 #define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3)
3292 #define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07)
3293 #define C_008F0C_DST_SEL_Y 0xFFFFFFC7
3294 #define V_008F0C_SQ_SEL_0 0x00
3295 #define V_008F0C_SQ_SEL_1 0x01
3296 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3297 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3298 #define V_008F0C_SQ_SEL_X 0x04
3299 #define V_008F0C_SQ_SEL_Y 0x05
3300 #define V_008F0C_SQ_SEL_Z 0x06
3301 #define V_008F0C_SQ_SEL_W 0x07
3302 #define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6)
3303 #define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07)
3304 #define C_008F0C_DST_SEL_Z 0xFFFFFE3F
3305 #define V_008F0C_SQ_SEL_0 0x00
3306 #define V_008F0C_SQ_SEL_1 0x01
3307 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3308 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3309 #define V_008F0C_SQ_SEL_X 0x04
3310 #define V_008F0C_SQ_SEL_Y 0x05
3311 #define V_008F0C_SQ_SEL_Z 0x06
3312 #define V_008F0C_SQ_SEL_W 0x07
3313 #define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9)
3314 #define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07)
3315 #define C_008F0C_DST_SEL_W 0xFFFFF1FF
3316 #define V_008F0C_SQ_SEL_0 0x00
3317 #define V_008F0C_SQ_SEL_1 0x01
3318 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3319 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3320 #define V_008F0C_SQ_SEL_X 0x04
3321 #define V_008F0C_SQ_SEL_Y 0x05
3322 #define V_008F0C_SQ_SEL_Z 0x06
3323 #define V_008F0C_SQ_SEL_W 0x07
3324 #define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12)
3325 #define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07)
3326 #define C_008F0C_NUM_FORMAT 0xFFFF8FFF
3327 #define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00
3328 #define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01
3329 #define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02
3330 #define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03
3331 #define V_008F0C_BUF_NUM_FORMAT_UINT 0x04
3332 #define V_008F0C_BUF_NUM_FORMAT_SINT 0x05
3333 #define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06
3334 #define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07
3335 #define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15)
3336 #define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F)
3337 #define C_008F0C_DATA_FORMAT 0xFFF87FFF
3338 #define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00
3339 #define V_008F0C_BUF_DATA_FORMAT_8 0x01
3340 #define V_008F0C_BUF_DATA_FORMAT_16 0x02
3341 #define V_008F0C_BUF_DATA_FORMAT_8_8 0x03
3342 #define V_008F0C_BUF_DATA_FORMAT_32 0x04
3343 #define V_008F0C_BUF_DATA_FORMAT_16_16 0x05
3344 #define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06
3345 #define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07
3346 #define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08
3347 #define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09
3348 #define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A
3349 #define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B
3350 #define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C
3351 #define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D
3352 #define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E
3353 #define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F
3354 #define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19)
3355 #define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03)
3356 #define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF
3357 #define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21)
3358 #define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03)
3359 #define C_008F0C_INDEX_STRIDE 0xFF9FFFFF
3360 #define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23)
3361 #define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1)
3362 #define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF
3363 #define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25)
3364 #define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1)
3365 #define C_008F0C_HASH_ENABLE 0xFDFFFFFF
3366 #define S_008F0C_HEAP(x) (((x) & 0x1) << 26)
3367 #define G_008F0C_HEAP(x) (((x) >> 26) & 0x1)
3368 #define C_008F0C_HEAP 0xFBFFFFFF
3369 #define S_008F0C_TYPE(x) (((x) & 0x03) << 30)
3370 #define G_008F0C_TYPE(x) (((x) >> 30) & 0x03)
3371 #define C_008F0C_TYPE 0x3FFFFFFF
3372 #define V_008F0C_SQ_RSRC_BUF 0x00
3373 #define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01
3374 #define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02
3375 #define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03
3376 #define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10
3377 #define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14
3378 #define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0)
3379 #define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF)
3380 #define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00
3381 #define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8)
3382 #define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF)
3383 #define C_008F14_MIN_LOD 0xFFF000FF
3384 #define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20)
3385 #define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F)
3386 #define C_008F14_DATA_FORMAT 0xFC0FFFFF
3387 #define V_008F14_IMG_DATA_FORMAT_INVALID 0x00
3388 #define V_008F14_IMG_DATA_FORMAT_8 0x01
3389 #define V_008F14_IMG_DATA_FORMAT_16 0x02
3390 #define V_008F14_IMG_DATA_FORMAT_8_8 0x03
3391 #define V_008F14_IMG_DATA_FORMAT_32 0x04
3392 #define V_008F14_IMG_DATA_FORMAT_16_16 0x05
3393 #define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06
3394 #define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07
3395 #define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08
3396 #define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09
3397 #define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A
3398 #define V_008F14_IMG_DATA_FORMAT_32_32 0x0B
3399 #define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C
3400 #define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D
3401 #define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E
3402 #define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F
3403 #define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10
3404 #define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11
3405 #define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12
3406 #define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13
3407 #define V_008F14_IMG_DATA_FORMAT_8_24 0x14
3408 #define V_008F14_IMG_DATA_FORMAT_24_8 0x15
3409 #define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16
3410 #define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17
3411 #define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18
3412 #define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19
3413 #define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A
3414 #define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B
3415 #define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C
3416 #define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D
3417 #define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E
3418 #define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F
3419 #define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20
3420 #define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21
3421 #define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22
3422 #define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A
3423 #define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B
3424 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C
3425 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D
3426 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E
3427 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F
3428 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30
3429 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31
3430 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32
3431 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33
3432 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34
3433 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35
3434 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36
3435 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37
3436 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38
3437 #define V_008F14_IMG_DATA_FORMAT_4_4 0x39
3438 #define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A
3439 #define V_008F14_IMG_DATA_FORMAT_1 0x3B
3440 #define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C
3441 #define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D
3442 #define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E
3443 #define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F
3444 #define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26)
3445 #define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F)
3446 #define C_008F14_NUM_FORMAT 0xC3FFFFFF
3447 #define V_008F14_IMG_NUM_FORMAT_UNORM 0x00
3448 #define V_008F14_IMG_NUM_FORMAT_SNORM 0x01
3449 #define V_008F14_IMG_NUM_FORMAT_USCALED 0x02
3450 #define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03
3451 #define V_008F14_IMG_NUM_FORMAT_UINT 0x04
3452 #define V_008F14_IMG_NUM_FORMAT_SINT 0x05
3453 #define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06
3454 #define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07
3455 #define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08
3456 #define V_008F14_IMG_NUM_FORMAT_SRGB 0x09
3457 #define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A
3458 #define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B
3459 #define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C
3460 #define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D
3461 #define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E
3462 #define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F
3463 #define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18
3464 #define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0)
3465 #define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF)
3466 #define C_008F18_WIDTH 0xFFFFC000
3467 #define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14)
3468 #define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF)
3469 #define C_008F18_HEIGHT 0xF0003FFF
3470 #define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28)
3471 #define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07)
3472 #define C_008F18_PERF_MOD 0x8FFFFFFF
3473 #define S_008F18_INTERLACED(x) (((x) & 0x1) << 31)
3474 #define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1)
3475 #define C_008F18_INTERLACED 0x7FFFFFFF
3476 #define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C
3477 #define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0)
3478 #define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07)
3479 #define C_008F1C_DST_SEL_X 0xFFFFFFF8
3480 #define V_008F1C_SQ_SEL_0 0x00
3481 #define V_008F1C_SQ_SEL_1 0x01
3482 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
3483 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
3484 #define V_008F1C_SQ_SEL_X 0x04
3485 #define V_008F1C_SQ_SEL_Y 0x05
3486 #define V_008F1C_SQ_SEL_Z 0x06
3487 #define V_008F1C_SQ_SEL_W 0x07
3488 #define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3)
3489 #define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07)
3490 #define C_008F1C_DST_SEL_Y 0xFFFFFFC7
3491 #define V_008F1C_SQ_SEL_0 0x00
3492 #define V_008F1C_SQ_SEL_1 0x01
3493 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
3494 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
3495 #define V_008F1C_SQ_SEL_X 0x04
3496 #define V_008F1C_SQ_SEL_Y 0x05
3497 #define V_008F1C_SQ_SEL_Z 0x06
3498 #define V_008F1C_SQ_SEL_W 0x07
3499 #define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6)
3500 #define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07)
3501 #define C_008F1C_DST_SEL_Z 0xFFFFFE3F
3502 #define V_008F1C_SQ_SEL_0 0x00
3503 #define V_008F1C_SQ_SEL_1 0x01
3504 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
3505 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
3506 #define V_008F1C_SQ_SEL_X 0x04
3507 #define V_008F1C_SQ_SEL_Y 0x05
3508 #define V_008F1C_SQ_SEL_Z 0x06
3509 #define V_008F1C_SQ_SEL_W 0x07
3510 #define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9)
3511 #define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07)
3512 #define C_008F1C_DST_SEL_W 0xFFFFF1FF
3513 #define V_008F1C_SQ_SEL_0 0x00
3514 #define V_008F1C_SQ_SEL_1 0x01
3515 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
3516 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
3517 #define V_008F1C_SQ_SEL_X 0x04
3518 #define V_008F1C_SQ_SEL_Y 0x05
3519 #define V_008F1C_SQ_SEL_Z 0x06
3520 #define V_008F1C_SQ_SEL_W 0x07
3521 #define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12)
3522 #define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F)
3523 #define C_008F1C_BASE_LEVEL 0xFFFF0FFF
3524 #define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16)
3525 #define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F)
3526 #define C_008F1C_LAST_LEVEL 0xFFF0FFFF
3527 #define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20)
3528 #define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F)
3529 #define C_008F1C_TILING_INDEX 0xFE0FFFFF
3530 #define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25)
3531 #define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1)
3532 #define C_008F1C_POW2_PAD 0xFDFFFFFF
3533 #define S_008F1C_TYPE(x) (((x) & 0x0F) << 28)
3534 #define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F)
3535 #define C_008F1C_TYPE 0x0FFFFFFF
3536 #define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00
3537 #define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01
3538 #define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02
3539 #define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03
3540 #define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04
3541 #define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05
3542 #define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06
3543 #define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07
3544 #define V_008F1C_SQ_RSRC_IMG_1D 0x08
3545 #define V_008F1C_SQ_RSRC_IMG_2D 0x09
3546 #define V_008F1C_SQ_RSRC_IMG_3D 0x0A
3547 #define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B
3548 #define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C
3549 #define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D
3550 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E
3551 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F
3552 #define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20
3553 #define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0)
3554 #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF)
3555 #define C_008F20_DEPTH 0xFFFFE000
3556 #define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13)
3557 #define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF)
3558 #define C_008F20_PITCH 0xF8001FFF
3559 #define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24
3560 #define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0)
3561 #define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF)
3562 #define C_008F24_BASE_ARRAY 0xFFFFE000
3563 #define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13)
3564 #define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF)
3565 #define C_008F24_LAST_ARRAY 0xFC001FFF
3566 #define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28
3567 #define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0)
3568 #define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF)
3569 #define C_008F28_MIN_LOD_WARN 0xFFFFF000
3570 #define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C
3571 #define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30
3572 #define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0)
3573 #define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07)
3574 #define C_008F30_CLAMP_X 0xFFFFFFF8
3575 #define V_008F30_SQ_TEX_WRAP 0x00
3576 #define V_008F30_SQ_TEX_MIRROR 0x01
3577 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
3578 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
3579 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
3580 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
3581 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
3582 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
3583 #define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3)
3584 #define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07)
3585 #define C_008F30_CLAMP_Y 0xFFFFFFC7
3586 #define V_008F30_SQ_TEX_WRAP 0x00
3587 #define V_008F30_SQ_TEX_MIRROR 0x01
3588 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
3589 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
3590 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
3591 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
3592 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
3593 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
3594 #define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6)
3595 #define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07)
3596 #define C_008F30_CLAMP_Z 0xFFFFFE3F
3597 #define V_008F30_SQ_TEX_WRAP 0x00
3598 #define V_008F30_SQ_TEX_MIRROR 0x01
3599 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
3600 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
3601 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
3602 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
3603 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
3604 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
3605 #define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12)
3606 #define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07)
3607 #define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF
3608 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00
3609 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01
3610 #define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02
3611 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03
3612 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04
3613 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05
3614 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06
3615 #define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07
3616 #define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15)
3617 #define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1)
3618 #define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF
3619 #define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19)
3620 #define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1)
3621 #define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF
3622 #define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20)
3623 #define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1)
3624 #define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF
3625 #define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27)
3626 #define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1)
3627 #define C_008F30_TRUNC_COORD 0xF7FFFFFF
3628 #define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28)
3629 #define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1)
3630 #define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF
3631 #define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29)
3632 #define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03)
3633 #define C_008F30_FILTER_MODE 0x9FFFFFFF
3634 #define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34
3635 #define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0)
3636 #define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF)
3637 #define C_008F34_MIN_LOD 0xFFFFF000
3638 #define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12)
3639 #define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF)
3640 #define C_008F34_MAX_LOD 0xFF000FFF
3641 #define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24)
3642 #define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F)
3643 #define C_008F34_PERF_MIP 0xF0FFFFFF
3644 #define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28)
3645 #define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F)
3646 #define C_008F34_PERF_Z 0x0FFFFFFF
3647 #define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38
3648 #define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0)
3649 #define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF)
3650 #define C_008F38_LOD_BIAS 0xFFFFC000
3651 #define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14)
3652 #define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F)
3653 #define C_008F38_LOD_BIAS_SEC 0xFFF03FFF
3654 #define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20)
3655 #define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03)
3656 #define C_008F38_XY_MAG_FILTER 0xFFCFFFFF
3657 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00
3658 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01
3659 #define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22)
3660 #define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03)
3661 #define C_008F38_XY_MIN_FILTER 0xFF3FFFFF
3662 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00
3663 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01
3664 #define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24)
3665 #define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03)
3666 #define C_008F38_Z_FILTER 0xFCFFFFFF
3667 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00
3668 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01
3669 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02
3670 #define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26)
3671 #define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03)
3672 #define C_008F38_MIP_FILTER 0xF3FFFFFF
3673 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00
3674 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01
3675 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02
3676 #define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28)
3677 #define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1)
3678 #define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF
3679 #define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29)
3680 #define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1)
3681 #define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF
3682 #define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30)
3683 #define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1)
3684 #define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF
3685 #define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C
3686 #define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0)
3687 #define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF)
3688 #define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000
3689 #define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30)
3690 #define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03)
3691 #define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF
3692 #define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00
3693 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01
3694 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02
3695 #define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03
3696 #define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC
3697 #define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0)
3698 #define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F)
3699 #define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0
3700 #define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4)
3701 #define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F)
3702 #define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F
3703 #define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8)
3704 #define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F)
3705 #define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF
3706 #define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12)
3707 #define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F)
3708 #define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF
3709 #define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16)
3710 #define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F)
3711 #define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF
3712 #define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0
3713 #define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0)
3714 #define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF)
3715 #define C_0090E0_PS_CU_EN 0xFFFF0000
3716 #define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16)
3717 #define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF)
3718 #define C_0090E0_VS_CU_EN 0x0000FFFF
3719 #define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4
3720 #define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0)
3721 #define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF)
3722 #define C_0090E4_GS_CU_EN 0xFFFF0000
3723 #define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16)
3724 #define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF)
3725 #define C_0090E4_ES_CU_EN 0x0000FFFF
3726 #define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8
3727 #define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0)
3728 #define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF)
3729 #define C_0090E8_LSHS_CU_EN 0xFFFF0000
3730 #define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC
3731 #define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
3732 #define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
3733 #define C_0090EC_MAX_WAVE_ID 0xFFFFF000
3734 #define R_0090F0_SPI_ARB_PRIORITY 0x0090F0
3735 #define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0)
3736 #define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07)
3737 #define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8
3738 #define V_0090F0_X_R0 0x00
3739 #define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3)
3740 #define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07)
3741 #define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7
3742 #define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6)
3743 #define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07)
3744 #define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F
3745 #define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4
3746 #define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0)
3747 #define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF)
3748 #define C_0090F4_TS0_DURATION 0xFFFF0000
3749 #define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16)
3750 #define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF)
3751 #define C_0090F4_TS1_DURATION 0x0000FFFF
3752 #define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8
3753 #define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0)
3754 #define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF)
3755 #define C_0090F8_TS2_DURATION 0xFFFF0000
3756 #define R_009100_SPI_CONFIG_CNTL 0x009100
3757 #define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0)
3758 #define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF)
3759 #define C_009100_GPR_WRITE_PRIORITY 0xFFE00000
3760 #define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21)
3761 #define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07)
3762 #define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF
3763 #define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24)
3764 #define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1)
3765 #define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF
3766 #define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25)
3767 #define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1)
3768 #define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF
3769 #define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26)
3770 #define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1)
3771 #define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF
3772 #define R_00913C_SPI_CONFIG_CNTL_1 0x00913C
3773 #define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0)
3774 #define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F)
3775 #define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0
3776 #define V_00913C_X_DELAY_14_CLKS 0x00
3777 #define V_00913C_X_DELAY_16_CLKS 0x01
3778 #define V_00913C_X_DELAY_18_CLKS 0x02
3779 #define V_00913C_X_DELAY_20_CLKS 0x03
3780 #define V_00913C_X_DELAY_22_CLKS 0x04
3781 #define V_00913C_X_DELAY_24_CLKS 0x05
3782 #define V_00913C_X_DELAY_26_CLKS 0x06
3783 #define V_00913C_X_DELAY_28_CLKS 0x07
3784 #define V_00913C_X_DELAY_30_CLKS 0x08
3785 #define V_00913C_X_DELAY_32_CLKS 0x09
3786 #define V_00913C_X_DELAY_34_CLKS 0x0A
3787 #define V_00913C_X_DELAY_4_CLKS 0x0B
3788 #define V_00913C_X_DELAY_6_CLKS 0x0C
3789 #define V_00913C_X_DELAY_8_CLKS 0x0D
3790 #define V_00913C_X_DELAY_10_CLKS 0x0E
3791 #define V_00913C_X_DELAY_12_CLKS 0x0F
3792 #define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4)
3793 #define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1)
3794 #define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF
3795 #define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6)
3796 #define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1)
3797 #define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF
3798 #define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7)
3799 #define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1)
3800 #define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F
3801 #define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16)
3802 #define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF)
3803 #define C_00913C_PC_LIMIT_SIZE 0x0000FFFF
3804 #define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C
3805 #define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0)
3806 #define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F)
3807 #define C_00936C_TYPE_A 0xFFFFFFF0
3808 #define S_00936C_VGPR_A(x) (((x) & 0x07) << 4)
3809 #define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07)
3810 #define C_00936C_VGPR_A 0xFFFFFF8F
3811 #define S_00936C_SGPR_A(x) (((x) & 0x07) << 7)
3812 #define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07)
3813 #define C_00936C_SGPR_A 0xFFFFFC7F
3814 #define S_00936C_LDS_A(x) (((x) & 0x07) << 10)
3815 #define G_00936C_LDS_A(x) (((x) >> 10) & 0x07)
3816 #define C_00936C_LDS_A 0xFFFFE3FF
3817 #define S_00936C_WAVES_A(x) (((x) & 0x03) << 13)
3818 #define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03)
3819 #define C_00936C_WAVES_A 0xFFFF9FFF
3820 #define S_00936C_EN_A(x) (((x) & 0x1) << 15)
3821 #define G_00936C_EN_A(x) (((x) >> 15) & 0x1)
3822 #define C_00936C_EN_A 0xFFFF7FFF
3823 #define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16)
3824 #define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F)
3825 #define C_00936C_TYPE_B 0xFFF0FFFF
3826 #define S_00936C_VGPR_B(x) (((x) & 0x07) << 20)
3827 #define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07)
3828 #define C_00936C_VGPR_B 0xFF8FFFFF
3829 #define S_00936C_SGPR_B(x) (((x) & 0x07) << 23)
3830 #define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07)
3831 #define C_00936C_SGPR_B 0xFC7FFFFF
3832 #define S_00936C_LDS_B(x) (((x) & 0x07) << 26)
3833 #define G_00936C_LDS_B(x) (((x) >> 26) & 0x07)
3834 #define C_00936C_LDS_B 0xE3FFFFFF
3835 #define S_00936C_WAVES_B(x) (((x) & 0x03) << 29)
3836 #define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03)
3837 #define C_00936C_WAVES_B 0x9FFFFFFF
3838 #define S_00936C_EN_B(x) (((x) & 0x1) << 31)
3839 #define G_00936C_EN_B(x) (((x) >> 31) & 0x1)
3840 #define C_00936C_EN_B 0x7FFFFFFF
3841 #define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C
3842 #define R_009858_DB_SUBTILE_CONTROL 0x009858
3843 #define S_009858_MSAA1_X(x) (((x) & 0x03) << 0)
3844 #define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03)
3845 #define C_009858_MSAA1_X 0xFFFFFFFC
3846 #define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2)
3847 #define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03)
3848 #define C_009858_MSAA1_Y 0xFFFFFFF3
3849 #define S_009858_MSAA2_X(x) (((x) & 0x03) << 4)
3850 #define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03)
3851 #define C_009858_MSAA2_X 0xFFFFFFCF
3852 #define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6)
3853 #define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03)
3854 #define C_009858_MSAA2_Y 0xFFFFFF3F
3855 #define S_009858_MSAA4_X(x) (((x) & 0x03) << 8)
3856 #define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03)
3857 #define C_009858_MSAA4_X 0xFFFFFCFF
3858 #define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10)
3859 #define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03)
3860 #define C_009858_MSAA4_Y 0xFFFFF3FF
3861 #define S_009858_MSAA8_X(x) (((x) & 0x03) << 12)
3862 #define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03)
3863 #define C_009858_MSAA8_X 0xFFFFCFFF
3864 #define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14)
3865 #define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03)
3866 #define C_009858_MSAA8_Y 0xFFFF3FFF
3867 #define S_009858_MSAA16_X(x) (((x) & 0x03) << 16)
3868 #define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03)
3869 #define C_009858_MSAA16_X 0xFFFCFFFF
3870 #define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18)
3871 #define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03)
3872 #define C_009858_MSAA16_Y 0xFFF3FFFF
3873 #define R_009910_GB_TILE_MODE0 0x009910
3874 #define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0)
3875 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
3876 #define C_009910_MICRO_TILE_MODE 0xFFFFFFFC
3877 #define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00
3878 #define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01
3879 #define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02
3880 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
3881 #define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2)
3882 #define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F)
3883 #define C_009910_ARRAY_MODE 0xFFFFFFC3
3884 #define V_009910_ARRAY_LINEAR_GENERAL 0x00
3885 #define V_009910_ARRAY_LINEAR_ALIGNED 0x01
3886 #define V_009910_ARRAY_1D_TILED_THIN1 0x02
3887 #define V_009910_ARRAY_1D_TILED_THICK 0x03
3888 #define V_009910_ARRAY_2D_TILED_THIN1 0x04
3889 #define V_009910_ARRAY_2D_TILED_THICK 0x07
3890 #define V_009910_ARRAY_2D_TILED_XTHICK 0x08
3891 #define V_009910_ARRAY_3D_TILED_THIN1 0x0C
3892 #define V_009910_ARRAY_3D_TILED_THICK 0x0D
3893 #define V_009910_ARRAY_3D_TILED_XTHICK 0x0E
3894 #define V_009910_ARRAY_POWER_SAVE 0x0F
3895 #define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6)
3896 #define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F)
3897 #define C_009910_PIPE_CONFIG 0xFFFFF83F
3898 #define V_009910_ADDR_SURF_P2 0x00
3899 #define V_009910_ADDR_SURF_P2_RESERVED0 0x01
3900 #define V_009910_ADDR_SURF_P2_RESERVED1 0x02
3901 #define V_009910_ADDR_SURF_P2_RESERVED2 0x03
3902 #define V_009910_X_ADDR_SURF_P4_8X16 0x04
3903 #define V_009910_X_ADDR_SURF_P4_16X16 0x05
3904 #define V_009910_X_ADDR_SURF_P4_16X32 0x06
3905 #define V_009910_X_ADDR_SURF_P4_32X32 0x07
3906 #define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08
3907 #define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09
3908 #define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A
3909 #define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B
3910 #define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C
3911 #define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D
3912 #define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E
3913 #define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11)
3914 #define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07)
3915 #define C_009910_TILE_SPLIT 0xFFFFC7FF
3916 #define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00
3917 #define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01
3918 #define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02
3919 #define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03
3920 #define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04
3921 #define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05
3922 #define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06
3923 #define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14)
3924 #define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03)
3925 #define C_009910_BANK_WIDTH 0xFFFF3FFF
3926 #define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00
3927 #define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01
3928 #define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02
3929 #define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03
3930 #define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16)
3931 #define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03)
3932 #define C_009910_BANK_HEIGHT 0xFFFCFFFF
3933 #define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00
3934 #define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01
3935 #define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02
3936 #define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03
3937 #define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18)
3938 #define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03)
3939 #define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF
3940 #define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00
3941 #define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01
3942 #define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02
3943 #define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03
3944 #define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20)
3945 #define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03)
3946 #define C_009910_NUM_BANKS 0xFFCFFFFF
3947 #define V_009910_ADDR_SURF_2_BANK 0x00
3948 #define V_009910_ADDR_SURF_4_BANK 0x01
3949 #define V_009910_ADDR_SURF_8_BANK 0x02
3950 #define V_009910_ADDR_SURF_16_BANK 0x03
3951 #define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020
3952 #define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024
3953 #define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0)
3954 #define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF)
3955 #define C_00B024_MEM_BASE 0xFFFFFF00
3956 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
3957 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
3958 #define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F)
3959 #define C_00B028_VGPRS 0xFFFFFFC0
3960 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
3961 #define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F)
3962 #define C_00B028_SGPRS 0xFFFFFC3F
3963 #define S_00B028_PRIORITY(x) (((x) & 0x03) << 10)
3964 #define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03)
3965 #define C_00B028_PRIORITY 0xFFFFF3FF
3966 #define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12)
3967 #define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
3968 #define C_00B028_FLOAT_MODE 0xFFF00FFF
3969 #define S_00B028_PRIV(x) (((x) & 0x1) << 20)
3970 #define G_00B028_PRIV(x) (((x) >> 20) & 0x1)
3971 #define C_00B028_PRIV 0xFFEFFFFF
3972 #define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21)
3973 #define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1)
3974 #define C_00B028_DX10_CLAMP 0xFFDFFFFF
3975 #define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22)
3976 #define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1)
3977 #define C_00B028_DEBUG_MODE 0xFFBFFFFF
3978 #define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23)
3979 #define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1)
3980 #define C_00B028_IEEE_MODE 0xFF7FFFFF
3981 #define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24)
3982 #define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1)
3983 #define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF
3984 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
3985 #define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0)
3986 #define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
3987 #define C_00B02C_SCRATCH_EN 0xFFFFFFFE
3988 #define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1)
3989 #define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F)
3990 #define C_00B02C_USER_SGPR 0xFFFFFFC1
3991 #define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7)
3992 #define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1)
3993 #define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F
3994 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
3995 #define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF)
3996 #define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF
3997 #define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16)
3998 #define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F)
3999 #define C_00B02C_EXCP_EN 0xFF80FFFF
4000 #define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030
4001 #define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034
4002 #define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038
4003 #define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C
4004 #define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040
4005 #define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044
4006 #define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048
4007 #define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C
4008 #define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050
4009 #define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054
4010 #define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058
4011 #define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C
4012 #define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060
4013 #define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064
4014 #define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068
4015 #define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C
4016 #define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120
4017 #define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124
4018 #define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0)
4019 #define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF)
4020 #define C_00B124_MEM_BASE 0xFFFFFF00
4021 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
4022 #define S_00B128_VGPRS(x) (((x) & 0x3F) << 0)
4023 #define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F)
4024 #define C_00B128_VGPRS 0xFFFFFFC0
4025 #define S_00B128_SGPRS(x) (((x) & 0x0F) << 6)
4026 #define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F)
4027 #define C_00B128_SGPRS 0xFFFFFC3F
4028 #define S_00B128_PRIORITY(x) (((x) & 0x03) << 10)
4029 #define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03)
4030 #define C_00B128_PRIORITY 0xFFFFF3FF
4031 #define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4032 #define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4033 #define C_00B128_FLOAT_MODE 0xFFF00FFF
4034 #define S_00B128_PRIV(x) (((x) & 0x1) << 20)
4035 #define G_00B128_PRIV(x) (((x) >> 20) & 0x1)
4036 #define C_00B128_PRIV 0xFFEFFFFF
4037 #define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21)
4038 #define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4039 #define C_00B128_DX10_CLAMP 0xFFDFFFFF
4040 #define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22)
4041 #define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4042 #define C_00B128_DEBUG_MODE 0xFFBFFFFF
4043 #define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23)
4044 #define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1)
4045 #define C_00B128_IEEE_MODE 0xFF7FFFFF
4046 #define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
4047 #define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
4048 #define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF
4049 #define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26)
4050 #define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1)
4051 #define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF
4052 #define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C
4053 #define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4054 #define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4055 #define C_00B12C_SCRATCH_EN 0xFFFFFFFE
4056 #define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1)
4057 #define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4058 #define C_00B12C_USER_SGPR 0xFFFFFFC1
4059 #define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7)
4060 #define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
4061 #define C_00B12C_OC_LDS_EN 0xFFFFFF7F
4062 #define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8)
4063 #define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1)
4064 #define C_00B12C_SO_BASE0_EN 0xFFFFFEFF
4065 #define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9)
4066 #define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1)
4067 #define C_00B12C_SO_BASE1_EN 0xFFFFFDFF
4068 #define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10)
4069 #define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1)
4070 #define C_00B12C_SO_BASE2_EN 0xFFFFFBFF
4071 #define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11)
4072 #define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1)
4073 #define C_00B12C_SO_BASE3_EN 0xFFFFF7FF
4074 #define S_00B12C_SO_EN(x) (((x) & 0x1) << 12)
4075 #define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1)
4076 #define C_00B12C_SO_EN 0xFFFFEFFF
4077 #define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13)
4078 #define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F)
4079 #define C_00B12C_EXCP_EN 0xFFF01FFF
4080 #define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130
4081 #define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134
4082 #define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138
4083 #define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C
4084 #define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140
4085 #define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144
4086 #define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148
4087 #define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C
4088 #define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150
4089 #define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154
4090 #define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158
4091 #define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C
4092 #define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160
4093 #define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164
4094 #define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168
4095 #define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C
4096 #define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220
4097 #define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224
4098 #define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0)
4099 #define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF)
4100 #define C_00B224_MEM_BASE 0xFFFFFF00
4101 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
4102 #define S_00B228_VGPRS(x) (((x) & 0x3F) << 0)
4103 #define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F)
4104 #define C_00B228_VGPRS 0xFFFFFFC0
4105 #define S_00B228_SGPRS(x) (((x) & 0x0F) << 6)
4106 #define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F)
4107 #define C_00B228_SGPRS 0xFFFFFC3F
4108 #define S_00B228_PRIORITY(x) (((x) & 0x03) << 10)
4109 #define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03)
4110 #define C_00B228_PRIORITY 0xFFFFF3FF
4111 #define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4112 #define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4113 #define C_00B228_FLOAT_MODE 0xFFF00FFF
4114 #define S_00B228_PRIV(x) (((x) & 0x1) << 20)
4115 #define G_00B228_PRIV(x) (((x) >> 20) & 0x1)
4116 #define C_00B228_PRIV 0xFFEFFFFF
4117 #define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21)
4118 #define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4119 #define C_00B228_DX10_CLAMP 0xFFDFFFFF
4120 #define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22)
4121 #define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4122 #define C_00B228_DEBUG_MODE 0xFFBFFFFF
4123 #define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23)
4124 #define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1)
4125 #define C_00B228_IEEE_MODE 0xFF7FFFFF
4126 #define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24)
4127 #define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1)
4128 #define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF
4129 #define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C
4130 #define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4131 #define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4132 #define C_00B22C_SCRATCH_EN 0xFFFFFFFE
4133 #define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1)
4134 #define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4135 #define C_00B22C_USER_SGPR 0xFFFFFFC1
4136 #define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7)
4137 #define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F)
4138 #define C_00B22C_EXCP_EN 0xFFFFC07F
4139 #define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230
4140 #define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320
4141 #define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324
4142 #define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0)
4143 #define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF)
4144 #define C_00B324_MEM_BASE 0xFFFFFF00
4145 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
4146 #define S_00B328_VGPRS(x) (((x) & 0x3F) << 0)
4147 #define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F)
4148 #define C_00B328_VGPRS 0xFFFFFFC0
4149 #define S_00B328_SGPRS(x) (((x) & 0x0F) << 6)
4150 #define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F)
4151 #define C_00B328_SGPRS 0xFFFFFC3F
4152 #define S_00B328_PRIORITY(x) (((x) & 0x03) << 10)
4153 #define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03)
4154 #define C_00B328_PRIORITY 0xFFFFF3FF
4155 #define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4156 #define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4157 #define C_00B328_FLOAT_MODE 0xFFF00FFF
4158 #define S_00B328_PRIV(x) (((x) & 0x1) << 20)
4159 #define G_00B328_PRIV(x) (((x) >> 20) & 0x1)
4160 #define C_00B328_PRIV 0xFFEFFFFF
4161 #define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21)
4162 #define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4163 #define C_00B328_DX10_CLAMP 0xFFDFFFFF
4164 #define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22)
4165 #define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4166 #define C_00B328_DEBUG_MODE 0xFFBFFFFF
4167 #define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23)
4168 #define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1)
4169 #define C_00B328_IEEE_MODE 0xFF7FFFFF
4170 #define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
4171 #define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
4172 #define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF
4173 #define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26)
4174 #define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1)
4175 #define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF
4176 #define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C
4177 #define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4178 #define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4179 #define C_00B32C_SCRATCH_EN 0xFFFFFFFE
4180 #define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1)
4181 #define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4182 #define C_00B32C_USER_SGPR 0xFFFFFFC1
4183 #define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7)
4184 #define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
4185 #define C_00B32C_OC_LDS_EN 0xFFFFFF7F
4186 #define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8)
4187 #define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F)
4188 #define C_00B32C_EXCP_EN 0xFFFF80FF
4189 #define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330
4190 #define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420
4191 #define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424
4192 #define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0)
4193 #define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF)
4194 #define C_00B424_MEM_BASE 0xFFFFFF00
4195 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
4196 #define S_00B428_VGPRS(x) (((x) & 0x3F) << 0)
4197 #define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F)
4198 #define C_00B428_VGPRS 0xFFFFFFC0
4199 #define S_00B428_SGPRS(x) (((x) & 0x0F) << 6)
4200 #define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F)
4201 #define C_00B428_SGPRS 0xFFFFFC3F
4202 #define S_00B428_PRIORITY(x) (((x) & 0x03) << 10)
4203 #define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03)
4204 #define C_00B428_PRIORITY 0xFFFFF3FF
4205 #define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4206 #define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4207 #define C_00B428_FLOAT_MODE 0xFFF00FFF
4208 #define S_00B428_PRIV(x) (((x) & 0x1) << 20)
4209 #define G_00B428_PRIV(x) (((x) >> 20) & 0x1)
4210 #define C_00B428_PRIV 0xFFEFFFFF
4211 #define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21)
4212 #define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4213 #define C_00B428_DX10_CLAMP 0xFFDFFFFF
4214 #define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22)
4215 #define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4216 #define C_00B428_DEBUG_MODE 0xFFBFFFFF
4217 #define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23)
4218 #define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1)
4219 #define C_00B428_IEEE_MODE 0xFF7FFFFF
4220 #define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C
4221 #define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4222 #define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4223 #define C_00B42C_SCRATCH_EN 0xFFFFFFFE
4224 #define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1)
4225 #define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4226 #define C_00B42C_USER_SGPR 0xFFFFFFC1
4227 #define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7)
4228 #define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
4229 #define C_00B42C_OC_LDS_EN 0xFFFFFF7F
4230 #define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8)
4231 #define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1)
4232 #define C_00B42C_TG_SIZE_EN 0xFFFFFEFF
4233 #define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9)
4234 #define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F)
4235 #define C_00B42C_EXCP_EN 0xFFFF01FF
4236 #define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430
4237 #define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520
4238 #define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524
4239 #define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0)
4240 #define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF)
4241 #define C_00B524_MEM_BASE 0xFFFFFF00
4242 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
4243 #define S_00B528_VGPRS(x) (((x) & 0x3F) << 0)
4244 #define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F)
4245 #define C_00B528_VGPRS 0xFFFFFFC0
4246 #define S_00B528_SGPRS(x) (((x) & 0x0F) << 6)
4247 #define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F)
4248 #define C_00B528_SGPRS 0xFFFFFC3F
4249 #define S_00B528_PRIORITY(x) (((x) & 0x03) << 10)
4250 #define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03)
4251 #define C_00B528_PRIORITY 0xFFFFF3FF
4252 #define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4253 #define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4254 #define C_00B528_FLOAT_MODE 0xFFF00FFF
4255 #define S_00B528_PRIV(x) (((x) & 0x1) << 20)
4256 #define G_00B528_PRIV(x) (((x) >> 20) & 0x1)
4257 #define C_00B528_PRIV 0xFFEFFFFF
4258 #define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21)
4259 #define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4260 #define C_00B528_DX10_CLAMP 0xFFDFFFFF
4261 #define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22)
4262 #define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4263 #define C_00B528_DEBUG_MODE 0xFFBFFFFF
4264 #define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23)
4265 #define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1)
4266 #define C_00B528_IEEE_MODE 0xFF7FFFFF
4267 #define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
4268 #define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
4269 #define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF
4270 #define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C
4271 #define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4272 #define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4273 #define C_00B52C_SCRATCH_EN 0xFFFFFFFE
4274 #define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1)
4275 #define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4276 #define C_00B52C_USER_SGPR 0xFFFFFFC1
4277 #define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7)
4278 #define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF)
4279 #define C_00B52C_LDS_SIZE 0xFFFF007F
4280 #define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16)
4281 #define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F)
4282 #define C_00B52C_EXCP_EN 0xFF80FFFF
4283 #define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530
4284 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
4285 #define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0)
4286 #define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1)
4287 #define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE
4288 #define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1)
4289 #define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1)
4290 #define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD
4291 #define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2)
4292 #define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1)
4293 #define C_00B800_FORCE_START_AT_000 0xFFFFFFFB
4294 #define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3)
4295 #define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1)
4296 #define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7
4297 #define R_00B804_COMPUTE_DIM_X 0x00B804
4298 #define R_00B808_COMPUTE_DIM_Y 0x00B808
4299 #define R_00B80C_COMPUTE_DIM_Z 0x00B80C
4300 #define R_00B810_COMPUTE_START_X 0x00B810
4301 #define R_00B814_COMPUTE_START_Y 0x00B814
4302 #define R_00B818_COMPUTE_START_Z 0x00B818
4303 #define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C
4304 #define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
4305 #define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
4306 #define C_00B81C_NUM_THREAD_FULL 0xFFFF0000
4307 #define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
4308 #define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
4309 #define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF
4310 #define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820
4311 #define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
4312 #define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
4313 #define C_00B820_NUM_THREAD_FULL 0xFFFF0000
4314 #define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
4315 #define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
4316 #define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF
4317 #define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824
4318 #define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
4319 #define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
4320 #define C_00B824_NUM_THREAD_FULL 0xFFFF0000
4321 #define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
4322 #define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
4323 #define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF
4324 #define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C
4325 #define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
4326 #define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
4327 #define C_00B82C_MAX_WAVE_ID 0xFFFFF000
4328 #define R_00B830_COMPUTE_PGM_LO 0x00B830
4329 #define R_00B834_COMPUTE_PGM_HI 0x00B834
4330 #define S_00B834_DATA(x) (((x) & 0xFF) << 0)
4331 #define G_00B834_DATA(x) (((x) >> 0) & 0xFF)
4332 #define C_00B834_DATA 0xFFFFFF00
4333 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
4334 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
4335 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
4336 #define C_00B848_VGPRS 0xFFFFFFC0
4337 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
4338 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
4339 #define C_00B848_SGPRS 0xFFFFFC3F
4340 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
4341 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
4342 #define C_00B848_PRIORITY 0xFFFFF3FF
4343 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4344 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4345 #define C_00B848_FLOAT_MODE 0xFFF00FFF
4346 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
4347 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
4348 #define C_00B848_PRIV 0xFFEFFFFF
4349 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
4350 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4351 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
4352 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
4353 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4354 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
4355 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
4356 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
4357 #define C_00B848_IEEE_MODE 0xFF7FFFFF
4358 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
4359 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4360 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4361 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
4362 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
4363 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4364 #define C_00B84C_USER_SGPR 0xFFFFFFC1
4365 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
4366 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
4367 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
4368 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
4369 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
4370 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
4371 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
4372 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
4373 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
4374 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
4375 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
4376 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
4377 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
4378 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
4379 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
4380 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
4381 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
4382 #define C_00B84C_LDS_SIZE 0xFF007FFF
4383 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
4384 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
4385 #define C_00B84C_EXCP_EN 0x80FFFFFF
4386 #define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854
4387 #define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0)
4388 #define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F)
4389 #define C_00B854_WAVES_PER_SH 0xFFFFFFC0
4390 #define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12)
4391 #define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F)
4392 #define C_00B854_TG_PER_CU 0xFFFF0FFF
4393 #define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16)
4394 #define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F)
4395 #define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF
4396 #define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22)
4397 #define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1)
4398 #define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF
4399 #define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858
4400 #define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
4401 #define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
4402 #define C_00B858_SH0_CU_EN 0xFFFF0000
4403 #define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
4404 #define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
4405 #define C_00B858_SH1_CU_EN 0x0000FFFF
4406 #define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C
4407 #define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
4408 #define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
4409 #define C_00B85C_SH0_CU_EN 0xFFFF0000
4410 #define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
4411 #define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
4412 #define C_00B85C_SH1_CU_EN 0x0000FFFF
4413 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
4414 #define S_00B860_WAVES(x) (((x) & 0xFFF) << 0)
4415 #define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF)
4416 #define C_00B860_WAVES 0xFFFFF000
4417 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
4418 #define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF)
4419 #define C_00B860_WAVESIZE 0xFE000FFF
4420 #define R_00B900_COMPUTE_USER_DATA_0 0x00B900
4421 #define R_028000_DB_RENDER_CONTROL 0x028000
4422 #define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0)
4423 #define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1)
4424 #define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE
4425 #define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1)
4426 #define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1)
4427 #define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD
4428 #define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2)
4429 #define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1)
4430 #define C_028000_DEPTH_COPY 0xFFFFFFFB
4431 #define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3)
4432 #define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1)
4433 #define C_028000_STENCIL_COPY 0xFFFFFFF7
4434 #define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4)
4435 #define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1)
4436 #define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF
4437 #define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5)
4438 #define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1)
4439 #define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF
4440 #define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6)
4441 #define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1)
4442 #define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF
4443 #define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7)
4444 #define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1)
4445 #define C_028000_COPY_CENTROID 0xFFFFFF7F
4446 #define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8)
4447 #define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F)
4448 #define C_028000_COPY_SAMPLE 0xFFFFF0FF
4449 #define R_028004_DB_COUNT_CONTROL 0x028004
4450 #define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0)
4451 #define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1)
4452 #define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE
4453 #define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1)
4454 #define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1)
4455 #define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD
4456 #define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4)
4457 #define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07)
4458 #define C_028004_SAMPLE_RATE 0xFFFFFF8F
4459 #define R_028008_DB_DEPTH_VIEW 0x028008
4460 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
4461 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
4462 #define C_028008_SLICE_START 0xFFFFF800
4463 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
4464 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
4465 #define C_028008_SLICE_MAX 0xFF001FFF
4466 #define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24)
4467 #define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1)
4468 #define C_028008_Z_READ_ONLY 0xFEFFFFFF
4469 #define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25)
4470 #define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1)
4471 #define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF
4472 #define R_02800C_DB_RENDER_OVERRIDE 0x02800C
4473 #define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0)
4474 #define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03)
4475 #define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC
4476 #define V_02800C_FORCE_OFF 0x00
4477 #define V_02800C_FORCE_ENABLE 0x01
4478 #define V_02800C_FORCE_DISABLE 0x02
4479 #define V_02800C_FORCE_RESERVED 0x03
4480 #define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2)
4481 #define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03)
4482 #define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3
4483 #define V_02800C_FORCE_OFF 0x00
4484 #define V_02800C_FORCE_ENABLE 0x01
4485 #define V_02800C_FORCE_DISABLE 0x02
4486 #define V_02800C_FORCE_RESERVED 0x03
4487 #define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4)
4488 #define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03)
4489 #define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF
4490 #define V_02800C_FORCE_OFF 0x00
4491 #define V_02800C_FORCE_ENABLE 0x01
4492 #define V_02800C_FORCE_DISABLE 0x02
4493 #define V_02800C_FORCE_RESERVED 0x03
4494 #define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6)
4495 #define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1)
4496 #define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF
4497 #define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7)
4498 #define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1)
4499 #define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F
4500 #define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8)
4501 #define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1)
4502 #define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF
4503 #define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9)
4504 #define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1)
4505 #define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF
4506 #define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10)
4507 #define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1)
4508 #define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF
4509 #define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11)
4510 #define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1)
4511 #define C_02800C_FORCE_Z_READ 0xFFFFF7FF
4512 #define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12)
4513 #define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1)
4514 #define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF
4515 #define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13)
4516 #define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03)
4517 #define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF
4518 #define V_02800C_FORCE_OFF 0x00
4519 #define V_02800C_FORCE_ENABLE 0x01
4520 #define V_02800C_FORCE_DISABLE 0x02
4521 #define V_02800C_FORCE_RESERVED 0x03
4522 #define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15)
4523 #define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1)
4524 #define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF
4525 #define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16)
4526 #define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1)
4527 #define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF
4528 #define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17)
4529 #define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1)
4530 #define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF
4531 #define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18)
4532 #define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1)
4533 #define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF
4534 #define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19)
4535 #define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03)
4536 #define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF
4537 #define V_02800C_FORCE_SUMM_OFF 0x00
4538 #define V_02800C_FORCE_SUMM_MINZ 0x01
4539 #define V_02800C_FORCE_SUMM_MAXZ 0x02
4540 #define V_02800C_FORCE_SUMM_BOTH 0x03
4541 #define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21)
4542 #define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F)
4543 #define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF
4544 #define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26)
4545 #define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1)
4546 #define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF
4547 #define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27)
4548 #define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1)
4549 #define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF
4550 #define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28)
4551 #define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1)
4552 #define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF
4553 #define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29)
4554 #define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1)
4555 #define C_02800C_FORCE_Z_VALID 0xDFFFFFFF
4556 #define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30)
4557 #define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1)
4558 #define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF
4559 #define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31)
4560 #define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1)
4561 #define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF
4562 #define R_028010_DB_RENDER_OVERRIDE2 0x028010
4563 #define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0)
4564 #define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03)
4565 #define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC
4566 #define V_028010_PSLC_AUTO 0x00
4567 #define V_028010_PSLC_ON_HANG_ONLY 0x01
4568 #define V_028010_PSLC_ASAP 0x02
4569 #define V_028010_PSLC_COUNTDOWN 0x03
4570 #define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2)
4571 #define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07)
4572 #define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3
4573 #define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO(x) (((x) & 0x1) << 5)
4574 #define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO(x) (((x) >> 5) & 0x1)
4575 #define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO 0xFFFFFFDF
4576 #define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6)
4577 #define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1)
4578 #define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF
4579 #define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7)
4580 #define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1)
4581 #define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F
4582 #define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8)
4583 #define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1)
4584 #define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF
4585 #define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9)
4586 #define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1)
4587 #define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF
4588 #define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10)
4589 #define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1)
4590 #define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF
4591 #define R_028014_DB_HTILE_DATA_BASE 0x028014
4592 #define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020
4593 #define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024
4594 #define R_028028_DB_STENCIL_CLEAR 0x028028
4595 #define S_028028_CLEAR(x) (((x) & 0xFF) << 0)
4596 #define G_028028_CLEAR(x) (((x) >> 0) & 0xFF)
4597 #define C_028028_CLEAR 0xFFFFFF00
4598 #define R_02802C_DB_DEPTH_CLEAR 0x02802C
4599 #define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030
4600 #define S_028030_TL_X(x) (((x) & 0xFFFF) << 0)
4601 #define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF)
4602 #define C_028030_TL_X 0xFFFF0000
4603 #define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16)
4604 #define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF)
4605 #define C_028030_TL_Y 0x0000FFFF
4606 #define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034
4607 #define S_028034_BR_X(x) (((x) & 0xFFFF) << 0)
4608 #define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF)
4609 #define C_028034_BR_X 0xFFFF0000
4610 #define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16)
4611 #define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF)
4612 #define C_028034_BR_Y 0x0000FFFF
4613 #define R_02803C_DB_DEPTH_INFO 0x02803C
4614 #define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0)
4615 #define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F)
4616 #define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0
4617 #define R_028040_DB_Z_INFO 0x028040
4618 #define S_028040_FORMAT(x) (((x) & 0x03) << 0)
4619 #define G_028040_FORMAT(x) (((x) >> 0) & 0x03)
4620 #define C_028040_FORMAT 0xFFFFFFFC
4621 #define V_028040_Z_INVALID 0x00
4622 #define V_028040_Z_16 0x01
4623 #define V_028040_Z_24 0x02 /* deprecated */
4624 #define V_028040_Z_32_FLOAT 0x03
4625 #define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2)
4626 #define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03)
4627 #define C_028040_NUM_SAMPLES 0xFFFFFFF3
4628 #define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20)
4629 #define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07)
4630 #define C_028040_TILE_MODE_INDEX 0xFF8FFFFF
4631 #define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27)
4632 #define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1)
4633 #define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF
4634 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
4635 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
4636 #define C_028040_READ_SIZE 0xEFFFFFFF
4637 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
4638 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
4639 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
4640 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
4641 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
4642 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
4643 #define R_028044_DB_STENCIL_INFO 0x028044
4644 #define S_028044_FORMAT(x) (((x) & 0x1) << 0)
4645 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
4646 #define C_028044_FORMAT 0xFFFFFFFE
4647 #define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20)
4648 #define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07)
4649 #define C_028044_TILE_MODE_INDEX 0xFF8FFFFF
4650 #define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27)
4651 #define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1)
4652 #define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF
4653 #define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29)
4654 #define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1)
4655 #define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF
4656 #define R_028048_DB_Z_READ_BASE 0x028048
4657 #define R_02804C_DB_STENCIL_READ_BASE 0x02804C
4658 #define R_028050_DB_Z_WRITE_BASE 0x028050
4659 #define R_028054_DB_STENCIL_WRITE_BASE 0x028054
4660 #define R_028058_DB_DEPTH_SIZE 0x028058
4661 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
4662 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
4663 #define C_028058_PITCH_TILE_MAX 0xFFFFF800
4664 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
4665 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
4666 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
4667 #define R_02805C_DB_DEPTH_SLICE 0x02805C
4668 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
4669 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
4670 #define C_02805C_SLICE_TILE_MAX 0xFFC00000
4671 #define R_028080_TA_BC_BASE_ADDR 0x028080
4672 #define R_028200_PA_SC_WINDOW_OFFSET 0x028200
4673 #define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0)
4674 #define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF)
4675 #define C_028200_WINDOW_X_OFFSET 0xFFFF0000
4676 #define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16)
4677 #define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF)
4678 #define C_028200_WINDOW_Y_OFFSET 0x0000FFFF
4679 #define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204
4680 #define S_028204_TL_X(x) (((x) & 0x7FFF) << 0)
4681 #define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF)
4682 #define C_028204_TL_X 0xFFFF8000
4683 #define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16)
4684 #define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF)
4685 #define C_028204_TL_Y 0x8000FFFF
4686 #define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
4687 #define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
4688 #define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
4689 #define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208
4690 #define S_028208_BR_X(x) (((x) & 0x7FFF) << 0)
4691 #define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF)
4692 #define C_028208_BR_X 0xFFFF8000
4693 #define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16)
4694 #define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF)
4695 #define C_028208_BR_Y 0x8000FFFF
4696 #define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C
4697 #define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0)
4698 #define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF)
4699 #define C_02820C_CLIP_RULE 0xFFFF0000
4700 #define R_028210_PA_SC_CLIPRECT_0_TL 0x028210
4701 #define S_028210_TL_X(x) (((x) & 0x7FFF) << 0)
4702 #define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF)
4703 #define C_028210_TL_X 0xFFFF8000
4704 #define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16)
4705 #define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF)
4706 #define C_028210_TL_Y 0x8000FFFF
4707 #define R_028214_PA_SC_CLIPRECT_0_BR 0x028214
4708 #define S_028214_BR_X(x) (((x) & 0x7FFF) << 0)
4709 #define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF)
4710 #define C_028214_BR_X 0xFFFF8000
4711 #define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16)
4712 #define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF)
4713 #define C_028214_BR_Y 0x8000FFFF
4714 #define R_028218_PA_SC_CLIPRECT_1_TL 0x028218
4715 #define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C
4716 #define R_028220_PA_SC_CLIPRECT_2_TL 0x028220
4717 #define R_028224_PA_SC_CLIPRECT_2_BR 0x028224
4718 #define R_028228_PA_SC_CLIPRECT_3_TL 0x028228
4719 #define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C
4720 #define R_028230_PA_SC_EDGERULE 0x028230
4721 #define S_028230_ER_TRI(x) (((x) & 0x0F) << 0)
4722 #define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F)
4723 #define C_028230_ER_TRI 0xFFFFFFF0
4724 #define S_028230_ER_POINT(x) (((x) & 0x0F) << 4)
4725 #define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F)
4726 #define C_028230_ER_POINT 0xFFFFFF0F
4727 #define S_028230_ER_RECT(x) (((x) & 0x0F) << 8)
4728 #define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F)
4729 #define C_028230_ER_RECT 0xFFFFF0FF
4730 #define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12)
4731 #define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F)
4732 #define C_028230_ER_LINE_LR 0xFFFC0FFF
4733 #define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18)
4734 #define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F)
4735 #define C_028230_ER_LINE_RL 0xFF03FFFF
4736 #define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24)
4737 #define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F)
4738 #define C_028230_ER_LINE_TB 0xF0FFFFFF
4739 #define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28)
4740 #define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F)
4741 #define C_028230_ER_LINE_BT 0x0FFFFFFF
4742 #define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234
4743 #define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0)
4744 #define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF)
4745 #define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00
4746 #define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16)
4747 #define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF)
4748 #define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF
4749 #define R_028238_CB_TARGET_MASK 0x028238
4750 #define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0)
4751 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F)
4752 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
4753 #define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4)
4754 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F)
4755 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
4756 #define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8)
4757 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F)
4758 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
4759 #define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12)
4760 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F)
4761 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
4762 #define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16)
4763 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F)
4764 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
4765 #define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20)
4766 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F)
4767 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
4768 #define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24)
4769 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F)
4770 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
4771 #define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28)
4772 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F)
4773 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
4774 #define R_02823C_CB_SHADER_MASK 0x02823C
4775 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0)
4776 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F)
4777 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
4778 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4)
4779 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F)
4780 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
4781 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8)
4782 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F)
4783 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
4784 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12)
4785 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F)
4786 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
4787 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16)
4788 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F)
4789 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
4790 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20)
4791 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F)
4792 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
4793 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24)
4794 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F)
4795 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
4796 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28)
4797 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F)
4798 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
4799 #define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240
4800 #define S_028240_TL_X(x) (((x) & 0x7FFF) << 0)
4801 #define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF)
4802 #define C_028240_TL_X 0xFFFF8000
4803 #define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16)
4804 #define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF)
4805 #define C_028240_TL_Y 0x8000FFFF
4806 #define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
4807 #define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
4808 #define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
4809 #define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244
4810 #define S_028244_BR_X(x) (((x) & 0x7FFF) << 0)
4811 #define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF)
4812 #define C_028244_BR_X 0xFFFF8000
4813 #define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16)
4814 #define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF)
4815 #define C_028244_BR_Y 0x8000FFFF
4816 #define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
4817 #define S_028250_TL_X(x) (((x) & 0x7FFF) << 0)
4818 #define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF)
4819 #define C_028250_TL_X 0xFFFF8000
4820 #define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16)
4821 #define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF)
4822 #define C_028250_TL_Y 0x8000FFFF
4823 #define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
4824 #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
4825 #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
4826 #define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254
4827 #define S_028254_BR_X(x) (((x) & 0x7FFF) << 0)
4828 #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
4829 #define C_028254_BR_X 0xFFFF8000
4830 #define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16)
4831 #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
4832 #define C_028254_BR_Y 0x8000FFFF
4833 #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
4834 #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
4835 #define R_028350_PA_SC_RASTER_CONFIG 0x028350
4836 #define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0)
4837 #define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03)
4838 #define C_028350_RB_MAP_PKR0 0xFFFFFFFC
4839 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00
4840 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01
4841 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02
4842 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03
4843 #define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2)
4844 #define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03)
4845 #define C_028350_RB_MAP_PKR1 0xFFFFFFF3
4846 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00
4847 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01
4848 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02
4849 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03
4850 #define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4)
4851 #define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03)
4852 #define C_028350_RB_XSEL2 0xFFFFFFCF
4853 #define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00
4854 #define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01
4855 #define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02
4856 #define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03
4857 #define S_028350_RB_XSEL(x) (((x) & 0x1) << 6)
4858 #define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1)
4859 #define C_028350_RB_XSEL 0xFFFFFFBF
4860 #define S_028350_RB_YSEL(x) (((x) & 0x1) << 7)
4861 #define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1)
4862 #define C_028350_RB_YSEL 0xFFFFFF7F
4863 #define S_028350_PKR_MAP(x) (((x) & 0x03) << 8)
4864 #define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03)
4865 #define C_028350_PKR_MAP 0xFFFFFCFF
4866 #define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00
4867 #define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01
4868 #define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02
4869 #define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03
4870 #define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10)
4871 #define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03)
4872 #define C_028350_PKR_XSEL 0xFFFFF3FF
4873 #define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00
4874 #define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01
4875 #define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02
4876 #define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03
4877 #define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12)
4878 #define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03)
4879 #define C_028350_PKR_YSEL 0xFFFFCFFF
4880 #define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00
4881 #define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01
4882 #define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02
4883 #define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03
4884 #define S_028350_SC_MAP(x) (((x) & 0x03) << 16)
4885 #define G_028350_SC_MAP(x) (((x) >> 16) & 0x03)
4886 #define C_028350_SC_MAP 0xFFFCFFFF
4887 #define V_028350_RASTER_CONFIG_SC_MAP_0 0x00
4888 #define V_028350_RASTER_CONFIG_SC_MAP_1 0x01
4889 #define V_028350_RASTER_CONFIG_SC_MAP_2 0x02
4890 #define V_028350_RASTER_CONFIG_SC_MAP_3 0x03
4891 #define S_028350_SC_XSEL(x) (((x) & 0x03) << 18)
4892 #define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03)
4893 #define C_028350_SC_XSEL 0xFFF3FFFF
4894 #define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00
4895 #define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01
4896 #define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02
4897 #define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03
4898 #define S_028350_SC_YSEL(x) (((x) & 0x03) << 20)
4899 #define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03)
4900 #define C_028350_SC_YSEL 0xFFCFFFFF
4901 #define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00
4902 #define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01
4903 #define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02
4904 #define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03
4905 #define S_028350_SE_MAP(x) (((x) & 0x03) << 24)
4906 #define G_028350_SE_MAP(x) (((x) >> 24) & 0x03)
4907 #define C_028350_SE_MAP 0xFCFFFFFF
4908 #define V_028350_RASTER_CONFIG_SE_MAP_0 0x00
4909 #define V_028350_RASTER_CONFIG_SE_MAP_1 0x01
4910 #define V_028350_RASTER_CONFIG_SE_MAP_2 0x02
4911 #define V_028350_RASTER_CONFIG_SE_MAP_3 0x03
4912 #define S_028350_SE_XSEL(x) (((x) & 0x03) << 26)
4913 #define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03)
4914 #define C_028350_SE_XSEL 0xF3FFFFFF
4915 #define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00
4916 #define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01
4917 #define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02
4918 #define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03
4919 #define S_028350_SE_YSEL(x) (((x) & 0x03) << 28)
4920 #define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03)
4921 #define C_028350_SE_YSEL 0xCFFFFFFF
4922 #define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00
4923 #define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01
4924 #define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02
4925 #define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03
4926 #define R_028400_VGT_MAX_VTX_INDX 0x028400
4927 #define R_028404_VGT_MIN_VTX_INDX 0x028404
4928 #define R_028408_VGT_INDX_OFFSET 0x028408
4929 #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C
4930 #define R_028414_CB_BLEND_RED 0x028414
4931 #define R_028418_CB_BLEND_GREEN 0x028418
4932 #define R_02841C_CB_BLEND_BLUE 0x02841C
4933 #define R_028420_CB_BLEND_ALPHA 0x028420
4934 #define R_02842C_DB_STENCIL_CONTROL 0x02842C
4935 #define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0)
4936 #define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F)
4937 #define C_02842C_STENCILFAIL 0xFFFFFFF0
4938 #define V_02842C_STENCIL_KEEP 0x00
4939 #define V_02842C_STENCIL_ZERO 0x01
4940 #define V_02842C_STENCIL_ONES 0x02
4941 #define V_02842C_STENCIL_REPLACE_TEST 0x03
4942 #define V_02842C_STENCIL_REPLACE_OP 0x04
4943 #define V_02842C_STENCIL_ADD_CLAMP 0x05
4944 #define V_02842C_STENCIL_SUB_CLAMP 0x06
4945 #define V_02842C_STENCIL_INVERT 0x07
4946 #define V_02842C_STENCIL_ADD_WRAP 0x08
4947 #define V_02842C_STENCIL_SUB_WRAP 0x09
4948 #define V_02842C_STENCIL_AND 0x0A
4949 #define V_02842C_STENCIL_OR 0x0B
4950 #define V_02842C_STENCIL_XOR 0x0C
4951 #define V_02842C_STENCIL_NAND 0x0D
4952 #define V_02842C_STENCIL_NOR 0x0E
4953 #define V_02842C_STENCIL_XNOR 0x0F
4954 #define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4)
4955 #define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F)
4956 #define C_02842C_STENCILZPASS 0xFFFFFF0F
4957 #define V_02842C_STENCIL_KEEP 0x00
4958 #define V_02842C_STENCIL_ZERO 0x01
4959 #define V_02842C_STENCIL_ONES 0x02
4960 #define V_02842C_STENCIL_REPLACE_TEST 0x03
4961 #define V_02842C_STENCIL_REPLACE_OP 0x04
4962 #define V_02842C_STENCIL_ADD_CLAMP 0x05
4963 #define V_02842C_STENCIL_SUB_CLAMP 0x06
4964 #define V_02842C_STENCIL_INVERT 0x07
4965 #define V_02842C_STENCIL_ADD_WRAP 0x08
4966 #define V_02842C_STENCIL_SUB_WRAP 0x09
4967 #define V_02842C_STENCIL_AND 0x0A
4968 #define V_02842C_STENCIL_OR 0x0B
4969 #define V_02842C_STENCIL_XOR 0x0C
4970 #define V_02842C_STENCIL_NAND 0x0D
4971 #define V_02842C_STENCIL_NOR 0x0E
4972 #define V_02842C_STENCIL_XNOR 0x0F
4973 #define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8)
4974 #define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F)
4975 #define C_02842C_STENCILZFAIL 0xFFFFF0FF
4976 #define V_02842C_STENCIL_KEEP 0x00
4977 #define V_02842C_STENCIL_ZERO 0x01
4978 #define V_02842C_STENCIL_ONES 0x02
4979 #define V_02842C_STENCIL_REPLACE_TEST 0x03
4980 #define V_02842C_STENCIL_REPLACE_OP 0x04
4981 #define V_02842C_STENCIL_ADD_CLAMP 0x05
4982 #define V_02842C_STENCIL_SUB_CLAMP 0x06
4983 #define V_02842C_STENCIL_INVERT 0x07
4984 #define V_02842C_STENCIL_ADD_WRAP 0x08
4985 #define V_02842C_STENCIL_SUB_WRAP 0x09
4986 #define V_02842C_STENCIL_AND 0x0A
4987 #define V_02842C_STENCIL_OR 0x0B
4988 #define V_02842C_STENCIL_XOR 0x0C
4989 #define V_02842C_STENCIL_NAND 0x0D
4990 #define V_02842C_STENCIL_NOR 0x0E
4991 #define V_02842C_STENCIL_XNOR 0x0F
4992 #define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12)
4993 #define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F)
4994 #define C_02842C_STENCILFAIL_BF 0xFFFF0FFF
4995 #define V_02842C_STENCIL_KEEP 0x00
4996 #define V_02842C_STENCIL_ZERO 0x01
4997 #define V_02842C_STENCIL_ONES 0x02
4998 #define V_02842C_STENCIL_REPLACE_TEST 0x03
4999 #define V_02842C_STENCIL_REPLACE_OP 0x04
5000 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5001 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5002 #define V_02842C_STENCIL_INVERT 0x07
5003 #define V_02842C_STENCIL_ADD_WRAP 0x08
5004 #define V_02842C_STENCIL_SUB_WRAP 0x09
5005 #define V_02842C_STENCIL_AND 0x0A
5006 #define V_02842C_STENCIL_OR 0x0B
5007 #define V_02842C_STENCIL_XOR 0x0C
5008 #define V_02842C_STENCIL_NAND 0x0D
5009 #define V_02842C_STENCIL_NOR 0x0E
5010 #define V_02842C_STENCIL_XNOR 0x0F
5011 #define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16)
5012 #define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F)
5013 #define C_02842C_STENCILZPASS_BF 0xFFF0FFFF
5014 #define V_02842C_STENCIL_KEEP 0x00
5015 #define V_02842C_STENCIL_ZERO 0x01
5016 #define V_02842C_STENCIL_ONES 0x02
5017 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5018 #define V_02842C_STENCIL_REPLACE_OP 0x04
5019 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5020 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5021 #define V_02842C_STENCIL_INVERT 0x07
5022 #define V_02842C_STENCIL_ADD_WRAP 0x08
5023 #define V_02842C_STENCIL_SUB_WRAP 0x09
5024 #define V_02842C_STENCIL_AND 0x0A
5025 #define V_02842C_STENCIL_OR 0x0B
5026 #define V_02842C_STENCIL_XOR 0x0C
5027 #define V_02842C_STENCIL_NAND 0x0D
5028 #define V_02842C_STENCIL_NOR 0x0E
5029 #define V_02842C_STENCIL_XNOR 0x0F
5030 #define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20)
5031 #define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F)
5032 #define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF
5033 #define V_02842C_STENCIL_KEEP 0x00
5034 #define V_02842C_STENCIL_ZERO 0x01
5035 #define V_02842C_STENCIL_ONES 0x02
5036 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5037 #define V_02842C_STENCIL_REPLACE_OP 0x04
5038 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5039 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5040 #define V_02842C_STENCIL_INVERT 0x07
5041 #define V_02842C_STENCIL_ADD_WRAP 0x08
5042 #define V_02842C_STENCIL_SUB_WRAP 0x09
5043 #define V_02842C_STENCIL_AND 0x0A
5044 #define V_02842C_STENCIL_OR 0x0B
5045 #define V_02842C_STENCIL_XOR 0x0C
5046 #define V_02842C_STENCIL_NAND 0x0D
5047 #define V_02842C_STENCIL_NOR 0x0E
5048 #define V_02842C_STENCIL_XNOR 0x0F
5049 #define R_028430_DB_STENCILREFMASK 0x028430
5050 #define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0)
5051 #define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF)
5052 #define C_028430_STENCILTESTVAL 0xFFFFFF00
5053 #define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8)
5054 #define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF)
5055 #define C_028430_STENCILMASK 0xFFFF00FF
5056 #define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16)
5057 #define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF)
5058 #define C_028430_STENCILWRITEMASK 0xFF00FFFF
5059 #define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24)
5060 #define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF)
5061 #define C_028430_STENCILOPVAL 0x00FFFFFF
5062 #define R_028434_DB_STENCILREFMASK_BF 0x028434
5063 #define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0)
5064 #define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF)
5065 #define C_028434_STENCILTESTVAL_BF 0xFFFFFF00
5066 #define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8)
5067 #define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF)
5068 #define C_028434_STENCILMASK_BF 0xFFFF00FF
5069 #define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16)
5070 #define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF)
5071 #define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF
5072 #define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24)
5073 #define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF)
5074 #define C_028434_STENCILOPVAL_BF 0x00FFFFFF
5075 #define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C
5076 #define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440
5077 #define R_028444_PA_CL_VPORT_YSCALE_0 0x028444
5078 #define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448
5079 #define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C
5080 #define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450
5081 #define R_0285BC_PA_CL_UCP_0_X 0x0285BC
5082 #define R_0285C0_PA_CL_UCP_0_Y 0x0285C0
5083 #define R_0285C4_PA_CL_UCP_0_Z 0x0285C4
5084 #define R_0285C8_PA_CL_UCP_0_W 0x0285C8
5085 #define R_0285CC_PA_CL_UCP_1_X 0x0285CC
5086 #define R_0285D0_PA_CL_UCP_1_Y 0x0285D0
5087 #define R_0285D4_PA_CL_UCP_1_Z 0x0285D4
5088 #define R_0285D8_PA_CL_UCP_1_W 0x0285D8
5089 #define R_0285DC_PA_CL_UCP_2_X 0x0285DC
5090 #define R_0285E0_PA_CL_UCP_2_Y 0x0285E0
5091 #define R_0285E4_PA_CL_UCP_2_Z 0x0285E4
5092 #define R_0285E8_PA_CL_UCP_2_W 0x0285E8
5093 #define R_0285EC_PA_CL_UCP_3_X 0x0285EC
5094 #define R_0285F0_PA_CL_UCP_3_Y 0x0285F0
5095 #define R_0285F4_PA_CL_UCP_3_Z 0x0285F4
5096 #define R_0285F8_PA_CL_UCP_3_W 0x0285F8
5097 #define R_0285FC_PA_CL_UCP_4_X 0x0285FC
5098 #define R_028600_PA_CL_UCP_4_Y 0x028600
5099 #define R_028604_PA_CL_UCP_4_Z 0x028604
5100 #define R_028608_PA_CL_UCP_4_W 0x028608
5101 #define R_02860C_PA_CL_UCP_5_X 0x02860C
5102 #define R_028610_PA_CL_UCP_5_Y 0x028610
5103 #define R_028614_PA_CL_UCP_5_Z 0x028614
5104 #define R_028618_PA_CL_UCP_5_W 0x028618
5105 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644
5106 #define S_028644_OFFSET(x) (((x) & 0x3F) << 0)
5107 #define G_028644_OFFSET(x) (((x) >> 0) & 0x3F)
5108 #define C_028644_OFFSET 0xFFFFFFC0
5109 #define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8)
5110 #define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03)
5111 #define C_028644_DEFAULT_VAL 0xFFFFFCFF
5112 #define V_028644_X_0_0F 0x00
5113 #define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10)
5114 #define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1)
5115 #define C_028644_FLAT_SHADE 0xFFFFFBFF
5116 #define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13)
5117 #define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F)
5118 #define C_028644_CYL_WRAP 0xFFFE1FFF
5119 #define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17)
5120 #define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1)
5121 #define C_028644_PT_SPRITE_TEX 0xFFFDFFFF
5122 #define R_028648_SPI_PS_INPUT_CNTL_1 0x028648
5123 #define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C
5124 #define R_028650_SPI_PS_INPUT_CNTL_3 0x028650
5125 #define R_028654_SPI_PS_INPUT_CNTL_4 0x028654
5126 #define R_028658_SPI_PS_INPUT_CNTL_5 0x028658
5127 #define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C
5128 #define R_028660_SPI_PS_INPUT_CNTL_7 0x028660
5129 #define R_028664_SPI_PS_INPUT_CNTL_8 0x028664
5130 #define R_028668_SPI_PS_INPUT_CNTL_9 0x028668
5131 #define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C
5132 #define R_028670_SPI_PS_INPUT_CNTL_11 0x028670
5133 #define R_028674_SPI_PS_INPUT_CNTL_12 0x028674
5134 #define R_028678_SPI_PS_INPUT_CNTL_13 0x028678
5135 #define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C
5136 #define R_028680_SPI_PS_INPUT_CNTL_15 0x028680
5137 #define R_028684_SPI_PS_INPUT_CNTL_16 0x028684
5138 #define R_028688_SPI_PS_INPUT_CNTL_17 0x028688
5139 #define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C
5140 #define R_028690_SPI_PS_INPUT_CNTL_19 0x028690
5141 #define R_028694_SPI_PS_INPUT_CNTL_20 0x028694
5142 #define R_028698_SPI_PS_INPUT_CNTL_21 0x028698
5143 #define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C
5144 #define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0
5145 #define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4
5146 #define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8
5147 #define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC
5148 #define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0
5149 #define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4
5150 #define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8
5151 #define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC
5152 #define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0
5153 #define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4
5154 #define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1)
5155 #define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F)
5156 #define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1
5157 #define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6)
5158 #define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1)
5159 #define C_0286C4_VS_HALF_PACK 0xFFFFFFBF
5160 #define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7)
5161 #define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1)
5162 #define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F
5163 #define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8)
5164 #define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F)
5165 #define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF
5166 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
5167 #define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0)
5168 #define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1)
5169 #define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE
5170 #define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1)
5171 #define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1)
5172 #define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD
5173 #define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2)
5174 #define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1)
5175 #define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB
5176 #define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3)
5177 #define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1)
5178 #define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7
5179 #define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4)
5180 #define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1)
5181 #define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF
5182 #define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5)
5183 #define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1)
5184 #define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF
5185 #define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6)
5186 #define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1)
5187 #define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF
5188 #define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7)
5189 #define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1)
5190 #define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F
5191 #define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8)
5192 #define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1)
5193 #define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF
5194 #define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9)
5195 #define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1)
5196 #define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF
5197 #define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10)
5198 #define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1)
5199 #define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF
5200 #define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11)
5201 #define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1)
5202 #define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF
5203 #define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12)
5204 #define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1)
5205 #define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF
5206 #define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13)
5207 #define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1)
5208 #define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF
5209 #define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14)
5210 #define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1)
5211 #define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF
5212 #define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15)
5213 #define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1)
5214 #define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF
5215 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
5216 #define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0)
5217 #define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1)
5218 #define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE
5219 #define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1)
5220 #define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1)
5221 #define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD
5222 #define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2)
5223 #define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1)
5224 #define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB
5225 #define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3)
5226 #define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1)
5227 #define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7
5228 #define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4)
5229 #define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1)
5230 #define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF
5231 #define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5)
5232 #define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1)
5233 #define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF
5234 #define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6)
5235 #define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1)
5236 #define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF
5237 #define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7)
5238 #define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1)
5239 #define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F
5240 #define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8)
5241 #define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1)
5242 #define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF
5243 #define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9)
5244 #define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1)
5245 #define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF
5246 #define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10)
5247 #define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1)
5248 #define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF
5249 #define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11)
5250 #define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1)
5251 #define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF
5252 #define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12)
5253 #define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1)
5254 #define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF
5255 #define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13)
5256 #define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1)
5257 #define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF
5258 #define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14)
5259 #define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1)
5260 #define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF
5261 #define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15)
5262 #define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1)
5263 #define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF
5264 #define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4
5265 #define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0)
5266 #define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1)
5267 #define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE
5268 #define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1)
5269 #define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1)
5270 #define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD
5271 #define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2)
5272 #define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07)
5273 #define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3
5274 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
5275 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
5276 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
5277 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
5278 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
5279 #define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5)
5280 #define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07)
5281 #define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F
5282 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
5283 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
5284 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
5285 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
5286 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
5287 #define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8)
5288 #define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07)
5289 #define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF
5290 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
5291 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
5292 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
5293 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
5294 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
5295 #define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11)
5296 #define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07)
5297 #define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF
5298 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
5299 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
5300 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
5301 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
5302 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
5303 #define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14)
5304 #define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1)
5305 #define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF
5306 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
5307 #define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0)
5308 #define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F)
5309 #define C_0286D8_NUM_INTERP 0xFFFFFFC0
5310 #define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6)
5311 #define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1)
5312 #define C_0286D8_PARAM_GEN 0xFFFFFFBF
5313 #define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7)
5314 #define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F)
5315 #define C_0286D8_FOG_ADDR 0xFFFFC07F
5316 #define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14)
5317 #define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1)
5318 #define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF
5319 #define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15)
5320 #define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1)
5321 #define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF
5322 #define R_0286E0_SPI_BARYC_CNTL 0x0286E0
5323 #define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0)
5324 #define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1)
5325 #define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE
5326 #define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4)
5327 #define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1)
5328 #define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF
5329 #define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8)
5330 #define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1)
5331 #define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF
5332 #define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12)
5333 #define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1)
5334 #define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF
5335 #define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16)
5336 #define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03)
5337 #define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF
5338 #define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00
5339 #define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20)
5340 #define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1)
5341 #define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF
5342 #define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24)
5343 #define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1)
5344 #define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF
5345 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
5346 #define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0)
5347 #define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF)
5348 #define C_0286E8_WAVES 0xFFFFF000
5349 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
5350 #define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF)
5351 #define C_0286E8_WAVESIZE 0xFE000FFF
5352 #define R_028704_SPI_WAVE_MGMT_1 0x028704
5353 #define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0)
5354 #define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F)
5355 #define C_028704_NUM_PS_WAVES 0xFFFFFFC0
5356 #define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6)
5357 #define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F)
5358 #define C_028704_NUM_VS_WAVES 0xFFFFF03F
5359 #define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12)
5360 #define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F)
5361 #define C_028704_NUM_GS_WAVES 0xFFFC0FFF
5362 #define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18)
5363 #define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F)
5364 #define C_028704_NUM_ES_WAVES 0xFF03FFFF
5365 #define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24)
5366 #define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F)
5367 #define C_028704_NUM_HS_WAVES 0xC0FFFFFF
5368 #define R_028708_SPI_WAVE_MGMT_2 0x028708
5369 #define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0)
5370 #define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F)
5371 #define C_028708_NUM_LS_WAVES 0xFFFFFFC0
5372 #define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C
5373 #define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
5374 #define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
5375 #define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0
5376 #define V_02870C_SPI_SHADER_NONE 0x00
5377 #define V_02870C_SPI_SHADER_1COMP 0x01
5378 #define V_02870C_SPI_SHADER_2COMP 0x02
5379 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
5380 #define V_02870C_SPI_SHADER_4COMP 0x04
5381 #define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4)
5382 #define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F)
5383 #define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F
5384 #define V_02870C_SPI_SHADER_NONE 0x00
5385 #define V_02870C_SPI_SHADER_1COMP 0x01
5386 #define V_02870C_SPI_SHADER_2COMP 0x02
5387 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
5388 #define V_02870C_SPI_SHADER_4COMP 0x04
5389 #define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8)
5390 #define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F)
5391 #define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF
5392 #define V_02870C_SPI_SHADER_NONE 0x00
5393 #define V_02870C_SPI_SHADER_1COMP 0x01
5394 #define V_02870C_SPI_SHADER_2COMP 0x02
5395 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
5396 #define V_02870C_SPI_SHADER_4COMP 0x04
5397 #define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12)
5398 #define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F)
5399 #define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF
5400 #define V_02870C_SPI_SHADER_NONE 0x00
5401 #define V_02870C_SPI_SHADER_1COMP 0x01
5402 #define V_02870C_SPI_SHADER_2COMP 0x02
5403 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
5404 #define V_02870C_SPI_SHADER_4COMP 0x04
5405 #define R_028710_SPI_SHADER_Z_FORMAT 0x028710
5406 #define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
5407 #define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
5408 #define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0
5409 #define V_028710_SPI_SHADER_ZERO 0x00
5410 #define V_028710_SPI_SHADER_32_R 0x01
5411 #define V_028710_SPI_SHADER_32_GR 0x02
5412 #define V_028710_SPI_SHADER_32_AR 0x03
5413 #define V_028710_SPI_SHADER_FP16_ABGR 0x04
5414 #define V_028710_SPI_SHADER_UNORM16_ABGR 0x05
5415 #define V_028710_SPI_SHADER_SNORM16_ABGR 0x06
5416 #define V_028710_SPI_SHADER_UINT16_ABGR 0x07
5417 #define V_028710_SPI_SHADER_SINT16_ABGR 0x08
5418 #define V_028710_SPI_SHADER_32_ABGR 0x09
5419 #define R_028714_SPI_SHADER_COL_FORMAT 0x028714
5420 #define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
5421 #define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
5422 #define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0
5423 #define V_028714_SPI_SHADER_ZERO 0x00
5424 #define V_028714_SPI_SHADER_32_R 0x01
5425 #define V_028714_SPI_SHADER_32_GR 0x02
5426 #define V_028714_SPI_SHADER_32_AR 0x03
5427 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5428 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5429 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5430 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5431 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5432 #define V_028714_SPI_SHADER_32_ABGR 0x09
5433 #define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4)
5434 #define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F)
5435 #define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F
5436 #define V_028714_SPI_SHADER_ZERO 0x00
5437 #define V_028714_SPI_SHADER_32_R 0x01
5438 #define V_028714_SPI_SHADER_32_GR 0x02
5439 #define V_028714_SPI_SHADER_32_AR 0x03
5440 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5441 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5442 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5443 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5444 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5445 #define V_028714_SPI_SHADER_32_ABGR 0x09
5446 #define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8)
5447 #define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F)
5448 #define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF
5449 #define V_028714_SPI_SHADER_ZERO 0x00
5450 #define V_028714_SPI_SHADER_32_R 0x01
5451 #define V_028714_SPI_SHADER_32_GR 0x02
5452 #define V_028714_SPI_SHADER_32_AR 0x03
5453 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5454 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5455 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5456 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5457 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5458 #define V_028714_SPI_SHADER_32_ABGR 0x09
5459 #define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12)
5460 #define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F)
5461 #define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF
5462 #define V_028714_SPI_SHADER_ZERO 0x00
5463 #define V_028714_SPI_SHADER_32_R 0x01
5464 #define V_028714_SPI_SHADER_32_GR 0x02
5465 #define V_028714_SPI_SHADER_32_AR 0x03
5466 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5467 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5468 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5469 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5470 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5471 #define V_028714_SPI_SHADER_32_ABGR 0x09
5472 #define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16)
5473 #define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F)
5474 #define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF
5475 #define V_028714_SPI_SHADER_ZERO 0x00
5476 #define V_028714_SPI_SHADER_32_R 0x01
5477 #define V_028714_SPI_SHADER_32_GR 0x02
5478 #define V_028714_SPI_SHADER_32_AR 0x03
5479 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5480 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5481 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5482 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5483 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5484 #define V_028714_SPI_SHADER_32_ABGR 0x09
5485 #define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20)
5486 #define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F)
5487 #define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF
5488 #define V_028714_SPI_SHADER_ZERO 0x00
5489 #define V_028714_SPI_SHADER_32_R 0x01
5490 #define V_028714_SPI_SHADER_32_GR 0x02
5491 #define V_028714_SPI_SHADER_32_AR 0x03
5492 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5493 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5494 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5495 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5496 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5497 #define V_028714_SPI_SHADER_32_ABGR 0x09
5498 #define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24)
5499 #define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F)
5500 #define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF
5501 #define V_028714_SPI_SHADER_ZERO 0x00
5502 #define V_028714_SPI_SHADER_32_R 0x01
5503 #define V_028714_SPI_SHADER_32_GR 0x02
5504 #define V_028714_SPI_SHADER_32_AR 0x03
5505 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5506 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5507 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5508 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5509 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5510 #define V_028714_SPI_SHADER_32_ABGR 0x09
5511 #define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28)
5512 #define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F)
5513 #define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF
5514 #define V_028714_SPI_SHADER_ZERO 0x00
5515 #define V_028714_SPI_SHADER_32_R 0x01
5516 #define V_028714_SPI_SHADER_32_GR 0x02
5517 #define V_028714_SPI_SHADER_32_AR 0x03
5518 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
5519 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
5520 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
5521 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
5522 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
5523 #define V_028714_SPI_SHADER_32_ABGR 0x09
5524 #define R_028780_CB_BLEND0_CONTROL 0x028780
5525 #define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0)
5526 #define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F)
5527 #define C_028780_COLOR_SRCBLEND 0xFFFFFFE0
5528 #define V_028780_BLEND_ZERO 0x00
5529 #define V_028780_BLEND_ONE 0x01
5530 #define V_028780_BLEND_SRC_COLOR 0x02
5531 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
5532 #define V_028780_BLEND_SRC_ALPHA 0x04
5533 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
5534 #define V_028780_BLEND_DST_ALPHA 0x06
5535 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
5536 #define V_028780_BLEND_DST_COLOR 0x08
5537 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
5538 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
5539 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
5540 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
5541 #define V_028780_BLEND_SRC1_COLOR 0x0F
5542 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
5543 #define V_028780_BLEND_SRC1_ALPHA 0x11
5544 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
5545 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
5546 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
5547 #define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5)
5548 #define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07)
5549 #define C_028780_COLOR_COMB_FCN 0xFFFFFF1F
5550 #define V_028780_COMB_DST_PLUS_SRC 0x00
5551 #define V_028780_COMB_SRC_MINUS_DST 0x01
5552 #define V_028780_COMB_MIN_DST_SRC 0x02
5553 #define V_028780_COMB_MAX_DST_SRC 0x03
5554 #define V_028780_COMB_DST_MINUS_SRC 0x04
5555 #define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8)
5556 #define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F)
5557 #define C_028780_COLOR_DESTBLEND 0xFFFFE0FF
5558 #define V_028780_BLEND_ZERO 0x00
5559 #define V_028780_BLEND_ONE 0x01
5560 #define V_028780_BLEND_SRC_COLOR 0x02
5561 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
5562 #define V_028780_BLEND_SRC_ALPHA 0x04
5563 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
5564 #define V_028780_BLEND_DST_ALPHA 0x06
5565 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
5566 #define V_028780_BLEND_DST_COLOR 0x08
5567 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
5568 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
5569 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
5570 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
5571 #define V_028780_BLEND_SRC1_COLOR 0x0F
5572 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
5573 #define V_028780_BLEND_SRC1_ALPHA 0x11
5574 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
5575 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
5576 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
5577 #define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16)
5578 #define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F)
5579 #define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF
5580 #define V_028780_BLEND_ZERO 0x00
5581 #define V_028780_BLEND_ONE 0x01
5582 #define V_028780_BLEND_SRC_COLOR 0x02
5583 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
5584 #define V_028780_BLEND_SRC_ALPHA 0x04
5585 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
5586 #define V_028780_BLEND_DST_ALPHA 0x06
5587 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
5588 #define V_028780_BLEND_DST_COLOR 0x08
5589 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
5590 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
5591 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
5592 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
5593 #define V_028780_BLEND_SRC1_COLOR 0x0F
5594 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
5595 #define V_028780_BLEND_SRC1_ALPHA 0x11
5596 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
5597 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
5598 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
5599 #define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21)
5600 #define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07)
5601 #define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF
5602 #define V_028780_COMB_DST_PLUS_SRC 0x00
5603 #define V_028780_COMB_SRC_MINUS_DST 0x01
5604 #define V_028780_COMB_MIN_DST_SRC 0x02
5605 #define V_028780_COMB_MAX_DST_SRC 0x03
5606 #define V_028780_COMB_DST_MINUS_SRC 0x04
5607 #define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24)
5608 #define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F)
5609 #define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF
5610 #define V_028780_BLEND_ZERO 0x00
5611 #define V_028780_BLEND_ONE 0x01
5612 #define V_028780_BLEND_SRC_COLOR 0x02
5613 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
5614 #define V_028780_BLEND_SRC_ALPHA 0x04
5615 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
5616 #define V_028780_BLEND_DST_ALPHA 0x06
5617 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
5618 #define V_028780_BLEND_DST_COLOR 0x08
5619 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
5620 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
5621 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
5622 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
5623 #define V_028780_BLEND_SRC1_COLOR 0x0F
5624 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
5625 #define V_028780_BLEND_SRC1_ALPHA 0x11
5626 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
5627 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
5628 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
5629 #define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29)
5630 #define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1)
5631 #define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF
5632 #define S_028780_ENABLE(x) (((x) & 0x1) << 30)
5633 #define G_028780_ENABLE(x) (((x) >> 30) & 0x1)
5634 #define C_028780_ENABLE 0xBFFFFFFF
5635 #define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31)
5636 #define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1)
5637 #define C_028780_DISABLE_ROP3 0x7FFFFFFF
5638 #define R_028784_CB_BLEND1_CONTROL 0x028784
5639 #define R_028788_CB_BLEND2_CONTROL 0x028788
5640 #define R_02878C_CB_BLEND3_CONTROL 0x02878C
5641 #define R_028790_CB_BLEND4_CONTROL 0x028790
5642 #define R_028794_CB_BLEND5_CONTROL 0x028794
5643 #define R_028798_CB_BLEND6_CONTROL 0x028798
5644 #define R_02879C_CB_BLEND7_CONTROL 0x02879C
5645 #define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4
5646 #define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8
5647 #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC
5648 #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0
5649 #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4
5650 #define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0)
5651 #define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF)
5652 #define C_0287E4_BASE_ADDR 0xFFFFFF00
5653 #define R_0287E8_VGT_DMA_BASE 0x0287E8
5654 #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0
5655 #define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0)
5656 #define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03)
5657 #define C_0287F0_SOURCE_SELECT 0xFFFFFFFC
5658 #define V_0287F0_DI_SRC_SEL_DMA 0x00
5659 #define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01
5660 #define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02
5661 #define V_0287F0_DI_SRC_SEL_RESERVED 0x03
5662 #define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2)
5663 #define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03)
5664 #define C_0287F0_MAJOR_MODE 0xFFFFFFF3
5665 #define V_0287F0_DI_MAJOR_MODE_0 0x00
5666 #define V_0287F0_DI_MAJOR_MODE_1 0x01
5667 #define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5)
5668 #define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1)
5669 #define C_0287F0_NOT_EOP 0xFFFFFFDF
5670 #define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6)
5671 #define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1)
5672 #define C_0287F0_USE_OPAQUE 0xFFFFFFBF
5673 #define R_0287F4_VGT_IMMED_DATA 0x0287F4
5674 #define R_028800_DB_DEPTH_CONTROL 0x028800
5675 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
5676 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
5677 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
5678 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
5679 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
5680 #define C_028800_Z_ENABLE 0xFFFFFFFD
5681 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
5682 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
5683 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
5684 #define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3)
5685 #define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1)
5686 #define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7
5687 #define S_028800_ZFUNC(x) (((x) & 0x07) << 4)
5688 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x07)
5689 #define C_028800_ZFUNC 0xFFFFFF8F
5690 #define V_028800_FRAG_NEVER 0x00
5691 #define V_028800_FRAG_LESS 0x01
5692 #define V_028800_FRAG_EQUAL 0x02
5693 #define V_028800_FRAG_LEQUAL 0x03
5694 #define V_028800_FRAG_GREATER 0x04
5695 #define V_028800_FRAG_NOTEQUAL 0x05
5696 #define V_028800_FRAG_GEQUAL 0x06
5697 #define V_028800_FRAG_ALWAYS 0x07
5698 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
5699 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
5700 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
5701 #define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8)
5702 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07)
5703 #define C_028800_STENCILFUNC 0xFFFFF8FF
5704 #define V_028800_REF_NEVER 0x00
5705 #define V_028800_REF_LESS 0x01
5706 #define V_028800_REF_EQUAL 0x02
5707 #define V_028800_REF_LEQUAL 0x03
5708 #define V_028800_REF_GREATER 0x04
5709 #define V_028800_REF_NOTEQUAL 0x05
5710 #define V_028800_REF_GEQUAL 0x06
5711 #define V_028800_REF_ALWAYS 0x07
5712 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20)
5713 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07)
5714 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
5715 #define V_028800_REF_NEVER 0x00
5716 #define V_028800_REF_LESS 0x01
5717 #define V_028800_REF_EQUAL 0x02
5718 #define V_028800_REF_LEQUAL 0x03
5719 #define V_028800_REF_GREATER 0x04
5720 #define V_028800_REF_NOTEQUAL 0x05
5721 #define V_028800_REF_GEQUAL 0x06
5722 #define V_028800_REF_ALWAYS 0x07
5723 #define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30)
5724 #define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1)
5725 #define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF
5726 #define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31)
5727 #define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1)
5728 #define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF
5729 #define R_028804_DB_EQAA 0x028804
5730 #define R_028808_CB_COLOR_CONTROL 0x028808
5731 #define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3)
5732 #define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1)
5733 #define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7
5734 #define S_028808_MODE(x) (((x) & 0x07) << 4)
5735 #define G_028808_MODE(x) (((x) >> 4) & 0x07)
5736 #define C_028808_MODE 0xFFFFFF8F
5737 #define V_028808_CB_DISABLE 0x00
5738 #define V_028808_CB_NORMAL 0x01
5739 #define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02
5740 #define V_028808_CB_RESOLVE 0x03
5741 #define V_028808_CB_FMASK_DECOMPRESS 0x05
5742 #define S_028808_ROP3(x) (((x) & 0xFF) << 16)
5743 #define G_028808_ROP3(x) (((x) >> 16) & 0xFF)
5744 #define C_028808_ROP3 0xFF00FFFF
5745 #define V_028808_X_0X00 0x00
5746 #define V_028808_X_0X05 0x05
5747 #define V_028808_X_0X0A 0x0A
5748 #define V_028808_X_0X0F 0x0F
5749 #define V_028808_X_0X11 0x11
5750 #define V_028808_X_0X22 0x22
5751 #define V_028808_X_0X33 0x33
5752 #define V_028808_X_0X44 0x44
5753 #define V_028808_X_0X50 0x50
5754 #define V_028808_X_0X55 0x55
5755 #define V_028808_X_0X5A 0x5A
5756 #define V_028808_X_0X5F 0x5F
5757 #define V_028808_X_0X66 0x66
5758 #define V_028808_X_0X77 0x77
5759 #define V_028808_X_0X88 0x88
5760 #define V_028808_X_0X99 0x99
5761 #define V_028808_X_0XA0 0xA0
5762 #define V_028808_X_0XA5 0xA5
5763 #define V_028808_X_0XAA 0xAA
5764 #define V_028808_X_0XAF 0xAF
5765 #define V_028808_X_0XBB 0xBB
5766 #define V_028808_X_0XCC 0xCC
5767 #define V_028808_X_0XDD 0xDD
5768 #define V_028808_X_0XEE 0xEE
5769 #define V_028808_X_0XF0 0xF0
5770 #define V_028808_X_0XF5 0xF5
5771 #define V_028808_X_0XFA 0xFA
5772 #define V_028808_X_0XFF 0xFF
5773 #define R_02880C_DB_SHADER_CONTROL 0x02880C
5774 #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0)
5775 #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1)
5776 #define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE
5777 #define S_02880C_STENCIL_TEST_VAL_EXPORT_ENAB(x) (((x) & 0x1) << 1)
5778 #define G_02880C_STENCIL_TEST_VAL_EXPORT_ENAB(x) (((x) >> 1) & 0x1)
5779 #define C_02880C_STENCIL_TEST_VAL_EXPORT_ENAB 0xFFFFFFFD
5780 #define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2)
5781 #define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1)
5782 #define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB
5783 #define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4)
5784 #define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03)
5785 #define C_02880C_Z_ORDER 0xFFFFFFCF
5786 #define V_02880C_LATE_Z 0x00
5787 #define V_02880C_EARLY_Z_THEN_LATE_Z 0x01
5788 #define V_02880C_RE_Z 0x02
5789 #define V_02880C_EARLY_Z_THEN_RE_Z 0x03
5790 #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
5791 #define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1)
5792 #define C_02880C_KILL_ENABLE 0xFFFFFFBF
5793 #define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7)
5794 #define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1)
5795 #define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F
5796 #define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8)
5797 #define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1)
5798 #define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF
5799 #define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9)
5800 #define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1)
5801 #define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF
5802 #define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10)
5803 #define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1)
5804 #define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF
5805 #define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11)
5806 #define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1)
5807 #define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF
5808 #define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12)
5809 #define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1)
5810 #define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF
5811 #define R_028810_PA_CL_CLIP_CNTL 0x028810
5812 #define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0)
5813 #define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1)
5814 #define C_028810_UCP_ENA_0 0xFFFFFFFE
5815 #define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1)
5816 #define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1)
5817 #define C_028810_UCP_ENA_1 0xFFFFFFFD
5818 #define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2)
5819 #define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1)
5820 #define C_028810_UCP_ENA_2 0xFFFFFFFB
5821 #define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3)
5822 #define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1)
5823 #define C_028810_UCP_ENA_3 0xFFFFFFF7
5824 #define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4)
5825 #define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1)
5826 #define C_028810_UCP_ENA_4 0xFFFFFFEF
5827 #define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5)
5828 #define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1)
5829 #define C_028810_UCP_ENA_5 0xFFFFFFDF
5830 #define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13)
5831 #define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1)
5832 #define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF
5833 #define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14)
5834 #define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03)
5835 #define C_028810_PS_UCP_MODE 0xFFFF3FFF
5836 #define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16)
5837 #define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1)
5838 #define C_028810_CLIP_DISABLE 0xFFFEFFFF
5839 #define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17)
5840 #define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1)
5841 #define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF
5842 #define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18)
5843 #define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1)
5844 #define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF
5845 #define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19)
5846 #define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1)
5847 #define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF
5848 #define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20)
5849 #define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1)
5850 #define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF
5851 #define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21)
5852 #define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1)
5853 #define C_028810_VTX_KILL_OR 0xFFDFFFFF
5854 #define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22)
5855 #define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1)
5856 #define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF
5857 #define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24)
5858 #define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1)
5859 #define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF
5860 #define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25)
5861 #define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1)
5862 #define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF
5863 #define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26)
5864 #define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1)
5865 #define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF
5866 #define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27)
5867 #define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1)
5868 #define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF
5869 #define R_028814_PA_SU_SC_MODE_CNTL 0x028814
5870 #define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0)
5871 #define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1)
5872 #define C_028814_CULL_FRONT 0xFFFFFFFE
5873 #define S_028814_CULL_BACK(x) (((x) & 0x1) << 1)
5874 #define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1)
5875 #define C_028814_CULL_BACK 0xFFFFFFFD
5876 #define S_028814_FACE(x) (((x) & 0x1) << 2)
5877 #define G_028814_FACE(x) (((x) >> 2) & 0x1)
5878 #define C_028814_FACE 0xFFFFFFFB
5879 #define S_028814_POLY_MODE(x) (((x) & 0x03) << 3)
5880 #define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03)
5881 #define C_028814_POLY_MODE 0xFFFFFFE7
5882 #define V_028814_X_DISABLE_POLY_MODE 0x00
5883 #define V_028814_X_DUAL_MODE 0x01
5884 #define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5)
5885 #define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07)
5886 #define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F
5887 #define V_028814_X_DRAW_POINTS 0x00
5888 #define V_028814_X_DRAW_LINES 0x01
5889 #define V_028814_X_DRAW_TRIANGLES 0x02
5890 #define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8)
5891 #define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07)
5892 #define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF
5893 #define V_028814_X_DRAW_POINTS 0x00
5894 #define V_028814_X_DRAW_LINES 0x01
5895 #define V_028814_X_DRAW_TRIANGLES 0x02
5896 #define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11)
5897 #define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1)
5898 #define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF
5899 #define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12)
5900 #define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1)
5901 #define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF
5902 #define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13)
5903 #define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1)
5904 #define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF
5905 #define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16)
5906 #define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1)
5907 #define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF
5908 #define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19)
5909 #define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1)
5910 #define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF
5911 #define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20)
5912 #define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1)
5913 #define C_028814_PERSP_CORR_DIS 0xFFEFFFFF
5914 #define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21)
5915 #define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1)
5916 #define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF
5917 #define R_028818_PA_CL_VTE_CNTL 0x028818
5918 #define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0)
5919 #define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1)
5920 #define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE
5921 #define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1)
5922 #define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1)
5923 #define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD
5924 #define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2)
5925 #define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1)
5926 #define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB
5927 #define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3)
5928 #define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1)
5929 #define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7
5930 #define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4)
5931 #define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1)
5932 #define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF
5933 #define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5)
5934 #define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1)
5935 #define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF
5936 #define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8)
5937 #define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1)
5938 #define C_028818_VTX_XY_FMT 0xFFFFFEFF
5939 #define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9)
5940 #define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1)
5941 #define C_028818_VTX_Z_FMT 0xFFFFFDFF
5942 #define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10)
5943 #define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1)
5944 #define C_028818_VTX_W0_FMT 0xFFFFFBFF
5945 #define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C
5946 #define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0)
5947 #define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1)
5948 #define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE
5949 #define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1)
5950 #define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1)
5951 #define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD
5952 #define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2)
5953 #define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1)
5954 #define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB
5955 #define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3)
5956 #define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1)
5957 #define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7
5958 #define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4)
5959 #define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1)
5960 #define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF
5961 #define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5)
5962 #define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1)
5963 #define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF
5964 #define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6)
5965 #define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1)
5966 #define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF
5967 #define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7)
5968 #define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1)
5969 #define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F
5970 #define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8)
5971 #define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1)
5972 #define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF
5973 #define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9)
5974 #define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1)
5975 #define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF
5976 #define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10)
5977 #define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1)
5978 #define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF
5979 #define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11)
5980 #define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1)
5981 #define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF
5982 #define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12)
5983 #define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1)
5984 #define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF
5985 #define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13)
5986 #define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1)
5987 #define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF
5988 #define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14)
5989 #define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1)
5990 #define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF
5991 #define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15)
5992 #define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1)
5993 #define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF
5994 #define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16)
5995 #define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1)
5996 #define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF
5997 #define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17)
5998 #define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1)
5999 #define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF
6000 #define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18)
6001 #define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1)
6002 #define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF
6003 #define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19)
6004 #define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1)
6005 #define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF
6006 #define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20)
6007 #define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1)
6008 #define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF
6009 #define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21)
6010 #define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1)
6011 #define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF
6012 #define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22)
6013 #define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1)
6014 #define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF
6015 #define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23)
6016 #define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1)
6017 #define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF
6018 #define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24)
6019 #define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1)
6020 #define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF
6021 #define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25)
6022 #define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1)
6023 #define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF
6024 #define R_028820_PA_CL_NANINF_CNTL 0x028820
6025 #define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0)
6026 #define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1)
6027 #define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE
6028 #define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1)
6029 #define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1)
6030 #define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD
6031 #define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2)
6032 #define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1)
6033 #define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB
6034 #define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3)
6035 #define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1)
6036 #define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7
6037 #define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4)
6038 #define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1)
6039 #define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF
6040 #define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5)
6041 #define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1)
6042 #define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF
6043 #define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6)
6044 #define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1)
6045 #define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF
6046 #define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7)
6047 #define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1)
6048 #define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F
6049 #define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8)
6050 #define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1)
6051 #define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF
6052 #define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9)
6053 #define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1)
6054 #define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF
6055 #define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10)
6056 #define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1)
6057 #define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF
6058 #define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11)
6059 #define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1)
6060 #define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF
6061 #define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12)
6062 #define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1)
6063 #define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF
6064 #define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13)
6065 #define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1)
6066 #define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF
6067 #define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14)
6068 #define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1)
6069 #define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF
6070 #define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20)
6071 #define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1)
6072 #define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF
6073 #define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824
6074 #define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0)
6075 #define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03)
6076 #define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC
6077 #define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2)
6078 #define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1)
6079 #define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB
6080 #define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3)
6081 #define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1)
6082 #define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7
6083 #define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4)
6084 #define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1)
6085 #define C_028824_DIAMOND_ADJUST 0xFFFFFFEF
6086 #define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828
6087 #define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C
6088 #define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0)
6089 #define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1)
6090 #define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE
6091 #define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1)
6092 #define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1)
6093 #define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD
6094 #define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2)
6095 #define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1)
6096 #define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB
6097 #define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3)
6098 #define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1)
6099 #define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7
6100 #define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4)
6101 #define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1)
6102 #define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF
6103 #define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5)
6104 #define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1)
6105 #define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF
6106 #define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6)
6107 #define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1)
6108 #define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF
6109 #define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7)
6110 #define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1)
6111 #define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F
6112 #define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8)
6113 #define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF)
6114 #define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF
6115 #define R_028A00_PA_SU_POINT_SIZE 0x028A00
6116 #define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0)
6117 #define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF)
6118 #define C_028A00_HEIGHT 0xFFFF0000
6119 #define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16)
6120 #define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF)
6121 #define C_028A00_WIDTH 0x0000FFFF
6122 #define R_028A04_PA_SU_POINT_MINMAX 0x028A04
6123 #define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0)
6124 #define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF)
6125 #define C_028A04_MIN_SIZE 0xFFFF0000
6126 #define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16)
6127 #define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF)
6128 #define C_028A04_MAX_SIZE 0x0000FFFF
6129 #define R_028A08_PA_SU_LINE_CNTL 0x028A08
6130 #define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0)
6131 #define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF)
6132 #define C_028A08_WIDTH 0xFFFF0000
6133 #define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C
6134 #define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0)
6135 #define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF)
6136 #define C_028A0C_LINE_PATTERN 0xFFFF0000
6137 #define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16)
6138 #define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF)
6139 #define C_028A0C_REPEAT_COUNT 0xFF00FFFF
6140 #define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28)
6141 #define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1)
6142 #define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF
6143 #define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29)
6144 #define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03)
6145 #define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF
6146 #define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10
6147 #define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0)
6148 #define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07)
6149 #define C_028A10_PATH_SELECT 0xFFFFFFF8
6150 #define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00
6151 #define V_028A10_VGT_OUTPATH_TESS_EN 0x01
6152 #define V_028A10_VGT_OUTPATH_PASSTHRU 0x02
6153 #define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03
6154 #define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04
6155 #define R_028A14_VGT_HOS_CNTL 0x028A14
6156 #define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0)
6157 #define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03)
6158 #define C_028A14_TESS_MODE 0xFFFFFFFC
6159 #define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18
6160 #define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C
6161 #define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20
6162 #define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
6163 #define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
6164 #define C_028A20_REUSE_DEPTH 0xFFFFFF00
6165 #define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24
6166 #define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0)
6167 #define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F)
6168 #define C_028A24_PRIM_TYPE 0xFFFFFFE0
6169 #define V_028A24_VGT_GRP_3D_POINT 0x00
6170 #define V_028A24_VGT_GRP_3D_LINE 0x01
6171 #define V_028A24_VGT_GRP_3D_TRI 0x02
6172 #define V_028A24_VGT_GRP_3D_RECT 0x03
6173 #define V_028A24_VGT_GRP_3D_QUAD 0x04
6174 #define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05
6175 #define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06
6176 #define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07
6177 #define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08
6178 #define V_028A24_VGT_GRP_2D_FILL_RECT 0x09
6179 #define V_028A24_VGT_GRP_2D_LINE 0x0A
6180 #define V_028A24_VGT_GRP_2D_TRI 0x0B
6181 #define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C
6182 #define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D
6183 #define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E
6184 #define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F
6185 #define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10
6186 #define V_028A24_VGT_GRP_3D_PATCH 0x11
6187 #define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14)
6188 #define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1)
6189 #define C_028A24_RETAIN_ORDER 0xFFFFBFFF
6190 #define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15)
6191 #define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1)
6192 #define C_028A24_RETAIN_QUADS 0xFFFF7FFF
6193 #define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16)
6194 #define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07)
6195 #define C_028A24_PRIM_ORDER 0xFFF8FFFF
6196 #define V_028A24_VGT_GRP_LIST 0x00
6197 #define V_028A24_VGT_GRP_STRIP 0x01
6198 #define V_028A24_VGT_GRP_FAN 0x02
6199 #define V_028A24_VGT_GRP_LOOP 0x03
6200 #define V_028A24_VGT_GRP_POLYGON 0x04
6201 #define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28
6202 #define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0)
6203 #define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F)
6204 #define C_028A28_FIRST_DECR 0xFFFFFFF0
6205 #define R_028A2C_VGT_GROUP_DECR 0x028A2C
6206 #define S_028A2C_DECR(x) (((x) & 0x0F) << 0)
6207 #define G_028A2C_DECR(x) (((x) >> 0) & 0x0F)
6208 #define C_028A2C_DECR 0xFFFFFFF0
6209 #define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30
6210 #define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0)
6211 #define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1)
6212 #define C_028A30_COMP_X_EN 0xFFFFFFFE
6213 #define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1)
6214 #define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1)
6215 #define C_028A30_COMP_Y_EN 0xFFFFFFFD
6216 #define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2)
6217 #define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1)
6218 #define C_028A30_COMP_Z_EN 0xFFFFFFFB
6219 #define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3)
6220 #define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1)
6221 #define C_028A30_COMP_W_EN 0xFFFFFFF7
6222 #define S_028A30_STRIDE(x) (((x) & 0xFF) << 8)
6223 #define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF)
6224 #define C_028A30_STRIDE 0xFFFF00FF
6225 #define S_028A30_SHIFT(x) (((x) & 0xFF) << 16)
6226 #define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF)
6227 #define C_028A30_SHIFT 0xFF00FFFF
6228 #define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34
6229 #define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0)
6230 #define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1)
6231 #define C_028A34_COMP_X_EN 0xFFFFFFFE
6232 #define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1)
6233 #define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1)
6234 #define C_028A34_COMP_Y_EN 0xFFFFFFFD
6235 #define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2)
6236 #define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1)
6237 #define C_028A34_COMP_Z_EN 0xFFFFFFFB
6238 #define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3)
6239 #define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1)
6240 #define C_028A34_COMP_W_EN 0xFFFFFFF7
6241 #define S_028A34_STRIDE(x) (((x) & 0xFF) << 8)
6242 #define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF)
6243 #define C_028A34_STRIDE 0xFFFF00FF
6244 #define S_028A34_SHIFT(x) (((x) & 0xFF) << 16)
6245 #define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF)
6246 #define C_028A34_SHIFT 0xFF00FFFF
6247 #define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38
6248 #define S_028A38_X_CONV(x) (((x) & 0x0F) << 0)
6249 #define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F)
6250 #define C_028A38_X_CONV 0xFFFFFFF0
6251 #define V_028A38_VGT_GRP_INDEX_16 0x00
6252 #define V_028A38_VGT_GRP_INDEX_32 0x01
6253 #define V_028A38_VGT_GRP_UINT_16 0x02
6254 #define V_028A38_VGT_GRP_UINT_32 0x03
6255 #define V_028A38_VGT_GRP_SINT_16 0x04
6256 #define V_028A38_VGT_GRP_SINT_32 0x05
6257 #define V_028A38_VGT_GRP_FLOAT_32 0x06
6258 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
6259 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6260 #define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4)
6261 #define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F)
6262 #define C_028A38_X_OFFSET 0xFFFFFF0F
6263 #define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8)
6264 #define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F)
6265 #define C_028A38_Y_CONV 0xFFFFF0FF
6266 #define V_028A38_VGT_GRP_INDEX_16 0x00
6267 #define V_028A38_VGT_GRP_INDEX_32 0x01
6268 #define V_028A38_VGT_GRP_UINT_16 0x02
6269 #define V_028A38_VGT_GRP_UINT_32 0x03
6270 #define V_028A38_VGT_GRP_SINT_16 0x04
6271 #define V_028A38_VGT_GRP_SINT_32 0x05
6272 #define V_028A38_VGT_GRP_FLOAT_32 0x06
6273 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
6274 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6275 #define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12)
6276 #define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F)
6277 #define C_028A38_Y_OFFSET 0xFFFF0FFF
6278 #define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16)
6279 #define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F)
6280 #define C_028A38_Z_CONV 0xFFF0FFFF
6281 #define V_028A38_VGT_GRP_INDEX_16 0x00
6282 #define V_028A38_VGT_GRP_INDEX_32 0x01
6283 #define V_028A38_VGT_GRP_UINT_16 0x02
6284 #define V_028A38_VGT_GRP_UINT_32 0x03
6285 #define V_028A38_VGT_GRP_SINT_16 0x04
6286 #define V_028A38_VGT_GRP_SINT_32 0x05
6287 #define V_028A38_VGT_GRP_FLOAT_32 0x06
6288 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
6289 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6290 #define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20)
6291 #define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F)
6292 #define C_028A38_Z_OFFSET 0xFF0FFFFF
6293 #define S_028A38_W_CONV(x) (((x) & 0x0F) << 24)
6294 #define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F)
6295 #define C_028A38_W_CONV 0xF0FFFFFF
6296 #define V_028A38_VGT_GRP_INDEX_16 0x00
6297 #define V_028A38_VGT_GRP_INDEX_32 0x01
6298 #define V_028A38_VGT_GRP_UINT_16 0x02
6299 #define V_028A38_VGT_GRP_UINT_32 0x03
6300 #define V_028A38_VGT_GRP_SINT_16 0x04
6301 #define V_028A38_VGT_GRP_SINT_32 0x05
6302 #define V_028A38_VGT_GRP_FLOAT_32 0x06
6303 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
6304 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6305 #define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28)
6306 #define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F)
6307 #define C_028A38_W_OFFSET 0x0FFFFFFF
6308 #define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C
6309 #define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0)
6310 #define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F)
6311 #define C_028A3C_X_CONV 0xFFFFFFF0
6312 #define V_028A3C_VGT_GRP_INDEX_16 0x00
6313 #define V_028A3C_VGT_GRP_INDEX_32 0x01
6314 #define V_028A3C_VGT_GRP_UINT_16 0x02
6315 #define V_028A3C_VGT_GRP_UINT_32 0x03
6316 #define V_028A3C_VGT_GRP_SINT_16 0x04
6317 #define V_028A3C_VGT_GRP_SINT_32 0x05
6318 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
6319 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
6320 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6321 #define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4)
6322 #define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F)
6323 #define C_028A3C_X_OFFSET 0xFFFFFF0F
6324 #define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8)
6325 #define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F)
6326 #define C_028A3C_Y_CONV 0xFFFFF0FF
6327 #define V_028A3C_VGT_GRP_INDEX_16 0x00
6328 #define V_028A3C_VGT_GRP_INDEX_32 0x01
6329 #define V_028A3C_VGT_GRP_UINT_16 0x02
6330 #define V_028A3C_VGT_GRP_UINT_32 0x03
6331 #define V_028A3C_VGT_GRP_SINT_16 0x04
6332 #define V_028A3C_VGT_GRP_SINT_32 0x05
6333 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
6334 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
6335 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6336 #define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12)
6337 #define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F)
6338 #define C_028A3C_Y_OFFSET 0xFFFF0FFF
6339 #define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16)
6340 #define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F)
6341 #define C_028A3C_Z_CONV 0xFFF0FFFF
6342 #define V_028A3C_VGT_GRP_INDEX_16 0x00
6343 #define V_028A3C_VGT_GRP_INDEX_32 0x01
6344 #define V_028A3C_VGT_GRP_UINT_16 0x02
6345 #define V_028A3C_VGT_GRP_UINT_32 0x03
6346 #define V_028A3C_VGT_GRP_SINT_16 0x04
6347 #define V_028A3C_VGT_GRP_SINT_32 0x05
6348 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
6349 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
6350 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6351 #define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20)
6352 #define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F)
6353 #define C_028A3C_Z_OFFSET 0xFF0FFFFF
6354 #define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24)
6355 #define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F)
6356 #define C_028A3C_W_CONV 0xF0FFFFFF
6357 #define V_028A3C_VGT_GRP_INDEX_16 0x00
6358 #define V_028A3C_VGT_GRP_INDEX_32 0x01
6359 #define V_028A3C_VGT_GRP_UINT_16 0x02
6360 #define V_028A3C_VGT_GRP_UINT_32 0x03
6361 #define V_028A3C_VGT_GRP_SINT_16 0x04
6362 #define V_028A3C_VGT_GRP_SINT_32 0x05
6363 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
6364 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
6365 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
6366 #define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28)
6367 #define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F)
6368 #define C_028A3C_W_OFFSET 0x0FFFFFFF
6369 #define R_028A40_VGT_GS_MODE 0x028A40
6370 #define S_028A40_MODE(x) (((x) & 0x07) << 0)
6371 #define G_028A40_MODE(x) (((x) >> 0) & 0x07)
6372 #define C_028A40_MODE 0xFFFFFFF8
6373 #define V_028A40_GS_OFF 0x00
6374 #define V_028A40_GS_SCENARIO_A 0x01
6375 #define V_028A40_GS_SCENARIO_B 0x02
6376 #define V_028A40_GS_SCENARIO_G 0x03
6377 #define V_028A40_GS_SCENARIO_C 0x04
6378 #define V_028A40_SPRITE_EN 0x05
6379 #define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4)
6380 #define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03)
6381 #define C_028A40_CUT_MODE 0xFFFFFFCF
6382 #define V_028A40_GS_CUT_1024 0x00
6383 #define V_028A40_GS_CUT_512 0x01
6384 #define V_028A40_GS_CUT_256 0x02
6385 #define V_028A40_GS_CUT_128 0x03
6386 #define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11)
6387 #define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1)
6388 #define C_028A40_GS_C_PACK_EN 0xFFFFF7FF
6389 #define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13)
6390 #define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1)
6391 #define C_028A40_ES_PASSTHRU 0xFFFFDFFF
6392 #define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14)
6393 #define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1)
6394 #define C_028A40_COMPUTE_MODE 0xFFFFBFFF
6395 #define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15)
6396 #define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1)
6397 #define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF
6398 #define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16)
6399 #define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1)
6400 #define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF
6401 #define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17)
6402 #define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1)
6403 #define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF
6404 #define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18)
6405 #define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1)
6406 #define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF
6407 #define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19)
6408 #define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1)
6409 #define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF
6410 #define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20)
6411 #define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1)
6412 #define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF
6413 #define R_028A48_PA_SC_MODE_CNTL_0 0x028A48
6414 #define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0)
6415 #define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1)
6416 #define C_028A48_MSAA_ENABLE 0xFFFFFFFE
6417 #define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1)
6418 #define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1)
6419 #define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD
6420 #define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2)
6421 #define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1)
6422 #define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB
6423 #define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3)
6424 #define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1)
6425 #define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7
6426 #define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
6427 #define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0)
6428 #define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1)
6429 #define C_028A4C_WALK_SIZE 0xFFFFFFFE
6430 #define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1)
6431 #define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1)
6432 #define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD
6433 #define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2)
6434 #define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1)
6435 #define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB
6436 #define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3)
6437 #define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1)
6438 #define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7
6439 #define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4)
6440 #define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07)
6441 #define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F
6442 #define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7)
6443 #define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1)
6444 #define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F
6445 #define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8)
6446 #define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1)
6447 #define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF
6448 #define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9)
6449 #define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1)
6450 #define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF
6451 #define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10)
6452 #define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1)
6453 #define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF
6454 #define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11)
6455 #define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1)
6456 #define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF
6457 #define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12)
6458 #define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1)
6459 #define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF
6460 #define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13)
6461 #define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1)
6462 #define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF
6463 #define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14)
6464 #define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1)
6465 #define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF
6466 #define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15)
6467 #define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1)
6468 #define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF
6469 #define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16)
6470 #define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1)
6471 #define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF
6472 #define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) & 0x1) << 17)
6473 #define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) >> 17) & 0x1)
6474 #define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC 0xFFFDFFFF
6475 #define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25)
6476 #define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1)
6477 #define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF
6478 #define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26)
6479 #define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1)
6480 #define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF
6481 #define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27)
6482 #define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1)
6483 #define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF
6484 #define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28)
6485 #define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07)
6486 #define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF
6487 #define R_028A50_VGT_ENHANCE 0x028A50
6488 #define R_028A54_VGT_GS_PER_ES 0x028A54
6489 #define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0)
6490 #define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF)
6491 #define C_028A54_GS_PER_ES 0xFFFFF800
6492 #define R_028A58_VGT_ES_PER_GS 0x028A58
6493 #define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0)
6494 #define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF)
6495 #define C_028A58_ES_PER_GS 0xFFFFF800
6496 #define R_028A5C_VGT_GS_PER_VS 0x028A5C
6497 #define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0)
6498 #define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F)
6499 #define C_028A5C_GS_PER_VS 0xFFFFFFF0
6500 #define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60
6501 #define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0)
6502 #define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF)
6503 #define C_028A60_OFFSET 0xFFFF8000
6504 #define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64
6505 #define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0)
6506 #define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF)
6507 #define C_028A64_OFFSET 0xFFFF8000
6508 #define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68
6509 #define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0)
6510 #define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF)
6511 #define C_028A68_OFFSET 0xFFFF8000
6512 #define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C
6513 #define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0)
6514 #define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F)
6515 #define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0
6516 #define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8)
6517 #define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F)
6518 #define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF
6519 #define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16)
6520 #define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F)
6521 #define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF
6522 #define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22)
6523 #define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F)
6524 #define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF
6525 #define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31)
6526 #define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1)
6527 #define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF
6528 #define R_028A70_IA_ENHANCE 0x028A70
6529 #define R_028A74_VGT_DMA_SIZE 0x028A74
6530 #define R_028A78_VGT_DMA_MAX_SIZE 0x028A78
6531 #define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C
6532 #define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0)
6533 #define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
6534 #define C_028A7C_INDEX_TYPE 0xFFFFFFFC
6535 #define V_028A7C_VGT_INDEX_16 0x00
6536 #define V_028A7C_VGT_INDEX_32 0x01
6537 #define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2)
6538 #define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03)
6539 #define C_028A7C_SWAP_MODE 0xFFFFFFF3
6540 #define V_028A7C_VGT_DMA_SWAP_NONE 0x00
6541 #define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01
6542 #define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02
6543 #define V_028A7C_VGT_DMA_SWAP_WORD 0x03
6544 #define R_028A84_VGT_PRIMITIVEID_EN 0x028A84
6545 #define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0)
6546 #define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1)
6547 #define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE
6548 #define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1)
6549 #define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1)
6550 #define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD
6551 #define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88
6552 #define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C
6553 #define R_028A90_VGT_EVENT_INITIATOR 0x028A90
6554 #define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0)
6555 #define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F)
6556 #define C_028A90_EVENT_TYPE 0xFFFFFFC0
6557 #define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01
6558 #define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02
6559 #define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03
6560 #define V_028A90_CACHE_FLUSH_TS 0x04
6561 #define V_028A90_CONTEXT_DONE 0x05
6562 #define V_028A90_CACHE_FLUSH 0x06
6563 #define V_028A90_CS_PARTIAL_FLUSH 0x07
6564 #define V_028A90_VGT_STREAMOUT_SYNC 0x08
6565 #define V_028A90_VGT_STREAMOUT_RESET 0x0A
6566 #define V_028A90_END_OF_PIPE_INCR_DE 0x0B
6567 #define V_028A90_END_OF_PIPE_IB_END 0x0C
6568 #define V_028A90_RST_PIX_CNT 0x0D
6569 #define V_028A90_VS_PARTIAL_FLUSH 0x0F
6570 #define V_028A90_PS_PARTIAL_FLUSH 0x10
6571 #define V_028A90_FLUSH_HS_OUTPUT 0x11
6572 #define V_028A90_FLUSH_LS_OUTPUT 0x12
6573 #define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
6574 #define V_028A90_ZPASS_DONE 0x15
6575 #define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16
6576 #define V_028A90_PERFCOUNTER_START 0x17
6577 #define V_028A90_PERFCOUNTER_STOP 0x18
6578 #define V_028A90_PIPELINESTAT_START 0x19
6579 #define V_028A90_PIPELINESTAT_STOP 0x1A
6580 #define V_028A90_PERFCOUNTER_SAMPLE 0x1B
6581 #define V_028A90_FLUSH_ES_OUTPUT 0x1C
6582 #define V_028A90_FLUSH_GS_OUTPUT 0x1D
6583 #define V_028A90_SAMPLE_PIPELINESTAT 0x1E
6584 #define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F
6585 #define V_028A90_SAMPLE_STREAMOUTSTATS 0x20
6586 #define V_028A90_RESET_VTX_CNT 0x21
6587 #define V_028A90_BLOCK_CONTEXT_DONE 0x22
6588 #define V_028A90_CS_CONTEXT_DONE 0x23
6589 #define V_028A90_VGT_FLUSH 0x24
6590 #define V_028A90_SC_SEND_DB_VPZ 0x27
6591 #define V_028A90_BOTTOM_OF_PIPE_TS 0x28
6592 #define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A
6593 #define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B
6594 #define V_028A90_FLUSH_AND_INV_DB_META 0x2C
6595 #define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D
6596 #define V_028A90_FLUSH_AND_INV_CB_META 0x2E
6597 #define V_028A90_CS_DONE 0x2F
6598 #define V_028A90_PS_DONE 0x30
6599 #define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31
6600 #define V_028A90_THREAD_TRACE_START 0x33
6601 #define V_028A90_THREAD_TRACE_STOP 0x34
6602 #define V_028A90_THREAD_TRACE_MARKER 0x35
6603 #define V_028A90_THREAD_TRACE_FLUSH 0x36
6604 #define V_028A90_THREAD_TRACE_FINISH 0x37
6605 #define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18)
6606 #define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF)
6607 #define C_028A90_ADDRESS_HI 0xF803FFFF
6608 #define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27)
6609 #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1)
6610 #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF
6611 #define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94
6612 #define S_028A94_RESET_EN(x) (((x) & 0x1) << 0)
6613 #define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1)
6614 #define C_028A94_RESET_EN 0xFFFFFFFE
6615 #define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0
6616 #define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4
6617 #define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8
6618 #define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0)
6619 #define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF)
6620 #define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000
6621 #define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16)
6622 #define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1)
6623 #define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF
6624 #define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17)
6625 #define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1)
6626 #define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF
6627 #define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18)
6628 #define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1)
6629 #define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF
6630 #define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19)
6631 #define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1)
6632 #define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF
6633 #define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC
6634 #define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
6635 #define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
6636 #define C_028AAC_ITEMSIZE 0xFFFF8000
6637 #define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0
6638 #define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
6639 #define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
6640 #define C_028AB0_ITEMSIZE 0xFFFF8000
6641 #define R_028AB4_VGT_REUSE_OFF 0x028AB4
6642 #define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0)
6643 #define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1)
6644 #define C_028AB4_REUSE_OFF 0xFFFFFFFE
6645 #define R_028AB8_VGT_VTX_CNT_EN 0x028AB8
6646 #define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0)
6647 #define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1)
6648 #define C_028AB8_VTX_CNT_EN 0xFFFFFFFE
6649 #define R_028ABC_DB_HTILE_SURFACE 0x028ABC
6650 #define S_028ABC_LINEAR(x) (((x) & 0x1) << 0)
6651 #define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1)
6652 #define C_028ABC_LINEAR 0xFFFFFFFE
6653 #define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1)
6654 #define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1)
6655 #define C_028ABC_FULL_CACHE 0xFFFFFFFD
6656 #define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2)
6657 #define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1)
6658 #define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB
6659 #define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3)
6660 #define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1)
6661 #define C_028ABC_PRELOAD 0xFFFFFFF7
6662 #define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4)
6663 #define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F)
6664 #define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F
6665 #define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10)
6666 #define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F)
6667 #define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF
6668 #define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16)
6669 #define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1)
6670 #define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF
6671 #define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0
6672 #define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0)
6673 #define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07)
6674 #define C_028AC0_COMPAREFUNC0 0xFFFFFFF8
6675 #define V_028AC0_REF_NEVER 0x00
6676 #define V_028AC0_REF_LESS 0x01
6677 #define V_028AC0_REF_EQUAL 0x02
6678 #define V_028AC0_REF_LEQUAL 0x03
6679 #define V_028AC0_REF_GREATER 0x04
6680 #define V_028AC0_REF_NOTEQUAL 0x05
6681 #define V_028AC0_REF_GEQUAL 0x06
6682 #define V_028AC0_REF_ALWAYS 0x07
6683 #define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4)
6684 #define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF)
6685 #define C_028AC0_COMPAREVALUE0 0xFFFFF00F
6686 #define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12)
6687 #define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF)
6688 #define C_028AC0_COMPAREMASK0 0xFFF00FFF
6689 #define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24)
6690 #define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1)
6691 #define C_028AC0_ENABLE0 0xFEFFFFFF
6692 #define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4
6693 #define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0)
6694 #define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07)
6695 #define C_028AC4_COMPAREFUNC1 0xFFFFFFF8
6696 #define V_028AC4_REF_NEVER 0x00
6697 #define V_028AC4_REF_LESS 0x01
6698 #define V_028AC4_REF_EQUAL 0x02
6699 #define V_028AC4_REF_LEQUAL 0x03
6700 #define V_028AC4_REF_GREATER 0x04
6701 #define V_028AC4_REF_NOTEQUAL 0x05
6702 #define V_028AC4_REF_GEQUAL 0x06
6703 #define V_028AC4_REF_ALWAYS 0x07
6704 #define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4)
6705 #define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF)
6706 #define C_028AC4_COMPAREVALUE1 0xFFFFF00F
6707 #define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12)
6708 #define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF)
6709 #define C_028AC4_COMPAREMASK1 0xFFF00FFF
6710 #define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24)
6711 #define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1)
6712 #define C_028AC4_ENABLE1 0xFEFFFFFF
6713 #define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8
6714 #define S_028AC8_START_X(x) (((x) & 0xFF) << 0)
6715 #define G_028AC8_START_X(x) (((x) >> 0) & 0xFF)
6716 #define C_028AC8_START_X 0xFFFFFF00
6717 #define S_028AC8_START_Y(x) (((x) & 0xFF) << 8)
6718 #define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF)
6719 #define C_028AC8_START_Y 0xFFFF00FF
6720 #define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16)
6721 #define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF)
6722 #define C_028AC8_MAX_X 0xFF00FFFF
6723 #define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24)
6724 #define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF)
6725 #define C_028AC8_MAX_Y 0x00FFFFFF
6726 #define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0
6727 #define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4
6728 #define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0)
6729 #define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF)
6730 #define C_028AD4_STRIDE 0xFFFFFC00
6731 #define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC
6732 #define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0
6733 #define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4
6734 #define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0)
6735 #define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF)
6736 #define C_028AE4_STRIDE 0xFFFFFC00
6737 #define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC
6738 #define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0
6739 #define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4
6740 #define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0)
6741 #define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF)
6742 #define C_028AF4_STRIDE 0xFFFFFC00
6743 #define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC
6744 #define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00
6745 #define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04
6746 #define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0)
6747 #define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF)
6748 #define C_028B04_STRIDE 0xFFFFFC00
6749 #define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C
6750 #define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28
6751 #define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C
6752 #define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30
6753 #define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0)
6754 #define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF)
6755 #define C_028B30_VERTEX_STRIDE 0xFFFFFE00
6756 #define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38
6757 #define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0)
6758 #define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF)
6759 #define C_028B38_MAX_VERT_OUT 0xFFFFF800
6760 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
6761 #define S_028B54_LS_EN(x) (((x) & 0x03) << 0)
6762 #define G_028B54_LS_EN(x) (((x) >> 0) & 0x03)
6763 #define C_028B54_LS_EN 0xFFFFFFFC
6764 #define V_028B54_LS_STAGE_OFF 0x00
6765 #define V_028B54_LS_STAGE_ON 0x01
6766 #define V_028B54_CS_STAGE_ON 0x02
6767 #define S_028B54_HS_EN(x) (((x) & 0x1) << 2)
6768 #define G_028B54_HS_EN(x) (((x) >> 2) & 0x1)
6769 #define C_028B54_HS_EN 0xFFFFFFFB
6770 #define S_028B54_ES_EN(x) (((x) & 0x03) << 3)
6771 #define G_028B54_ES_EN(x) (((x) >> 3) & 0x03)
6772 #define C_028B54_ES_EN 0xFFFFFFE7
6773 #define V_028B54_ES_STAGE_OFF 0x00
6774 #define V_028B54_ES_STAGE_DS 0x01
6775 #define V_028B54_ES_STAGE_REAL 0x02
6776 #define S_028B54_GS_EN(x) (((x) & 0x1) << 5)
6777 #define G_028B54_GS_EN(x) (((x) >> 5) & 0x1)
6778 #define C_028B54_GS_EN 0xFFFFFFDF
6779 #define S_028B54_VS_EN(x) (((x) & 0x03) << 6)
6780 #define G_028B54_VS_EN(x) (((x) >> 6) & 0x03)
6781 #define C_028B54_VS_EN 0xFFFFFF3F
6782 #define V_028B54_VS_STAGE_REAL 0x00
6783 #define V_028B54_VS_STAGE_DS 0x01
6784 #define V_028B54_VS_STAGE_COPY_SHADER 0x02
6785 #define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8)
6786 #define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1)
6787 #define C_028B54_DYNAMIC_HS 0xFFFFFEFF
6788 #define R_028B58_VGT_LS_HS_CONFIG 0x028B58
6789 #define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0)
6790 #define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF)
6791 #define C_028B58_NUM_PATCHES 0xFFFFFF00
6792 #define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8)
6793 #define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F)
6794 #define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF
6795 #define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14)
6796 #define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F)
6797 #define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF
6798 #define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C
6799 #define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
6800 #define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
6801 #define C_028B5C_ITEMSIZE 0xFFFF8000
6802 #define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60
6803 #define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
6804 #define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
6805 #define C_028B60_ITEMSIZE 0xFFFF8000
6806 #define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64
6807 #define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
6808 #define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
6809 #define C_028B64_ITEMSIZE 0xFFFF8000
6810 #define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68
6811 #define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
6812 #define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
6813 #define C_028B68_ITEMSIZE 0xFFFF8000
6814 #define R_028B6C_VGT_TF_PARAM 0x028B6C
6815 #define S_028B6C_TYPE(x) (((x) & 0x03) << 0)
6816 #define G_028B6C_TYPE(x) (((x) >> 0) & 0x03)
6817 #define C_028B6C_TYPE 0xFFFFFFFC
6818 #define V_028B6C_TESS_ISOLINE 0x00
6819 #define V_028B6C_TESS_TRIANGLE 0x01
6820 #define V_028B6C_TESS_QUAD 0x02
6821 #define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2)
6822 #define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07)
6823 #define C_028B6C_PARTITIONING 0xFFFFFFE3
6824 #define V_028B6C_PART_INTEGER 0x00
6825 #define V_028B6C_PART_POW2 0x01
6826 #define V_028B6C_PART_FRAC_ODD 0x02
6827 #define V_028B6C_PART_FRAC_EVEN 0x03
6828 #define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5)
6829 #define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07)
6830 #define C_028B6C_TOPOLOGY 0xFFFFFF1F
6831 #define V_028B6C_OUTPUT_POINT 0x00
6832 #define V_028B6C_OUTPUT_LINE 0x01
6833 #define V_028B6C_OUTPUT_TRIANGLE_CW 0x02
6834 #define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03
6835 #define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8)
6836 #define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1)
6837 #define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF
6838 #define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10)
6839 #define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F)
6840 #define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF
6841 #define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14)
6842 #define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1)
6843 #define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF
6844 #define R_028B70_DB_ALPHA_TO_MASK 0x028B70
6845 #define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
6846 #define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1)
6847 #define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE
6848 #define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8)
6849 #define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03)
6850 #define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF
6851 #define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10)
6852 #define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03)
6853 #define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF
6854 #define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12)
6855 #define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03)
6856 #define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF
6857 #define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14)
6858 #define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03)
6859 #define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF
6860 #define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16)
6861 #define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1)
6862 #define C_028B70_OFFSET_ROUND 0xFFFEFFFF
6863 #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78
6864 #define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0)
6865 #define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF)
6866 #define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00
6867 #define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8)
6868 #define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1)
6869 #define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF
6870 #define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C
6871 #define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80
6872 #define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84
6873 #define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88
6874 #define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C
6875 #define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90
6876 #define S_028B90_ENABLE(x) (((x) & 0x1) << 0)
6877 #define G_028B90_ENABLE(x) (((x) >> 0) & 0x1)
6878 #define C_028B90_ENABLE 0xFFFFFFFE
6879 #define S_028B90_CNT(x) (((x) & 0x7F) << 2)
6880 #define G_028B90_CNT(x) (((x) >> 2) & 0x7F)
6881 #define C_028B90_CNT 0xFFFFFE03
6882 #define R_028B94_VGT_STRMOUT_CONFIG 0x028B94
6883 #define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0)
6884 #define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1)
6885 #define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE
6886 #define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1)
6887 #define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1)
6888 #define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD
6889 #define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2)
6890 #define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1)
6891 #define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB
6892 #define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3)
6893 #define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1)
6894 #define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7
6895 #define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4)
6896 #define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07)
6897 #define C_028B94_RAST_STREAM 0xFFFFFF8F
6898 #define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8)
6899 #define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F)
6900 #define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF
6901 #define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31)
6902 #define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1)
6903 #define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF
6904 #define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98
6905 #define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0)
6906 #define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F)
6907 #define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0
6908 #define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4)
6909 #define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F)
6910 #define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F
6911 #define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8)
6912 #define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F)
6913 #define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF
6914 #define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12)
6915 #define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
6916 #define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
6917 #define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4
6918 #define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0)
6919 #define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F)
6920 #define C_028BD4_DISTANCE_0 0xFFFFFFF0
6921 #define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4)
6922 #define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F)
6923 #define C_028BD4_DISTANCE_1 0xFFFFFF0F
6924 #define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8)
6925 #define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F)
6926 #define C_028BD4_DISTANCE_2 0xFFFFF0FF
6927 #define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12)
6928 #define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F)
6929 #define C_028BD4_DISTANCE_3 0xFFFF0FFF
6930 #define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16)
6931 #define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F)
6932 #define C_028BD4_DISTANCE_4 0xFFF0FFFF
6933 #define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20)
6934 #define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F)
6935 #define C_028BD4_DISTANCE_5 0xFF0FFFFF
6936 #define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24)
6937 #define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F)
6938 #define C_028BD4_DISTANCE_6 0xF0FFFFFF
6939 #define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28)
6940 #define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F)
6941 #define C_028BD4_DISTANCE_7 0x0FFFFFFF
6942 #define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8
6943 #define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0)
6944 #define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F)
6945 #define C_028BD8_DISTANCE_8 0xFFFFFFF0
6946 #define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4)
6947 #define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F)
6948 #define C_028BD8_DISTANCE_9 0xFFFFFF0F
6949 #define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8)
6950 #define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F)
6951 #define C_028BD8_DISTANCE_10 0xFFFFF0FF
6952 #define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12)
6953 #define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F)
6954 #define C_028BD8_DISTANCE_11 0xFFFF0FFF
6955 #define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16)
6956 #define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F)
6957 #define C_028BD8_DISTANCE_12 0xFFF0FFFF
6958 #define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20)
6959 #define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F)
6960 #define C_028BD8_DISTANCE_13 0xFF0FFFFF
6961 #define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24)
6962 #define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F)
6963 #define C_028BD8_DISTANCE_14 0xF0FFFFFF
6964 #define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28)
6965 #define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F)
6966 #define C_028BD8_DISTANCE_15 0x0FFFFFFF
6967 #define R_028BDC_PA_SC_LINE_CNTL 0x028BDC
6968 #define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9)
6969 #define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
6970 #define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
6971 #define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10)
6972 #define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
6973 #define C_028BDC_LAST_PIXEL 0xFFFFFBFF
6974 #define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11)
6975 #define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
6976 #define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
6977 #define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12)
6978 #define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
6979 #define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
6980 #define R_028BE0_PA_SC_AA_CONFIG 0x028BE0
6981 #define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x07) << 0)
6982 #define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07)
6983 #define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8
6984 #define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
6985 #define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
6986 #define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
6987 #define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0x0F) << 13)
6988 #define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F)
6989 #define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF
6990 #define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x07) << 20)
6991 #define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07)
6992 #define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF
6993 #define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x03) << 24)
6994 #define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03)
6995 #define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF
6996 #define R_028BE4_PA_SU_VTX_CNTL 0x028BE4
6997 #define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0)
6998 #define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1)
6999 #define C_028BE4_PIX_CENTER 0xFFFFFFFE
7000 #define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1)
7001 #define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03)
7002 #define C_028BE4_ROUND_MODE 0xFFFFFFF9
7003 #define V_028BE4_X_TRUNCATE 0x00
7004 #define V_028BE4_X_ROUND 0x01
7005 #define V_028BE4_X_ROUND_TO_EVEN 0x02
7006 #define V_028BE4_X_ROUND_TO_ODD 0x03
7007 #define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3)
7008 #define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07)
7009 #define C_028BE4_QUANT_MODE 0xFFFFFFC7
7010 #define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00
7011 #define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01
7012 #define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02
7013 #define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03
7014 #define V_028BE4_X_16_8_FIXED_POINT_1 0x04
7015 #define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05
7016 #define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06
7017 #define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07
7018 #define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8
7019 #define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC
7020 #define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0
7021 #define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4
7022 #define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8
7023 #define S_028BF8_S0_X(x) (((x) & 0x0F) << 0)
7024 #define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F)
7025 #define C_028BF8_S0_X 0xFFFFFFF0
7026 #define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4)
7027 #define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F)
7028 #define C_028BF8_S0_Y 0xFFFFFF0F
7029 #define S_028BF8_S1_X(x) (((x) & 0x0F) << 8)
7030 #define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F)
7031 #define C_028BF8_S1_X 0xFFFFF0FF
7032 #define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12)
7033 #define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F)
7034 #define C_028BF8_S1_Y 0xFFFF0FFF
7035 #define S_028BF8_S2_X(x) (((x) & 0x0F) << 16)
7036 #define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F)
7037 #define C_028BF8_S2_X 0xFFF0FFFF
7038 #define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20)
7039 #define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F)
7040 #define C_028BF8_S2_Y 0xFF0FFFFF
7041 #define S_028BF8_S3_X(x) (((x) & 0x0F) << 24)
7042 #define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F)
7043 #define C_028BF8_S3_X 0xF0FFFFFF
7044 #define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28)
7045 #define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F)
7046 #define C_028BF8_S3_Y 0x0FFFFFFF
7047 #define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC
7048 #define S_028BFC_S4_X(x) (((x) & 0x0F) << 0)
7049 #define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F)
7050 #define C_028BFC_S4_X 0xFFFFFFF0
7051 #define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4)
7052 #define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F)
7053 #define C_028BFC_S4_Y 0xFFFFFF0F
7054 #define S_028BFC_S5_X(x) (((x) & 0x0F) << 8)
7055 #define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F)
7056 #define C_028BFC_S5_X 0xFFFFF0FF
7057 #define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12)
7058 #define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F)
7059 #define C_028BFC_S5_Y 0xFFFF0FFF
7060 #define S_028BFC_S6_X(x) (((x) & 0x0F) << 16)
7061 #define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F)
7062 #define C_028BFC_S6_X 0xFFF0FFFF
7063 #define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20)
7064 #define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F)
7065 #define C_028BFC_S6_Y 0xFF0FFFFF
7066 #define S_028BFC_S7_X(x) (((x) & 0x0F) << 24)
7067 #define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F)
7068 #define C_028BFC_S7_X 0xF0FFFFFF
7069 #define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28)
7070 #define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F)
7071 #define C_028BFC_S7_Y 0x0FFFFFFF
7072 #define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00
7073 #define S_028C00_S8_X(x) (((x) & 0x0F) << 0)
7074 #define G_028C00_S8_X(x) (((x) >> 0) & 0x0F)
7075 #define C_028C00_S8_X 0xFFFFFFF0
7076 #define S_028C00_S8_Y(x) (((x) & 0x0F) << 4)
7077 #define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F)
7078 #define C_028C00_S8_Y 0xFFFFFF0F
7079 #define S_028C00_S9_X(x) (((x) & 0x0F) << 8)
7080 #define G_028C00_S9_X(x) (((x) >> 8) & 0x0F)
7081 #define C_028C00_S9_X 0xFFFFF0FF
7082 #define S_028C00_S9_Y(x) (((x) & 0x0F) << 12)
7083 #define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F)
7084 #define C_028C00_S9_Y 0xFFFF0FFF
7085 #define S_028C00_S10_X(x) (((x) & 0x0F) << 16)
7086 #define G_028C00_S10_X(x) (((x) >> 16) & 0x0F)
7087 #define C_028C00_S10_X 0xFFF0FFFF
7088 #define S_028C00_S10_Y(x) (((x) & 0x0F) << 20)
7089 #define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F)
7090 #define C_028C00_S10_Y 0xFF0FFFFF
7091 #define S_028C00_S11_X(x) (((x) & 0x0F) << 24)
7092 #define G_028C00_S11_X(x) (((x) >> 24) & 0x0F)
7093 #define C_028C00_S11_X 0xF0FFFFFF
7094 #define S_028C00_S11_Y(x) (((x) & 0x0F) << 28)
7095 #define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F)
7096 #define C_028C00_S11_Y 0x0FFFFFFF
7097 #define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04
7098 #define S_028C04_S12_X(x) (((x) & 0x0F) << 0)
7099 #define G_028C04_S12_X(x) (((x) >> 0) & 0x0F)
7100 #define C_028C04_S12_X 0xFFFFFFF0
7101 #define S_028C04_S12_Y(x) (((x) & 0x0F) << 4)
7102 #define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F)
7103 #define C_028C04_S12_Y 0xFFFFFF0F
7104 #define S_028C04_S13_X(x) (((x) & 0x0F) << 8)
7105 #define G_028C04_S13_X(x) (((x) >> 8) & 0x0F)
7106 #define C_028C04_S13_X 0xFFFFF0FF
7107 #define S_028C04_S13_Y(x) (((x) & 0x0F) << 12)
7108 #define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F)
7109 #define C_028C04_S13_Y 0xFFFF0FFF
7110 #define S_028C04_S14_X(x) (((x) & 0x0F) << 16)
7111 #define G_028C04_S14_X(x) (((x) >> 16) & 0x0F)
7112 #define C_028C04_S14_X 0xFFF0FFFF
7113 #define S_028C04_S14_Y(x) (((x) & 0x0F) << 20)
7114 #define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F)
7115 #define C_028C04_S14_Y 0xFF0FFFFF
7116 #define S_028C04_S15_X(x) (((x) & 0x0F) << 24)
7117 #define G_028C04_S15_X(x) (((x) >> 24) & 0x0F)
7118 #define C_028C04_S15_X 0xF0FFFFFF
7119 #define S_028C04_S15_Y(x) (((x) & 0x0F) << 28)
7120 #define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F)
7121 #define C_028C04_S15_Y 0x0FFFFFFF
7122 #define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08
7123 #define S_028C08_S0_X(x) (((x) & 0x0F) << 0)
7124 #define G_028C08_S0_X(x) (((x) >> 0) & 0x0F)
7125 #define C_028C08_S0_X 0xFFFFFFF0
7126 #define S_028C08_S0_Y(x) (((x) & 0x0F) << 4)
7127 #define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F)
7128 #define C_028C08_S0_Y 0xFFFFFF0F
7129 #define S_028C08_S1_X(x) (((x) & 0x0F) << 8)
7130 #define G_028C08_S1_X(x) (((x) >> 8) & 0x0F)
7131 #define C_028C08_S1_X 0xFFFFF0FF
7132 #define S_028C08_S1_Y(x) (((x) & 0x0F) << 12)
7133 #define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F)
7134 #define C_028C08_S1_Y 0xFFFF0FFF
7135 #define S_028C08_S2_X(x) (((x) & 0x0F) << 16)
7136 #define G_028C08_S2_X(x) (((x) >> 16) & 0x0F)
7137 #define C_028C08_S2_X 0xFFF0FFFF
7138 #define S_028C08_S2_Y(x) (((x) & 0x0F) << 20)
7139 #define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F)
7140 #define C_028C08_S2_Y 0xFF0FFFFF
7141 #define S_028C08_S3_X(x) (((x) & 0x0F) << 24)
7142 #define G_028C08_S3_X(x) (((x) >> 24) & 0x0F)
7143 #define C_028C08_S3_X 0xF0FFFFFF
7144 #define S_028C08_S3_Y(x) (((x) & 0x0F) << 28)
7145 #define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F)
7146 #define C_028C08_S3_Y 0x0FFFFFFF
7147 #define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C
7148 #define S_028C0C_S4_X(x) (((x) & 0x0F) << 0)
7149 #define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F)
7150 #define C_028C0C_S4_X 0xFFFFFFF0
7151 #define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4)
7152 #define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F)
7153 #define C_028C0C_S4_Y 0xFFFFFF0F
7154 #define S_028C0C_S5_X(x) (((x) & 0x0F) << 8)
7155 #define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F)
7156 #define C_028C0C_S5_X 0xFFFFF0FF
7157 #define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12)
7158 #define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F)
7159 #define C_028C0C_S5_Y 0xFFFF0FFF
7160 #define S_028C0C_S6_X(x) (((x) & 0x0F) << 16)
7161 #define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F)
7162 #define C_028C0C_S6_X 0xFFF0FFFF
7163 #define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20)
7164 #define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F)
7165 #define C_028C0C_S6_Y 0xFF0FFFFF
7166 #define S_028C0C_S7_X(x) (((x) & 0x0F) << 24)
7167 #define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F)
7168 #define C_028C0C_S7_X 0xF0FFFFFF
7169 #define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28)
7170 #define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F)
7171 #define C_028C0C_S7_Y 0x0FFFFFFF
7172 #define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10
7173 #define S_028C10_S8_X(x) (((x) & 0x0F) << 0)
7174 #define G_028C10_S8_X(x) (((x) >> 0) & 0x0F)
7175 #define C_028C10_S8_X 0xFFFFFFF0
7176 #define S_028C10_S8_Y(x) (((x) & 0x0F) << 4)
7177 #define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F)
7178 #define C_028C10_S8_Y 0xFFFFFF0F
7179 #define S_028C10_S9_X(x) (((x) & 0x0F) << 8)
7180 #define G_028C10_S9_X(x) (((x) >> 8) & 0x0F)
7181 #define C_028C10_S9_X 0xFFFFF0FF
7182 #define S_028C10_S9_Y(x) (((x) & 0x0F) << 12)
7183 #define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F)
7184 #define C_028C10_S9_Y 0xFFFF0FFF
7185 #define S_028C10_S10_X(x) (((x) & 0x0F) << 16)
7186 #define G_028C10_S10_X(x) (((x) >> 16) & 0x0F)
7187 #define C_028C10_S10_X 0xFFF0FFFF
7188 #define S_028C10_S10_Y(x) (((x) & 0x0F) << 20)
7189 #define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F)
7190 #define C_028C10_S10_Y 0xFF0FFFFF
7191 #define S_028C10_S11_X(x) (((x) & 0x0F) << 24)
7192 #define G_028C10_S11_X(x) (((x) >> 24) & 0x0F)
7193 #define C_028C10_S11_X 0xF0FFFFFF
7194 #define S_028C10_S11_Y(x) (((x) & 0x0F) << 28)
7195 #define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F)
7196 #define C_028C10_S11_Y 0x0FFFFFFF
7197 #define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14
7198 #define S_028C14_S12_X(x) (((x) & 0x0F) << 0)
7199 #define G_028C14_S12_X(x) (((x) >> 0) & 0x0F)
7200 #define C_028C14_S12_X 0xFFFFFFF0
7201 #define S_028C14_S12_Y(x) (((x) & 0x0F) << 4)
7202 #define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F)
7203 #define C_028C14_S12_Y 0xFFFFFF0F
7204 #define S_028C14_S13_X(x) (((x) & 0x0F) << 8)
7205 #define G_028C14_S13_X(x) (((x) >> 8) & 0x0F)
7206 #define C_028C14_S13_X 0xFFFFF0FF
7207 #define S_028C14_S13_Y(x) (((x) & 0x0F) << 12)
7208 #define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F)
7209 #define C_028C14_S13_Y 0xFFFF0FFF
7210 #define S_028C14_S14_X(x) (((x) & 0x0F) << 16)
7211 #define G_028C14_S14_X(x) (((x) >> 16) & 0x0F)
7212 #define C_028C14_S14_X 0xFFF0FFFF
7213 #define S_028C14_S14_Y(x) (((x) & 0x0F) << 20)
7214 #define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F)
7215 #define C_028C14_S14_Y 0xFF0FFFFF
7216 #define S_028C14_S15_X(x) (((x) & 0x0F) << 24)
7217 #define G_028C14_S15_X(x) (((x) >> 24) & 0x0F)
7218 #define C_028C14_S15_X 0xF0FFFFFF
7219 #define S_028C14_S15_Y(x) (((x) & 0x0F) << 28)
7220 #define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F)
7221 #define C_028C14_S15_Y 0x0FFFFFFF
7222 #define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18
7223 #define S_028C18_S0_X(x) (((x) & 0x0F) << 0)
7224 #define G_028C18_S0_X(x) (((x) >> 0) & 0x0F)
7225 #define C_028C18_S0_X 0xFFFFFFF0
7226 #define S_028C18_S0_Y(x) (((x) & 0x0F) << 4)
7227 #define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F)
7228 #define C_028C18_S0_Y 0xFFFFFF0F
7229 #define S_028C18_S1_X(x) (((x) & 0x0F) << 8)
7230 #define G_028C18_S1_X(x) (((x) >> 8) & 0x0F)
7231 #define C_028C18_S1_X 0xFFFFF0FF
7232 #define S_028C18_S1_Y(x) (((x) & 0x0F) << 12)
7233 #define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F)
7234 #define C_028C18_S1_Y 0xFFFF0FFF
7235 #define S_028C18_S2_X(x) (((x) & 0x0F) << 16)
7236 #define G_028C18_S2_X(x) (((x) >> 16) & 0x0F)
7237 #define C_028C18_S2_X 0xFFF0FFFF
7238 #define S_028C18_S2_Y(x) (((x) & 0x0F) << 20)
7239 #define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F)
7240 #define C_028C18_S2_Y 0xFF0FFFFF
7241 #define S_028C18_S3_X(x) (((x) & 0x0F) << 24)
7242 #define G_028C18_S3_X(x) (((x) >> 24) & 0x0F)
7243 #define C_028C18_S3_X 0xF0FFFFFF
7244 #define S_028C18_S3_Y(x) (((x) & 0x0F) << 28)
7245 #define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F)
7246 #define C_028C18_S3_Y 0x0FFFFFFF
7247 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C
7248 #define S_028C1C_S4_X(x) (((x) & 0x0F) << 0)
7249 #define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F)
7250 #define C_028C1C_S4_X 0xFFFFFFF0
7251 #define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4)
7252 #define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F)
7253 #define C_028C1C_S4_Y 0xFFFFFF0F
7254 #define S_028C1C_S5_X(x) (((x) & 0x0F) << 8)
7255 #define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F)
7256 #define C_028C1C_S5_X 0xFFFFF0FF
7257 #define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12)
7258 #define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F)
7259 #define C_028C1C_S5_Y 0xFFFF0FFF
7260 #define S_028C1C_S6_X(x) (((x) & 0x0F) << 16)
7261 #define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F)
7262 #define C_028C1C_S6_X 0xFFF0FFFF
7263 #define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20)
7264 #define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F)
7265 #define C_028C1C_S6_Y 0xFF0FFFFF
7266 #define S_028C1C_S7_X(x) (((x) & 0x0F) << 24)
7267 #define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F)
7268 #define C_028C1C_S7_X 0xF0FFFFFF
7269 #define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28)
7270 #define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F)
7271 #define C_028C1C_S7_Y 0x0FFFFFFF
7272 #define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20
7273 #define S_028C20_S8_X(x) (((x) & 0x0F) << 0)
7274 #define G_028C20_S8_X(x) (((x) >> 0) & 0x0F)
7275 #define C_028C20_S8_X 0xFFFFFFF0
7276 #define S_028C20_S8_Y(x) (((x) & 0x0F) << 4)
7277 #define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F)
7278 #define C_028C20_S8_Y 0xFFFFFF0F
7279 #define S_028C20_S9_X(x) (((x) & 0x0F) << 8)
7280 #define G_028C20_S9_X(x) (((x) >> 8) & 0x0F)
7281 #define C_028C20_S9_X 0xFFFFF0FF
7282 #define S_028C20_S9_Y(x) (((x) & 0x0F) << 12)
7283 #define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F)
7284 #define C_028C20_S9_Y 0xFFFF0FFF
7285 #define S_028C20_S10_X(x) (((x) & 0x0F) << 16)
7286 #define G_028C20_S10_X(x) (((x) >> 16) & 0x0F)
7287 #define C_028C20_S10_X 0xFFF0FFFF
7288 #define S_028C20_S10_Y(x) (((x) & 0x0F) << 20)
7289 #define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F)
7290 #define C_028C20_S10_Y 0xFF0FFFFF
7291 #define S_028C20_S11_X(x) (((x) & 0x0F) << 24)
7292 #define G_028C20_S11_X(x) (((x) >> 24) & 0x0F)
7293 #define C_028C20_S11_X 0xF0FFFFFF
7294 #define S_028C20_S11_Y(x) (((x) & 0x0F) << 28)
7295 #define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F)
7296 #define C_028C20_S11_Y 0x0FFFFFFF
7297 #define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24
7298 #define S_028C24_S12_X(x) (((x) & 0x0F) << 0)
7299 #define G_028C24_S12_X(x) (((x) >> 0) & 0x0F)
7300 #define C_028C24_S12_X 0xFFFFFFF0
7301 #define S_028C24_S12_Y(x) (((x) & 0x0F) << 4)
7302 #define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F)
7303 #define C_028C24_S12_Y 0xFFFFFF0F
7304 #define S_028C24_S13_X(x) (((x) & 0x0F) << 8)
7305 #define G_028C24_S13_X(x) (((x) >> 8) & 0x0F)
7306 #define C_028C24_S13_X 0xFFFFF0FF
7307 #define S_028C24_S13_Y(x) (((x) & 0x0F) << 12)
7308 #define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F)
7309 #define C_028C24_S13_Y 0xFFFF0FFF
7310 #define S_028C24_S14_X(x) (((x) & 0x0F) << 16)
7311 #define G_028C24_S14_X(x) (((x) >> 16) & 0x0F)
7312 #define C_028C24_S14_X 0xFFF0FFFF
7313 #define S_028C24_S14_Y(x) (((x) & 0x0F) << 20)
7314 #define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F)
7315 #define C_028C24_S14_Y 0xFF0FFFFF
7316 #define S_028C24_S15_X(x) (((x) & 0x0F) << 24)
7317 #define G_028C24_S15_X(x) (((x) >> 24) & 0x0F)
7318 #define C_028C24_S15_X 0xF0FFFFFF
7319 #define S_028C24_S15_Y(x) (((x) & 0x0F) << 28)
7320 #define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F)
7321 #define C_028C24_S15_Y 0x0FFFFFFF
7322 #define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28
7323 #define S_028C28_S0_X(x) (((x) & 0x0F) << 0)
7324 #define G_028C28_S0_X(x) (((x) >> 0) & 0x0F)
7325 #define C_028C28_S0_X 0xFFFFFFF0
7326 #define S_028C28_S0_Y(x) (((x) & 0x0F) << 4)
7327 #define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F)
7328 #define C_028C28_S0_Y 0xFFFFFF0F
7329 #define S_028C28_S1_X(x) (((x) & 0x0F) << 8)
7330 #define G_028C28_S1_X(x) (((x) >> 8) & 0x0F)
7331 #define C_028C28_S1_X 0xFFFFF0FF
7332 #define S_028C28_S1_Y(x) (((x) & 0x0F) << 12)
7333 #define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F)
7334 #define C_028C28_S1_Y 0xFFFF0FFF
7335 #define S_028C28_S2_X(x) (((x) & 0x0F) << 16)
7336 #define G_028C28_S2_X(x) (((x) >> 16) & 0x0F)
7337 #define C_028C28_S2_X 0xFFF0FFFF
7338 #define S_028C28_S2_Y(x) (((x) & 0x0F) << 20)
7339 #define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F)
7340 #define C_028C28_S2_Y 0xFF0FFFFF
7341 #define S_028C28_S3_X(x) (((x) & 0x0F) << 24)
7342 #define G_028C28_S3_X(x) (((x) >> 24) & 0x0F)
7343 #define C_028C28_S3_X 0xF0FFFFFF
7344 #define S_028C28_S3_Y(x) (((x) & 0x0F) << 28)
7345 #define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F)
7346 #define C_028C28_S3_Y 0x0FFFFFFF
7347 #define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C
7348 #define S_028C2C_S4_X(x) (((x) & 0x0F) << 0)
7349 #define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F)
7350 #define C_028C2C_S4_X 0xFFFFFFF0
7351 #define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4)
7352 #define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F)
7353 #define C_028C2C_S4_Y 0xFFFFFF0F
7354 #define S_028C2C_S5_X(x) (((x) & 0x0F) << 8)
7355 #define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F)
7356 #define C_028C2C_S5_X 0xFFFFF0FF
7357 #define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12)
7358 #define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F)
7359 #define C_028C2C_S5_Y 0xFFFF0FFF
7360 #define S_028C2C_S6_X(x) (((x) & 0x0F) << 16)
7361 #define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F)
7362 #define C_028C2C_S6_X 0xFFF0FFFF
7363 #define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20)
7364 #define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F)
7365 #define C_028C2C_S6_Y 0xFF0FFFFF
7366 #define S_028C2C_S7_X(x) (((x) & 0x0F) << 24)
7367 #define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F)
7368 #define C_028C2C_S7_X 0xF0FFFFFF
7369 #define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28)
7370 #define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F)
7371 #define C_028C2C_S7_Y 0x0FFFFFFF
7372 #define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30
7373 #define S_028C30_S8_X(x) (((x) & 0x0F) << 0)
7374 #define G_028C30_S8_X(x) (((x) >> 0) & 0x0F)
7375 #define C_028C30_S8_X 0xFFFFFFF0
7376 #define S_028C30_S8_Y(x) (((x) & 0x0F) << 4)
7377 #define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F)
7378 #define C_028C30_S8_Y 0xFFFFFF0F
7379 #define S_028C30_S9_X(x) (((x) & 0x0F) << 8)
7380 #define G_028C30_S9_X(x) (((x) >> 8) & 0x0F)
7381 #define C_028C30_S9_X 0xFFFFF0FF
7382 #define S_028C30_S9_Y(x) (((x) & 0x0F) << 12)
7383 #define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F)
7384 #define C_028C30_S9_Y 0xFFFF0FFF
7385 #define S_028C30_S10_X(x) (((x) & 0x0F) << 16)
7386 #define G_028C30_S10_X(x) (((x) >> 16) & 0x0F)
7387 #define C_028C30_S10_X 0xFFF0FFFF
7388 #define S_028C30_S10_Y(x) (((x) & 0x0F) << 20)
7389 #define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F)
7390 #define C_028C30_S10_Y 0xFF0FFFFF
7391 #define S_028C30_S11_X(x) (((x) & 0x0F) << 24)
7392 #define G_028C30_S11_X(x) (((x) >> 24) & 0x0F)
7393 #define C_028C30_S11_X 0xF0FFFFFF
7394 #define S_028C30_S11_Y(x) (((x) & 0x0F) << 28)
7395 #define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F)
7396 #define C_028C30_S11_Y 0x0FFFFFFF
7397 #define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34
7398 #define S_028C34_S12_X(x) (((x) & 0x0F) << 0)
7399 #define G_028C34_S12_X(x) (((x) >> 0) & 0x0F)
7400 #define C_028C34_S12_X 0xFFFFFFF0
7401 #define S_028C34_S12_Y(x) (((x) & 0x0F) << 4)
7402 #define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F)
7403 #define C_028C34_S12_Y 0xFFFFFF0F
7404 #define S_028C34_S13_X(x) (((x) & 0x0F) << 8)
7405 #define G_028C34_S13_X(x) (((x) >> 8) & 0x0F)
7406 #define C_028C34_S13_X 0xFFFFF0FF
7407 #define S_028C34_S13_Y(x) (((x) & 0x0F) << 12)
7408 #define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F)
7409 #define C_028C34_S13_Y 0xFFFF0FFF
7410 #define S_028C34_S14_X(x) (((x) & 0x0F) << 16)
7411 #define G_028C34_S14_X(x) (((x) >> 16) & 0x0F)
7412 #define C_028C34_S14_X 0xFFF0FFFF
7413 #define S_028C34_S14_Y(x) (((x) & 0x0F) << 20)
7414 #define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F)
7415 #define C_028C34_S14_Y 0xFF0FFFFF
7416 #define S_028C34_S15_X(x) (((x) & 0x0F) << 24)
7417 #define G_028C34_S15_X(x) (((x) >> 24) & 0x0F)
7418 #define C_028C34_S15_X 0xF0FFFFFF
7419 #define S_028C34_S15_Y(x) (((x) & 0x0F) << 28)
7420 #define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F)
7421 #define C_028C34_S15_Y 0x0FFFFFFF
7422 #define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38
7423 #define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0)
7424 #define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF)
7425 #define C_028C38_AA_MASK_X0Y0 0xFFFF0000
7426 #define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16)
7427 #define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF)
7428 #define C_028C38_AA_MASK_X1Y0 0x0000FFFF
7429 #define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C
7430 #define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0)
7431 #define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF)
7432 #define C_028C3C_AA_MASK_X0Y1 0xFFFF0000
7433 #define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16)
7434 #define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF)
7435 #define C_028C3C_AA_MASK_X1Y1 0x0000FFFF
7436 #define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58
7437 #define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
7438 #define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
7439 #define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00
7440 #define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C
7441 #define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0)
7442 #define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F)
7443 #define C_028C5C_DEALLOC_DIST 0xFFFFFF80
7444 #define R_028C60_CB_COLOR0_BASE 0x028C60
7445 #define R_028C64_CB_COLOR0_PITCH 0x028C64
7446 #define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0)
7447 #define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF)
7448 #define C_028C64_TILE_MAX 0xFFFFF800
7449 #define R_028C68_CB_COLOR0_SLICE 0x028C68
7450 #define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
7451 #define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
7452 #define C_028C68_TILE_MAX 0xFFC00000
7453 #define R_028C6C_CB_COLOR0_VIEW 0x028C6C
7454 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
7455 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
7456 #define C_028C6C_SLICE_START 0xFFFFF800
7457 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
7458 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
7459 #define C_028C6C_SLICE_MAX 0xFF001FFF
7460 #define R_028C70_CB_COLOR0_INFO 0x028C70
7461 #define S_028C70_ENDIAN(x) (((x) & 0x03) << 0)
7462 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03)
7463 #define C_028C70_ENDIAN 0xFFFFFFFC
7464 #define V_028C70_ENDIAN_NONE 0x00
7465 #define V_028C70_ENDIAN_8IN16 0x01
7466 #define V_028C70_ENDIAN_8IN32 0x02
7467 #define V_028C70_ENDIAN_8IN64 0x03
7468 #define S_028C70_FORMAT(x) (((x) & 0x1F) << 2)
7469 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F)
7470 #define C_028C70_FORMAT 0xFFFFFF83
7471 #define V_028C70_COLOR_INVALID 0x00
7472 #define V_028C70_COLOR_8 0x01
7473 #define V_028C70_COLOR_16 0x02
7474 #define V_028C70_COLOR_8_8 0x03
7475 #define V_028C70_COLOR_32 0x04
7476 #define V_028C70_COLOR_16_16 0x05
7477 #define V_028C70_COLOR_10_11_11 0x06
7478 #define V_028C70_COLOR_11_11_10 0x07
7479 #define V_028C70_COLOR_10_10_10_2 0x08
7480 #define V_028C70_COLOR_2_10_10_10 0x09
7481 #define V_028C70_COLOR_8_8_8_8 0x0A
7482 #define V_028C70_COLOR_32_32 0x0B
7483 #define V_028C70_COLOR_16_16_16_16 0x0C
7484 #define V_028C70_COLOR_32_32_32_32 0x0E
7485 #define V_028C70_COLOR_5_6_5 0x10
7486 #define V_028C70_COLOR_1_5_5_5 0x11
7487 #define V_028C70_COLOR_5_5_5_1 0x12
7488 #define V_028C70_COLOR_4_4_4_4 0x13
7489 #define V_028C70_COLOR_8_24 0x14
7490 #define V_028C70_COLOR_24_8 0x15
7491 #define V_028C70_COLOR_X24_8_32_FLOAT 0x16
7492 #define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7)
7493 #define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1)
7494 #define C_028C70_LINEAR_GENERAL 0xFFFFFF7F
7495 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8)
7496 #define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07)
7497 #define C_028C70_NUMBER_TYPE 0xFFFFF8FF
7498 #define V_028C70_NUMBER_UNORM 0x00
7499 #define V_028C70_NUMBER_SNORM 0x01
7500 #define V_028C70_NUMBER_UINT 0x04
7501 #define V_028C70_NUMBER_SINT 0x05
7502 #define V_028C70_NUMBER_SRGB 0x06
7503 #define V_028C70_NUMBER_FLOAT 0x07
7504 #define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11)
7505 #define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03)
7506 #define C_028C70_COMP_SWAP 0xFFFFE7FF
7507 #define V_028C70_SWAP_STD 0x00
7508 #define V_028C70_SWAP_ALT 0x01
7509 #define V_028C70_SWAP_STD_REV 0x02
7510 #define V_028C70_SWAP_ALT_REV 0x03
7511 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13)
7512 #define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1)
7513 #define C_028C70_FAST_CLEAR 0xFFFFDFFF
7514 #define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14)
7515 #define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1)
7516 #define C_028C70_COMPRESSION 0xFFFFBFFF
7517 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15)
7518 #define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1)
7519 #define C_028C70_BLEND_CLAMP 0xFFFF7FFF
7520 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16)
7521 #define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1)
7522 #define C_028C70_BLEND_BYPASS 0xFFFEFFFF
7523 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17)
7524 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1)
7525 #define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF
7526 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18)
7527 #define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1)
7528 #define C_028C70_ROUND_MODE 0xFFFBFFFF
7529 #define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19)
7530 #define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1)
7531 #define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF
7532 #define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20)
7533 #define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07)
7534 #define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF
7535 #define V_028C70_FORCE_OPT_AUTO 0x00
7536 #define V_028C70_FORCE_OPT_DISABLE 0x01
7537 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02
7538 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03
7539 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04
7540 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05
7541 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06
7542 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07
7543 #define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23)
7544 #define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07)
7545 #define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF
7546 #define V_028C70_FORCE_OPT_AUTO 0x00
7547 #define V_028C70_FORCE_OPT_DISABLE 0x01
7548 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02
7549 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03
7550 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04
7551 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05
7552 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06
7553 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07
7554 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74
7555 #define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0)
7556 #define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F)
7557 #define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0
7558 #define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5)
7559 #define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F)
7560 #define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F
7561 #define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12)
7562 #define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
7563 #define C_028C74_NUM_SAMPLES 0xFFFF8FFF
7564 #define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15)
7565 #define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03)
7566 #define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF
7567 #define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17)
7568 #define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1)
7569 #define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF
7570 #define R_028C7C_CB_COLOR0_CMASK 0x028C7C
7571 #define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80
7572 #define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0)
7573 #define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF)
7574 #define C_028C80_TILE_MAX 0xFFFFC000
7575 #define R_028C84_CB_COLOR0_FMASK 0x028C84
7576 #define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88
7577 #define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
7578 #define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
7579 #define C_028C88_TILE_MAX 0xFFC00000
7580 #define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C
7581 #define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90
7582 #define R_028C9C_CB_COLOR1_BASE 0x028C9C
7583 #define R_028CA0_CB_COLOR1_PITCH 0x028CA0
7584 #define R_028CA4_CB_COLOR1_SLICE 0x028CA4
7585 #define R_028CA8_CB_COLOR1_VIEW 0x028CA8
7586 #define R_028CAC_CB_COLOR1_INFO 0x028CAC
7587 #define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0
7588 #define R_028CD4_CB_COLOR1_CMASK 0x028CB8
7589 #define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC
7590 #define R_028CC0_CB_COLOR1_FMASK 0x028CC0
7591 #define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4
7592 #define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8
7593 #define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC
7594 #define R_028CD8_CB_COLOR2_BASE 0x028CD8
7595 #define R_028CDC_CB_COLOR2_PITCH 0x028CDC
7596 #define R_028CE0_CB_COLOR2_SLICE 0x028CE0
7597 #define R_028CE4_CB_COLOR2_VIEW 0x028CE4
7598 #define R_028CE8_CB_COLOR2_INFO 0x028CE8
7599 #define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC
7600 #define R_028CF4_CB_COLOR2_CMASK 0x028CF4
7601 #define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8
7602 #define R_028CFC_CB_COLOR2_FMASK 0x028CFC
7603 #define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00
7604 #define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04
7605 #define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08
7606 #define R_028D14_CB_COLOR3_BASE 0x028D14
7607 #define R_028D18_CB_COLOR3_PITCH 0x028D18
7608 #define R_028D1C_CB_COLOR3_SLICE 0x028D1C
7609 #define R_028D20_CB_COLOR3_VIEW 0x028D20
7610 #define R_028D24_CB_COLOR3_INFO 0x028D24
7611 #define R_028D28_CB_COLOR3_ATTRIB 0x028D28
7612 #define R_028D30_CB_COLOR3_CMASK 0x028D30
7613 #define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34
7614 #define R_028D38_CB_COLOR3_FMASK 0x028D38
7615 #define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C
7616 #define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40
7617 #define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44
7618 #define R_028D50_CB_COLOR4_BASE 0x028D50
7619 #define R_028D54_CB_COLOR4_PITCH 0x028D54
7620 #define R_028D58_CB_COLOR4_SLICE 0x028D58
7621 #define R_028D5C_CB_COLOR4_VIEW 0x028D5C
7622 #define R_028D60_CB_COLOR4_INFO 0x028D60
7623 #define R_028D64_CB_COLOR4_ATTRIB 0x028D64
7624 #define R_028D6C_CB_COLOR4_CMASK 0x028D6C
7625 #define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70
7626 #define R_028D74_CB_COLOR4_FMASK 0x028D74
7627 #define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78
7628 #define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C
7629 #define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80
7630 #define R_028D8C_CB_COLOR5_BASE 0x028D8C
7631 #define R_028D90_CB_COLOR5_PITCH 0x028D90
7632 #define R_028D94_CB_COLOR5_SLICE 0x028D94
7633 #define R_028D98_CB_COLOR5_VIEW 0x028D98
7634 #define R_028D9C_CB_COLOR5_INFO 0x028D9C
7635 #define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0
7636 #define R_028DA8_CB_COLOR5_CMASK 0x028DA8
7637 #define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC
7638 #define R_028DB0_CB_COLOR5_FMASK 0x028DB0
7639 #define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4
7640 #define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8
7641 #define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC
7642 #define R_028DC8_CB_COLOR6_BASE 0x028DC8
7643 #define R_028DCC_CB_COLOR6_PITCH 0x028DCC
7644 #define R_028DD0_CB_COLOR6_SLICE 0x028DD0
7645 #define R_028DD4_CB_COLOR6_VIEW 0x028DD4
7646 #define R_028DD8_CB_COLOR6_INFO 0x028DD8
7647 #define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC
7648 #define R_028DE4_CB_COLOR6_CMASK 0x028DE4
7649 #define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8
7650 #define R_028DEC_CB_COLOR6_FMASK 0x028DEC
7651 #define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0
7652 #define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4
7653 #define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8
7654 #define R_028E04_CB_COLOR7_BASE 0x028E04
7655 #define R_028E08_CB_COLOR7_PITCH 0x028E08
7656 #define R_028E0C_CB_COLOR7_SLICE 0x028E0C
7657 #define R_028E10_CB_COLOR7_VIEW 0x028E10
7658 #define R_028E14_CB_COLOR7_INFO 0x028E14
7659 #define R_028E18_CB_COLOR7_ATTRIB 0x028E18
7660 #define R_028E20_CB_COLOR7_CMASK 0x028E20
7661 #define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24
7662 #define R_028E28_CB_COLOR7_FMASK 0x028E28
7663 #define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C
7664 #define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30
7665 #define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34