1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "svga3d_reg.h"
27 #include "svga3d_surfacedefs.h"
29 #include "pipe/p_state.h"
30 #include "pipe/p_defines.h"
31 #include "os/os_thread.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_math.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_context.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource_buffer.h"
44 #include "svga_sampler_view.h"
45 #include "svga_winsys.h"
46 #include "svga_debug.h"
50 svga_transfer_dma_band(struct svga_context *svga,
51 struct svga_transfer *st,
52 SVGA3dTransferType transfer,
53 unsigned x, unsigned y, unsigned z,
54 unsigned w, unsigned h, unsigned d,
55 unsigned srcx, unsigned srcy, unsigned srcz,
56 SVGA3dSurfaceDMAFlags flags)
58 struct svga_texture *texture = svga_texture(st->base.resource);
62 assert(!st->use_direct_map);
74 SVGA_DBG(DEBUG_DMA, "dma %s sid %p, face %u, (%u, %u, %u) - "
75 "(%u, %u, %u), %ubpp\n",
76 transfer == SVGA3D_WRITE_HOST_VRAM ? "to" : "from",
85 util_format_get_blocksize(texture->b.b.format) * 8 /
86 (util_format_get_blockwidth(texture->b.b.format)
87 * util_format_get_blockheight(texture->b.b.format)));
89 ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags);
91 svga_context_flush(svga, NULL);
92 ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags);
93 assert(ret == PIPE_OK);
99 svga_transfer_dma(struct svga_context *svga,
100 struct svga_transfer *st,
101 SVGA3dTransferType transfer,
102 SVGA3dSurfaceDMAFlags flags)
104 struct svga_texture *texture = svga_texture(st->base.resource);
105 struct svga_screen *screen = svga_screen(texture->b.b.screen);
106 struct svga_winsys_screen *sws = screen->sws;
107 struct pipe_fence_handle *fence = NULL;
109 assert(!st->use_direct_map);
111 if (transfer == SVGA3D_READ_HOST_VRAM) {
112 SVGA_DBG(DEBUG_PERF, "%s: readback transfer\n", __FUNCTION__);
115 /* Ensure any pending operations on host surfaces are queued on the command
118 svga_surfaces_flush( svga );
121 /* Do the DMA transfer in a single go */
122 svga_transfer_dma_band(svga, st, transfer,
123 st->base.box.x, st->base.box.y, st->base.box.z,
124 st->base.box.width, st->base.box.height, st->base.box.depth,
128 if (transfer == SVGA3D_READ_HOST_VRAM) {
129 svga_context_flush(svga, &fence);
130 sws->fence_finish(sws, fence, 0);
131 sws->fence_reference(sws, &fence, NULL);
136 unsigned blockheight =
137 util_format_get_blockheight(st->base.resource->format);
139 h = st->hw_nblocksy * blockheight;
142 for (y = 0; y < st->base.box.height; y += h) {
143 unsigned offset, length;
146 if (y + h > st->base.box.height)
147 h = st->base.box.height - y;
149 /* Transfer band must be aligned to pixel block boundaries */
150 assert(y % blockheight == 0);
151 assert(h % blockheight == 0);
153 offset = y * st->base.stride / blockheight;
154 length = h * st->base.stride / blockheight;
156 sw = (uint8_t *) st->swbuf + offset;
158 if (transfer == SVGA3D_WRITE_HOST_VRAM) {
159 unsigned usage = PIPE_TRANSFER_WRITE;
161 /* Wait for the previous DMAs to complete */
162 /* TODO: keep one DMA (at half the size) in the background */
164 svga_context_flush(svga, NULL);
165 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
168 hw = sws->buffer_map(sws, st->hwbuf, usage);
171 memcpy(hw, sw, length);
172 sws->buffer_unmap(sws, st->hwbuf);
176 svga_transfer_dma_band(svga, st, transfer,
177 st->base.box.x, y, st->base.box.z,
178 st->base.box.width, h, st->base.box.depth,
182 * Prevent the texture contents to be discarded on the next band
185 flags.discard = FALSE;
187 if (transfer == SVGA3D_READ_HOST_VRAM) {
188 svga_context_flush(svga, &fence);
189 sws->fence_finish(sws, fence, 0);
191 hw = sws->buffer_map(sws, st->hwbuf, PIPE_TRANSFER_READ);
194 memcpy(sw, hw, length);
195 sws->buffer_unmap(sws, st->hwbuf);
204 svga_texture_get_handle(struct pipe_screen *screen,
205 struct pipe_resource *texture,
206 struct winsys_handle *whandle)
208 struct svga_winsys_screen *sws = svga_winsys_screen(texture->screen);
211 assert(svga_texture(texture)->key.cachable == 0);
212 svga_texture(texture)->key.cachable = 0;
214 stride = util_format_get_nblocksx(texture->format, texture->width0) *
215 util_format_get_blocksize(texture->format);
217 return sws->surface_get_handle(sws, svga_texture(texture)->handle,
223 svga_texture_destroy(struct pipe_screen *screen,
224 struct pipe_resource *pt)
226 struct svga_screen *ss = svga_screen(screen);
227 struct svga_texture *tex = svga_texture(pt);
229 ss->texture_timestamp++;
231 svga_sampler_view_reference(&tex->cached_view, NULL);
234 DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
236 SVGA_DBG(DEBUG_DMA, "unref sid %p (texture)\n", tex->handle);
237 svga_screen_surface_destroy(ss, &tex->key, &tex->handle);
239 ss->hud.total_resource_bytes -= tex->size;
242 FREE(tex->rendered_to);
246 assert(ss->hud.num_resources > 0);
247 if (ss->hud.num_resources > 0)
248 ss->hud.num_resources--;
253 * Determine if we need to read back a texture image before mapping it.
256 need_tex_readback(struct pipe_transfer *transfer)
258 struct svga_texture *t = svga_texture(transfer->resource);
260 if (transfer->usage & PIPE_TRANSFER_READ)
263 if ((transfer->usage & PIPE_TRANSFER_WRITE) &&
264 ((transfer->usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) == 0)) {
267 if (transfer->resource->target == PIPE_TEXTURE_CUBE) {
268 assert(transfer->box.depth == 1);
269 face = transfer->box.z;
274 if (svga_was_texture_rendered_to(t, face, transfer->level)) {
283 static enum pipe_error
284 readback_image_vgpu9(struct svga_context *svga,
285 struct svga_winsys_surface *surf,
291 ret = SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level);
292 if (ret != PIPE_OK) {
293 svga_context_flush(svga, NULL);
294 ret = SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level);
300 static enum pipe_error
301 readback_image_vgpu10(struct svga_context *svga,
302 struct svga_winsys_surface *surf,
305 unsigned numMipLevels)
308 unsigned subResource;
310 subResource = slice * numMipLevels + level;
311 ret = SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf, subResource);
312 if (ret != PIPE_OK) {
313 svga_context_flush(svga, NULL);
314 ret = SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf, subResource);
321 svga_texture_transfer_map(struct pipe_context *pipe,
322 struct pipe_resource *texture,
325 const struct pipe_box *box,
326 struct pipe_transfer **ptransfer)
328 struct svga_context *svga = svga_context(pipe);
329 struct svga_screen *ss = svga_screen(pipe->screen);
330 struct svga_winsys_screen *sws = ss->sws;
331 struct svga_texture *tex = svga_texture(texture);
332 struct svga_transfer *st;
333 unsigned nblocksx, nblocksy;
334 boolean use_direct_map = svga_have_gb_objects(svga) &&
335 !svga_have_gb_dma(svga);
338 int64_t begin = svga_get_time(svga);
340 /* We can't map texture storage directly unless we have GB objects */
341 if (usage & PIPE_TRANSFER_MAP_DIRECTLY) {
342 if (svga_have_gb_objects(svga))
343 use_direct_map = TRUE;
348 st = CALLOC_STRUCT(svga_transfer);
352 st->base.level = level;
353 st->base.usage = usage;
356 switch (tex->b.b.target) {
357 case PIPE_TEXTURE_CUBE:
358 st->slice = st->base.box.z;
359 st->base.box.z = 0; /* so we don't apply double offsets below */
361 case PIPE_TEXTURE_2D_ARRAY:
362 case PIPE_TEXTURE_1D_ARRAY:
363 st->slice = st->base.box.z;
364 st->base.box.z = 0; /* so we don't apply double offsets below */
366 /* Force direct map for transfering multiple slices */
367 if (st->base.box.depth > 1)
368 use_direct_map = svga_have_gb_objects(svga);
378 if (use_direct_map) {
379 /* we'll directly access the guest-backed surface */
380 w = u_minify(texture->width0, level);
381 h = u_minify(texture->height0, level);
382 d = u_minify(texture->depth0, level);
385 /* we'll put the data into a tightly packed buffer */
390 nblocksx = util_format_get_nblocksx(texture->format, w);
391 nblocksy = util_format_get_nblocksy(texture->format, h);
394 pipe_resource_reference(&st->base.resource, texture);
396 st->base.stride = nblocksx*util_format_get_blocksize(texture->format);
397 st->base.layer_stride = st->base.stride * nblocksy;
399 if (usage & PIPE_TRANSFER_WRITE) {
400 /* record texture upload for HUD */
401 svga->hud.num_bytes_uploaded +=
402 nblocksx * nblocksy * d * util_format_get_blocksize(texture->format);
405 if (!use_direct_map) {
406 /* Use a DMA buffer */
407 st->hw_nblocksy = nblocksy;
409 st->hwbuf = svga_winsys_buffer_create(svga, 1, 0,
410 st->hw_nblocksy * st->base.stride * d);
411 while(!st->hwbuf && (st->hw_nblocksy /= 2)) {
412 st->hwbuf = svga_winsys_buffer_create(svga, 1, 0,
413 st->hw_nblocksy * st->base.stride * d);
421 if (st->hw_nblocksy < nblocksy) {
422 /* We couldn't allocate a hardware buffer big enough for the transfer,
423 * so allocate regular malloc memory instead */
425 debug_printf("%s: failed to allocate %u KB of DMA, "
426 "splitting into %u x %u KB DMA transfers\n",
428 (nblocksy*st->base.stride + 1023)/1024,
429 (nblocksy + st->hw_nblocksy - 1)/st->hw_nblocksy,
430 (st->hw_nblocksy*st->base.stride + 1023)/1024);
433 st->swbuf = MALLOC(nblocksy * st->base.stride * d);
435 sws->buffer_destroy(sws, st->hwbuf);
441 if (usage & PIPE_TRANSFER_READ) {
442 SVGA3dSurfaceDMAFlags flags;
443 memset(&flags, 0, sizeof flags);
444 svga_transfer_dma(svga, st, SVGA3D_READ_HOST_VRAM, flags);
447 struct pipe_transfer *transfer = &st->base;
448 struct svga_winsys_surface *surf = tex->handle;
455 /* If this is the first time mapping to the surface in this
456 * command buffer, clear the dirty masks of this surface.
458 if (sws->surface_is_flushed(sws, surf)) {
459 svga_clear_texture_dirty(tex);
462 if (need_tex_readback(transfer)) {
465 svga_surfaces_flush(svga);
467 if (svga_have_vgpu10(svga)) {
468 ret = readback_image_vgpu10(svga, surf, st->slice, transfer->level,
469 tex->b.b.last_level + 1);
471 ret = readback_image_vgpu9(svga, surf, st->slice, transfer->level);
474 svga->hud.num_readbacks++;
476 assert(ret == PIPE_OK);
479 svga_context_flush(svga, NULL);
482 * Note: if PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE were specified
483 * we could potentially clear the flag for all faces/layers/mips.
485 svga_clear_texture_rendered_to(tex, st->slice, transfer->level);
488 assert(transfer->usage & PIPE_TRANSFER_WRITE);
489 if ((transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) == 0) {
490 if (svga_is_texture_dirty(tex, st->slice, transfer->level)) {
492 * do a surface flush if the subresource has been modified
493 * in this command buffer.
495 svga_surfaces_flush(svga);
496 if (!sws->surface_is_flushed(sws, surf)) {
497 svga->hud.surface_write_flushes++;
498 svga_context_flush(svga, NULL);
503 if (transfer->usage & PIPE_TRANSFER_WRITE) {
504 /* mark this texture level as dirty */
505 svga_set_texture_dirty(tex, st->slice, transfer->level);
509 st->use_direct_map = use_direct_map;
511 *ptransfer = &st->base;
517 returnVal = st->swbuf;
519 else if (!st->use_direct_map) {
520 returnVal = sws->buffer_map(sws, st->hwbuf, usage);
523 SVGA3dSize baseLevelSize;
524 struct svga_texture *tex = svga_texture(texture);
525 struct svga_winsys_surface *surf = tex->handle;
528 unsigned offset, mip_width, mip_height;
529 unsigned xoffset = st->base.box.x;
530 unsigned yoffset = st->base.box.y;
531 unsigned zoffset = st->base.box.z;
533 map = svga->swc->surface_map(svga->swc, surf, usage, &retry);
534 if (map == NULL && retry) {
536 * At this point, the svga_surfaces_flush() should already have
537 * called in svga_texture_get_transfer().
539 svga_context_flush(svga, NULL);
540 map = svga->swc->surface_map(svga->swc, surf, usage, &retry);
544 * Make sure we return NULL if the map fails
552 * Compute the offset to the specific texture slice in the buffer.
554 baseLevelSize.width = tex->b.b.width0;
555 baseLevelSize.height = tex->b.b.height0;
556 baseLevelSize.depth = tex->b.b.depth0;
558 if ((tex->b.b.target == PIPE_TEXTURE_1D_ARRAY) ||
559 (tex->b.b.target == PIPE_TEXTURE_2D_ARRAY)) {
560 st->base.layer_stride =
561 svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
562 tex->b.b.last_level + 1, 1, 0);
565 offset = svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
566 tex->b.b.last_level + 1, /* numMips */
572 mip_width = u_minify(tex->b.b.width0, level);
573 mip_height = u_minify(tex->b.b.height0, level);
575 offset += svga3dsurface_get_pixel_offset(tex->key.format,
576 mip_width, mip_height,
577 xoffset, yoffset, zoffset);
578 returnVal = (void *) (map + offset);
581 svga->hud.map_buffer_time += (svga_get_time(svga) - begin);
582 svga->hud.num_resources_mapped++;
589 * Unmap a GB texture surface.
592 svga_texture_surface_unmap(struct svga_context *svga,
593 struct pipe_transfer *transfer)
595 struct svga_winsys_surface *surf = svga_texture(transfer->resource)->handle;
596 struct svga_winsys_context *swc = svga->swc;
601 swc->surface_unmap(swc, surf, &rebind);
604 ret = SVGA3D_BindGBSurface(swc, surf);
605 if (ret != PIPE_OK) {
606 /* flush and retry */
607 svga_context_flush(svga, NULL);
608 ret = SVGA3D_BindGBSurface(swc, surf);
609 assert(ret == PIPE_OK);
615 static enum pipe_error
616 update_image_vgpu9(struct svga_context *svga,
617 struct svga_winsys_surface *surf,
618 const SVGA3dBox *box,
624 ret = SVGA3D_UpdateGBImage(svga->swc, surf, box, slice, level);
625 if (ret != PIPE_OK) {
626 svga_context_flush(svga, NULL);
627 ret = SVGA3D_UpdateGBImage(svga->swc, surf, box, slice, level);
633 static enum pipe_error
634 update_image_vgpu10(struct svga_context *svga,
635 struct svga_winsys_surface *surf,
636 const SVGA3dBox *box,
639 unsigned numMipLevels)
642 unsigned subResource;
644 subResource = slice * numMipLevels + level;
645 ret = SVGA3D_vgpu10_UpdateSubResource(svga->swc, surf, box, subResource);
646 if (ret != PIPE_OK) {
647 svga_context_flush(svga, NULL);
648 ret = SVGA3D_vgpu10_UpdateSubResource(svga->swc, surf, box, subResource);
655 svga_texture_transfer_unmap(struct pipe_context *pipe,
656 struct pipe_transfer *transfer)
658 struct svga_context *svga = svga_context(pipe);
659 struct svga_screen *ss = svga_screen(pipe->screen);
660 struct svga_winsys_screen *sws = ss->sws;
661 struct svga_transfer *st = svga_transfer(transfer);
662 struct svga_texture *tex = svga_texture(transfer->resource);
665 if (st->use_direct_map) {
666 svga_texture_surface_unmap(svga, transfer);
669 sws->buffer_unmap(sws, st->hwbuf);
673 if (!st->use_direct_map && (st->base.usage & PIPE_TRANSFER_WRITE)) {
674 /* Use DMA to transfer texture data */
675 SVGA3dSurfaceDMAFlags flags;
677 memset(&flags, 0, sizeof flags);
678 if (transfer->usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
679 flags.discard = TRUE;
681 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
682 flags.unsynchronized = TRUE;
685 svga_transfer_dma(svga, st, SVGA3D_WRITE_HOST_VRAM, flags);
686 } else if (transfer->usage & PIPE_TRANSFER_WRITE) {
687 struct svga_winsys_surface *surf =
688 svga_texture(transfer->resource)->handle;
691 unsigned nlayers = 1;
693 assert(svga_have_gb_objects(svga));
695 /* update the effected region */
696 box.x = transfer->box.x;
697 box.y = transfer->box.y;
698 box.w = transfer->box.width;
699 box.h = transfer->box.height;
700 box.d = transfer->box.depth;
702 switch (tex->b.b.target) {
703 case PIPE_TEXTURE_CUBE:
706 case PIPE_TEXTURE_2D_ARRAY:
711 case PIPE_TEXTURE_1D_ARRAY:
717 box.z = transfer->box.z;
722 debug_printf("%s %d, %d, %d %d x %d x %d\n",
725 box.w, box.h, box.d);
727 if (svga_have_vgpu10(svga)) {
729 for (i = 0; i < nlayers; i++) {
730 ret = update_image_vgpu10(svga, surf, &box,
731 st->slice + i, transfer->level,
732 tex->b.b.last_level + 1);
733 assert(ret == PIPE_OK);
736 assert(nlayers == 1);
737 ret = update_image_vgpu9(svga, surf, &box, st->slice, transfer->level);
738 assert(ret == PIPE_OK);
741 svga->hud.num_resource_updates++;
746 ss->texture_timestamp++;
747 svga_age_texture_view(tex, transfer->level);
748 if (transfer->resource->target == PIPE_TEXTURE_CUBE)
749 svga_define_texture_level(tex, st->slice, transfer->level);
751 svga_define_texture_level(tex, 0, transfer->level);
753 pipe_resource_reference(&st->base.resource, NULL);
756 if (!st->use_direct_map) {
757 sws->buffer_destroy(sws, st->hwbuf);
764 * Does format store depth values?
766 static inline boolean
767 format_has_depth(enum pipe_format format)
769 const struct util_format_description *desc = util_format_description(format);
770 return util_format_has_depth(desc);
774 struct u_resource_vtbl svga_texture_vtbl =
776 svga_texture_get_handle, /* get_handle */
777 svga_texture_destroy, /* resource_destroy */
778 svga_texture_transfer_map, /* transfer_map */
779 u_default_transfer_flush_region, /* transfer_flush_region */
780 svga_texture_transfer_unmap, /* transfer_unmap */
784 struct pipe_resource *
785 svga_texture_create(struct pipe_screen *screen,
786 const struct pipe_resource *template)
788 struct svga_screen *svgascreen = svga_screen(screen);
789 struct svga_texture *tex;
790 unsigned bindings = template->bind;
792 assert(template->last_level < SVGA_MAX_TEXTURE_LEVELS);
793 if (template->last_level >= SVGA_MAX_TEXTURE_LEVELS) {
797 tex = CALLOC_STRUCT(svga_texture);
802 tex->defined = CALLOC(template->depth0 * template->array_size,
803 sizeof(tex->defined[0]));
809 tex->rendered_to = CALLOC(template->depth0 * template->array_size,
810 sizeof(tex->rendered_to[0]));
811 if (!tex->rendered_to) {
815 tex->dirty = CALLOC(template->depth0 * template->array_size,
816 sizeof(tex->dirty[0]));
821 tex->b.b = *template;
822 tex->b.vtbl = &svga_texture_vtbl;
823 pipe_reference_init(&tex->b.b.reference, 1);
824 tex->b.b.screen = screen;
827 tex->key.size.width = template->width0;
828 tex->key.size.height = template->height0;
829 tex->key.size.depth = template->depth0;
830 tex->key.arraySize = 1;
831 tex->key.numFaces = 1;
832 tex->key.sampleCount = template->nr_samples;
834 if (template->nr_samples > 1) {
835 tex->key.flags |= SVGA3D_SURFACE_MASKABLE_ANTIALIAS;
838 if (svgascreen->sws->have_vgpu10) {
839 switch (template->target) {
840 case PIPE_TEXTURE_1D:
841 tex->key.flags |= SVGA3D_SURFACE_1D;
843 case PIPE_TEXTURE_1D_ARRAY:
844 tex->key.flags |= SVGA3D_SURFACE_1D;
846 case PIPE_TEXTURE_2D_ARRAY:
847 tex->key.flags |= SVGA3D_SURFACE_ARRAY;
848 tex->key.arraySize = template->array_size;
850 case PIPE_TEXTURE_3D:
851 tex->key.flags |= SVGA3D_SURFACE_VOLUME;
853 case PIPE_TEXTURE_CUBE:
854 tex->key.flags |= (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_ARRAY);
855 tex->key.numFaces = 6;
862 switch (template->target) {
863 case PIPE_TEXTURE_3D:
864 tex->key.flags |= SVGA3D_SURFACE_VOLUME;
866 case PIPE_TEXTURE_CUBE:
867 tex->key.flags |= SVGA3D_SURFACE_CUBEMAP;
868 tex->key.numFaces = 6;
875 tex->key.cachable = 1;
877 if ((bindings & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) &&
878 !(bindings & PIPE_BIND_SAMPLER_VIEW)) {
879 /* Also check if the format can be sampled from */
880 if (screen->is_format_supported(screen, template->format,
882 template->nr_samples,
883 PIPE_BIND_SAMPLER_VIEW)) {
884 bindings |= PIPE_BIND_SAMPLER_VIEW;
888 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
889 tex->key.flags |= SVGA3D_SURFACE_HINT_TEXTURE;
890 tex->key.flags |= SVGA3D_SURFACE_BIND_SHADER_RESOURCE;
892 if (!(bindings & PIPE_BIND_RENDER_TARGET)) {
893 /* Also check if the format is renderable */
894 if (screen->is_format_supported(screen, template->format,
896 template->nr_samples,
897 PIPE_BIND_RENDER_TARGET)) {
898 bindings |= PIPE_BIND_RENDER_TARGET;
903 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
904 tex->key.cachable = 0;
907 if (bindings & PIPE_BIND_SHARED) {
908 tex->key.cachable = 0;
911 if (bindings & (PIPE_BIND_SCANOUT | PIPE_BIND_CURSOR)) {
912 tex->key.scanout = 1;
913 tex->key.cachable = 0;
917 * Note: Previously we never passed the
918 * SVGA3D_SURFACE_HINT_RENDERTARGET hint. Mesa cannot
919 * know beforehand whether a texture will be used as a rendertarget or not
920 * and it always requests PIPE_BIND_RENDER_TARGET, therefore
921 * passing the SVGA3D_SURFACE_HINT_RENDERTARGET here defeats its purpose.
923 * However, this was changed since other state trackers
924 * (XA for example) uses it accurately and certain device versions
925 * relies on it in certain situations to render correctly.
927 if ((bindings & PIPE_BIND_RENDER_TARGET) &&
928 !util_format_is_s3tc(template->format)) {
929 tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
930 tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
933 if (bindings & PIPE_BIND_DEPTH_STENCIL) {
934 tex->key.flags |= SVGA3D_SURFACE_HINT_DEPTHSTENCIL;
935 tex->key.flags |= SVGA3D_SURFACE_BIND_DEPTH_STENCIL;
938 tex->key.numMipLevels = template->last_level + 1;
940 tex->key.format = svga_translate_format(svgascreen, template->format,
942 if (tex->key.format == SVGA3D_FORMAT_INVALID) {
946 /* The actual allocation is done with a typeless format. Typeless
947 * formats can be reinterpreted as other formats. For example,
948 * SVGA3D_R8G8B8A8_UNORM_TYPELESS can be interpreted as
949 * SVGA3D_R8G8B8A8_UNORM_SRGB or SVGA3D_R8G8B8A8_UNORM.
950 * Do not use typeless formats for SHARED, DISPLAY_TARGET or SCANOUT
953 if (svgascreen->sws->have_vgpu10
954 && ((bindings & (PIPE_BIND_SHARED |
955 PIPE_BIND_DISPLAY_TARGET |
956 PIPE_BIND_SCANOUT)) == 0)) {
957 SVGA3dSurfaceFormat typeless = svga_typeless_format(tex->key.format);
959 debug_printf("Convert resource type %s -> %s (bind 0x%x)\n",
960 svga_format_name(tex->key.format),
961 svga_format_name(typeless),
965 if (svga_format_is_uncompressed_snorm(tex->key.format)) {
966 /* We can't normally render to snorm surfaces, but once we
967 * substitute a typeless format, we can if the rendertarget view
968 * is unorm. This can happen with GL_ARB_copy_image.
970 tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
971 tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
974 tex->key.format = typeless;
977 SVGA_DBG(DEBUG_DMA, "surface_create for texture\n", tex->handle);
978 tex->handle = svga_screen_surface_create(svgascreen, bindings,
979 tex->b.b.usage, &tex->key);
984 SVGA_DBG(DEBUG_DMA, " --> got sid %p (texture)\n", tex->handle);
986 debug_reference(&tex->b.b.reference,
987 (debug_reference_descriptor)debug_describe_resource, 0);
989 tex->size = util_resource_size(template);
990 svgascreen->hud.total_resource_bytes += tex->size;
991 svgascreen->hud.num_resources++;
998 if (tex->rendered_to)
999 FREE(tex->rendered_to);
1007 struct pipe_resource *
1008 svga_texture_from_handle(struct pipe_screen *screen,
1009 const struct pipe_resource *template,
1010 struct winsys_handle *whandle)
1012 struct svga_winsys_screen *sws = svga_winsys_screen(screen);
1013 struct svga_screen *ss = svga_screen(screen);
1014 struct svga_winsys_surface *srf;
1015 struct svga_texture *tex;
1016 enum SVGA3dSurfaceFormat format = 0;
1019 /* Only supports one type */
1020 if ((template->target != PIPE_TEXTURE_2D &&
1021 template->target != PIPE_TEXTURE_RECT) ||
1022 template->last_level != 0 ||
1023 template->depth0 != 1) {
1027 srf = sws->surface_from_handle(sws, whandle, &format);
1032 if (svga_translate_format(svga_screen(screen), template->format,
1033 template->bind) != format) {
1034 unsigned f1 = svga_translate_format(svga_screen(screen),
1035 template->format, template->bind);
1036 unsigned f2 = format;
1038 /* It's okay for XRGB and ARGB or depth with/out stencil to get mixed up.
1040 if (f1 == SVGA3D_B8G8R8A8_UNORM)
1041 f1 = SVGA3D_A8R8G8B8;
1042 if (f1 == SVGA3D_B8G8R8X8_UNORM)
1043 f1 = SVGA3D_X8R8G8B8;
1045 if ( !( (f1 == f2) ||
1046 (f1 == SVGA3D_X8R8G8B8 && f2 == SVGA3D_A8R8G8B8) ||
1047 (f1 == SVGA3D_X8R8G8B8 && f2 == SVGA3D_B8G8R8X8_UNORM) ||
1048 (f1 == SVGA3D_A8R8G8B8 && f2 == SVGA3D_X8R8G8B8) ||
1049 (f1 == SVGA3D_A8R8G8B8 && f2 == SVGA3D_B8G8R8A8_UNORM) ||
1050 (f1 == SVGA3D_Z_D24X8 && f2 == SVGA3D_Z_D24S8) ||
1051 (f1 == SVGA3D_Z_DF24 && f2 == SVGA3D_Z_D24S8_INT) ) ) {
1052 debug_printf("%s wrong format %s != %s\n", __FUNCTION__,
1053 svga_format_name(f1), svga_format_name(f2));
1058 tex = CALLOC_STRUCT(svga_texture);
1062 tex->defined = CALLOC(template->depth0 * template->array_size,
1063 sizeof(tex->defined[0]));
1064 if (!tex->defined) {
1069 tex->b.b = *template;
1070 tex->b.vtbl = &svga_texture_vtbl;
1071 pipe_reference_init(&tex->b.b.reference, 1);
1072 tex->b.b.screen = screen;
1074 SVGA_DBG(DEBUG_DMA, "wrap surface sid %p\n", srf);
1076 tex->key.cachable = 0;
1077 tex->key.format = format;
1080 tex->rendered_to = CALLOC(1, sizeof(tex->rendered_to[0]));
1081 if (!tex->rendered_to)
1084 tex->dirty = CALLOC(1, sizeof(tex->dirty[0]));
1088 tex->imported = TRUE;
1090 ss->hud.num_resources++;
1097 if (tex->rendered_to)
1098 FREE(tex->rendered_to);
1106 svga_texture_generate_mipmap(struct pipe_context *pipe,
1107 struct pipe_resource *pt,
1108 enum pipe_format format,
1109 unsigned base_level,
1110 unsigned last_level,
1111 unsigned first_layer,
1112 unsigned last_layer)
1114 struct pipe_sampler_view templ, *psv;
1115 struct svga_pipe_sampler_view *sv;
1116 struct svga_context *svga = svga_context(pipe);
1117 struct svga_texture *tex = svga_texture(pt);
1118 enum pipe_error ret;
1120 assert(svga_have_vgpu10(svga));
1122 /* Only support 2D texture for now */
1123 if (pt->target != PIPE_TEXTURE_2D)
1126 /* Fallback to the mipmap generation utility for those formats that
1127 * do not support hw generate mipmap
1129 if (!svga_format_support_gen_mips(format))
1132 /* Make sure the texture surface was created with
1133 * SVGA3D_SURFACE_BIND_RENDER_TARGET
1135 if (!tex->handle || !(tex->key.flags & SVGA3D_SURFACE_BIND_RENDER_TARGET))
1138 templ.format = format;
1139 templ.u.tex.first_layer = first_layer;
1140 templ.u.tex.last_layer = last_layer;
1141 templ.u.tex.first_level = base_level;
1142 templ.u.tex.last_level = last_level;
1144 psv = pipe->create_sampler_view(pipe, pt, &templ);
1148 sv = svga_pipe_sampler_view(psv);
1149 ret = svga_validate_pipe_sampler_view(svga, sv);
1150 if (ret != PIPE_OK) {
1151 svga_context_flush(svga, NULL);
1152 ret = svga_validate_pipe_sampler_view(svga, sv);
1153 assert(ret == PIPE_OK);
1156 ret = SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle);
1157 if (ret != PIPE_OK) {
1158 svga_context_flush(svga, NULL);
1159 ret = SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle);
1161 pipe_sampler_view_reference(&psv, NULL);
1163 svga->hud.num_generate_mipmap++;