1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_string.h"
31 #include "util/u_math.h"
33 #include "os/os_process.h"
35 #include "svga_winsys.h"
36 #include "svga_public.h"
37 #include "svga_context.h"
38 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
55 static const struct debug_named_value svga_debug_flags[] = {
56 { "dma", DEBUG_DMA, NULL },
57 { "tgsi", DEBUG_TGSI, NULL },
58 { "pipe", DEBUG_PIPE, NULL },
59 { "state", DEBUG_STATE, NULL },
60 { "screen", DEBUG_SCREEN, NULL },
61 { "tex", DEBUG_TEX, NULL },
62 { "swtnl", DEBUG_SWTNL, NULL },
63 { "const", DEBUG_CONSTS, NULL },
64 { "viewport", DEBUG_VIEWPORT, NULL },
65 { "views", DEBUG_VIEWS, NULL },
66 { "perf", DEBUG_PERF, NULL },
67 { "flush", DEBUG_FLUSH, NULL },
68 { "sync", DEBUG_SYNC, NULL },
69 { "cache", DEBUG_CACHE, NULL },
70 { "streamout", DEBUG_STREAMOUT, NULL },
71 { "query", DEBUG_QUERY, NULL },
72 { "samplers", DEBUG_SAMPLERS, NULL },
78 svga_get_vendor( struct pipe_screen *pscreen )
80 return "VMware, Inc.";
85 svga_get_name( struct pipe_screen *pscreen )
87 const char *build = "", *llvm = "", *mutex = "";
88 static char name[100];
90 /* Only return internal details in the DEBUG version:
92 build = "build: DEBUG;";
93 mutex = "mutex: " PIPE_ATOMIC ";";
94 #elif defined(VMX86_STATS)
95 build = "build: OPT;";
97 build = "build: RELEASE;";
103 util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
108 /** Helper for querying float-valued device cap */
110 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
113 SVGA3dDevCapResult result;
114 if (sws->get_cap(sws, cap, &result))
121 /** Helper for querying uint-valued device cap */
123 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
126 SVGA3dDevCapResult result;
127 if (sws->get_cap(sws, cap, &result))
134 /** Helper for querying boolean-valued device cap */
136 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
139 SVGA3dDevCapResult result;
140 if (sws->get_cap(sws, cap, &result))
148 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
150 struct svga_screen *svgascreen = svga_screen(screen);
151 struct svga_winsys_screen *sws = svgascreen->sws;
154 case PIPE_CAPF_MAX_LINE_WIDTH:
155 return svgascreen->maxLineWidth;
156 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
157 return svgascreen->maxLineWidthAA;
159 case PIPE_CAPF_MAX_POINT_WIDTH:
161 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
162 return svgascreen->maxPointSize;
164 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
165 return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
167 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
170 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
172 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
174 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
179 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
185 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
187 struct svga_screen *svgascreen = svga_screen(screen);
188 struct svga_winsys_screen *sws = svgascreen->sws;
189 SVGA3dDevCapResult result;
192 case PIPE_CAP_NPOT_TEXTURES:
193 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
194 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
196 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
198 * "In virtually every OpenGL implementation and hardware,
199 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
200 * http://www.opengl.org/wiki/Blending
202 return sws->have_vgpu10 ? 1 : 0;
203 case PIPE_CAP_ANISOTROPIC_FILTER:
205 case PIPE_CAP_POINT_SPRITE:
207 case PIPE_CAP_TGSI_TEXCOORD:
209 case PIPE_CAP_MAX_RENDER_TARGETS:
210 return svgascreen->max_color_buffers;
211 case PIPE_CAP_OCCLUSION_QUERY:
213 case PIPE_CAP_QUERY_TIME_ELAPSED:
215 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
216 return sws->have_vgpu10;
217 case PIPE_CAP_TEXTURE_SWIZZLE:
219 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
221 case PIPE_CAP_USER_VERTEX_BUFFERS:
223 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
226 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
228 unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
229 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
230 levels = MIN2(util_logbase2(result.u) + 1, levels);
232 levels = 12 /* 2048x2048 */;
233 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
234 levels = MIN2(util_logbase2(result.u) + 1, levels);
236 levels = 12 /* 2048x2048 */;
240 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
241 if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
242 return 8; /* max 128x128x128 */
243 return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
245 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
247 * No mechanism to query the host, and at least limited to 2048x2048 on
250 return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
253 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
254 return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
256 case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
259 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
261 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
262 return sws->have_vgpu10;
263 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
265 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
266 return !sws->have_vgpu10;
268 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
269 return 1; /* The color outputs of vertex shaders are not clamped */
270 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
271 return 0; /* The driver can't clamp vertex colors */
272 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
273 return 0; /* The driver can't clamp fragment colors */
275 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
276 return 1; /* expected for GL_ARB_framebuffer_object */
278 case PIPE_CAP_GLSL_FEATURE_LEVEL:
279 return sws->have_vgpu10 ? 330 : 120;
281 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
282 return sws->have_vgpu10 ? 140 : 120;
284 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
290 case PIPE_CAP_DEPTH_CLIP_DISABLE:
291 case PIPE_CAP_INDEP_BLEND_ENABLE:
292 case PIPE_CAP_CONDITIONAL_RENDER:
293 case PIPE_CAP_QUERY_TIMESTAMP:
294 case PIPE_CAP_TGSI_INSTANCEID:
295 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
296 case PIPE_CAP_SEAMLESS_CUBE_MAP:
297 case PIPE_CAP_FAKE_SW_MSAA:
298 return sws->have_vgpu10;
300 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
301 return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
302 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
303 return sws->have_vgpu10 ? 4 : 0;
304 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
305 return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
306 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
307 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
309 case PIPE_CAP_TEXTURE_MULTISAMPLE:
310 return svgascreen->ms_samples ? 1 : 0;
312 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
313 /* convert bytes to texels for the case of the largest texel
316 return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
318 case PIPE_CAP_MIN_TEXEL_OFFSET:
319 return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
320 case PIPE_CAP_MAX_TEXEL_OFFSET:
321 return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
323 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
324 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
327 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
328 return sws->have_vgpu10 ? 256 : 0;
329 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
330 return sws->have_vgpu10 ? 1024 : 0;
332 case PIPE_CAP_PRIMITIVE_RESTART:
333 return 1; /* may be a sw fallback, depending on restart index */
335 case PIPE_CAP_GENERATE_MIPMAP:
336 return sws->have_generate_mipmap_cmd;
338 case PIPE_CAP_NATIVE_FENCE_FD:
339 return sws->have_fence_fd;
341 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
344 /* Unsupported features */
345 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
346 case PIPE_CAP_SHADER_STENCIL_EXPORT:
347 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
348 case PIPE_CAP_INDEP_BLEND_FUNC:
349 case PIPE_CAP_TEXTURE_BARRIER:
350 case PIPE_CAP_MAX_VERTEX_STREAMS:
351 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
352 case PIPE_CAP_COMPUTE:
353 case PIPE_CAP_START_INSTANCE:
354 case PIPE_CAP_CUBE_MAP_ARRAY:
355 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
356 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
357 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
358 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
359 case PIPE_CAP_TEXTURE_GATHER_SM5:
360 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
361 case PIPE_CAP_TEXTURE_QUERY_LOD:
362 case PIPE_CAP_SAMPLE_SHADING:
363 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
364 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
365 case PIPE_CAP_DRAW_INDIRECT:
366 case PIPE_CAP_MULTI_DRAW_INDIRECT:
367 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
368 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
369 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
370 case PIPE_CAP_SAMPLER_VIEW_TARGET:
371 case PIPE_CAP_CLIP_HALFZ:
372 case PIPE_CAP_VERTEXID_NOBASE:
373 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
374 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
375 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
376 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
377 case PIPE_CAP_INVALIDATE_BUFFER:
378 case PIPE_CAP_STRING_MARKER:
379 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
380 case PIPE_CAP_QUERY_MEMORY_INFO:
381 case PIPE_CAP_PCI_GROUP:
382 case PIPE_CAP_PCI_BUS:
383 case PIPE_CAP_PCI_DEVICE:
384 case PIPE_CAP_PCI_FUNCTION:
385 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
386 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
387 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
388 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
389 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
390 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
391 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
393 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
395 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
396 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
397 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
398 return 1; /* need 4-byte alignment for all offsets and strides */
399 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
401 case PIPE_CAP_MAX_VIEWPORTS:
403 case PIPE_CAP_ENDIANNESS:
404 return PIPE_ENDIAN_LITTLE;
406 case PIPE_CAP_VENDOR_ID:
407 return 0x15ad; /* VMware Inc. */
408 case PIPE_CAP_DEVICE_ID:
409 return 0x0405; /* assume SVGA II */
410 case PIPE_CAP_ACCELERATED:
412 case PIPE_CAP_VIDEO_MEMORY:
413 /* XXX: Query the host ? */
415 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
416 return sws->have_vgpu10;
417 case PIPE_CAP_CLEAR_TEXTURE:
418 return sws->have_vgpu10;
420 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
421 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
422 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
423 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
424 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
425 case PIPE_CAP_DEPTH_BOUNDS_TEST:
426 case PIPE_CAP_TGSI_TXQS:
427 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
428 case PIPE_CAP_SHAREABLE_SHADERS:
429 case PIPE_CAP_DRAW_PARAMETERS:
430 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
431 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
432 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
433 case PIPE_CAP_QUERY_BUFFER_OBJECT:
434 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
435 case PIPE_CAP_CULL_DISTANCE:
436 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
437 case PIPE_CAP_TGSI_VOTE:
438 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
439 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
440 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
441 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
442 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
443 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
444 case PIPE_CAP_TGSI_FS_FBFETCH:
445 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
446 case PIPE_CAP_DOUBLES:
448 case PIPE_CAP_INT64_DIVMOD:
449 case PIPE_CAP_TGSI_TEX_TXF_LZ:
450 case PIPE_CAP_TGSI_CLOCK:
451 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
452 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
453 case PIPE_CAP_TGSI_BALLOT:
454 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
455 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
456 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
457 case PIPE_CAP_POST_DEPTH_COVERAGE:
458 case PIPE_CAP_BINDLESS_TEXTURE:
459 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
460 case PIPE_CAP_QUERY_SO_OVERFLOW:
461 case PIPE_CAP_MEMOBJ:
462 case PIPE_CAP_LOAD_CONSTBUF:
463 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
464 case PIPE_CAP_TILE_RASTER_ORDER:
465 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
466 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
467 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
468 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
469 case PIPE_CAP_FENCE_SIGNAL:
470 case PIPE_CAP_CONSTBUF0_FLAGS:
471 case PIPE_CAP_PACKED_UNIFORMS:
472 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
474 case PIPE_CAP_MAX_GS_INVOCATIONS:
478 debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
484 vgpu9_get_shader_param(struct pipe_screen *screen,
485 enum pipe_shader_type shader,
486 enum pipe_shader_cap param)
488 struct svga_screen *svgascreen = svga_screen(screen);
489 struct svga_winsys_screen *sws = svgascreen->sws;
492 assert(!sws->have_vgpu10);
496 case PIPE_SHADER_FRAGMENT:
499 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
500 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
501 return get_uint_cap(sws,
502 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
504 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
505 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
507 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
508 return SVGA3D_MAX_NESTING_LEVEL;
509 case PIPE_SHADER_CAP_MAX_INPUTS:
511 case PIPE_SHADER_CAP_MAX_OUTPUTS:
512 return svgascreen->max_color_buffers;
513 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
514 return 224 * sizeof(float[4]);
515 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
517 case PIPE_SHADER_CAP_MAX_TEMPS:
518 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
519 return MIN2(val, SVGA3D_TEMPREG_MAX);
520 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
522 * Although PS 3.0 has some addressing abilities it can only represent
523 * loops that can be statically determined and unrolled. Given we can
524 * only handle a subset of the cases that the state tracker already
525 * does it is better to defer loop unrolling to the state tracker.
528 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
530 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
532 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
533 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
534 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
536 case PIPE_SHADER_CAP_SUBROUTINES:
538 case PIPE_SHADER_CAP_INT64_ATOMICS:
539 case PIPE_SHADER_CAP_INTEGERS:
541 case PIPE_SHADER_CAP_FP16:
543 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
544 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
546 case PIPE_SHADER_CAP_PREFERRED_IR:
547 return PIPE_SHADER_IR_TGSI;
548 case PIPE_SHADER_CAP_SUPPORTED_IRS:
550 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
551 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
552 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
553 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
554 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
555 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
556 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
557 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
558 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
559 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
560 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
562 case PIPE_SHADER_CAP_SCALAR_ISA:
564 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
567 /* If we get here, we failed to handle a cap above */
568 debug_printf("Unexpected fragment shader query %u\n", param);
570 case PIPE_SHADER_VERTEX:
573 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
574 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
575 return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
577 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
578 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
579 /* XXX: until we have vertex texture support */
581 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
582 return SVGA3D_MAX_NESTING_LEVEL;
583 case PIPE_SHADER_CAP_MAX_INPUTS:
585 case PIPE_SHADER_CAP_MAX_OUTPUTS:
587 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
588 return 256 * sizeof(float[4]);
589 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
591 case PIPE_SHADER_CAP_MAX_TEMPS:
592 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
593 return MIN2(val, SVGA3D_TEMPREG_MAX);
594 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
596 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
598 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
599 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
601 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
603 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
605 case PIPE_SHADER_CAP_SUBROUTINES:
607 case PIPE_SHADER_CAP_INT64_ATOMICS:
608 case PIPE_SHADER_CAP_INTEGERS:
610 case PIPE_SHADER_CAP_FP16:
612 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
613 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
615 case PIPE_SHADER_CAP_PREFERRED_IR:
616 return PIPE_SHADER_IR_TGSI;
617 case PIPE_SHADER_CAP_SUPPORTED_IRS:
619 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
620 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
621 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
622 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
623 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
624 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
625 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
626 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
627 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
628 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
629 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
631 case PIPE_SHADER_CAP_SCALAR_ISA:
633 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
636 /* If we get here, we failed to handle a cap above */
637 debug_printf("Unexpected vertex shader query %u\n", param);
639 case PIPE_SHADER_GEOMETRY:
640 case PIPE_SHADER_COMPUTE:
641 case PIPE_SHADER_TESS_CTRL:
642 case PIPE_SHADER_TESS_EVAL:
643 /* no support for geometry, tess or compute shaders at this time */
646 debug_printf("Unexpected shader type (%u) query\n", shader);
654 vgpu10_get_shader_param(struct pipe_screen *screen,
655 enum pipe_shader_type shader,
656 enum pipe_shader_cap param)
658 struct svga_screen *svgascreen = svga_screen(screen);
659 struct svga_winsys_screen *sws = svgascreen->sws;
661 assert(sws->have_vgpu10);
662 (void) sws; /* silence unused var warnings in non-debug builds */
664 /* Only VS, GS, FS supported */
665 if (shader != PIPE_SHADER_VERTEX &&
666 shader != PIPE_SHADER_GEOMETRY &&
667 shader != PIPE_SHADER_FRAGMENT) {
671 /* NOTE: we do not query the device for any caps/limits at this time */
673 /* Generally the same limits for vertex, geometry and fragment shaders */
675 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
676 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
677 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
678 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
680 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
682 case PIPE_SHADER_CAP_MAX_INPUTS:
683 if (shader == PIPE_SHADER_FRAGMENT)
684 return VGPU10_MAX_FS_INPUTS;
685 else if (shader == PIPE_SHADER_GEOMETRY)
686 return VGPU10_MAX_GS_INPUTS;
688 return VGPU10_MAX_VS_INPUTS;
689 case PIPE_SHADER_CAP_MAX_OUTPUTS:
690 if (shader == PIPE_SHADER_FRAGMENT)
691 return VGPU10_MAX_FS_OUTPUTS;
692 else if (shader == PIPE_SHADER_GEOMETRY)
693 return VGPU10_MAX_GS_OUTPUTS;
695 return VGPU10_MAX_VS_OUTPUTS;
696 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
697 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
698 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
699 return svgascreen->max_const_buffers;
700 case PIPE_SHADER_CAP_MAX_TEMPS:
701 return VGPU10_MAX_TEMPS;
702 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
703 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
704 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
705 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
706 return TRUE; /* XXX verify */
707 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
708 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
709 case PIPE_SHADER_CAP_SUBROUTINES:
710 case PIPE_SHADER_CAP_INTEGERS:
712 case PIPE_SHADER_CAP_FP16:
714 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
715 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
716 return SVGA3D_DX_MAX_SAMPLERS;
717 case PIPE_SHADER_CAP_PREFERRED_IR:
718 return PIPE_SHADER_IR_TGSI;
719 case PIPE_SHADER_CAP_SUPPORTED_IRS:
721 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
722 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
723 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
724 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
725 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
726 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
727 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
728 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
729 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
730 case PIPE_SHADER_CAP_INT64_ATOMICS:
731 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
732 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
734 case PIPE_SHADER_CAP_SCALAR_ISA:
736 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
739 debug_printf("Unexpected vgpu10 shader query %u\n", param);
747 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
748 enum pipe_shader_cap param)
750 struct svga_screen *svgascreen = svga_screen(screen);
751 struct svga_winsys_screen *sws = svgascreen->sws;
752 if (sws->have_vgpu10) {
753 return vgpu10_get_shader_param(screen, shader, param);
756 return vgpu9_get_shader_param(screen, shader, param);
762 svga_fence_reference(struct pipe_screen *screen,
763 struct pipe_fence_handle **ptr,
764 struct pipe_fence_handle *fence)
766 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
767 sws->fence_reference(sws, ptr, fence);
772 svga_fence_finish(struct pipe_screen *screen,
773 struct pipe_context *ctx,
774 struct pipe_fence_handle *fence,
777 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
780 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
783 retVal = sws->fence_signalled(sws, fence, 0) == 0;
786 SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
787 __FUNCTION__, fence);
789 retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
792 SVGA_STATS_TIME_POP(sws);
799 svga_fence_get_fd(struct pipe_screen *screen,
800 struct pipe_fence_handle *fence)
802 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
804 return sws->fence_get_fd(sws, fence, TRUE);
809 svga_get_driver_query_info(struct pipe_screen *screen,
811 struct pipe_driver_query_info *info)
813 #define QUERY(NAME, ENUM, UNITS) \
814 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
816 static const struct pipe_driver_query_info queries[] = {
817 /* per-frame counters */
818 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
819 PIPE_DRIVER_QUERY_TYPE_UINT64),
820 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
821 PIPE_DRIVER_QUERY_TYPE_UINT64),
822 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
823 PIPE_DRIVER_QUERY_TYPE_UINT64),
824 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
825 PIPE_DRIVER_QUERY_TYPE_UINT64),
826 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
827 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
828 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
829 PIPE_DRIVER_QUERY_TYPE_UINT64),
830 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
831 PIPE_DRIVER_QUERY_TYPE_UINT64),
832 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
833 PIPE_DRIVER_QUERY_TYPE_BYTES),
834 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
835 PIPE_DRIVER_QUERY_TYPE_BYTES),
836 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
837 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
838 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
839 PIPE_DRIVER_QUERY_TYPE_UINT64),
840 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
841 PIPE_DRIVER_QUERY_TYPE_UINT64),
842 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
843 PIPE_DRIVER_QUERY_TYPE_UINT64),
844 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
845 PIPE_DRIVER_QUERY_TYPE_UINT64),
846 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
847 PIPE_DRIVER_QUERY_TYPE_UINT64),
848 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
849 PIPE_DRIVER_QUERY_TYPE_UINT64),
851 /* running total counters */
852 QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
853 PIPE_DRIVER_QUERY_TYPE_BYTES),
854 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
855 PIPE_DRIVER_QUERY_TYPE_UINT64),
856 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
857 PIPE_DRIVER_QUERY_TYPE_UINT64),
858 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
859 PIPE_DRIVER_QUERY_TYPE_UINT64),
860 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
861 PIPE_DRIVER_QUERY_TYPE_UINT64),
862 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
863 PIPE_DRIVER_QUERY_TYPE_UINT64),
864 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
865 PIPE_DRIVER_QUERY_TYPE_UINT64),
866 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
867 PIPE_DRIVER_QUERY_TYPE_FLOAT),
872 return ARRAY_SIZE(queries);
874 if (index >= ARRAY_SIZE(queries))
877 *info = queries[index];
883 init_logging(struct pipe_screen *screen)
885 static const char *log_prefix = "Mesa: ";
888 /* Log Version to Host */
889 util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
890 "%s%s", log_prefix, svga_get_name(screen));
891 svga_host_log(host_log);
893 util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
894 "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
895 svga_host_log(host_log);
897 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
898 * line (program name and arguments).
900 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
902 if (os_get_command_line(cmdline, sizeof(cmdline))) {
903 util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
904 "%s%s", log_prefix, cmdline);
905 svga_host_log(host_log);
912 svga_destroy_screen( struct pipe_screen *screen )
914 struct svga_screen *svgascreen = svga_screen(screen);
916 svga_screen_cache_cleanup(svgascreen);
918 mtx_destroy(&svgascreen->swc_mutex);
919 mtx_destroy(&svgascreen->tex_mutex);
921 svgascreen->sws->destroy(svgascreen->sws);
928 * Create a new svga_screen object
931 svga_screen_create(struct svga_winsys_screen *sws)
933 struct svga_screen *svgascreen;
934 struct pipe_screen *screen;
937 SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
940 svgascreen = CALLOC_STRUCT(svga_screen);
944 svgascreen->debug.force_level_surface_view =
945 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
946 svgascreen->debug.force_surface_view =
947 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
948 svgascreen->debug.force_sampler_view =
949 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
950 svgascreen->debug.no_surface_view =
951 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
952 svgascreen->debug.no_sampler_view =
953 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
954 svgascreen->debug.no_cache_index_buffers =
955 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
957 screen = &svgascreen->screen;
959 screen->destroy = svga_destroy_screen;
960 screen->get_name = svga_get_name;
961 screen->get_vendor = svga_get_vendor;
962 screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
963 screen->get_param = svga_get_param;
964 screen->get_shader_param = svga_get_shader_param;
965 screen->get_paramf = svga_get_paramf;
966 screen->get_timestamp = NULL;
967 screen->is_format_supported = svga_is_format_supported;
968 screen->context_create = svga_context_create;
969 screen->fence_reference = svga_fence_reference;
970 screen->fence_finish = svga_fence_finish;
971 screen->fence_get_fd = svga_fence_get_fd;
973 screen->get_driver_query_info = svga_get_driver_query_info;
974 svgascreen->sws = sws;
976 svga_init_screen_resource_functions(svgascreen);
978 if (sws->get_hw_version) {
979 svgascreen->hw_version = sws->get_hw_version(sws);
981 svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
984 if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
985 /* too old for 3D acceleration */
986 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
987 svgascreen->hw_version);
992 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
993 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
994 * we prefer the later when available.
996 * This mimics hardware vendors extensions for D3D depth sampling. See also
997 * http://aras-p.info/texts/D3D9GPUHacks.html
1001 boolean has_df16, has_df24, has_d24s8_int;
1002 SVGA3dSurfaceFormatCaps caps;
1003 SVGA3dSurfaceFormatCaps mask;
1008 svgascreen->depth.z16 = SVGA3D_Z_D16;
1009 svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1010 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1012 svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1013 has_df16 = (caps.value & mask.value) == mask.value;
1015 svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1016 has_df24 = (caps.value & mask.value) == mask.value;
1018 svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1019 has_d24s8_int = (caps.value & mask.value) == mask.value;
1021 /* XXX: We might want some other logic here.
1022 * Like if we only have d24s8_int we should
1023 * emulate the other formats with that.
1026 svgascreen->depth.z16 = SVGA3D_Z_DF16;
1029 svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1031 if (has_d24s8_int) {
1032 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1036 /* Query device caps
1038 if (sws->have_vgpu10) {
1039 svgascreen->haveProvokingVertex
1040 = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1041 svgascreen->haveLineSmooth = TRUE;
1042 svgascreen->maxPointSize = 80.0F;
1043 svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1045 /* Multisample samples per pixel */
1046 if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1047 svgascreen->ms_samples =
1048 get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1051 /* We only support 4x, 8x, 16x MSAA */
1052 svgascreen->ms_samples &= ((1 << (4-1)) |
1056 /* Maximum number of constant buffers */
1057 svgascreen->max_const_buffers =
1058 get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1059 assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1063 unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1064 SVGA3DVSVERSION_NONE);
1065 unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1066 SVGA3DPSVERSION_NONE);
1068 /* we require Shader model 3.0 or later */
1069 if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1073 svgascreen->haveProvokingVertex = FALSE;
1075 svgascreen->haveLineSmooth =
1076 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1078 svgascreen->maxPointSize =
1079 get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1080 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1081 svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1083 /* The SVGA3D device always supports 4 targets at this time, regardless
1084 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1086 svgascreen->max_color_buffers = 4;
1088 /* Only support one constant buffer
1090 svgascreen->max_const_buffers = 1;
1092 /* No multisampling */
1093 svgascreen->ms_samples = 0;
1096 /* common VGPU9 / VGPU10 caps */
1097 svgascreen->haveLineStipple =
1098 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1100 svgascreen->maxLineWidth =
1101 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1103 svgascreen->maxLineWidthAA =
1104 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1107 debug_printf("svga: haveProvokingVertex %u\n",
1108 svgascreen->haveProvokingVertex);
1109 debug_printf("svga: haveLineStip %u "
1110 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1111 svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1112 svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1113 debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1114 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1117 (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1118 (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1120 svga_screen_cache_init(svgascreen);
1122 init_logging(screen);
1132 struct svga_winsys_screen *
1133 svga_winsys_screen(struct pipe_screen *screen)
1135 return svga_screen(screen)->sws;
1140 struct svga_screen *
1141 svga_screen(struct pipe_screen *screen)
1144 assert(screen->destroy == svga_destroy_screen);
1145 return (struct svga_screen *)screen;