src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #elif defined(VMX86_STATS)
  90    build = "build: OPT;";
  91 #else
  92    build = "build: RELEASE;";
  93 #endif
  94 #ifdef HAVE_LLVM
  95    llvm = "LLVM;";
  96 #endif
  97
  98    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  99    return name;
 100 }
 101
 102
 103 /** Helper for querying float-valued device cap */
 104 static float
 105 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 106 {
 107    SVGA3dDevCapResult result;
 108    if (sws->get_cap(sws, cap, &result))
 109       return result.f;
 110    else
 111       return defaultVal;
 112 }
 113
 114
 115 /** Helper for querying uint-valued device cap */
 116 static unsigned
 117 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 118 {
 119    SVGA3dDevCapResult result;
 120    if (sws->get_cap(sws, cap, &result))
 121       return result.u;
 122    else
 123       return defaultVal;
 124 }
 125
 126
 127 /** Helper for querying boolean-valued device cap */
 128 static boolean
 129 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 130 {
 131    SVGA3dDevCapResult result;
 132    if (sws->get_cap(sws, cap, &result))
 133       return result.b;
 134    else
 135       return defaultVal;
 136 }
 137
 138
 139 static float
 140 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 141 {
 142    struct svga_screen *svgascreen = svga_screen(screen);
 143    struct svga_winsys_screen *sws = svgascreen->sws;
 144
 145    switch (param) {
 146    case PIPE_CAPF_MAX_LINE_WIDTH:
 147       return svgascreen->maxLineWidth;
 148    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 149       return svgascreen->maxLineWidthAA;
 150
 151    case PIPE_CAPF_MAX_POINT_WIDTH:
 152       /* fall-through */
 153    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 154       return svgascreen->maxPointSize;
 155
 156    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 157       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 158
 159    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 160       return 15.0;
 161
 162    case PIPE_CAPF_GUARD_BAND_LEFT:
 163    case PIPE_CAPF_GUARD_BAND_TOP:
 164    case PIPE_CAPF_GUARD_BAND_RIGHT:
 165    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 166       return 0.0;
 167    }
 168
 169    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 170    return 0;
 171 }
 172
 173
 174 static int
 175 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 176 {
 177    struct svga_screen *svgascreen = svga_screen(screen);
 178    struct svga_winsys_screen *sws = svgascreen->sws;
 179    SVGA3dDevCapResult result;
 180
 181    switch (param) {
 182    case PIPE_CAP_NPOT_TEXTURES:
 183    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 184    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 185       return 1;
 186    case PIPE_CAP_TWO_SIDED_STENCIL:
 187       return 1;
 188    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 189       /*
 190        * "In virtually every OpenGL implementation and hardware,
 191        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 192        * http://www.opengl.org/wiki/Blending
 193        */
 194       return sws->have_vgpu10 ? 1 : 0;
 195    case PIPE_CAP_ANISOTROPIC_FILTER:
 196       return 1;
 197    case PIPE_CAP_POINT_SPRITE:
 198       return 1;
 199    case PIPE_CAP_TGSI_TEXCOORD:
 200       return 0;
 201    case PIPE_CAP_MAX_RENDER_TARGETS:
 202       return svgascreen->max_color_buffers;
 203    case PIPE_CAP_OCCLUSION_QUERY:
 204       return 1;
 205    case PIPE_CAP_QUERY_TIME_ELAPSED:
 206       return 0;
 207    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208       return sws->have_vgpu10;
 209    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 210       return 1;
 211    case PIPE_CAP_TEXTURE_SWIZZLE:
 212       return 1;
 213    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 214       return 0;
 215    case PIPE_CAP_USER_VERTEX_BUFFERS:
 216       return 0;
 217    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 218       return 1;
 219    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 220       return 256;
 221
 222    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 223       {
 224          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 225          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 226             levels = MIN2(util_logbase2(result.u) + 1, levels);
 227          else
 228             levels = 12 /* 2048x2048 */;
 229          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 230             levels = MIN2(util_logbase2(result.u) + 1, levels);
 231          else
 232             levels = 12 /* 2048x2048 */;
 233          return levels;
 234       }
 235
 236    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 237       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 238          return 8;  /* max 128x128x128 */
 239       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 240
 241    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 242       /*
 243        * No mechanism to query the host, and at least limited to 2048x2048 on
 244        * certain hardware.
 245        */
 246       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 247                   12 /* 2048x2048 */);
 248
 249    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 250       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 251
 252    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 253       return 1;
 254
 255    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 256       return 1;
 257    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 258       return sws->have_vgpu10;
 259    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 260       return 0;
 261    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 262       return !sws->have_vgpu10;
 263
 264    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 265       return 1; /* The color outputs of vertex shaders are not clamped */
 266    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 267       return 0; /* The driver can't clamp vertex colors */
 268    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 269       return 0; /* The driver can't clamp fragment colors */
 270
 271    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 272       return 1; /* expected for GL_ARB_framebuffer_object */
 273
 274    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 275       return sws->have_vgpu10 ? 330 : 120;
 276
 277    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 278       return 0;
 279
 280    case PIPE_CAP_SM3:
 281       return 1;
 282
 283    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 284    case PIPE_CAP_INDEP_BLEND_ENABLE:
 285    case PIPE_CAP_CONDITIONAL_RENDER:
 286    case PIPE_CAP_QUERY_TIMESTAMP:
 287    case PIPE_CAP_TGSI_INSTANCEID:
 288    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 289    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 290    case PIPE_CAP_FAKE_SW_MSAA:
 291       return sws->have_vgpu10;
 292
 293    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 294       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 295    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 296       return sws->have_vgpu10 ? 4 : 0;
 297    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 298       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 299    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 300    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 301       return 0;
 302    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 303       return svgascreen->ms_samples ? 1 : 0;
 304
 305    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 306       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 307
 308    case PIPE_CAP_MIN_TEXEL_OFFSET:
 309       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 310    case PIPE_CAP_MAX_TEXEL_OFFSET:
 311       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 312
 313    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 314    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 315       return 0;
 316
 317    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 318       return sws->have_vgpu10 ? 256 : 0;
 319    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 320       return sws->have_vgpu10 ? 1024 : 0;
 321
 322    case PIPE_CAP_PRIMITIVE_RESTART:
 323       return 1; /* may be a sw fallback, depending on restart index */
 324
 325    case PIPE_CAP_GENERATE_MIPMAP:
 326       return sws->have_generate_mipmap_cmd;
 327
 328    /* Unsupported features */
 329    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 330    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 331    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 332    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 333    case PIPE_CAP_INDEP_BLEND_FUNC:
 334    case PIPE_CAP_TEXTURE_BARRIER:
 335    case PIPE_CAP_MAX_VERTEX_STREAMS:
 336    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 337    case PIPE_CAP_COMPUTE:
 338    case PIPE_CAP_START_INSTANCE:
 339    case PIPE_CAP_CUBE_MAP_ARRAY:
 340    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 341    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 342    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 343    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 344    case PIPE_CAP_TEXTURE_GATHER_SM5:
 345    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 346    case PIPE_CAP_TEXTURE_QUERY_LOD:
 347    case PIPE_CAP_SAMPLE_SHADING:
 348    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 349    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 350    case PIPE_CAP_DRAW_INDIRECT:
 351    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 352    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 353    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 354    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 355    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 356    case PIPE_CAP_CLIP_HALFZ:
 357    case PIPE_CAP_VERTEXID_NOBASE:
 358    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 359    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 360    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 361    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 362    case PIPE_CAP_INVALIDATE_BUFFER:
 363    case PIPE_CAP_STRING_MARKER:
 364    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 365    case PIPE_CAP_QUERY_MEMORY_INFO:
 366    case PIPE_CAP_PCI_GROUP:
 367    case PIPE_CAP_PCI_BUS:
 368    case PIPE_CAP_PCI_DEVICE:
 369    case PIPE_CAP_PCI_FUNCTION:
 370    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 371    case PIPE_CAP_NATIVE_FENCE_FD:
 372       return 0;
 373    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 374       return 64;
 375    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 376    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 377    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 378       return 1;  /* need 4-byte alignment for all offsets and strides */
 379    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 380       return 2048;
 381    case PIPE_CAP_MAX_VIEWPORTS:
 382       return 1;
 383    case PIPE_CAP_ENDIANNESS:
 384       return PIPE_ENDIAN_LITTLE;
 385
 386    case PIPE_CAP_VENDOR_ID:
 387       return 0x15ad; /* VMware Inc. */
 388    case PIPE_CAP_DEVICE_ID:
 389       return 0x0405; /* assume SVGA II */
 390    case PIPE_CAP_ACCELERATED:
 391       return 0; /* XXX: */
 392    case PIPE_CAP_VIDEO_MEMORY:
 393       /* XXX: Query the host ? */
 394       return 1;
 395    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 396       return sws->have_vgpu10;
 397    case PIPE_CAP_CLEAR_TEXTURE:
 398       return sws->have_vgpu10;
 399    case PIPE_CAP_UMA:
 400    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 401    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 402    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 403    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 404    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 405    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 406    case PIPE_CAP_TGSI_TXQS:
 407    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 408    case PIPE_CAP_SHAREABLE_SHADERS:
 409    case PIPE_CAP_DRAW_PARAMETERS:
 410    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 411    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 412    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 413    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 414    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 415    case PIPE_CAP_CULL_DISTANCE:
 416    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 417    case PIPE_CAP_TGSI_VOTE:
 418    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 419    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 420    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 421    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 422    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 423    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 424    case PIPE_CAP_TGSI_FS_FBFETCH:
 425    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 426    case PIPE_CAP_DOUBLES:
 427    case PIPE_CAP_INT64:
 428    case PIPE_CAP_INT64_DIVMOD:
 429    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 430    case PIPE_CAP_TGSI_CLOCK:
 431    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 432    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 433    case PIPE_CAP_TGSI_BALLOT:
 434    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 435       return 0;
 436    }
 437
 438    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 439    return 0;
 440 }
 441
 442
 443 static int
 444 vgpu9_get_shader_param(struct pipe_screen *screen,
 445                        enum pipe_shader_type shader,
 446                        enum pipe_shader_cap param)
 447 {
 448    struct svga_screen *svgascreen = svga_screen(screen);
 449    struct svga_winsys_screen *sws = svgascreen->sws;
 450    unsigned val;
 451
 452    assert(!sws->have_vgpu10);
 453
 454    switch (shader)
 455    {
 456    case PIPE_SHADER_FRAGMENT:
 457       switch (param)
 458       {
 459       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 460       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 461          return get_uint_cap(sws,
 462                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 463                              512);
 464       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 465       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 466          return 512;
 467       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 468          return SVGA3D_MAX_NESTING_LEVEL;
 469       case PIPE_SHADER_CAP_MAX_INPUTS:
 470          return 10;
 471       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 472          return svgascreen->max_color_buffers;
 473       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 474          return 224 * sizeof(float[4]);
 475       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 476          return 1;
 477       case PIPE_SHADER_CAP_MAX_TEMPS:
 478          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 479          return MIN2(val, SVGA3D_TEMPREG_MAX);
 480       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 481          /*
 482           * Although PS 3.0 has some addressing abilities it can only represent
 483           * loops that can be statically determined and unrolled. Given we can
 484           * only handle a subset of the cases that the state tracker already
 485           * does it is better to defer loop unrolling to the state tracker.
 486           */
 487          return 0;
 488       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 489          return 0;
 490       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 491          return 0;
 492       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 493       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 494       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 495          return 0;
 496       case PIPE_SHADER_CAP_SUBROUTINES:
 497          return 0;
 498       case PIPE_SHADER_CAP_INTEGERS:
 499          return 0;
 500       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 501       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 502          return 16;
 503       case PIPE_SHADER_CAP_PREFERRED_IR:
 504          return PIPE_SHADER_IR_TGSI;
 505       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 506          return 0;
 507       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 508       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 509       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 510       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 511       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 512       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 513       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 514       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 515          return 0;
 516       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 517          return 32;
 518       }
 519       /* If we get here, we failed to handle a cap above */
 520       debug_printf("Unexpected fragment shader query %u\n", param);
 521       return 0;
 522    case PIPE_SHADER_VERTEX:
 523       switch (param)
 524       {
 525       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 526       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 527          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 528                              512);
 529       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 530       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 531          /* XXX: until we have vertex texture support */
 532          return 0;
 533       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 534          return SVGA3D_MAX_NESTING_LEVEL;
 535       case PIPE_SHADER_CAP_MAX_INPUTS:
 536          return 16;
 537       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 538          return 10;
 539       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 540          return 256 * sizeof(float[4]);
 541       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 542          return 1;
 543       case PIPE_SHADER_CAP_MAX_TEMPS:
 544          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 545          return MIN2(val, SVGA3D_TEMPREG_MAX);
 546       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 547          return 0;
 548       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 549          return 0;
 550       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 551       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 552          return 1;
 553       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 554          return 0;
 555       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 556          return 1;
 557       case PIPE_SHADER_CAP_SUBROUTINES:
 558          return 0;
 559       case PIPE_SHADER_CAP_INTEGERS:
 560          return 0;
 561       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 562       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 563          return 0;
 564       case PIPE_SHADER_CAP_PREFERRED_IR:
 565          return PIPE_SHADER_IR_TGSI;
 566       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 567          return 0;
 568       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 569       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 570       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 571       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 572       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 573       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 574       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 575       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 576          return 0;
 577       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 578          return 32;
 579       }
 580       /* If we get here, we failed to handle a cap above */
 581       debug_printf("Unexpected vertex shader query %u\n", param);
 582       return 0;
 583    case PIPE_SHADER_GEOMETRY:
 584    case PIPE_SHADER_COMPUTE:
 585    case PIPE_SHADER_TESS_CTRL:
 586    case PIPE_SHADER_TESS_EVAL:
 587       /* no support for geometry, tess or compute shaders at this time */
 588       return 0;
 589    default:
 590       debug_printf("Unexpected shader type (%u) query\n", shader);
 591       return 0;
 592    }
 593    return 0;
 594 }
 595
 596
 597 static int
 598 vgpu10_get_shader_param(struct pipe_screen *screen,
 599                         enum pipe_shader_type shader,
 600                         enum pipe_shader_cap param)
 601 {
 602    struct svga_screen *svgascreen = svga_screen(screen);
 603    struct svga_winsys_screen *sws = svgascreen->sws;
 604
 605    assert(sws->have_vgpu10);
 606    (void) sws;  /* silence unused var warnings in non-debug builds */
 607
 608    /* Only VS, GS, FS supported */
 609    if (shader != PIPE_SHADER_VERTEX &&
 610        shader != PIPE_SHADER_GEOMETRY &&
 611        shader != PIPE_SHADER_FRAGMENT) {
 612       return 0;
 613    }
 614
 615    /* NOTE: we do not query the device for any caps/limits at this time */
 616
 617    /* Generally the same limits for vertex, geometry and fragment shaders */
 618    switch (param) {
 619    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 620    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 621    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 622    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 623       return 64 * 1024;
 624    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 625       return 64;
 626    case PIPE_SHADER_CAP_MAX_INPUTS:
 627       if (shader == PIPE_SHADER_FRAGMENT)
 628          return VGPU10_MAX_FS_INPUTS;
 629       else if (shader == PIPE_SHADER_GEOMETRY)
 630          return VGPU10_MAX_GS_INPUTS;
 631       else
 632          return VGPU10_MAX_VS_INPUTS;
 633    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 634       if (shader == PIPE_SHADER_FRAGMENT)
 635          return VGPU10_MAX_FS_OUTPUTS;
 636       else if (shader == PIPE_SHADER_GEOMETRY)
 637          return VGPU10_MAX_GS_OUTPUTS;
 638       else
 639          return VGPU10_MAX_VS_OUTPUTS;
 640    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 641       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 642    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 643       return svgascreen->max_const_buffers;
 644    case PIPE_SHADER_CAP_MAX_TEMPS:
 645       return VGPU10_MAX_TEMPS;
 646    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 647    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 648    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 649    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 650       return TRUE; /* XXX verify */
 651    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 652    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 653    case PIPE_SHADER_CAP_SUBROUTINES:
 654    case PIPE_SHADER_CAP_INTEGERS:
 655       return TRUE;
 656    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 657    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 658       return SVGA3D_DX_MAX_SAMPLERS;
 659    case PIPE_SHADER_CAP_PREFERRED_IR:
 660       return PIPE_SHADER_IR_TGSI;
 661    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 662          return 0;
 663    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 664    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 665    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 666    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 667    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 668    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 669    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 670    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 671       return 0;
 672    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 673       return 32;
 674    default:
 675       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 676       return 0;
 677    }
 678    return 0;
 679 }
 680
 681
 682 static int
 683 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 684                       enum pipe_shader_cap param)
 685 {
 686    struct svga_screen *svgascreen = svga_screen(screen);
 687    struct svga_winsys_screen *sws = svgascreen->sws;
 688    if (sws->have_vgpu10) {
 689       return vgpu10_get_shader_param(screen, shader, param);
 690    }
 691    else {
 692       return vgpu9_get_shader_param(screen, shader, param);
 693    }
 694 }
 695
 696
 697 /**
 698  * Implement pipe_screen::is_format_supported().
 699  * \param bindings  bitmask of PIPE_BIND_x flags
 700  */
 701 static boolean
 702 svga_is_format_supported( struct pipe_screen *screen,
 703                           enum pipe_format format,
 704                           enum pipe_texture_target target,
 705                           unsigned sample_count,
 706                           unsigned bindings)
 707 {
 708    struct svga_screen *ss = svga_screen(screen);
 709    SVGA3dSurfaceFormat svga_format;
 710    SVGA3dSurfaceFormatCaps caps;
 711    SVGA3dSurfaceFormatCaps mask;
 712
 713    assert(bindings);
 714
 715    if (sample_count > 1) {
 716       /* In ms_samples, if bit N is set it means that we support
 717        * multisample with N+1 samples per pixel.
 718        */
 719       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 720          return FALSE;
 721       }
 722    }
 723
 724    svga_format = svga_translate_format(ss, format, bindings);
 725    if (svga_format == SVGA3D_FORMAT_INVALID) {
 726       return FALSE;
 727    }
 728
 729    /* we don't support sRGB rendering into display targets */
 730    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 731       return FALSE;
 732    }
 733
 734    /*
 735     * For VGPU10 vertex formats, skip querying host capabilities
 736     */
 737
 738    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 739       SVGA3dSurfaceFormat svga_format;
 740       unsigned flags;
 741       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 742       return svga_format != SVGA3D_FORMAT_INVALID;
 743    }
 744
 745    /*
 746     * Override host capabilities, so that we end up with the same
 747     * visuals for all virtual hardware implementations.
 748     */
 749
 750    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 751       switch (svga_format) {
 752       case SVGA3D_A8R8G8B8:
 753       case SVGA3D_X8R8G8B8:
 754       case SVGA3D_R5G6B5:
 755          break;
 756
 757       /* VGPU10 formats */
 758       case SVGA3D_B8G8R8A8_UNORM:
 759       case SVGA3D_B8G8R8X8_UNORM:
 760       case SVGA3D_B5G6R5_UNORM:
 761          break;
 762
 763       /* Often unsupported/problematic. This means we end up with the same
 764        * visuals for all virtual hardware implementations.
 765        */
 766       case SVGA3D_A4R4G4B4:
 767       case SVGA3D_A1R5G5B5:
 768          return FALSE;
 769
 770       default:
 771          return FALSE;
 772       }
 773    }
 774
 775    /*
 776     * Query the host capabilities.
 777     */
 778
 779    svga_get_format_cap(ss, svga_format, &caps);
 780
 781    if (bindings & PIPE_BIND_RENDER_TARGET) {
 782       /* Check that the color surface is blendable, unless it's an
 783        * integer format.
 784        */
 785       if (!svga_format_is_integer(svga_format) &&
 786           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 787          return FALSE;
 788       }
 789    }
 790
 791    mask.value = 0;
 792    if (bindings & PIPE_BIND_RENDER_TARGET) {
 793       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 794    }
 795    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 796       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 797    }
 798    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 799       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 800    }
 801
 802    if (target == PIPE_TEXTURE_CUBE) {
 803       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 804    }
 805    else if (target == PIPE_TEXTURE_3D) {
 806       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 807    }
 808
 809    return (caps.value & mask.value) == mask.value;
 810 }
 811
 812
 813 static void
 814 svga_fence_reference(struct pipe_screen *screen,
 815                      struct pipe_fence_handle **ptr,
 816                      struct pipe_fence_handle *fence)
 817 {
 818    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 819    sws->fence_reference(sws, ptr, fence);
 820 }
 821
 822
 823 static boolean
 824 svga_fence_finish(struct pipe_screen *screen,
 825                   struct pipe_context *ctx,
 826                   struct pipe_fence_handle *fence,
 827                   uint64_t timeout)
 828 {
 829    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 830    boolean retVal;
 831
 832    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 833
 834    if (!timeout) {
 835       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 836    }
 837    else {
 838       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 839                __FUNCTION__, fence);
 840
 841       retVal = sws->fence_finish(sws, fence, 0) == 0;
 842    }
 843
 844    SVGA_STATS_TIME_POP(sws);
 845
 846    return retVal;
 847 }
 848
 849
 850 static int
 851 svga_get_driver_query_info(struct pipe_screen *screen,
 852                            unsigned index,
 853                            struct pipe_driver_query_info *info)
 854 {
 855 #define QUERY(NAME, ENUM, UNITS) \
 856    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 857
 858    static const struct pipe_driver_query_info queries[] = {
 859       /* per-frame counters */
 860       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 861             PIPE_DRIVER_QUERY_TYPE_UINT64),
 862       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 863             PIPE_DRIVER_QUERY_TYPE_UINT64),
 864       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 865             PIPE_DRIVER_QUERY_TYPE_UINT64),
 866       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 867             PIPE_DRIVER_QUERY_TYPE_UINT64),
 868       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 869             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 870       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 871             PIPE_DRIVER_QUERY_TYPE_UINT64),
 872       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 873             PIPE_DRIVER_QUERY_TYPE_UINT64),
 874       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 875             PIPE_DRIVER_QUERY_TYPE_BYTES),
 876       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 877             PIPE_DRIVER_QUERY_TYPE_BYTES),
 878       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 879             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 880       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 881             PIPE_DRIVER_QUERY_TYPE_UINT64),
 882       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 883             PIPE_DRIVER_QUERY_TYPE_UINT64),
 884       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 885             PIPE_DRIVER_QUERY_TYPE_UINT64),
 886       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 887             PIPE_DRIVER_QUERY_TYPE_UINT64),
 888       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 889             PIPE_DRIVER_QUERY_TYPE_UINT64),
 890       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 891             PIPE_DRIVER_QUERY_TYPE_UINT64),
 892
 893       /* running total counters */
 894       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 895             PIPE_DRIVER_QUERY_TYPE_BYTES),
 896       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 897             PIPE_DRIVER_QUERY_TYPE_UINT64),
 898       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 899             PIPE_DRIVER_QUERY_TYPE_UINT64),
 900       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 901             PIPE_DRIVER_QUERY_TYPE_UINT64),
 902       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 903             PIPE_DRIVER_QUERY_TYPE_UINT64),
 904       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 905             PIPE_DRIVER_QUERY_TYPE_UINT64),
 906    };
 907 #undef QUERY
 908
 909    if (!info)
 910       return ARRAY_SIZE(queries);
 911
 912    if (index >= ARRAY_SIZE(queries))
 913       return 0;
 914
 915    *info = queries[index];
 916    return 1;
 917 }
 918
 919
 920 static void
 921 svga_destroy_screen( struct pipe_screen *screen )
 922 {
 923    struct svga_screen *svgascreen = svga_screen(screen);
 924
 925    svga_screen_cache_cleanup(svgascreen);
 926
 927    mtx_destroy(&svgascreen->swc_mutex);
 928    mtx_destroy(&svgascreen->tex_mutex);
 929
 930    svgascreen->sws->destroy(svgascreen->sws);
 931
 932    FREE(svgascreen);
 933 }
 934
 935
 936 /**
 937  * Create a new svga_screen object
 938  */
 939 struct pipe_screen *
 940 svga_screen_create(struct svga_winsys_screen *sws)
 941 {
 942    struct svga_screen *svgascreen;
 943    struct pipe_screen *screen;
 944
 945 #ifdef DEBUG
 946    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 947 #endif
 948
 949    svgascreen = CALLOC_STRUCT(svga_screen);
 950    if (!svgascreen)
 951       goto error1;
 952
 953    svgascreen->debug.force_level_surface_view =
 954       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 955    svgascreen->debug.force_surface_view =
 956       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 957    svgascreen->debug.force_sampler_view =
 958       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 959    svgascreen->debug.no_surface_view =
 960       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 961    svgascreen->debug.no_sampler_view =
 962       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 963    svgascreen->debug.no_cache_index_buffers =
 964       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 965
 966    screen = &svgascreen->screen;
 967
 968    screen->destroy = svga_destroy_screen;
 969    screen->get_name = svga_get_name;
 970    screen->get_vendor = svga_get_vendor;
 971    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 972    screen->get_param = svga_get_param;
 973    screen->get_shader_param = svga_get_shader_param;
 974    screen->get_paramf = svga_get_paramf;
 975    screen->get_timestamp = NULL;
 976    screen->is_format_supported = svga_is_format_supported;
 977    screen->context_create = svga_context_create;
 978    screen->fence_reference = svga_fence_reference;
 979    screen->fence_finish = svga_fence_finish;
 980    screen->get_driver_query_info = svga_get_driver_query_info;
 981    svgascreen->sws = sws;
 982
 983    svga_init_screen_resource_functions(svgascreen);
 984
 985    if (sws->get_hw_version) {
 986       svgascreen->hw_version = sws->get_hw_version(sws);
 987    } else {
 988       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 989    }
 990
 991    /*
 992     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 993     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 994     * we prefer the later when available.
 995     *
 996     * This mimics hardware vendors extensions for D3D depth sampling. See also
 997     * http://aras-p.info/texts/D3D9GPUHacks.html
 998     */
 999
1000    {
1001       boolean has_df16, has_df24, has_d24s8_int;
1002       SVGA3dSurfaceFormatCaps caps;
1003       SVGA3dSurfaceFormatCaps mask;
1004       mask.value = 0;
1005       mask.zStencil = 1;
1006       mask.texture = 1;
1007
1008       svgascreen->depth.z16 = SVGA3D_Z_D16;
1009       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1010       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1011
1012       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1013       has_df16 = (caps.value & mask.value) == mask.value;
1014
1015       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1016       has_df24 = (caps.value & mask.value) == mask.value;
1017
1018       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1019       has_d24s8_int = (caps.value & mask.value) == mask.value;
1020
1021       /* XXX: We might want some other logic here.
1022        * Like if we only have d24s8_int we should
1023        * emulate the other formats with that.
1024        */
1025       if (has_df16) {
1026          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1027       }
1028       if (has_df24) {
1029          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1030       }
1031       if (has_d24s8_int) {
1032          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1033       }
1034    }
1035
1036    /* Query device caps
1037     */
1038    if (sws->have_vgpu10) {
1039       svgascreen->haveProvokingVertex
1040          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1041       svgascreen->haveLineSmooth = TRUE;
1042       svgascreen->maxPointSize = 80.0F;
1043       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1044
1045       /* Multisample samples per pixel */
1046       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1047          svgascreen->ms_samples =
1048             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1049       }
1050
1051       /* Maximum number of constant buffers */
1052       svgascreen->max_const_buffers =
1053          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1054       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1055    }
1056    else {
1057       /* VGPU9 */
1058       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1059                                      SVGA3DVSVERSION_NONE);
1060       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1061                                      SVGA3DPSVERSION_NONE);
1062
1063       /* we require Shader model 3.0 or later */
1064       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1065          goto error2;
1066       }
1067
1068       svgascreen->haveProvokingVertex = FALSE;
1069
1070       svgascreen->haveLineSmooth =
1071          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1072
1073       svgascreen->maxPointSize =
1074          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1075       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1076       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1077
1078       /* The SVGA3D device always supports 4 targets at this time, regardless
1079        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1080        */
1081       svgascreen->max_color_buffers = 4;
1082
1083       /* Only support one constant buffer
1084        */
1085       svgascreen->max_const_buffers = 1;
1086
1087       /* No multisampling */
1088       svgascreen->ms_samples = 0;
1089    }
1090
1091    /* common VGPU9 / VGPU10 caps */
1092    svgascreen->haveLineStipple =
1093       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1094
1095    svgascreen->maxLineWidth =
1096       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1097
1098    svgascreen->maxLineWidthAA =
1099       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1100
1101    if (0) {
1102       debug_printf("svga: haveProvokingVertex %u\n",
1103                    svgascreen->haveProvokingVertex);
1104       debug_printf("svga: haveLineStip %u  "
1105                    "haveLineSmooth %u  maxLineWidth %f\n",
1106                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1107                    svgascreen->maxLineWidth);
1108       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1109       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1110    }
1111
1112    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1113    (void) mtx_init(&svgascreen->swc_mutex, mtx_plain);
1114
1115    svga_screen_cache_init(svgascreen);
1116
1117    return screen;
1118 error2:
1119    FREE(svgascreen);
1120 error1:
1121    return NULL;
1122 }
1123
1124 struct svga_winsys_screen *
1125 svga_winsys_screen(struct pipe_screen *screen)
1126 {
1127    return svga_screen(screen)->sws;
1128 }
1129
1130 #ifdef DEBUG
1131 struct svga_screen *
1132 svga_screen(struct pipe_screen *screen)
1133 {
1134    assert(screen);
1135    assert(screen->destroy == svga_destroy_screen);
1136    return (struct svga_screen *)screen;
1137 }
1138 #endif