src/gallium/drivers/swr/swr_screen.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_context.h"
  25 #include "swr_public.h"
  26 #include "swr_screen.h"
  27 #include "swr_resource.h"
  28 #include "swr_fence.h"
  29 #include "gen_knobs.h"
  30
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_defines.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_format.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_cpu_detect.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39
  40 #include "state_tracker/sw_winsys.h"
  41
  42 #include "jit_api.h"
  43
  44 #include "memory/TilingFunctions.h"
  45
  46 #include <stdio.h>
  47 #include <map>
  48
  49 /*
  50  * Max texture sizes
  51  * XXX Check max texture size values against core and sampler.
  52  */
  53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
  54 #define SWR_MAX_TEXTURE_2D_LEVELS 14  /* 8K x 8K for now */
  55 #define SWR_MAX_TEXTURE_3D_LEVELS 12  /* 2K x 2K x 2K for now */
  56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14  /* 8K x 8K for now */
  57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
  58
  59 /* Default max client_copy_limit */
  60 #define SWR_CLIENT_COPY_LIMIT 8192
  61
  62 /* Flag indicates creation of alternate surface, to prevent recursive loop
  63  * in resource creation when msaa_force_enable is set. */
  64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  65
  66
  67 static const char *
  68 swr_get_name(struct pipe_screen *screen)
  69 {
  70    static char buf[100];
  71    util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
  72                  HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
  73                  lp_native_vector_width );
  74    return buf;
  75 }
  76
  77 static const char *
  78 swr_get_vendor(struct pipe_screen *screen)
  79 {
  80    return "Intel Corporation";
  81 }
  82
  83 static boolean
  84 swr_is_format_supported(struct pipe_screen *_screen,
  85                         enum pipe_format format,
  86                         enum pipe_texture_target target,
  87                         unsigned sample_count,
  88                         unsigned storage_sample_count,
  89                         unsigned bind)
  90 {
  91    struct swr_screen *screen = swr_screen(_screen);
  92    struct sw_winsys *winsys = screen->winsys;
  93    const struct util_format_description *format_desc;
  94
  95    assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
  96           || target == PIPE_TEXTURE_1D_ARRAY
  97           || target == PIPE_TEXTURE_2D
  98           || target == PIPE_TEXTURE_2D_ARRAY
  99           || target == PIPE_TEXTURE_RECT
 100           || target == PIPE_TEXTURE_3D
 101           || target == PIPE_TEXTURE_CUBE
 102           || target == PIPE_TEXTURE_CUBE_ARRAY);
 103
 104    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 105       return false;
 106
 107    format_desc = util_format_description(format);
 108    if (!format_desc)
 109       return FALSE;
 110
 111    if ((sample_count > screen->msaa_max_count)
 112       || !util_is_power_of_two_or_zero(sample_count))
 113       return FALSE;
 114
 115    if (bind & PIPE_BIND_DISPLAY_TARGET) {
 116       if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
 117          return FALSE;
 118    }
 119
 120    if (bind & PIPE_BIND_RENDER_TARGET) {
 121       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 122          return FALSE;
 123
 124       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 125          return FALSE;
 126
 127       /*
 128        * Although possible, it is unnatural to render into compressed or YUV
 129        * surfaces. So disable these here to avoid going into weird paths
 130        * inside the state trackers.
 131        */
 132       if (format_desc->block.width != 1 || format_desc->block.height != 1)
 133          return FALSE;
 134    }
 135
 136    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 137       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 138          return FALSE;
 139
 140       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 141          return FALSE;
 142    }
 143
 144    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
 145        format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
 146       return FALSE;
 147    }
 148
 149    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
 150        format != PIPE_FORMAT_ETC1_RGB8) {
 151       return FALSE;
 152    }
 153
 154    return TRUE;
 155 }
 156
 157 static int
 158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
 159 {
 160    switch (param) {
 161       /* limits */
 162    case PIPE_CAP_MAX_RENDER_TARGETS:
 163       return PIPE_MAX_COLOR_BUFS;
 164    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 165       return SWR_MAX_TEXTURE_2D_LEVELS;
 166    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 167       return SWR_MAX_TEXTURE_3D_LEVELS;
 168    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 169       return SWR_MAX_TEXTURE_CUBE_LEVELS;
 170    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 171       return MAX_SO_STREAMS;
 172    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 173    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 174       return MAX_ATTRIBUTES * 4;
 175    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 176    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 177       return 1024;
 178    case PIPE_CAP_MAX_VERTEX_STREAMS:
 179       return 1;
 180    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 181       return 2048;
 182    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 183       return SWR_MAX_TEXTURE_ARRAY_LAYERS;
 184    case PIPE_CAP_MIN_TEXEL_OFFSET:
 185       return -8;
 186    case PIPE_CAP_MAX_TEXEL_OFFSET:
 187       return 7;
 188    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 189       return 330;
 190    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 191       return 140;
 192    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 193       return 16;
 194    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 195       return 64;
 196    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 197       return 65536;
 198    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 199       return 0;
 200    case PIPE_CAP_MAX_VIEWPORTS:
 201       return 1;
 202    case PIPE_CAP_ENDIANNESS:
 203       return PIPE_ENDIAN_NATIVE;
 204    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 205    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 206       return 0;
 207
 208       /* supported features */
 209    case PIPE_CAP_NPOT_TEXTURES:
 210    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 211    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 212    case PIPE_CAP_SM3:
 213    case PIPE_CAP_POINT_SPRITE:
 214    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 215    case PIPE_CAP_OCCLUSION_QUERY:
 216    case PIPE_CAP_QUERY_TIME_ELAPSED:
 217    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 218    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 219    case PIPE_CAP_TEXTURE_SWIZZLE:
 220    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 221    case PIPE_CAP_INDEP_BLEND_ENABLE:
 222    case PIPE_CAP_INDEP_BLEND_FUNC:
 223    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 224    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 225    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 226    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 227    case PIPE_CAP_PRIMITIVE_RESTART:
 228    case PIPE_CAP_TGSI_INSTANCEID:
 229    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 230    case PIPE_CAP_START_INSTANCE:
 231    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 232    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 233    case PIPE_CAP_CONDITIONAL_RENDER:
 234    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 235    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 236    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 237    case PIPE_CAP_USER_VERTEX_BUFFERS:
 238    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 239    case PIPE_CAP_QUERY_TIMESTAMP:
 240    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 241    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 242    case PIPE_CAP_DRAW_INDIRECT:
 243    case PIPE_CAP_UMA:
 244    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 245    case PIPE_CAP_CLIP_HALFZ:
 246    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 247    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 248    case PIPE_CAP_CLEAR_TEXTURE:
 249    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 250    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 251    case PIPE_CAP_CULL_DISTANCE:
 252    case PIPE_CAP_CUBE_MAP_ARRAY:
 253    case PIPE_CAP_DOUBLES:
 254       return 1;
 255
 256    /* MSAA support
 257     * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
 258     * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
 259    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 260    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 261       return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
 262    case PIPE_CAP_FAKE_SW_MSAA:
 263       return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
 264
 265    /* fetch jit change for 2-4GB buffers requires alignment */
 266    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 267    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 268    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 269       return 1;
 270
 271       /* unsupported features */
 272    case PIPE_CAP_ANISOTROPIC_FILTER:
 273    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 274    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 275    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 276    case PIPE_CAP_TEXTURE_BARRIER:
 277    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 278    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 279    case PIPE_CAP_COMPUTE:
 280    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 281    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 282    case PIPE_CAP_TGSI_TEXCOORD:
 283    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 284    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 285    case PIPE_CAP_TEXTURE_GATHER_SM5:
 286    case PIPE_CAP_TEXTURE_QUERY_LOD:
 287    case PIPE_CAP_SAMPLE_SHADING:
 288    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 289    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 290    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 291    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 292    case PIPE_CAP_VERTEXID_NOBASE:
 293    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 294    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 295    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 296    case PIPE_CAP_TGSI_TXQS:
 297    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 298    case PIPE_CAP_SHAREABLE_SHADERS:
 299    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 300    case PIPE_CAP_DRAW_PARAMETERS:
 301    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 302    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 303    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 304    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 305    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 306    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 307    case PIPE_CAP_INVALIDATE_BUFFER:
 308    case PIPE_CAP_GENERATE_MIPMAP:
 309    case PIPE_CAP_STRING_MARKER:
 310    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 311    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 312    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 313    case PIPE_CAP_QUERY_MEMORY_INFO:
 314    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 315    case PIPE_CAP_PCI_GROUP:
 316    case PIPE_CAP_PCI_BUS:
 317    case PIPE_CAP_PCI_DEVICE:
 318    case PIPE_CAP_PCI_FUNCTION:
 319    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 320    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 321    case PIPE_CAP_TGSI_VOTE:
 322    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 323    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 324    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 325    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 326    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 327    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 328    case PIPE_CAP_NATIVE_FENCE_FD:
 329    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 330    case PIPE_CAP_TGSI_FS_FBFETCH:
 331    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 332    case PIPE_CAP_INT64:
 333    case PIPE_CAP_INT64_DIVMOD:
 334    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 335    case PIPE_CAP_TGSI_CLOCK:
 336    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 337    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 338    case PIPE_CAP_TGSI_BALLOT:
 339    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 340    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 341    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 342    case PIPE_CAP_POST_DEPTH_COVERAGE:
 343    case PIPE_CAP_BINDLESS_TEXTURE:
 344    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 345    case PIPE_CAP_QUERY_SO_OVERFLOW:
 346    case PIPE_CAP_MEMOBJ:
 347    case PIPE_CAP_LOAD_CONSTBUF:
 348    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 349    case PIPE_CAP_TILE_RASTER_ORDER:
 350    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 351    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 352    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 353    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 354    case PIPE_CAP_FENCE_SIGNAL:
 355    case PIPE_CAP_CONSTBUF0_FLAGS:
 356    case PIPE_CAP_PACKED_UNIFORMS:
 357    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 358    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 359    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 360    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 361    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 362    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 363    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 364       return 0;
 365    case PIPE_CAP_MAX_GS_INVOCATIONS:
 366       return 32;
 367
 368    case PIPE_CAP_VENDOR_ID:
 369       return 0xFFFFFFFF;
 370    case PIPE_CAP_DEVICE_ID:
 371       return 0xFFFFFFFF;
 372    case PIPE_CAP_ACCELERATED:
 373       return 0;
 374    case PIPE_CAP_VIDEO_MEMORY: {
 375       /* XXX: Do we want to return the full amount of system memory ? */
 376       uint64_t system_memory;
 377
 378       if (!os_get_total_physical_memory(&system_memory))
 379          return 0;
 380
 381       return (int)(system_memory >> 20);
 382    }
 383    }
 384
 385    /* should only get here on unhandled cases */
 386    debug_printf("Unexpected PIPE_CAP %d query\n", param);
 387    return 0;
 388 }
 389
 390 static int
 391 swr_get_shader_param(struct pipe_screen *screen,
 392                      enum pipe_shader_type shader,
 393                      enum pipe_shader_cap param)
 394 {
 395    if (shader == PIPE_SHADER_VERTEX ||
 396        shader == PIPE_SHADER_FRAGMENT ||
 397        shader == PIPE_SHADER_GEOMETRY)
 398       return gallivm_get_shader_param(param);
 399
 400    // Todo: tesselation, compute
 401    return 0;
 402 }
 403
 404
 405 static float
 406 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 407 {
 408    switch (param) {
 409    case PIPE_CAPF_MAX_LINE_WIDTH:
 410    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 411    case PIPE_CAPF_MAX_POINT_WIDTH:
 412       return 255.0; /* arbitrary */
 413    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 414       return 0.0;
 415    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 416       return 0.0;
 417    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 418       return 16.0; /* arbitrary */
 419    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 420    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 421    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 422       return 0.0f;
 423    }
 424    /* should only get here on unhandled cases */
 425    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 426    return 0.0;
 427 }
 428
 429 SWR_FORMAT
 430 mesa_to_swr_format(enum pipe_format format)
 431 {
 432    static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
 433       /* depth / stencil */
 434       {PIPE_FORMAT_Z16_UNORM,              R16_UNORM}, // z
 435       {PIPE_FORMAT_Z32_FLOAT,              R32_FLOAT}, // z
 436       {PIPE_FORMAT_Z24_UNORM_S8_UINT,      R24_UNORM_X8_TYPELESS}, // z
 437       {PIPE_FORMAT_Z24X8_UNORM,            R24_UNORM_X8_TYPELESS}, // z
 438       {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
 439
 440       /* alpha */
 441       {PIPE_FORMAT_A8_UNORM,               A8_UNORM},
 442       {PIPE_FORMAT_A16_UNORM,              A16_UNORM},
 443       {PIPE_FORMAT_A16_FLOAT,              A16_FLOAT},
 444       {PIPE_FORMAT_A32_FLOAT,              A32_FLOAT},
 445
 446       /* odd sizes, bgr */
 447       {PIPE_FORMAT_B5G6R5_UNORM,           B5G6R5_UNORM},
 448       {PIPE_FORMAT_B5G6R5_SRGB,            B5G6R5_UNORM_SRGB},
 449       {PIPE_FORMAT_B5G5R5A1_UNORM,         B5G5R5A1_UNORM},
 450       {PIPE_FORMAT_B5G5R5X1_UNORM,         B5G5R5X1_UNORM},
 451       {PIPE_FORMAT_B4G4R4A4_UNORM,         B4G4R4A4_UNORM},
 452       {PIPE_FORMAT_B8G8R8A8_UNORM,         B8G8R8A8_UNORM},
 453       {PIPE_FORMAT_B8G8R8A8_SRGB,          B8G8R8A8_UNORM_SRGB},
 454       {PIPE_FORMAT_B8G8R8X8_UNORM,         B8G8R8X8_UNORM},
 455       {PIPE_FORMAT_B8G8R8X8_SRGB,          B8G8R8X8_UNORM_SRGB},
 456
 457       /* rgb10a2 */
 458       {PIPE_FORMAT_R10G10B10A2_UNORM,      R10G10B10A2_UNORM},
 459       {PIPE_FORMAT_R10G10B10A2_SNORM,      R10G10B10A2_SNORM},
 460       {PIPE_FORMAT_R10G10B10A2_USCALED,    R10G10B10A2_USCALED},
 461       {PIPE_FORMAT_R10G10B10A2_SSCALED,    R10G10B10A2_SSCALED},
 462       {PIPE_FORMAT_R10G10B10A2_UINT,       R10G10B10A2_UINT},
 463
 464       /* rgb10x2 */
 465       {PIPE_FORMAT_R10G10B10X2_USCALED,    R10G10B10X2_USCALED},
 466
 467       /* bgr10a2 */
 468       {PIPE_FORMAT_B10G10R10A2_UNORM,      B10G10R10A2_UNORM},
 469       {PIPE_FORMAT_B10G10R10A2_SNORM,      B10G10R10A2_SNORM},
 470       {PIPE_FORMAT_B10G10R10A2_USCALED,    B10G10R10A2_USCALED},
 471       {PIPE_FORMAT_B10G10R10A2_SSCALED,    B10G10R10A2_SSCALED},
 472       {PIPE_FORMAT_B10G10R10A2_UINT,       B10G10R10A2_UINT},
 473
 474       /* bgr10x2 */
 475       {PIPE_FORMAT_B10G10R10X2_UNORM,      B10G10R10X2_UNORM},
 476
 477       /* r11g11b10 */
 478       {PIPE_FORMAT_R11G11B10_FLOAT,        R11G11B10_FLOAT},
 479
 480       /* 32 bits per component */
 481       {PIPE_FORMAT_R32_FLOAT,              R32_FLOAT},
 482       {PIPE_FORMAT_R32G32_FLOAT,           R32G32_FLOAT},
 483       {PIPE_FORMAT_R32G32B32_FLOAT,        R32G32B32_FLOAT},
 484       {PIPE_FORMAT_R32G32B32A32_FLOAT,     R32G32B32A32_FLOAT},
 485       {PIPE_FORMAT_R32G32B32X32_FLOAT,     R32G32B32X32_FLOAT},
 486
 487       {PIPE_FORMAT_R32_USCALED,            R32_USCALED},
 488       {PIPE_FORMAT_R32G32_USCALED,         R32G32_USCALED},
 489       {PIPE_FORMAT_R32G32B32_USCALED,      R32G32B32_USCALED},
 490       {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
 491
 492       {PIPE_FORMAT_R32_SSCALED,            R32_SSCALED},
 493       {PIPE_FORMAT_R32G32_SSCALED,         R32G32_SSCALED},
 494       {PIPE_FORMAT_R32G32B32_SSCALED,      R32G32B32_SSCALED},
 495       {PIPE_FORMAT_R32G32B32A32_SSCALED,   R32G32B32A32_SSCALED},
 496
 497       {PIPE_FORMAT_R32_UINT,               R32_UINT},
 498       {PIPE_FORMAT_R32G32_UINT,            R32G32_UINT},
 499       {PIPE_FORMAT_R32G32B32_UINT,         R32G32B32_UINT},
 500       {PIPE_FORMAT_R32G32B32A32_UINT,      R32G32B32A32_UINT},
 501
 502       {PIPE_FORMAT_R32_SINT,               R32_SINT},
 503       {PIPE_FORMAT_R32G32_SINT,            R32G32_SINT},
 504       {PIPE_FORMAT_R32G32B32_SINT,         R32G32B32_SINT},
 505       {PIPE_FORMAT_R32G32B32A32_SINT,      R32G32B32A32_SINT},
 506
 507       /* 16 bits per component */
 508       {PIPE_FORMAT_R16_UNORM,              R16_UNORM},
 509       {PIPE_FORMAT_R16G16_UNORM,           R16G16_UNORM},
 510       {PIPE_FORMAT_R16G16B16_UNORM,        R16G16B16_UNORM},
 511       {PIPE_FORMAT_R16G16B16A16_UNORM,     R16G16B16A16_UNORM},
 512       {PIPE_FORMAT_R16G16B16X16_UNORM,     R16G16B16X16_UNORM},
 513
 514       {PIPE_FORMAT_R16_USCALED,            R16_USCALED},
 515       {PIPE_FORMAT_R16G16_USCALED,         R16G16_USCALED},
 516       {PIPE_FORMAT_R16G16B16_USCALED,      R16G16B16_USCALED},
 517       {PIPE_FORMAT_R16G16B16A16_USCALED,   R16G16B16A16_USCALED},
 518
 519       {PIPE_FORMAT_R16_SNORM,              R16_SNORM},
 520       {PIPE_FORMAT_R16G16_SNORM,           R16G16_SNORM},
 521       {PIPE_FORMAT_R16G16B16_SNORM,        R16G16B16_SNORM},
 522       {PIPE_FORMAT_R16G16B16A16_SNORM,     R16G16B16A16_SNORM},
 523
 524       {PIPE_FORMAT_R16_SSCALED,            R16_SSCALED},
 525       {PIPE_FORMAT_R16G16_SSCALED,         R16G16_SSCALED},
 526       {PIPE_FORMAT_R16G16B16_SSCALED,      R16G16B16_SSCALED},
 527       {PIPE_FORMAT_R16G16B16A16_SSCALED,   R16G16B16A16_SSCALED},
 528
 529       {PIPE_FORMAT_R16_UINT,               R16_UINT},
 530       {PIPE_FORMAT_R16G16_UINT,            R16G16_UINT},
 531       {PIPE_FORMAT_R16G16B16_UINT,         R16G16B16_UINT},
 532       {PIPE_FORMAT_R16G16B16A16_UINT,      R16G16B16A16_UINT},
 533
 534       {PIPE_FORMAT_R16_SINT,               R16_SINT},
 535       {PIPE_FORMAT_R16G16_SINT,            R16G16_SINT},
 536       {PIPE_FORMAT_R16G16B16_SINT,         R16G16B16_SINT},
 537       {PIPE_FORMAT_R16G16B16A16_SINT,      R16G16B16A16_SINT},
 538
 539       {PIPE_FORMAT_R16_FLOAT,              R16_FLOAT},
 540       {PIPE_FORMAT_R16G16_FLOAT,           R16G16_FLOAT},
 541       {PIPE_FORMAT_R16G16B16_FLOAT,        R16G16B16_FLOAT},
 542       {PIPE_FORMAT_R16G16B16A16_FLOAT,     R16G16B16A16_FLOAT},
 543       {PIPE_FORMAT_R16G16B16X16_FLOAT,     R16G16B16X16_FLOAT},
 544
 545       /* 8 bits per component */
 546       {PIPE_FORMAT_R8_UNORM,               R8_UNORM},
 547       {PIPE_FORMAT_R8G8_UNORM,             R8G8_UNORM},
 548       {PIPE_FORMAT_R8G8B8_UNORM,           R8G8B8_UNORM},
 549       {PIPE_FORMAT_R8G8B8_SRGB,            R8G8B8_UNORM_SRGB},
 550       {PIPE_FORMAT_R8G8B8A8_UNORM,         R8G8B8A8_UNORM},
 551       {PIPE_FORMAT_R8G8B8A8_SRGB,          R8G8B8A8_UNORM_SRGB},
 552       {PIPE_FORMAT_R8G8B8X8_UNORM,         R8G8B8X8_UNORM},
 553       {PIPE_FORMAT_R8G8B8X8_SRGB,          R8G8B8X8_UNORM_SRGB},
 554
 555       {PIPE_FORMAT_R8_USCALED,             R8_USCALED},
 556       {PIPE_FORMAT_R8G8_USCALED,           R8G8_USCALED},
 557       {PIPE_FORMAT_R8G8B8_USCALED,         R8G8B8_USCALED},
 558       {PIPE_FORMAT_R8G8B8A8_USCALED,       R8G8B8A8_USCALED},
 559
 560       {PIPE_FORMAT_R8_SNORM,               R8_SNORM},
 561       {PIPE_FORMAT_R8G8_SNORM,             R8G8_SNORM},
 562       {PIPE_FORMAT_R8G8B8_SNORM,           R8G8B8_SNORM},
 563       {PIPE_FORMAT_R8G8B8A8_SNORM,         R8G8B8A8_SNORM},
 564
 565       {PIPE_FORMAT_R8_SSCALED,             R8_SSCALED},
 566       {PIPE_FORMAT_R8G8_SSCALED,           R8G8_SSCALED},
 567       {PIPE_FORMAT_R8G8B8_SSCALED,         R8G8B8_SSCALED},
 568       {PIPE_FORMAT_R8G8B8A8_SSCALED,       R8G8B8A8_SSCALED},
 569
 570       {PIPE_FORMAT_R8_UINT,                R8_UINT},
 571       {PIPE_FORMAT_R8G8_UINT,              R8G8_UINT},
 572       {PIPE_FORMAT_R8G8B8_UINT,            R8G8B8_UINT},
 573       {PIPE_FORMAT_R8G8B8A8_UINT,          R8G8B8A8_UINT},
 574
 575       {PIPE_FORMAT_R8_SINT,                R8_SINT},
 576       {PIPE_FORMAT_R8G8_SINT,              R8G8_SINT},
 577       {PIPE_FORMAT_R8G8B8_SINT,            R8G8B8_SINT},
 578       {PIPE_FORMAT_R8G8B8A8_SINT,          R8G8B8A8_SINT},
 579
 580       /* These formats are valid for vertex data, but should not be used
 581        * for render targets.
 582        */
 583
 584       {PIPE_FORMAT_R32_FIXED,              R32_SFIXED},
 585       {PIPE_FORMAT_R32G32_FIXED,           R32G32_SFIXED},
 586       {PIPE_FORMAT_R32G32B32_FIXED,        R32G32B32_SFIXED},
 587       {PIPE_FORMAT_R32G32B32A32_FIXED,     R32G32B32A32_SFIXED},
 588
 589       {PIPE_FORMAT_R64_FLOAT,              R64_FLOAT},
 590       {PIPE_FORMAT_R64G64_FLOAT,           R64G64_FLOAT},
 591       {PIPE_FORMAT_R64G64B64_FLOAT,        R64G64B64_FLOAT},
 592       {PIPE_FORMAT_R64G64B64A64_FLOAT,     R64G64B64A64_FLOAT},
 593
 594       /* These formats have entries in SWR but don't have Load/StoreTile
 595        * implementations. That means these aren't renderable, and thus having
 596        * a mapping entry here is detrimental.
 597        */
 598       /*
 599
 600       {PIPE_FORMAT_L8_UNORM,               L8_UNORM},
 601       {PIPE_FORMAT_I8_UNORM,               I8_UNORM},
 602       {PIPE_FORMAT_L8A8_UNORM,             L8A8_UNORM},
 603       {PIPE_FORMAT_L16_UNORM,              L16_UNORM},
 604       {PIPE_FORMAT_UYVY,                   YCRCB_SWAPUVY},
 605
 606       {PIPE_FORMAT_L8_SRGB,                L8_UNORM_SRGB},
 607       {PIPE_FORMAT_L8A8_SRGB,              L8A8_UNORM_SRGB},
 608
 609       {PIPE_FORMAT_DXT1_RGBA,              BC1_UNORM},
 610       {PIPE_FORMAT_DXT3_RGBA,              BC2_UNORM},
 611       {PIPE_FORMAT_DXT5_RGBA,              BC3_UNORM},
 612
 613       {PIPE_FORMAT_DXT1_SRGBA,             BC1_UNORM_SRGB},
 614       {PIPE_FORMAT_DXT3_SRGBA,             BC2_UNORM_SRGB},
 615       {PIPE_FORMAT_DXT5_SRGBA,             BC3_UNORM_SRGB},
 616
 617       {PIPE_FORMAT_RGTC1_UNORM,            BC4_UNORM},
 618       {PIPE_FORMAT_RGTC1_SNORM,            BC4_SNORM},
 619       {PIPE_FORMAT_RGTC2_UNORM,            BC5_UNORM},
 620       {PIPE_FORMAT_RGTC2_SNORM,            BC5_SNORM},
 621
 622       {PIPE_FORMAT_L16A16_UNORM,           L16A16_UNORM},
 623       {PIPE_FORMAT_I16_UNORM,              I16_UNORM},
 624       {PIPE_FORMAT_L16_FLOAT,              L16_FLOAT},
 625       {PIPE_FORMAT_L16A16_FLOAT,           L16A16_FLOAT},
 626       {PIPE_FORMAT_I16_FLOAT,              I16_FLOAT},
 627       {PIPE_FORMAT_L32_FLOAT,              L32_FLOAT},
 628       {PIPE_FORMAT_L32A32_FLOAT,           L32A32_FLOAT},
 629       {PIPE_FORMAT_I32_FLOAT,              I32_FLOAT},
 630
 631       {PIPE_FORMAT_I8_UINT,                I8_UINT},
 632       {PIPE_FORMAT_L8_UINT,                L8_UINT},
 633       {PIPE_FORMAT_L8A8_UINT,              L8A8_UINT},
 634
 635       {PIPE_FORMAT_I8_SINT,                I8_SINT},
 636       {PIPE_FORMAT_L8_SINT,                L8_SINT},
 637       {PIPE_FORMAT_L8A8_SINT,              L8A8_SINT},
 638
 639       */
 640    };
 641
 642    auto it = mesa2swr.find(format);
 643    if (it == mesa2swr.end())
 644       return (SWR_FORMAT)-1;
 645    else
 646       return it->second;
 647 }
 648
 649 static boolean
 650 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
 651 {
 652    struct sw_winsys *winsys = screen->winsys;
 653    struct sw_displaytarget *dt;
 654
 655    const unsigned width = align(res->swr.width, res->swr.halign);
 656    const unsigned height = align(res->swr.height, res->swr.valign);
 657
 658    UINT stride;
 659    dt = winsys->displaytarget_create(winsys,
 660                                      res->base.bind,
 661                                      res->base.format,
 662                                      width, height,
 663                                      64, NULL,
 664                                      &stride);
 665
 666    if (dt == NULL)
 667       return FALSE;
 668
 669    void *map = winsys->displaytarget_map(winsys, dt, 0);
 670
 671    res->display_target = dt;
 672    res->swr.xpBaseAddress = (gfxptr_t)map;
 673
 674    /* Clear the display target surface */
 675    if (map)
 676       memset(map, 0, height * stride);
 677
 678    winsys->displaytarget_unmap(winsys, dt);
 679
 680    return TRUE;
 681 }
 682
 683 static bool
 684 swr_texture_layout(struct swr_screen *screen,
 685                    struct swr_resource *res,
 686                    boolean allocate)
 687 {
 688    struct pipe_resource *pt = &res->base;
 689
 690    pipe_format fmt = pt->format;
 691    const struct util_format_description *desc = util_format_description(fmt);
 692
 693    res->has_depth = util_format_has_depth(desc);
 694    res->has_stencil = util_format_has_stencil(desc);
 695
 696    if (res->has_stencil && !res->has_depth)
 697       fmt = PIPE_FORMAT_R8_UINT;
 698
 699    /* We always use the SWR layout. For 2D and 3D textures this looks like:
 700     *
 701     * |<------- pitch ------->|
 702     * +=======================+-------
 703     * |Array 0                |   ^
 704     * |                       |   |
 705     * |        Level 0        |   |
 706     * |                       |   |
 707     * |                       | qpitch
 708     * +-----------+-----------+   |
 709     * |           | L2L2L2L2  |   |
 710     * |  Level 1  | L3L3      |   |
 711     * |           | L4        |   v
 712     * +===========+===========+-------
 713     * |Array 1                |
 714     * |                       |
 715     * |        Level 0        |
 716     * |                       |
 717     * |                       |
 718     * +-----------+-----------+
 719     * |           | L2L2L2L2  |
 720     * |  Level 1  | L3L3      |
 721     * |           | L4        |
 722     * +===========+===========+
 723     *
 724     * The overall width in bytes is known as the pitch, while the overall
 725     * height in rows is the qpitch. Array slices are laid out logically below
 726     * one another, qpitch rows apart. For 3D surfaces, the "level" values are
 727     * just invalid for the higher array numbers (since depth is also
 728     * minified). 1D and 1D array surfaces are stored effectively the same way,
 729     * except that pitch never plays into it. All the levels are logically
 730     * adjacent to each other on the X axis. The qpitch becomes the number of
 731     * elements between array slices, while the pitch is unused.
 732     *
 733     * Each level's sizes are subject to the valign and halign settings of the
 734     * surface. For compressed formats that swr is unaware of, we will use an
 735     * appropriately-sized uncompressed format, and scale the widths/heights.
 736     *
 737     * This surface is stored inside res->swr. For depth/stencil textures,
 738     * res->secondary will have an identically-laid-out but R8_UINT-formatted
 739     * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
 740     * texels, to simplify map/unmap logic which copies the stencil values
 741     * in/out.
 742     */
 743
 744    res->swr.width = pt->width0;
 745    res->swr.height = pt->height0;
 746    res->swr.type = swr_convert_target_type(pt->target);
 747    res->swr.tileMode = SWR_TILE_NONE;
 748    res->swr.format = mesa_to_swr_format(fmt);
 749    res->swr.numSamples = std::max(1u, pt->nr_samples);
 750
 751    if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
 752       res->swr.halign = KNOB_MACROTILE_X_DIM;
 753       res->swr.valign = KNOB_MACROTILE_Y_DIM;
 754
 755       /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
 756        * surface sample count. */
 757       if (screen->msaa_force_enable) {
 758          res->swr.numSamples = screen->msaa_max_count;
 759          fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
 760                  res->swr.numSamples);
 761       }
 762    } else {
 763       res->swr.halign = 1;
 764       res->swr.valign = 1;
 765    }
 766
 767    unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
 768    unsigned width = align(pt->width0, halign);
 769    if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
 770       for (int level = 1; level <= pt->last_level; level++)
 771          width += align(u_minify(pt->width0, level), halign);
 772       res->swr.pitch = util_format_get_blocksize(fmt);
 773       res->swr.qpitch = util_format_get_nblocksx(fmt, width);
 774    } else {
 775       // The pitch is the overall width of the texture in bytes. Most of the
 776       // time this is the pitch of level 0 since all the other levels fit
 777       // underneath it. However in some degenerate situations, the width of
 778       // level1 + level2 may be larger. In that case, we use those
 779       // widths. This can happen if, e.g. halign is 32, and the width of level
 780       // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
 781       // be 32 each, adding up to 64.
 782       unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
 783       if (pt->last_level > 1) {
 784          width = std::max<uint32_t>(
 785                width,
 786                align(u_minify(pt->width0, 1), halign) +
 787                align(u_minify(pt->width0, 2), halign));
 788       }
 789       res->swr.pitch = util_format_get_stride(fmt, width);
 790
 791       // The qpitch is controlled by either the height of the second LOD, or
 792       // the combination of all the later LODs.
 793       unsigned height = align(pt->height0, valign);
 794       if (pt->last_level == 1) {
 795          height += align(u_minify(pt->height0, 1), valign);
 796       } else if (pt->last_level > 1) {
 797          unsigned level1 = align(u_minify(pt->height0, 1), valign);
 798          unsigned level2 = 0;
 799          for (int level = 2; level <= pt->last_level; level++) {
 800             level2 += align(u_minify(pt->height0, level), valign);
 801          }
 802          height += std::max(level1, level2);
 803       }
 804       res->swr.qpitch = util_format_get_nblocksy(fmt, height);
 805    }
 806
 807    if (pt->target == PIPE_TEXTURE_3D)
 808       res->swr.depth = pt->depth0;
 809    else
 810       res->swr.depth = pt->array_size;
 811
 812    // Fix up swr format if necessary so that LOD offset computation works
 813    if (res->swr.format == (SWR_FORMAT)-1) {
 814       switch (util_format_get_blocksize(fmt)) {
 815       default:
 816          unreachable("Unexpected format block size");
 817       case 1: res->swr.format = R8_UINT; break;
 818       case 2: res->swr.format = R16_UINT; break;
 819       case 4: res->swr.format = R32_UINT; break;
 820       case 8:
 821          if (util_format_is_compressed(fmt))
 822             res->swr.format = BC4_UNORM;
 823          else
 824             res->swr.format = R32G32_UINT;
 825          break;
 826       case 16:
 827          if (util_format_is_compressed(fmt))
 828             res->swr.format = BC5_UNORM;
 829          else
 830             res->swr.format = R32G32B32A32_UINT;
 831          break;
 832       }
 833    }
 834
 835    for (int level = 0; level <= pt->last_level; level++) {
 836       res->mip_offsets[level] =
 837          ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
 838    }
 839
 840    size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
 841                                  res->swr.pitch * res->swr.numSamples;
 842    if (total_size > SWR_MAX_TEXTURE_SIZE)
 843       return false;
 844
 845    if (allocate) {
 846       res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
 847       if (!res->swr.xpBaseAddress)
 848          return false;
 849
 850       if (res->has_depth && res->has_stencil) {
 851          res->secondary = res->swr;
 852          res->secondary.format = R8_UINT;
 853          res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
 854
 855          for (int level = 0; level <= pt->last_level; level++) {
 856             res->secondary_mip_offsets[level] =
 857                ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
 858          }
 859
 860          total_size = res->secondary.depth * res->secondary.qpitch *
 861                       res->secondary.pitch * res->secondary.numSamples;
 862
 863          res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
 864          if (!res->secondary.xpBaseAddress) {
 865             AlignedFree((void *)res->swr.xpBaseAddress);
 866             return false;
 867          }
 868       }
 869    }
 870
 871    return true;
 872 }
 873
 874 static boolean
 875 swr_can_create_resource(struct pipe_screen *screen,
 876                         const struct pipe_resource *templat)
 877 {
 878    struct swr_resource res;
 879    memset(&res, 0, sizeof(res));
 880    res.base = *templat;
 881    return swr_texture_layout(swr_screen(screen), &res, false);
 882 }
 883
 884 /* Helper function that conditionally creates a single-sample resolve resource
 885  * and attaches it to main multisample resource. */
 886 static boolean
 887 swr_create_resolve_resource(struct pipe_screen *_screen,
 888                             struct swr_resource *msaa_res)
 889 {
 890    struct swr_screen *screen = swr_screen(_screen);
 891
 892    /* If resource is multisample, create a single-sample resolve resource */
 893    if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
 894             !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
 895
 896       /* Create a single-sample copy of the resource.  Copy the original
 897        * resource parameters and set flag to prevent recursion when re-calling
 898        * resource_create */
 899       struct pipe_resource alt_template = msaa_res->base;
 900       alt_template.nr_samples = 0;
 901       alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
 902
 903       /* Note: Display_target is a special single-sample resource, only the
 904        * display_target has been created already. */
 905       if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 906                | PIPE_BIND_SHARED)) {
 907          /* Allocate the multisample buffers. */
 908          if (!swr_texture_layout(screen, msaa_res, true))
 909             return false;
 910
 911          /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
 912           * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
 913          alt_template.bind = PIPE_BIND_RENDER_TARGET;
 914       }
 915
 916       /* Allocate single-sample resolve surface */
 917       struct pipe_resource *alt;
 918       alt = _screen->resource_create(_screen, &alt_template);
 919       if (!alt)
 920          return false;
 921
 922       /* Attach it to the multisample resource */
 923       msaa_res->resolve_target = alt;
 924
 925       /* Hang resolve surface state off the multisample surface state to so
 926        * StoreTiles knows where to resolve the surface. */
 927       msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
 928    }
 929
 930    return true; /* success */
 931 }
 932
 933 static struct pipe_resource *
 934 swr_resource_create(struct pipe_screen *_screen,
 935                     const struct pipe_resource *templat)
 936 {
 937    struct swr_screen *screen = swr_screen(_screen);
 938    struct swr_resource *res = CALLOC_STRUCT(swr_resource);
 939    if (!res)
 940       return NULL;
 941
 942    res->base = *templat;
 943    pipe_reference_init(&res->base.reference, 1);
 944    res->base.screen = &screen->base;
 945
 946    if (swr_resource_is_texture(&res->base)) {
 947       if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 948                             | PIPE_BIND_SHARED)) {
 949          /* displayable surface
 950           * first call swr_texture_layout without allocating to finish
 951           * filling out the SWR_SURFACE_STATE in res */
 952          swr_texture_layout(screen, res, false);
 953          if (!swr_displaytarget_layout(screen, res))
 954             goto fail;
 955       } else {
 956          /* texture map */
 957          if (!swr_texture_layout(screen, res, true))
 958             goto fail;
 959       }
 960
 961       /* If resource was multisample, create resolve resource and attach
 962        * it to multisample resource. */
 963       if (!swr_create_resolve_resource(_screen, res))
 964             goto fail;
 965
 966    } else {
 967       /* other data (vertex buffer, const buffer, etc) */
 968       assert(util_format_get_blocksize(templat->format) == 1);
 969       assert(templat->height0 == 1);
 970       assert(templat->depth0 == 1);
 971       assert(templat->last_level == 0);
 972
 973       /* Easiest to just call swr_texture_layout, as it sets up
 974        * SWR_SURFACE_STATE in res */
 975       if (!swr_texture_layout(screen, res, true))
 976          goto fail;
 977    }
 978
 979    return &res->base;
 980
 981 fail:
 982    FREE(res);
 983    return NULL;
 984 }
 985
 986 static void
 987 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
 988 {
 989    struct swr_screen *screen = swr_screen(p_screen);
 990    struct swr_resource *spr = swr_resource(pt);
 991
 992    if (spr->display_target) {
 993       /* If resource is display target, winsys manages the buffer and will
 994        * free it on displaytarget_destroy. */
 995       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 996
 997       struct sw_winsys *winsys = screen->winsys;
 998       winsys->displaytarget_destroy(winsys, spr->display_target);
 999
1000       if (spr->swr.numSamples > 1) {
1001          /* Free an attached resolve resource */
1002          struct swr_resource *alt = swr_resource(spr->resolve_target);
1003          swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1004
1005          /* Free multisample buffer */
1006          swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1007       }
1008    } else {
1009       /* For regular resources, defer deletion */
1010       swr_resource_unused(pt);
1011
1012       if (spr->swr.numSamples > 1) {
1013          /* Free an attached resolve resource */
1014          struct swr_resource *alt = swr_resource(spr->resolve_target);
1015          swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1016       }
1017
1018       swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1019       swr_fence_work_free(screen->flush_fence,
1020                           (void*)(spr->secondary.xpBaseAddress), true);
1021
1022       /* If work queue grows too large, submit a fence to force queue to
1023        * drain.  This is mainly to decrease the amount of memory used by the
1024        * piglit streaming-texture-leak test */
1025       if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1026          swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1027    }
1028
1029    FREE(spr);
1030 }
1031
1032
1033 static void
1034 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1035                       struct pipe_resource *resource,
1036                       unsigned level,
1037                       unsigned layer,
1038                       void *context_private,
1039                       struct pipe_box *sub_box)
1040 {
1041    struct swr_screen *screen = swr_screen(p_screen);
1042    struct sw_winsys *winsys = screen->winsys;
1043    struct swr_resource *spr = swr_resource(resource);
1044    struct pipe_context *pipe = screen->pipe;
1045    struct swr_context *ctx = swr_context(pipe);
1046
1047    if (pipe) {
1048       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1049       swr_resource_unused(resource);
1050       ctx->api.pfnSwrEndFrame(ctx->swrContext);
1051    }
1052
1053    /* Multisample resolved into resolve_target at flush with store_resource */
1054    if (pipe && spr->swr.numSamples > 1) {
1055       struct pipe_resource *resolve_target = spr->resolve_target;
1056
1057       /* Once resolved, copy into display target */
1058       SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1059
1060       void *map = winsys->displaytarget_map(winsys, spr->display_target,
1061                                             PIPE_TRANSFER_WRITE);
1062       memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1063       winsys->displaytarget_unmap(winsys, spr->display_target);
1064    }
1065
1066    debug_assert(spr->display_target);
1067    if (spr->display_target)
1068       winsys->displaytarget_display(
1069          winsys, spr->display_target, context_private, sub_box);
1070 }
1071
1072
1073 void
1074 swr_destroy_screen_internal(struct swr_screen **screen)
1075 {
1076    struct pipe_screen *p_screen = &(*screen)->base;
1077
1078    swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1079    swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1080
1081    JitDestroyContext((*screen)->hJitMgr);
1082
1083    if ((*screen)->pLibrary)
1084       util_dl_close((*screen)->pLibrary);
1085
1086    FREE(*screen);
1087    *screen = NULL;
1088 }
1089
1090
1091 static void
1092 swr_destroy_screen(struct pipe_screen *p_screen)
1093 {
1094    struct swr_screen *screen = swr_screen(p_screen);
1095    struct sw_winsys *winsys = screen->winsys;
1096
1097    fprintf(stderr, "SWR destroy screen!\n");
1098
1099    if (winsys->destroy)
1100       winsys->destroy(winsys);
1101
1102    swr_destroy_screen_internal(&screen);
1103 }
1104
1105
1106 static void
1107 swr_validate_env_options(struct swr_screen *screen)
1108 {
1109    /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1110     * copied to scratch space on a draw.  Past this, the draw will access
1111     * user-buffer directly and then block.  This is faster than queuing many
1112     * large client draws. */
1113    screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1114    int client_copy_limit =
1115       debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1116    if (client_copy_limit > 0)
1117       screen->client_copy_limit = client_copy_limit;
1118
1119    /* XXX msaa under development, disable by default for now */
1120    screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1121
1122    /* validate env override values, within range and power of 2 */
1123    int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1124    if (msaa_max_count != 1) {
1125       if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1126             || !util_is_power_of_two_or_zero(msaa_max_count)) {
1127          fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1128          fprintf(stderr, "must be power of 2 between 1 and %d" \
1129                          " (or 1 to disable msaa)\n",
1130                SWR_MAX_NUM_MULTISAMPLES);
1131          msaa_max_count = 1;
1132       }
1133
1134       fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1135       if (msaa_max_count == 1)
1136          fprintf(stderr, "(msaa disabled)\n");
1137
1138       screen->msaa_max_count = msaa_max_count;
1139    }
1140
1141    screen->msaa_force_enable = debug_get_bool_option(
1142          "SWR_MSAA_FORCE_ENABLE", false);
1143    if (screen->msaa_force_enable)
1144       fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1145 }
1146
1147
1148 struct pipe_screen *
1149 swr_create_screen_internal(struct sw_winsys *winsys)
1150 {
1151    struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1152
1153    if (!screen)
1154       return NULL;
1155
1156    if (!lp_build_init()) {
1157       FREE(screen);
1158       return NULL;
1159    }
1160
1161    screen->winsys = winsys;
1162    screen->base.get_name = swr_get_name;
1163    screen->base.get_vendor = swr_get_vendor;
1164    screen->base.is_format_supported = swr_is_format_supported;
1165    screen->base.context_create = swr_create_context;
1166    screen->base.can_create_resource = swr_can_create_resource;
1167
1168    screen->base.destroy = swr_destroy_screen;
1169    screen->base.get_param = swr_get_param;
1170    screen->base.get_shader_param = swr_get_shader_param;
1171    screen->base.get_paramf = swr_get_paramf;
1172
1173    screen->base.resource_create = swr_resource_create;
1174    screen->base.resource_destroy = swr_resource_destroy;
1175
1176    screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1177
1178    // Pass in "" for architecture for run-time determination
1179    screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1180
1181    swr_fence_init(&screen->base);
1182
1183    swr_validate_env_options(screen);
1184
1185    return &screen->base;
1186 }
1187