src/gallium/drivers/vc4/vc4_program.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <inttypes.h>
  26 #include "util/u_format.h"
  27 #include "util/u_hash.h"
  28 #include "util/u_math.h"
  29 #include "util/u_memory.h"
  30 #include "util/ralloc.h"
  31 #include "util/hash_table.h"
  32 #include "tgsi/tgsi_dump.h"
  33 #include "tgsi/tgsi_lowering.h"
  34 #include "tgsi/tgsi_parse.h"
  35 #include "glsl/nir/nir.h"
  36 #include "glsl/nir/nir_builder.h"
  37 #include "nir/tgsi_to_nir.h"
  38 #include "vc4_context.h"
  39 #include "vc4_qpu.h"
  40 #include "vc4_qir.h"
  41 #ifdef USE_VC4_SIMULATOR
  42 #include "simpenrose/simpenrose.h"
  43 #endif
  44
  45 static struct qreg
  46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
  47
  48 static void
  49 resize_qreg_array(struct vc4_compile *c,
  50                   struct qreg **regs,
  51                   uint32_t *size,
  52                   uint32_t decl_size)
  53 {
  54         if (*size >= decl_size)
  55                 return;
  56
  57         uint32_t old_size = *size;
  58         *size = MAX2(*size * 2, decl_size);
  59         *regs = reralloc(c, *regs, struct qreg, *size);
  60         if (!*regs) {
  61                 fprintf(stderr, "Malloc failure\n");
  62                 abort();
  63         }
  64
  65         for (uint32_t i = old_size; i < *size; i++)
  66                 (*regs)[i] = c->undef;
  67 }
  68
  69 static struct qreg
  70 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
  71 {
  72         struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
  73         uint32_t offset = intr->const_index[0];
  74         struct vc4_compiler_ubo_range *range = NULL;
  75         unsigned i;
  76         for (i = 0; i < c->num_uniform_ranges; i++) {
  77                 range = &c->ubo_ranges[i];
  78                 if (offset >= range->src_offset &&
  79                     offset < range->src_offset + range->size) {
  80                         break;
  81                 }
  82         }
  83         /* The driver-location-based offset always has to be within a declared
  84          * uniform range.
  85          */
  86         assert(range);
  87         if (!range->used) {
  88                 range->used = true;
  89                 range->dst_offset = c->next_ubo_dst_offset;
  90                 c->next_ubo_dst_offset += range->size;
  91                 c->num_ubo_ranges++;
  92         };
  93
  94         offset -= range->src_offset;
  95
  96         /* Adjust for where we stored the TGSI register base. */
  97         indirect_offset = qir_ADD(c, indirect_offset,
  98                                   qir_uniform_ui(c, (range->dst_offset +
  99                                                      offset)));
 100
 101         /* Clamp to [0, array size).  Note that MIN/MAX are signed. */
 102         indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
 103         indirect_offset = qir_MIN(c, indirect_offset,
 104                                   qir_uniform_ui(c, (range->dst_offset +
 105                                                      range->size - 4)));
 106
 107         qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
 108         c->num_texture_samples++;
 109         return qir_TEX_RESULT(c);
 110 }
 111
 112 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
 113                                        enum quniform_contents contents)
 114 {
 115         nir_intrinsic_instr *intr =
 116                 nir_intrinsic_instr_create(b->shader,
 117                                            nir_intrinsic_load_uniform);
 118         intr->const_index[0] = VC4_NIR_STATE_UNIFORM_OFFSET + contents;
 119         intr->num_components = 1;
 120         nir_ssa_dest_init(&intr->instr, &intr->dest, 1, NULL);
 121         nir_builder_instr_insert(b, &intr->instr);
 122         return &intr->dest.ssa;
 123 }
 124
 125 nir_ssa_def *
 126 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
 127 {
 128         switch (swiz) {
 129         default:
 130         case UTIL_FORMAT_SWIZZLE_NONE:
 131                 fprintf(stderr, "warning: unknown swizzle\n");
 132                 /* FALLTHROUGH */
 133         case UTIL_FORMAT_SWIZZLE_0:
 134                 return nir_imm_float(b, 0.0);
 135         case UTIL_FORMAT_SWIZZLE_1:
 136                 return nir_imm_float(b, 1.0);
 137         case UTIL_FORMAT_SWIZZLE_X:
 138         case UTIL_FORMAT_SWIZZLE_Y:
 139         case UTIL_FORMAT_SWIZZLE_Z:
 140         case UTIL_FORMAT_SWIZZLE_W:
 141                 return srcs[swiz];
 142         }
 143 }
 144
 145 static struct qreg *
 146 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
 147 {
 148         struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
 149                                           def->num_components);
 150         _mesa_hash_table_insert(c->def_ht, def, qregs);
 151         return qregs;
 152 }
 153
 154 static struct qreg *
 155 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
 156 {
 157         if (dest->is_ssa) {
 158                 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
 159                 for (int i = 0; i < dest->ssa.num_components; i++)
 160                         qregs[i] = c->undef;
 161                 return qregs;
 162         } else {
 163                 nir_register *reg = dest->reg.reg;
 164                 assert(dest->reg.base_offset == 0);
 165                 assert(reg->num_array_elems == 0);
 166                 struct hash_entry *entry =
 167                         _mesa_hash_table_search(c->def_ht, reg);
 168                 return entry->data;
 169         }
 170 }
 171
 172 static struct qreg
 173 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
 174 {
 175         struct hash_entry *entry;
 176         if (src.is_ssa) {
 177                 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
 178                 assert(i < src.ssa->num_components);
 179         } else {
 180                 nir_register *reg = src.reg.reg;
 181                 entry = _mesa_hash_table_search(c->def_ht, reg);
 182                 assert(reg->num_array_elems == 0);
 183                 assert(src.reg.base_offset == 0);
 184                 assert(i < reg->num_components);
 185         }
 186
 187         struct qreg *qregs = entry->data;
 188         return qregs[i];
 189 }
 190
 191 static struct qreg
 192 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
 193                 unsigned src)
 194 {
 195         assert(util_is_power_of_two(instr->dest.write_mask));
 196         unsigned chan = ffs(instr->dest.write_mask) - 1;
 197         struct qreg r = ntq_get_src(c, instr->src[src].src,
 198                                     instr->src[src].swizzle[chan]);
 199
 200         assert(!instr->src[src].abs);
 201         assert(!instr->src[src].negate);
 202
 203         return r;
 204 };
 205
 206 static struct qreg
 207 get_swizzled_channel(struct vc4_compile *c,
 208                      struct qreg *srcs, int swiz)
 209 {
 210         switch (swiz) {
 211         default:
 212         case UTIL_FORMAT_SWIZZLE_NONE:
 213                 fprintf(stderr, "warning: unknown swizzle\n");
 214                 /* FALLTHROUGH */
 215         case UTIL_FORMAT_SWIZZLE_0:
 216                 return qir_uniform_f(c, 0.0);
 217         case UTIL_FORMAT_SWIZZLE_1:
 218                 return qir_uniform_f(c, 1.0);
 219         case UTIL_FORMAT_SWIZZLE_X:
 220         case UTIL_FORMAT_SWIZZLE_Y:
 221         case UTIL_FORMAT_SWIZZLE_Z:
 222         case UTIL_FORMAT_SWIZZLE_W:
 223                 return srcs[swiz];
 224         }
 225 }
 226
 227 static inline struct qreg
 228 qir_SAT(struct vc4_compile *c, struct qreg val)
 229 {
 230         return qir_FMAX(c,
 231                         qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
 232                         qir_uniform_f(c, 0.0));
 233 }
 234
 235 static struct qreg
 236 ntq_rcp(struct vc4_compile *c, struct qreg x)
 237 {
 238         struct qreg r = qir_RCP(c, x);
 239
 240         /* Apply a Newton-Raphson step to improve the accuracy. */
 241         r = qir_FMUL(c, r, qir_FSUB(c,
 242                                     qir_uniform_f(c, 2.0),
 243                                     qir_FMUL(c, x, r)));
 244
 245         return r;
 246 }
 247
 248 static struct qreg
 249 ntq_rsq(struct vc4_compile *c, struct qreg x)
 250 {
 251         struct qreg r = qir_RSQ(c, x);
 252
 253         /* Apply a Newton-Raphson step to improve the accuracy. */
 254         r = qir_FMUL(c, r, qir_FSUB(c,
 255                                     qir_uniform_f(c, 1.5),
 256                                     qir_FMUL(c,
 257                                              qir_uniform_f(c, 0.5),
 258                                              qir_FMUL(c, x,
 259                                                       qir_FMUL(c, r, r)))));
 260
 261         return r;
 262 }
 263
 264 static struct qreg
 265 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
 266 {
 267         struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
 268         struct qreg high = qir_POW(c,
 269                                    qir_FMUL(c,
 270                                             qir_FADD(c,
 271                                                      srgb,
 272                                                      qir_uniform_f(c, 0.055)),
 273                                             qir_uniform_f(c, 1.0 / 1.055)),
 274                                    qir_uniform_f(c, 2.4));
 275
 276         qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
 277         return qir_SEL_X_Y_NS(c, low, high);
 278 }
 279
 280 static struct qreg
 281 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
 282 {
 283         struct qreg src0_hi = qir_SHR(c, src0,
 284                                       qir_uniform_ui(c, 24));
 285         struct qreg src1_hi = qir_SHR(c, src1,
 286                                       qir_uniform_ui(c, 24));
 287
 288         struct qreg hilo = qir_MUL24(c, src0_hi, src1);
 289         struct qreg lohi = qir_MUL24(c, src0, src1_hi);
 290         struct qreg lolo = qir_MUL24(c, src0, src1);
 291
 292         return qir_ADD(c, lolo, qir_SHL(c,
 293                                         qir_ADD(c, hilo, lohi),
 294                                         qir_uniform_ui(c, 24)));
 295 }
 296
 297 static void
 298 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
 299 {
 300         struct qreg s, t, r, lod, proj, compare;
 301         bool is_txb = false, is_txl = false, has_proj = false;
 302         unsigned unit = instr->sampler_index;
 303
 304         for (unsigned i = 0; i < instr->num_srcs; i++) {
 305                 switch (instr->src[i].src_type) {
 306                 case nir_tex_src_coord:
 307                         s = ntq_get_src(c, instr->src[i].src, 0);
 308                         if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
 309                                 t = qir_uniform_f(c, 0.5);
 310                         else
 311                                 t = ntq_get_src(c, instr->src[i].src, 1);
 312                         if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
 313                                 r = ntq_get_src(c, instr->src[i].src, 2);
 314                         break;
 315                 case nir_tex_src_bias:
 316                         lod = ntq_get_src(c, instr->src[i].src, 0);
 317                         is_txb = true;
 318                         break;
 319                 case nir_tex_src_lod:
 320                         lod = ntq_get_src(c, instr->src[i].src, 0);
 321                         is_txl = true;
 322                         break;
 323                 case nir_tex_src_comparitor:
 324                         compare = ntq_get_src(c, instr->src[i].src, 0);
 325                         break;
 326                 case nir_tex_src_projector:
 327                         proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
 328                         s = qir_FMUL(c, s, proj);
 329                         t = qir_FMUL(c, t, proj);
 330                         has_proj = true;
 331                         break;
 332                 default:
 333                         unreachable("unknown texture source");
 334                 }
 335         }
 336
 337         struct qreg texture_u[] = {
 338                 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
 339                 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
 340                 qir_uniform(c, QUNIFORM_CONSTANT, 0),
 341                 qir_uniform(c, QUNIFORM_CONSTANT, 0),
 342         };
 343         uint32_t next_texture_u = 0;
 344
 345         /* There is no native support for GL texture rectangle coordinates, so
 346          * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
 347          * 1]).
 348          */
 349         if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
 350                 s = qir_FMUL(c, s,
 351                              qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
 352                 t = qir_FMUL(c, t,
 353                              qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
 354         }
 355
 356         if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
 357                 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
 358                                            unit | (is_txl << 16));
 359         }
 360
 361         if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
 362                 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
 363                 struct qreg rcp_ma = qir_RCP(c, ma);
 364                 s = qir_FMUL(c, s, rcp_ma);
 365                 t = qir_FMUL(c, t, rcp_ma);
 366                 r = qir_FMUL(c, r, rcp_ma);
 367
 368                 qir_TEX_R(c, r, texture_u[next_texture_u++]);
 369         } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
 370                    c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
 371                    c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
 372                    c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
 373                 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
 374                           texture_u[next_texture_u++]);
 375         }
 376
 377         if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
 378                 s = qir_SAT(c, s);
 379         }
 380
 381         if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
 382                 t = qir_SAT(c, t);
 383         }
 384
 385         qir_TEX_T(c, t, texture_u[next_texture_u++]);
 386
 387         if (is_txl || is_txb)
 388                 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
 389
 390         qir_TEX_S(c, s, texture_u[next_texture_u++]);
 391
 392         c->num_texture_samples++;
 393         struct qreg tex = qir_TEX_RESULT(c);
 394
 395         enum pipe_format format = c->key->tex[unit].format;
 396
 397         struct qreg unpacked[4];
 398         if (util_format_is_depth_or_stencil(format)) {
 399                 struct qreg depthf = qir_ITOF(c, qir_SHR(c, tex,
 400                                                          qir_uniform_ui(c, 8)));
 401                 struct qreg normalized = qir_FMUL(c, depthf,
 402                                                   qir_uniform_f(c, 1.0f/0xffffff));
 403
 404                 struct qreg depth_output;
 405
 406                 struct qreg one = qir_uniform_f(c, 1.0f);
 407                 if (c->key->tex[unit].compare_mode) {
 408                         if (has_proj)
 409                                 compare = qir_FMUL(c, compare, proj);
 410
 411                         switch (c->key->tex[unit].compare_func) {
 412                         case PIPE_FUNC_NEVER:
 413                                 depth_output = qir_uniform_f(c, 0.0f);
 414                                 break;
 415                         case PIPE_FUNC_ALWAYS:
 416                                 depth_output = one;
 417                                 break;
 418                         case PIPE_FUNC_EQUAL:
 419                                 qir_SF(c, qir_FSUB(c, compare, normalized));
 420                                 depth_output = qir_SEL_X_0_ZS(c, one);
 421                                 break;
 422                         case PIPE_FUNC_NOTEQUAL:
 423                                 qir_SF(c, qir_FSUB(c, compare, normalized));
 424                                 depth_output = qir_SEL_X_0_ZC(c, one);
 425                                 break;
 426                         case PIPE_FUNC_GREATER:
 427                                 qir_SF(c, qir_FSUB(c, compare, normalized));
 428                                 depth_output = qir_SEL_X_0_NC(c, one);
 429                                 break;
 430                         case PIPE_FUNC_GEQUAL:
 431                                 qir_SF(c, qir_FSUB(c, normalized, compare));
 432                                 depth_output = qir_SEL_X_0_NS(c, one);
 433                                 break;
 434                         case PIPE_FUNC_LESS:
 435                                 qir_SF(c, qir_FSUB(c, compare, normalized));
 436                                 depth_output = qir_SEL_X_0_NS(c, one);
 437                                 break;
 438                         case PIPE_FUNC_LEQUAL:
 439                                 qir_SF(c, qir_FSUB(c, normalized, compare));
 440                                 depth_output = qir_SEL_X_0_NC(c, one);
 441                                 break;
 442                         }
 443                 } else {
 444                         depth_output = normalized;
 445                 }
 446
 447                 for (int i = 0; i < 4; i++)
 448                         unpacked[i] = depth_output;
 449         } else {
 450                 for (int i = 0; i < 4; i++)
 451                         unpacked[i] = qir_UNPACK_8_F(c, tex, i);
 452         }
 453
 454         const uint8_t *format_swiz = vc4_get_format_swizzle(format);
 455         struct qreg texture_output[4];
 456         for (int i = 0; i < 4; i++) {
 457                 texture_output[i] = get_swizzled_channel(c, unpacked,
 458                                                          format_swiz[i]);
 459         }
 460
 461         if (util_format_is_srgb(format)) {
 462                 for (int i = 0; i < 3; i++)
 463                         texture_output[i] = qir_srgb_decode(c,
 464                                                             texture_output[i]);
 465         }
 466
 467         struct qreg *dest = ntq_get_dest(c, &instr->dest);
 468         for (int i = 0; i < 4; i++) {
 469                 dest[i] = get_swizzled_channel(c, texture_output,
 470                                                c->key->tex[unit].swizzle[i]);
 471         }
 472 }
 473
 474 /**
 475  * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
 476  * to zero).
 477  */
 478 static struct qreg
 479 ntq_ffract(struct vc4_compile *c, struct qreg src)
 480 {
 481         struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
 482         struct qreg diff = qir_FSUB(c, src, trunc);
 483         qir_SF(c, diff);
 484         return qir_SEL_X_Y_NS(c,
 485                               qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
 486                               diff);
 487 }
 488
 489 /**
 490  * Computes floor(x), which is tricky because our FTOI truncates (rounds to
 491  * zero).
 492  */
 493 static struct qreg
 494 ntq_ffloor(struct vc4_compile *c, struct qreg src)
 495 {
 496         struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
 497
 498         /* This will be < 0 if we truncated and the truncation was of a value
 499          * that was < 0 in the first place.
 500          */
 501         qir_SF(c, qir_FSUB(c, src, trunc));
 502
 503         return qir_SEL_X_Y_NS(c,
 504                               qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
 505                               trunc);
 506 }
 507
 508 /**
 509  * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
 510  * zero).
 511  */
 512 static struct qreg
 513 ntq_fceil(struct vc4_compile *c, struct qreg src)
 514 {
 515         struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
 516
 517         /* This will be < 0 if we truncated and the truncation was of a value
 518          * that was > 0 in the first place.
 519          */
 520         qir_SF(c, qir_FSUB(c, trunc, src));
 521
 522         return qir_SEL_X_Y_NS(c,
 523                               qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
 524                               trunc);
 525 }
 526
 527 static struct qreg
 528 ntq_fsin(struct vc4_compile *c, struct qreg src)
 529 {
 530         float coeff[] = {
 531                 -2.0 * M_PI,
 532                 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
 533                 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
 534                 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
 535                 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
 536         };
 537
 538         struct qreg scaled_x =
 539                 qir_FMUL(c,
 540                          src,
 541                          qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
 542
 543         struct qreg x = qir_FADD(c,
 544                                  ntq_ffract(c, scaled_x),
 545                                  qir_uniform_f(c, -0.5));
 546         struct qreg x2 = qir_FMUL(c, x, x);
 547         struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
 548         for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
 549                 x = qir_FMUL(c, x, x2);
 550                 sum = qir_FADD(c,
 551                                sum,
 552                                qir_FMUL(c,
 553                                         x,
 554                                         qir_uniform_f(c, coeff[i])));
 555         }
 556         return sum;
 557 }
 558
 559 static struct qreg
 560 ntq_fcos(struct vc4_compile *c, struct qreg src)
 561 {
 562         float coeff[] = {
 563                 -1.0f,
 564                 pow(2.0 * M_PI, 2) / (2 * 1),
 565                 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
 566                 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
 567                 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
 568                 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
 569         };
 570
 571         struct qreg scaled_x =
 572                 qir_FMUL(c, src,
 573                          qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
 574         struct qreg x_frac = qir_FADD(c,
 575                                       ntq_ffract(c, scaled_x),
 576                                       qir_uniform_f(c, -0.5));
 577
 578         struct qreg sum = qir_uniform_f(c, coeff[0]);
 579         struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
 580         struct qreg x = x2; /* Current x^2, x^4, or x^6 */
 581         for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
 582                 if (i != 1)
 583                         x = qir_FMUL(c, x, x2);
 584
 585                 struct qreg mul = qir_FMUL(c,
 586                                            x,
 587                                            qir_uniform_f(c, coeff[i]));
 588                 if (i == 0)
 589                         sum = mul;
 590                 else
 591                         sum = qir_FADD(c, sum, mul);
 592         }
 593         return sum;
 594 }
 595
 596 static struct qreg
 597 ntq_fsign(struct vc4_compile *c, struct qreg src)
 598 {
 599         qir_SF(c, src);
 600         return qir_SEL_X_Y_NC(c,
 601                               qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
 602                               qir_uniform_f(c, -1.0));
 603 }
 604
 605 static void
 606 emit_vertex_input(struct vc4_compile *c, int attr)
 607 {
 608         enum pipe_format format = c->vs_key->attr_formats[attr];
 609         uint32_t attr_size = util_format_get_blocksize(format);
 610
 611         c->vattr_sizes[attr] = align(attr_size, 4);
 612         for (int i = 0; i < align(attr_size, 4) / 4; i++) {
 613                 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
 614                 c->inputs[attr * 4 + i] = qir_MOV(c, vpm);
 615                 c->num_inputs++;
 616         }
 617 }
 618
 619 static void
 620 emit_fragcoord_input(struct vc4_compile *c, int attr)
 621 {
 622         c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
 623         c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
 624         c->inputs[attr * 4 + 2] =
 625                 qir_FMUL(c,
 626                          qir_ITOF(c, qir_FRAG_Z(c)),
 627                          qir_uniform_f(c, 1.0 / 0xffffff));
 628         c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
 629 }
 630
 631 static struct qreg
 632 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
 633                       uint8_t swizzle)
 634 {
 635         uint32_t i = c->num_input_slots++;
 636         struct qreg vary = {
 637                 QFILE_VARY,
 638                 i
 639         };
 640
 641         if (c->num_input_slots >= c->input_slots_array_size) {
 642                 c->input_slots_array_size =
 643                         MAX2(4, c->input_slots_array_size * 2);
 644
 645                 c->input_slots = reralloc(c, c->input_slots,
 646                                           struct vc4_varying_slot,
 647                                           c->input_slots_array_size);
 648         }
 649
 650         c->input_slots[i].slot = slot;
 651         c->input_slots[i].swizzle = swizzle;
 652
 653         return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
 654 }
 655
 656 static void
 657 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
 658 {
 659         for (int i = 0; i < 4; i++) {
 660                 c->inputs[attr * 4 + i] =
 661                         emit_fragment_varying(c, slot, i);
 662                 c->num_inputs++;
 663         }
 664 }
 665
 666 static void
 667 add_output(struct vc4_compile *c,
 668            uint32_t decl_offset,
 669            uint8_t slot,
 670            uint8_t swizzle)
 671 {
 672         uint32_t old_array_size = c->outputs_array_size;
 673         resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
 674                           decl_offset + 1);
 675
 676         if (old_array_size != c->outputs_array_size) {
 677                 c->output_slots = reralloc(c,
 678                                            c->output_slots,
 679                                            struct vc4_varying_slot,
 680                                            c->outputs_array_size);
 681         }
 682
 683         c->output_slots[decl_offset].slot = slot;
 684         c->output_slots[decl_offset].swizzle = swizzle;
 685 }
 686
 687 static void
 688 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
 689 {
 690         unsigned array_id = c->num_uniform_ranges++;
 691         if (array_id >= c->ubo_ranges_array_size) {
 692                 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
 693                                                 array_id + 1);
 694                 c->ubo_ranges = reralloc(c, c->ubo_ranges,
 695                                          struct vc4_compiler_ubo_range,
 696                                          c->ubo_ranges_array_size);
 697         }
 698
 699         c->ubo_ranges[array_id].dst_offset = 0;
 700         c->ubo_ranges[array_id].src_offset = start;
 701         c->ubo_ranges[array_id].size = size;
 702         c->ubo_ranges[array_id].used = false;
 703 }
 704
 705 static bool
 706 ntq_src_is_only_ssa_def_user(nir_src *src)
 707 {
 708         if (!src->is_ssa)
 709                 return false;
 710
 711         if (!list_empty(&src->ssa->if_uses))
 712                 return false;
 713
 714         return (src->ssa->uses.next == &src->use_link &&
 715                 src->ssa->uses.next->next == &src->ssa->uses);
 716 }
 717
 718 /**
 719  * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
 720  * bit set.
 721  *
 722  * However, as an optimization, it tries to find the instructions generating
 723  * the sources to be packed and just emit the pack flag there, if possible.
 724  */
 725 static void
 726 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
 727 {
 728         struct qreg result = qir_get_temp(c);
 729         struct nir_alu_instr *vec4 = NULL;
 730
 731         /* If packing from a vec4 op (as expected), identify it so that we can
 732          * peek back at what generated its sources.
 733          */
 734         if (instr->src[0].src.is_ssa &&
 735             instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
 736             nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
 737             nir_op_vec4) {
 738                 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
 739         }
 740
 741         for (int i = 0; i < 4; i++) {
 742                 int swiz = instr->src[0].swizzle[i];
 743                 struct qreg src;
 744                 if (vec4) {
 745                         src = ntq_get_src(c, vec4->src[swiz].src,
 746                                           vec4->src[swiz].swizzle[0]);
 747                 } else {
 748                         src = ntq_get_src(c, instr->src[0].src, swiz);
 749                 }
 750
 751                 if (vec4 &&
 752                     ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
 753                     src.file == QFILE_TEMP &&
 754                     c->defs[src.index] &&
 755                     qir_is_mul(c->defs[src.index]) &&
 756                     !c->defs[src.index]->dst.pack) {
 757                         struct qinst *rewrite = c->defs[src.index];
 758                         c->defs[src.index] = NULL;
 759                         rewrite->dst = result;
 760                         rewrite->dst.pack = QPU_PACK_MUL_8A + i;
 761                         continue;
 762                 }
 763
 764                 qir_PACK_8_F(c, result, src, i);
 765         }
 766
 767         struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
 768         *dest = result;
 769 }
 770
 771 /** Handles sign-extended bitfield extracts for 16 bits. */
 772 static struct qreg
 773 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
 774               struct qreg bits)
 775 {
 776         assert(bits.file == QFILE_UNIF &&
 777                c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
 778                c->uniform_data[bits.index] == 16);
 779
 780         assert(offset.file == QFILE_UNIF &&
 781                c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
 782         int offset_bit = c->uniform_data[offset.index];
 783         assert(offset_bit % 16 == 0);
 784
 785         return qir_UNPACK_16_I(c, base, offset_bit / 16);
 786 }
 787
 788 /** Handles unsigned bitfield extracts for 8 bits. */
 789 static struct qreg
 790 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
 791               struct qreg bits)
 792 {
 793         assert(bits.file == QFILE_UNIF &&
 794                c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
 795                c->uniform_data[bits.index] == 8);
 796
 797         assert(offset.file == QFILE_UNIF &&
 798                c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
 799         int offset_bit = c->uniform_data[offset.index];
 800         assert(offset_bit % 8 == 0);
 801
 802         return qir_UNPACK_8_I(c, base, offset_bit / 8);
 803 }
 804
 805 static void
 806 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
 807 {
 808         /* Vectors are special in that they have non-scalarized writemasks,
 809          * and just take the first swizzle channel for each argument in order
 810          * into each writemask channel.
 811          */
 812         if (instr->op == nir_op_vec2 ||
 813             instr->op == nir_op_vec3 ||
 814             instr->op == nir_op_vec4) {
 815                 struct qreg srcs[4];
 816                 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
 817                         srcs[i] = ntq_get_src(c, instr->src[i].src,
 818                                               instr->src[i].swizzle[0]);
 819                 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
 820                 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
 821                         dest[i] = srcs[i];
 822                 return;
 823         }
 824
 825         if (instr->op == nir_op_pack_unorm_4x8) {
 826                 ntq_emit_pack_unorm_4x8(c, instr);
 827                 return;
 828         }
 829
 830         if (instr->op == nir_op_unpack_unorm_4x8) {
 831                 struct qreg src = ntq_get_src(c, instr->src[0].src,
 832                                               instr->src[0].swizzle[0]);
 833                 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
 834                 for (int i = 0; i < 4; i++) {
 835                         if (instr->dest.write_mask & (1 << i))
 836                                 dest[i] = qir_UNPACK_8_F(c, src, i);
 837                 }
 838                 return;
 839         }
 840
 841         /* General case: We can just grab the one used channel per src. */
 842         struct qreg src[nir_op_infos[instr->op].num_inputs];
 843         for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
 844                 src[i] = ntq_get_alu_src(c, instr, i);
 845         }
 846
 847         /* Pick the channel to store the output in. */
 848         assert(!instr->dest.saturate);
 849         struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
 850         assert(util_is_power_of_two(instr->dest.write_mask));
 851         dest += ffs(instr->dest.write_mask) - 1;
 852
 853         switch (instr->op) {
 854         case nir_op_fmov:
 855         case nir_op_imov:
 856                 *dest = qir_MOV(c, src[0]);
 857                 break;
 858         case nir_op_fmul:
 859                 *dest = qir_FMUL(c, src[0], src[1]);
 860                 break;
 861         case nir_op_fadd:
 862                 *dest = qir_FADD(c, src[0], src[1]);
 863                 break;
 864         case nir_op_fsub:
 865                 *dest = qir_FSUB(c, src[0], src[1]);
 866                 break;
 867         case nir_op_fmin:
 868                 *dest = qir_FMIN(c, src[0], src[1]);
 869                 break;
 870         case nir_op_fmax:
 871                 *dest = qir_FMAX(c, src[0], src[1]);
 872                 break;
 873
 874         case nir_op_f2i:
 875         case nir_op_f2u:
 876                 *dest = qir_FTOI(c, src[0]);
 877                 break;
 878         case nir_op_i2f:
 879         case nir_op_u2f:
 880                 *dest = qir_ITOF(c, src[0]);
 881                 break;
 882         case nir_op_b2f:
 883                 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
 884                 break;
 885         case nir_op_b2i:
 886                 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
 887                 break;
 888         case nir_op_i2b:
 889         case nir_op_f2b:
 890                 qir_SF(c, src[0]);
 891                 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
 892                 break;
 893
 894         case nir_op_iadd:
 895                 *dest = qir_ADD(c, src[0], src[1]);
 896                 break;
 897         case nir_op_ushr:
 898                 *dest = qir_SHR(c, src[0], src[1]);
 899                 break;
 900         case nir_op_isub:
 901                 *dest = qir_SUB(c, src[0], src[1]);
 902                 break;
 903         case nir_op_ishr:
 904                 *dest = qir_ASR(c, src[0], src[1]);
 905                 break;
 906         case nir_op_ishl:
 907                 *dest = qir_SHL(c, src[0], src[1]);
 908                 break;
 909         case nir_op_imin:
 910                 *dest = qir_MIN(c, src[0], src[1]);
 911                 break;
 912         case nir_op_imax:
 913                 *dest = qir_MAX(c, src[0], src[1]);
 914                 break;
 915         case nir_op_iand:
 916                 *dest = qir_AND(c, src[0], src[1]);
 917                 break;
 918         case nir_op_ior:
 919                 *dest = qir_OR(c, src[0], src[1]);
 920                 break;
 921         case nir_op_ixor:
 922                 *dest = qir_XOR(c, src[0], src[1]);
 923                 break;
 924         case nir_op_inot:
 925                 *dest = qir_NOT(c, src[0]);
 926                 break;
 927
 928         case nir_op_imul:
 929                 *dest = ntq_umul(c, src[0], src[1]);
 930                 break;
 931
 932         case nir_op_seq:
 933                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 934                 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
 935                 break;
 936         case nir_op_sne:
 937                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 938                 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
 939                 break;
 940         case nir_op_sge:
 941                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 942                 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
 943                 break;
 944         case nir_op_slt:
 945                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 946                 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
 947                 break;
 948         case nir_op_feq:
 949                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 950                 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
 951                 break;
 952         case nir_op_fne:
 953                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 954                 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
 955                 break;
 956         case nir_op_fge:
 957                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 958                 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
 959                 break;
 960         case nir_op_flt:
 961                 qir_SF(c, qir_FSUB(c, src[0], src[1]));
 962                 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
 963                 break;
 964         case nir_op_ieq:
 965                 qir_SF(c, qir_SUB(c, src[0], src[1]));
 966                 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
 967                 break;
 968         case nir_op_ine:
 969                 qir_SF(c, qir_SUB(c, src[0], src[1]));
 970                 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
 971                 break;
 972         case nir_op_ige:
 973                 qir_SF(c, qir_SUB(c, src[0], src[1]));
 974                 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
 975                 break;
 976         case nir_op_ilt:
 977                 qir_SF(c, qir_SUB(c, src[0], src[1]));
 978                 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
 979                 break;
 980
 981         case nir_op_bcsel:
 982                 qir_SF(c, src[0]);
 983                 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
 984                 break;
 985         case nir_op_fcsel:
 986                 qir_SF(c, src[0]);
 987                 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
 988                 break;
 989
 990         case nir_op_frcp:
 991                 *dest = ntq_rcp(c, src[0]);
 992                 break;
 993         case nir_op_frsq:
 994                 *dest = ntq_rsq(c, src[0]);
 995                 break;
 996         case nir_op_fexp2:
 997                 *dest = qir_EXP2(c, src[0]);
 998                 break;
 999         case nir_op_flog2:
1000                 *dest = qir_LOG2(c, src[0]);
1001                 break;
1002
1003         case nir_op_ftrunc:
1004                 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
1005                 break;
1006         case nir_op_fceil:
1007                 *dest = ntq_fceil(c, src[0]);
1008                 break;
1009         case nir_op_ffract:
1010                 *dest = ntq_ffract(c, src[0]);
1011                 break;
1012         case nir_op_ffloor:
1013                 *dest = ntq_ffloor(c, src[0]);
1014                 break;
1015
1016         case nir_op_fsin:
1017                 *dest = ntq_fsin(c, src[0]);
1018                 break;
1019         case nir_op_fcos:
1020                 *dest = ntq_fcos(c, src[0]);
1021                 break;
1022
1023         case nir_op_fsign:
1024                 *dest = ntq_fsign(c, src[0]);
1025                 break;
1026
1027         case nir_op_fabs:
1028                 *dest = qir_FMAXABS(c, src[0], src[0]);
1029                 break;
1030         case nir_op_iabs:
1031                 *dest = qir_MAX(c, src[0],
1032                                 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1033                 break;
1034
1035         case nir_op_ibitfield_extract:
1036                 *dest = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1037                 break;
1038
1039         case nir_op_ubitfield_extract:
1040                 *dest = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1041                 break;
1042
1043         default:
1044                 fprintf(stderr, "unknown NIR ALU inst: ");
1045                 nir_print_instr(&instr->instr, stderr);
1046                 fprintf(stderr, "\n");
1047                 abort();
1048         }
1049 }
1050
1051 static void
1052 emit_frag_end(struct vc4_compile *c)
1053 {
1054         struct qreg color;
1055         if (c->output_color_index != -1) {
1056                 color = c->outputs[c->output_color_index];
1057         } else {
1058                 color = qir_uniform_ui(c, 0);
1059         }
1060
1061         if (c->discard.file != QFILE_NULL)
1062                 qir_TLB_DISCARD_SETUP(c, c->discard);
1063
1064         if (c->fs_key->stencil_enabled) {
1065                 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1066                 if (c->fs_key->stencil_twoside) {
1067                         qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1068                 }
1069                 if (c->fs_key->stencil_full_writemasks) {
1070                         qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1071                 }
1072         }
1073
1074         if (c->fs_key->depth_enabled) {
1075                 struct qreg z;
1076                 if (c->output_position_index != -1) {
1077                         z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1078                                                  qir_uniform_f(c, 0xffffff)));
1079                 } else {
1080                         z = qir_FRAG_Z(c);
1081                 }
1082                 qir_TLB_Z_WRITE(c, z);
1083         }
1084
1085         qir_TLB_COLOR_WRITE(c, color);
1086 }
1087
1088 static void
1089 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1090 {
1091         struct qreg packed = qir_get_temp(c);
1092
1093         for (int i = 0; i < 2; i++) {
1094                 struct qreg scale =
1095                         qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1096
1097                 struct qreg packed_chan = packed;
1098                 packed_chan.pack = QPU_PACK_A_16A + i;
1099
1100                 qir_FTOI_dest(c, packed_chan,
1101                               qir_FMUL(c,
1102                                        qir_FMUL(c,
1103                                                 c->outputs[c->output_position_index + i],
1104                                                 scale),
1105                                        rcp_w));
1106         }
1107
1108         qir_VPM_WRITE(c, packed);
1109 }
1110
1111 static void
1112 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1113 {
1114         struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1115         struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1116
1117         qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1118                                                           c->outputs[c->output_position_index + 2],
1119                                                           zscale),
1120                                               rcp_w),
1121                                   zoffset));
1122 }
1123
1124 static void
1125 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1126 {
1127         qir_VPM_WRITE(c, rcp_w);
1128 }
1129
1130 static void
1131 emit_point_size_write(struct vc4_compile *c)
1132 {
1133         struct qreg point_size;
1134
1135         if (c->output_point_size_index != -1)
1136                 point_size = c->outputs[c->output_point_size_index + 3];
1137         else
1138                 point_size = qir_uniform_f(c, 1.0);
1139
1140         /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1141          * BCM21553).
1142          */
1143         point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1144
1145         qir_VPM_WRITE(c, point_size);
1146 }
1147
1148 /**
1149  * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1150  *
1151  * The simulator insists that there be at least one vertex attribute, so
1152  * vc4_draw.c will emit one if it wouldn't have otherwise.  The simulator also
1153  * insists that all vertex attributes loaded get read by the VS/CS, so we have
1154  * to consume it here.
1155  */
1156 static void
1157 emit_stub_vpm_read(struct vc4_compile *c)
1158 {
1159         if (c->num_inputs)
1160                 return;
1161
1162         c->vattr_sizes[0] = 4;
1163         struct qreg vpm = { QFILE_VPM, 0 };
1164         (void)qir_MOV(c, vpm);
1165         c->num_inputs++;
1166 }
1167
1168 static void
1169 emit_vert_end(struct vc4_compile *c,
1170               struct vc4_varying_slot *fs_inputs,
1171               uint32_t num_fs_inputs)
1172 {
1173         struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1174
1175         emit_stub_vpm_read(c);
1176
1177         emit_scaled_viewport_write(c, rcp_w);
1178         emit_zs_write(c, rcp_w);
1179         emit_rcp_wc_write(c, rcp_w);
1180         if (c->vs_key->per_vertex_point_size)
1181                 emit_point_size_write(c);
1182
1183         for (int i = 0; i < num_fs_inputs; i++) {
1184                 struct vc4_varying_slot *input = &fs_inputs[i];
1185                 int j;
1186
1187                 for (j = 0; j < c->num_outputs; j++) {
1188                         struct vc4_varying_slot *output =
1189                                 &c->output_slots[j];
1190
1191                         if (input->slot == output->slot &&
1192                             input->swizzle == output->swizzle) {
1193                                 qir_VPM_WRITE(c, c->outputs[j]);
1194                                 break;
1195                         }
1196                 }
1197                 /* Emit padding if we didn't find a declared VS output for
1198                  * this FS input.
1199                  */
1200                 if (j == c->num_outputs)
1201                         qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1202         }
1203 }
1204
1205 static void
1206 emit_coord_end(struct vc4_compile *c)
1207 {
1208         struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1209
1210         emit_stub_vpm_read(c);
1211
1212         for (int i = 0; i < 4; i++)
1213                 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1214
1215         emit_scaled_viewport_write(c, rcp_w);
1216         emit_zs_write(c, rcp_w);
1217         emit_rcp_wc_write(c, rcp_w);
1218         if (c->vs_key->per_vertex_point_size)
1219                 emit_point_size_write(c);
1220 }
1221
1222 static void
1223 vc4_optimize_nir(struct nir_shader *s)
1224 {
1225         bool progress;
1226
1227         do {
1228                 progress = false;
1229
1230                 nir_lower_vars_to_ssa(s);
1231                 nir_lower_alu_to_scalar(s);
1232
1233                 progress = nir_copy_prop(s) || progress;
1234                 progress = nir_opt_dce(s) || progress;
1235                 progress = nir_opt_cse(s) || progress;
1236                 progress = nir_opt_peephole_select(s) || progress;
1237                 progress = nir_opt_algebraic(s) || progress;
1238                 progress = nir_opt_constant_folding(s) || progress;
1239                 progress = nir_opt_undef(s) || progress;
1240         } while (progress);
1241 }
1242
1243 static int
1244 driver_location_compare(const void *in_a, const void *in_b)
1245 {
1246         const nir_variable *const *a = in_a;
1247         const nir_variable *const *b = in_b;
1248
1249         return (*a)->data.driver_location - (*b)->data.driver_location;
1250 }
1251
1252 static void
1253 ntq_setup_inputs(struct vc4_compile *c)
1254 {
1255         unsigned num_entries = 0;
1256         nir_foreach_variable(var, &c->s->inputs)
1257                 num_entries++;
1258
1259         nir_variable *vars[num_entries];
1260
1261         unsigned i = 0;
1262         nir_foreach_variable(var, &c->s->inputs)
1263                 vars[i++] = var;
1264
1265         /* Sort the variables so that we emit the input setup in
1266          * driver_location order.  This is required for VPM reads, whose data
1267          * is fetched into the VPM in driver_location (TGSI register index)
1268          * order.
1269          */
1270         qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1271
1272         for (unsigned i = 0; i < num_entries; i++) {
1273                 nir_variable *var = vars[i];
1274                 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1275                 unsigned loc = var->data.driver_location;
1276
1277                 assert(array_len == 1);
1278                 (void)array_len;
1279                 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1280                                   (loc + 1) * 4);
1281
1282                 if (c->stage == QSTAGE_FRAG) {
1283                         if (var->data.location == VARYING_SLOT_POS) {
1284                                 emit_fragcoord_input(c, loc);
1285                         } else if (var->data.location == VARYING_SLOT_FACE) {
1286                                 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1287                         } else if (var->data.location >= VARYING_SLOT_VAR0 &&
1288                                    (c->fs_key->point_sprite_mask &
1289                                     (1 << (var->data.location -
1290                                            VARYING_SLOT_VAR0)))) {
1291                                 c->inputs[loc * 4 + 0] = c->point_x;
1292                                 c->inputs[loc * 4 + 1] = c->point_y;
1293                         } else {
1294                                 emit_fragment_input(c, loc, var->data.location);
1295                         }
1296                 } else {
1297                         emit_vertex_input(c, loc);
1298                 }
1299         }
1300 }
1301
1302 static void
1303 ntq_setup_outputs(struct vc4_compile *c)
1304 {
1305         nir_foreach_variable(var, &c->s->outputs) {
1306                 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1307                 unsigned loc = var->data.driver_location * 4;
1308
1309                 assert(array_len == 1);
1310                 (void)array_len;
1311
1312                 for (int i = 0; i < 4; i++)
1313                         add_output(c, loc + i, var->data.location, i);
1314
1315                 if (c->stage == QSTAGE_FRAG) {
1316                         switch (var->data.location) {
1317                         case FRAG_RESULT_COLOR:
1318                         case FRAG_RESULT_DATA0:
1319                                 c->output_color_index = loc;
1320                                 break;
1321                         case FRAG_RESULT_DEPTH:
1322                                 c->output_position_index = loc;
1323                                 break;
1324                         }
1325                 } else {
1326                         switch (var->data.location) {
1327                         case VARYING_SLOT_POS:
1328                                 c->output_position_index = loc;
1329                                 break;
1330                         case VARYING_SLOT_PSIZ:
1331                                 c->output_point_size_index = loc;
1332                                 break;
1333                         }
1334                 }
1335         }
1336 }
1337
1338 static void
1339 ntq_setup_uniforms(struct vc4_compile *c)
1340 {
1341         nir_foreach_variable(var, &c->s->uniforms) {
1342                 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1343                 unsigned array_elem_size = 4 * sizeof(float);
1344
1345                 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1346                                       array_len * array_elem_size);
1347
1348         }
1349 }
1350
1351 /**
1352  * Sets up the mapping from nir_register to struct qreg *.
1353  *
1354  * Each nir_register gets a struct qreg per 32-bit component being stored.
1355  */
1356 static void
1357 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1358 {
1359         foreach_list_typed(nir_register, nir_reg, node, list) {
1360                 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1361                 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1362                                                   array_len *
1363                                                   nir_reg->num_components);
1364
1365                 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1366
1367                 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1368                         qregs[i] = qir_uniform_ui(c, 0);
1369         }
1370 }
1371
1372 static void
1373 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1374 {
1375         struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1376         for (int i = 0; i < instr->def.num_components; i++)
1377                 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1378
1379         _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1380 }
1381
1382 static void
1383 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1384 {
1385         struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1386
1387         /* QIR needs there to be *some* value, so pick 0 (same as for
1388          * ntq_setup_registers().
1389          */
1390         for (int i = 0; i < instr->def.num_components; i++)
1391                 qregs[i] = qir_uniform_ui(c, 0);
1392 }
1393
1394 static void
1395 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1396 {
1397         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1398         struct qreg *dest = NULL;
1399
1400         if (info->has_dest) {
1401                 dest = ntq_get_dest(c, &instr->dest);
1402         }
1403
1404         switch (instr->intrinsic) {
1405         case nir_intrinsic_load_uniform:
1406                 assert(instr->num_components == 1);
1407                 if (instr->const_index[0] < VC4_NIR_STATE_UNIFORM_OFFSET) {
1408                         *dest = qir_uniform(c, QUNIFORM_UNIFORM,
1409                                             instr->const_index[0]);
1410                 } else {
1411                         *dest = qir_uniform(c, instr->const_index[0] -
1412                                             VC4_NIR_STATE_UNIFORM_OFFSET,
1413                                             0);
1414                 }
1415                 break;
1416
1417         case nir_intrinsic_load_uniform_indirect:
1418                 *dest = indirect_uniform_load(c, instr);
1419
1420                 break;
1421
1422         case nir_intrinsic_load_user_clip_plane:
1423                 *dest = qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1424                                     instr->const_index[0]);
1425                 break;
1426
1427         case nir_intrinsic_load_input:
1428                 assert(instr->num_components == 1);
1429                 if (instr->const_index[0] == VC4_NIR_TLB_COLOR_READ_INPUT) {
1430                         *dest = qir_TLB_COLOR_READ(c);
1431                 } else {
1432                         *dest = c->inputs[instr->const_index[0]];
1433                 }
1434                 break;
1435
1436         case nir_intrinsic_store_output:
1437                 assert(instr->num_components == 1);
1438                 c->outputs[instr->const_index[0]] =
1439                         qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1440                 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1441                 break;
1442
1443         case nir_intrinsic_discard:
1444                 c->discard = qir_uniform_ui(c, ~0);
1445                 break;
1446
1447         case nir_intrinsic_discard_if:
1448                 if (c->discard.file == QFILE_NULL)
1449                         c->discard = qir_uniform_ui(c, 0);
1450                 c->discard = qir_OR(c, c->discard,
1451                                     ntq_get_src(c, instr->src[0], 0));
1452                 break;
1453
1454         default:
1455                 fprintf(stderr, "Unknown intrinsic: ");
1456                 nir_print_instr(&instr->instr, stderr);
1457                 fprintf(stderr, "\n");
1458                 break;
1459         }
1460 }
1461
1462 static void
1463 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1464 {
1465         fprintf(stderr, "general IF statements not handled.\n");
1466 }
1467
1468 static void
1469 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1470 {
1471         switch (instr->type) {
1472         case nir_instr_type_alu:
1473                 ntq_emit_alu(c, nir_instr_as_alu(instr));
1474                 break;
1475
1476         case nir_instr_type_intrinsic:
1477                 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1478                 break;
1479
1480         case nir_instr_type_load_const:
1481                 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1482                 break;
1483
1484         case nir_instr_type_ssa_undef:
1485                 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1486                 break;
1487
1488         case nir_instr_type_tex:
1489                 ntq_emit_tex(c, nir_instr_as_tex(instr));
1490                 break;
1491
1492         default:
1493                 fprintf(stderr, "Unknown NIR instr type: ");
1494                 nir_print_instr(instr, stderr);
1495                 fprintf(stderr, "\n");
1496                 abort();
1497         }
1498 }
1499
1500 static void
1501 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1502 {
1503         nir_foreach_instr(block, instr) {
1504                 ntq_emit_instr(c, instr);
1505         }
1506 }
1507
1508 static void
1509 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1510 {
1511         foreach_list_typed(nir_cf_node, node, node, list) {
1512                 switch (node->type) {
1513                         /* case nir_cf_node_loop: */
1514                 case nir_cf_node_block:
1515                         ntq_emit_block(c, nir_cf_node_as_block(node));
1516                         break;
1517
1518                 case nir_cf_node_if:
1519                         ntq_emit_if(c, nir_cf_node_as_if(node));
1520                         break;
1521
1522                 default:
1523                         assert(0);
1524                 }
1525         }
1526 }
1527
1528 static void
1529 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1530 {
1531         ntq_setup_registers(c, &impl->registers);
1532         ntq_emit_cf_list(c, &impl->body);
1533 }
1534
1535 static void
1536 nir_to_qir(struct vc4_compile *c)
1537 {
1538         ntq_setup_inputs(c);
1539         ntq_setup_outputs(c);
1540         ntq_setup_uniforms(c);
1541         ntq_setup_registers(c, &c->s->registers);
1542
1543         /* Find the main function and emit the body. */
1544         nir_foreach_overload(c->s, overload) {
1545                 assert(strcmp(overload->function->name, "main") == 0);
1546                 assert(overload->impl);
1547                 ntq_emit_impl(c, overload->impl);
1548         }
1549 }
1550
1551 static const nir_shader_compiler_options nir_options = {
1552         .lower_ffma = true,
1553         .lower_flrp = true,
1554         .lower_fpow = true,
1555         .lower_fsat = true,
1556         .lower_fsqrt = true,
1557         .lower_negate = true,
1558 };
1559
1560 static bool
1561 count_nir_instrs_in_block(nir_block *block, void *state)
1562 {
1563         int *count = (int *) state;
1564         nir_foreach_instr(block, instr) {
1565                 *count = *count + 1;
1566         }
1567         return true;
1568 }
1569
1570 static int
1571 count_nir_instrs(nir_shader *nir)
1572 {
1573         int count = 0;
1574         nir_foreach_overload(nir, overload) {
1575                 if (!overload->impl)
1576                         continue;
1577                 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1578         }
1579         return count;
1580 }
1581
1582 static struct vc4_compile *
1583 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1584                        struct vc4_key *key)
1585 {
1586         struct vc4_compile *c = qir_compile_init();
1587
1588         c->stage = stage;
1589         c->shader_state = &key->shader_state->base;
1590         c->program_id = key->shader_state->program_id;
1591         c->variant_id = key->shader_state->compiled_variant_count++;
1592
1593         c->key = key;
1594         switch (stage) {
1595         case QSTAGE_FRAG:
1596                 c->fs_key = (struct vc4_fs_key *)key;
1597                 if (c->fs_key->is_points) {
1598                         c->point_x = emit_fragment_varying(c, ~0, 0);
1599                         c->point_y = emit_fragment_varying(c, ~0, 0);
1600                 } else if (c->fs_key->is_lines) {
1601                         c->line_x = emit_fragment_varying(c, ~0, 0);
1602                 }
1603                 break;
1604         case QSTAGE_VERT:
1605                 c->vs_key = (struct vc4_vs_key *)key;
1606                 break;
1607         case QSTAGE_COORD:
1608                 c->vs_key = (struct vc4_vs_key *)key;
1609                 break;
1610         }
1611
1612         const struct tgsi_token *tokens = key->shader_state->base.tokens;
1613
1614         if (vc4_debug & VC4_DEBUG_TGSI) {
1615                 fprintf(stderr, "%s prog %d/%d TGSI:\n",
1616                         qir_get_stage_name(c->stage),
1617                         c->program_id, c->variant_id);
1618                 tgsi_dump(tokens, 0);
1619         }
1620
1621         c->s = tgsi_to_nir(tokens, &nir_options);
1622         nir_opt_global_to_local(c->s);
1623         nir_convert_to_ssa(c->s);
1624
1625         if (stage == QSTAGE_FRAG)
1626                 vc4_nir_lower_blend(c);
1627
1628         if (c->fs_key && c->fs_key->light_twoside)
1629                 nir_lower_two_sided_color(c->s);
1630
1631         if (stage == QSTAGE_FRAG)
1632                 nir_lower_clip_fs(c->s, c->key->ucp_enables);
1633         else
1634                 nir_lower_clip_vs(c->s, c->key->ucp_enables);
1635
1636         vc4_nir_lower_io(c);
1637         nir_lower_idiv(c->s);
1638         nir_lower_load_const_to_scalar(c->s);
1639
1640         vc4_optimize_nir(c->s);
1641
1642         nir_remove_dead_variables(c->s);
1643
1644         nir_convert_from_ssa(c->s, true);
1645
1646         if (vc4_debug & VC4_DEBUG_SHADERDB) {
1647                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
1648                         qir_get_stage_name(c->stage),
1649                         c->program_id, c->variant_id,
1650                         count_nir_instrs(c->s));
1651         }
1652
1653         if (vc4_debug & VC4_DEBUG_NIR) {
1654                 fprintf(stderr, "%s prog %d/%d NIR:\n",
1655                         qir_get_stage_name(c->stage),
1656                         c->program_id, c->variant_id);
1657                 nir_print_shader(c->s, stderr);
1658         }
1659
1660         nir_to_qir(c);
1661
1662         switch (stage) {
1663         case QSTAGE_FRAG:
1664                 emit_frag_end(c);
1665                 break;
1666         case QSTAGE_VERT:
1667                 emit_vert_end(c,
1668                               vc4->prog.fs->input_slots,
1669                               vc4->prog.fs->num_inputs);
1670                 break;
1671         case QSTAGE_COORD:
1672                 emit_coord_end(c);
1673                 break;
1674         }
1675
1676         if (vc4_debug & VC4_DEBUG_QIR) {
1677                 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
1678                         qir_get_stage_name(c->stage),
1679                         c->program_id, c->variant_id);
1680                 qir_dump(c);
1681         }
1682
1683         qir_optimize(c);
1684         qir_lower_uniforms(c);
1685
1686         if (vc4_debug & VC4_DEBUG_QIR) {
1687                 fprintf(stderr, "%s prog %d/%d QIR:\n",
1688                         qir_get_stage_name(c->stage),
1689                         c->program_id, c->variant_id);
1690                 qir_dump(c);
1691         }
1692         qir_reorder_uniforms(c);
1693         vc4_generate_code(vc4, c);
1694
1695         if (vc4_debug & VC4_DEBUG_SHADERDB) {
1696                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1697                         qir_get_stage_name(c->stage),
1698                         c->program_id, c->variant_id,
1699                         c->qpu_inst_count);
1700                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1701                         qir_get_stage_name(c->stage),
1702                         c->program_id, c->variant_id,
1703                         c->num_uniforms);
1704         }
1705
1706         ralloc_free(c->s);
1707
1708         return c;
1709 }
1710
1711 static void *
1712 vc4_shader_state_create(struct pipe_context *pctx,
1713                         const struct pipe_shader_state *cso)
1714 {
1715         struct vc4_context *vc4 = vc4_context(pctx);
1716         struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1717         if (!so)
1718                 return NULL;
1719
1720         so->base.tokens = tgsi_dup_tokens(cso->tokens);
1721         so->program_id = vc4->next_uncompiled_program_id++;
1722
1723         return so;
1724 }
1725
1726 static void
1727 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1728                              struct vc4_compile *c)
1729 {
1730         int count = c->num_uniforms;
1731         struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1732
1733         uinfo->count = count;
1734         uinfo->data = ralloc_array(shader, uint32_t, count);
1735         memcpy(uinfo->data, c->uniform_data,
1736                count * sizeof(*uinfo->data));
1737         uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1738         memcpy(uinfo->contents, c->uniform_contents,
1739                count * sizeof(*uinfo->contents));
1740         uinfo->num_texture_samples = c->num_texture_samples;
1741
1742         vc4_set_shader_uniform_dirty_flags(shader);
1743 }
1744
1745 static struct vc4_compiled_shader *
1746 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1747                         struct vc4_key *key)
1748 {
1749         struct hash_table *ht;
1750         uint32_t key_size;
1751         if (stage == QSTAGE_FRAG) {
1752                 ht = vc4->fs_cache;
1753                 key_size = sizeof(struct vc4_fs_key);
1754         } else {
1755                 ht = vc4->vs_cache;
1756                 key_size = sizeof(struct vc4_vs_key);
1757         }
1758
1759         struct vc4_compiled_shader *shader;
1760         struct hash_entry *entry = _mesa_hash_table_search(ht, key);
1761         if (entry)
1762                 return entry->data;
1763
1764         struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
1765         shader = rzalloc(NULL, struct vc4_compiled_shader);
1766
1767         shader->program_id = vc4->next_compiled_program_id++;
1768         if (stage == QSTAGE_FRAG) {
1769                 bool input_live[c->num_input_slots];
1770
1771                 memset(input_live, 0, sizeof(input_live));
1772                 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
1773                         for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
1774                                 if (inst->src[i].file == QFILE_VARY)
1775                                         input_live[inst->src[i].index] = true;
1776                         }
1777                 }
1778
1779                 shader->input_slots = ralloc_array(shader,
1780                                                    struct vc4_varying_slot,
1781                                                    c->num_input_slots);
1782
1783                 for (int i = 0; i < c->num_input_slots; i++) {
1784                         struct vc4_varying_slot *slot = &c->input_slots[i];
1785
1786                         if (!input_live[i])
1787                                 continue;
1788
1789                         /* Skip non-VS-output inputs. */
1790                         if (slot->slot == (uint8_t)~0)
1791                                 continue;
1792
1793                         if (slot->slot == VARYING_SLOT_COL0 ||
1794                             slot->slot == VARYING_SLOT_COL1 ||
1795                             slot->slot == VARYING_SLOT_BFC0 ||
1796                             slot->slot == VARYING_SLOT_BFC1) {
1797                                 shader->color_inputs |= (1 << shader->num_inputs);
1798                         }
1799
1800                         shader->input_slots[shader->num_inputs] = *slot;
1801                         shader->num_inputs++;
1802                 }
1803         } else {
1804                 shader->num_inputs = c->num_inputs;
1805
1806                 shader->vattr_offsets[0] = 0;
1807                 for (int i = 0; i < 8; i++) {
1808                         shader->vattr_offsets[i + 1] =
1809                                 shader->vattr_offsets[i] + c->vattr_sizes[i];
1810
1811                         if (c->vattr_sizes[i])
1812                                 shader->vattrs_live |= (1 << i);
1813                 }
1814         }
1815
1816         copy_uniform_state_to_shader(shader, c);
1817         shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
1818                                          c->qpu_inst_count * sizeof(uint64_t));
1819
1820         /* Copy the compiler UBO range state to the compiled shader, dropping
1821          * out arrays that were never referenced by an indirect load.
1822          *
1823          * (Note that QIR dead code elimination of an array access still
1824          * leaves that array alive, though)
1825          */
1826         if (c->num_ubo_ranges) {
1827                 shader->num_ubo_ranges = c->num_ubo_ranges;
1828                 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
1829                                                   c->num_ubo_ranges);
1830                 uint32_t j = 0;
1831                 for (int i = 0; i < c->num_uniform_ranges; i++) {
1832                         struct vc4_compiler_ubo_range *range =
1833                                 &c->ubo_ranges[i];
1834                         if (!range->used)
1835                                 continue;
1836
1837                         shader->ubo_ranges[j].dst_offset = range->dst_offset;
1838                         shader->ubo_ranges[j].src_offset = range->src_offset;
1839                         shader->ubo_ranges[j].size = range->size;
1840                         shader->ubo_size += c->ubo_ranges[i].size;
1841                         j++;
1842                 }
1843         }
1844         if (shader->ubo_size) {
1845                 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1846                         fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
1847                                 qir_get_stage_name(c->stage),
1848                                 c->program_id, c->variant_id,
1849                                 shader->ubo_size / 4);
1850                 }
1851         }
1852
1853         qir_compile_destroy(c);
1854
1855         struct vc4_key *dup_key;
1856         dup_key = ralloc_size(shader, key_size);
1857         memcpy(dup_key, key, key_size);
1858         _mesa_hash_table_insert(ht, dup_key, shader);
1859
1860         return shader;
1861 }
1862
1863 static void
1864 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
1865                      struct vc4_texture_stateobj *texstate)
1866 {
1867         for (int i = 0; i < texstate->num_textures; i++) {
1868                 struct pipe_sampler_view *sampler = texstate->textures[i];
1869                 struct pipe_sampler_state *sampler_state =
1870                         texstate->samplers[i];
1871
1872                 if (sampler) {
1873                         key->tex[i].format = sampler->format;
1874                         key->tex[i].swizzle[0] = sampler->swizzle_r;
1875                         key->tex[i].swizzle[1] = sampler->swizzle_g;
1876                         key->tex[i].swizzle[2] = sampler->swizzle_b;
1877                         key->tex[i].swizzle[3] = sampler->swizzle_a;
1878                         key->tex[i].compare_mode = sampler_state->compare_mode;
1879                         key->tex[i].compare_func = sampler_state->compare_func;
1880                         key->tex[i].wrap_s = sampler_state->wrap_s;
1881                         key->tex[i].wrap_t = sampler_state->wrap_t;
1882                 }
1883         }
1884
1885         key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
1886 }
1887
1888 static void
1889 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1890 {
1891         struct vc4_fs_key local_key;
1892         struct vc4_fs_key *key = &local_key;
1893
1894         if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1895                             VC4_DIRTY_BLEND |
1896                             VC4_DIRTY_FRAMEBUFFER |
1897                             VC4_DIRTY_ZSA |
1898                             VC4_DIRTY_RASTERIZER |
1899                             VC4_DIRTY_FRAGTEX |
1900                             VC4_DIRTY_TEXSTATE |
1901                             VC4_DIRTY_UNCOMPILED_FS))) {
1902                 return;
1903         }
1904
1905         memset(key, 0, sizeof(*key));
1906         vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
1907         key->base.shader_state = vc4->prog.bind_fs;
1908         key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1909         key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1910                          prim_mode <= PIPE_PRIM_LINE_STRIP);
1911         key->blend = vc4->blend->rt[0];
1912         if (vc4->blend->logicop_enable) {
1913                 key->logicop_func = vc4->blend->logicop_func;
1914         } else {
1915                 key->logicop_func = PIPE_LOGICOP_COPY;
1916         }
1917         if (vc4->framebuffer.cbufs[0])
1918                 key->color_format = vc4->framebuffer.cbufs[0]->format;
1919
1920         key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1921         key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1922         key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1923         key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1924                               key->stencil_enabled);
1925         if (vc4->zsa->base.alpha.enabled) {
1926                 key->alpha_test = true;
1927                 key->alpha_test_func = vc4->zsa->base.alpha.func;
1928         }
1929
1930         if (key->is_points) {
1931                 key->point_sprite_mask =
1932                         vc4->rasterizer->base.sprite_coord_enable;
1933                 key->point_coord_upper_left =
1934                         (vc4->rasterizer->base.sprite_coord_mode ==
1935                          PIPE_SPRITE_COORD_UPPER_LEFT);
1936         }
1937
1938         key->light_twoside = vc4->rasterizer->base.light_twoside;
1939
1940         struct vc4_compiled_shader *old_fs = vc4->prog.fs;
1941         vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
1942         if (vc4->prog.fs == old_fs)
1943                 return;
1944
1945         vc4->dirty |= VC4_DIRTY_COMPILED_FS;
1946         if (vc4->rasterizer->base.flatshade &&
1947             old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
1948                 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1949         }
1950 }
1951
1952 static void
1953 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1954 {
1955         struct vc4_vs_key local_key;
1956         struct vc4_vs_key *key = &local_key;
1957
1958         if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1959                             VC4_DIRTY_RASTERIZER |
1960                             VC4_DIRTY_VERTTEX |
1961                             VC4_DIRTY_TEXSTATE |
1962                             VC4_DIRTY_VTXSTATE |
1963                             VC4_DIRTY_UNCOMPILED_VS |
1964                             VC4_DIRTY_COMPILED_FS))) {
1965                 return;
1966         }
1967
1968         memset(key, 0, sizeof(*key));
1969         vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
1970         key->base.shader_state = vc4->prog.bind_vs;
1971         key->compiled_fs_id = vc4->prog.fs->program_id;
1972
1973         for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1974                 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1975
1976         key->per_vertex_point_size =
1977                 (prim_mode == PIPE_PRIM_POINTS &&
1978                  vc4->rasterizer->base.point_size_per_vertex);
1979
1980         struct vc4_compiled_shader *vs =
1981                 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
1982         if (vs != vc4->prog.vs) {
1983                 vc4->prog.vs = vs;
1984                 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
1985         }
1986
1987         key->is_coord = true;
1988         struct vc4_compiled_shader *cs =
1989                 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
1990         if (cs != vc4->prog.cs) {
1991                 vc4->prog.cs = cs;
1992                 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
1993         }
1994 }
1995
1996 void
1997 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1998 {
1999         vc4_update_compiled_fs(vc4, prim_mode);
2000         vc4_update_compiled_vs(vc4, prim_mode);
2001 }
2002
2003 static uint32_t
2004 fs_cache_hash(const void *key)
2005 {
2006         return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2007 }
2008
2009 static uint32_t
2010 vs_cache_hash(const void *key)
2011 {
2012         return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2013 }
2014
2015 static bool
2016 fs_cache_compare(const void *key1, const void *key2)
2017 {
2018         return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2019 }
2020
2021 static bool
2022 vs_cache_compare(const void *key1, const void *key2)
2023 {
2024         return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2025 }
2026
2027 static void
2028 delete_from_cache_if_matches(struct hash_table *ht,
2029                              struct hash_entry *entry,
2030                              struct vc4_uncompiled_shader *so)
2031 {
2032         const struct vc4_key *key = entry->key;
2033
2034         if (key->shader_state == so) {
2035                 struct vc4_compiled_shader *shader = entry->data;
2036                 _mesa_hash_table_remove(ht, entry);
2037                 vc4_bo_unreference(&shader->bo);
2038                 ralloc_free(shader);
2039         }
2040 }
2041
2042 static void
2043 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2044 {
2045         struct vc4_context *vc4 = vc4_context(pctx);
2046         struct vc4_uncompiled_shader *so = hwcso;
2047
2048         struct hash_entry *entry;
2049         hash_table_foreach(vc4->fs_cache, entry)
2050                 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2051         hash_table_foreach(vc4->vs_cache, entry)
2052                 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2053
2054         free((void *)so->base.tokens);
2055         free(so);
2056 }
2057
2058 static void
2059 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2060 {
2061         struct vc4_context *vc4 = vc4_context(pctx);
2062         vc4->prog.bind_fs = hwcso;
2063         vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2064 }
2065
2066 static void
2067 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2068 {
2069         struct vc4_context *vc4 = vc4_context(pctx);
2070         vc4->prog.bind_vs = hwcso;
2071         vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2072 }
2073
2074 void
2075 vc4_program_init(struct pipe_context *pctx)
2076 {
2077         struct vc4_context *vc4 = vc4_context(pctx);
2078
2079         pctx->create_vs_state = vc4_shader_state_create;
2080         pctx->delete_vs_state = vc4_shader_state_delete;
2081
2082         pctx->create_fs_state = vc4_shader_state_create;
2083         pctx->delete_fs_state = vc4_shader_state_delete;
2084
2085         pctx->bind_fs_state = vc4_fp_state_bind;
2086         pctx->bind_vs_state = vc4_vp_state_bind;
2087
2088         vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2089                                                 fs_cache_compare);
2090         vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2091                                                 vs_cache_compare);
2092 }
2093
2094 void
2095 vc4_program_fini(struct pipe_context *pctx)
2096 {
2097         struct vc4_context *vc4 = vc4_context(pctx);
2098
2099         struct hash_entry *entry;
2100         hash_table_foreach(vc4->fs_cache, entry) {
2101                 struct vc4_compiled_shader *shader = entry->data;
2102                 vc4_bo_unreference(&shader->bo);
2103                 ralloc_free(shader);
2104                 _mesa_hash_table_remove(vc4->fs_cache, entry);
2105         }
2106
2107         hash_table_foreach(vc4->vs_cache, entry) {
2108                 struct vc4_compiled_shader *shader = entry->data;
2109                 vc4_bo_unreference(&shader->bo);
2110                 ralloc_free(shader);
2111                 _mesa_hash_table_remove(vc4->vs_cache, entry);
2112         }
2113 }