2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "vc4_context.h"
31 vc4_dump_program(struct vc4_compile *c)
33 fprintf(stderr, "%s prog %d/%d QPU:\n",
34 qir_get_stage_name(c->stage),
35 c->program_id, c->variant_id);
37 for (int i = 0; i < c->qpu_inst_count; i++) {
38 fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
39 vc4_qpu_disasm(&c->qpu_insts[i], 1);
40 fprintf(stderr, "\n");
45 queue(struct vc4_compile *c, uint64_t inst)
47 struct queued_qpu_inst *q = calloc(1, sizeof(*q));
49 insert_at_tail(&c->qpu_inst_list, &q->link);
53 last_inst(struct vc4_compile *c)
55 struct queued_qpu_inst *q =
56 (struct queued_qpu_inst *)last_elem(&c->qpu_inst_list);
61 set_last_cond_add(struct vc4_compile *c, uint32_t cond)
63 *last_inst(c) = qpu_set_cond_add(*last_inst(c), cond);
67 * Some special registers can be read from either file, which lets us resolve
68 * raddr conflicts without extra MOVs.
71 swap_file(struct qpu_reg *src)
76 if (src->mux == QPU_MUX_A)
88 * This is used to resolve the fact that we might register-allocate two
89 * different operands of an instruction to the same physical register file
90 * even though instructions have only one field for the register file source
93 * In that case, we need to move one to a temporary that can be used in the
94 * instruction, instead.
97 fixup_raddr_conflict(struct vc4_compile *c,
98 struct qpu_reg *src0, struct qpu_reg *src1)
100 if ((src0->mux != QPU_MUX_A && src0->mux != QPU_MUX_B) ||
101 src0->mux != src1->mux ||
102 src0->addr == src1->addr) {
106 if (swap_file(src0) || swap_file(src1))
109 queue(c, qpu_a_MOV(qpu_r3(), *src1));
114 vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
116 struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c);
117 bool discard = false;
118 uint32_t inputs_remaining = c->num_inputs;
119 uint32_t vpm_read_fifo_count = 0;
120 uint32_t vpm_read_offset = 0;
122 make_empty_list(&c->qpu_inst_list);
127 /* There's a 4-entry FIFO for VPMVCD reads, each of which can
128 * load up to 16 dwords (4 vec4s) per vertex.
130 while (inputs_remaining) {
131 uint32_t num_entries = MIN2(inputs_remaining, 16);
132 queue(c, qpu_load_imm_ui(qpu_vrsetup(),
135 ((num_entries & 0xf) << 20)));
136 inputs_remaining -= num_entries;
137 vpm_read_offset += num_entries;
138 vpm_read_fifo_count++;
140 assert(vpm_read_fifo_count <= 4);
142 queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
148 struct simple_node *node;
149 foreach(node, &c->instructions) {
150 struct qinst *qinst = (struct qinst *)node;
153 fprintf(stderr, "translating qinst to qpu: ");
154 qir_dump_inst(qinst);
155 fprintf(stderr, "\n");
158 static const struct {
162 #define A(name) [QOP_##name] = {QPU_A_##name, false}
163 #define M(name) [QOP_##name] = {QPU_M_##name, true}
188 struct qpu_reg src[4];
189 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
190 int index = qinst->src[i].index;
191 switch (qinst->src[i].file) {
196 src[i] = temp_registers[index];
208 switch (qinst->dst.file) {
210 dst = qpu_ra(QPU_W_NOP);
213 dst = temp_registers[qinst->dst.index];
217 assert(!"not reached");
223 /* Skip emitting the MOV if it's a no-op. */
224 if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B ||
225 dst.mux != src[0].mux || dst.addr != src[0].addr) {
226 queue(c, qpu_a_MOV(dst, src[0]));
231 queue(c, qpu_a_MOV(qpu_ra(QPU_W_NOP), src[0]));
232 *last_inst(c) |= QPU_SF;
239 queue(c, qpu_a_MOV(dst, src[0]));
240 set_last_cond_add(c, qinst->op - QOP_SEL_X_0_ZS +
243 queue(c, qpu_a_XOR(dst, qpu_r0(), qpu_r0()));
244 set_last_cond_add(c, ((qinst->op - QOP_SEL_X_0_ZS) ^
252 queue(c, qpu_a_MOV(dst, src[0]));
253 set_last_cond_add(c, qinst->op - QOP_SEL_X_Y_ZS +
256 queue(c, qpu_a_MOV(dst, src[1]));
257 set_last_cond_add(c, ((qinst->op - QOP_SEL_X_Y_ZS) ^
263 queue(c, qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0]));
267 queue(c, qpu_a_MOV(dst, qpu_ra(QPU_R_VPM)));
276 queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
280 queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
284 queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
288 queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
295 queue(c, qpu_a_MOV(dst, qpu_r4()));
299 case QOP_PACK_COLORS: {
300 /* We have to be careful not to start writing over one
301 * of our source values when incrementally writing the
302 * destination. So, if the dst is one of the srcs, we
303 * pack that one first (and we pack 4 channels at once
304 * for the first pack).
306 struct qpu_reg first_pack = src[0];
307 for (int i = 0; i < 4; i++) {
308 if (src[i].mux == dst.mux &&
309 src[i].addr == dst.addr) {
314 queue(c, qpu_m_MOV(dst, first_pack));
315 *last_inst(c) |= QPU_PM;
316 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8888,
319 for (int i = 0; i < 4; i++) {
320 if (src[i].mux == first_pack.mux &&
321 src[i].addr == first_pack.addr) {
325 queue(c, qpu_m_MOV(dst, src[i]));
326 *last_inst(c) |= QPU_PM;
327 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
335 queue(c, qpu_a_ITOF(dst,
336 qpu_ra(QPU_R_XY_PIXEL_COORD)));
340 queue(c, qpu_a_ITOF(dst,
341 qpu_rb(QPU_R_XY_PIXEL_COORD)));
344 case QOP_FRAG_REV_FLAG:
345 queue(c, qpu_a_ITOF(dst,
346 qpu_rb(QPU_R_MS_REV_FLAGS)));
351 /* QOP_FRAG_Z/W don't emit instructions, just allocate
352 * the register to the Z/W payload.
356 case QOP_TLB_DISCARD_SETUP:
358 queue(c, qpu_a_MOV(src[0], src[0]));
359 *last_inst(c) |= QPU_SF;
362 case QOP_TLB_STENCIL_SETUP:
363 queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP), src[0]));
366 case QOP_TLB_Z_WRITE:
367 queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), src[0]));
369 set_last_cond_add(c, QPU_COND_ZS);
373 case QOP_TLB_COLOR_READ:
375 *last_inst(c) = qpu_set_sig(*last_inst(c),
380 case QOP_TLB_COLOR_WRITE:
381 queue(c, qpu_a_MOV(qpu_tlbc(), src[0]));
383 set_last_cond_add(c, QPU_COND_ZS);
388 queue(c, qpu_a_FADD(dst, src[0], qpu_r5()));
391 case QOP_PACK_SCALED: {
392 uint64_t a = (qpu_a_MOV(dst, src[0]) |
393 QPU_SET_FIELD(QPU_PACK_A_16A,
395 uint64_t b = (qpu_a_MOV(dst, src[1]) |
396 QPU_SET_FIELD(QPU_PACK_A_16B,
399 if (dst.mux == src[1].mux && dst.addr == src[1].addr) {
413 queue(c, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S +
414 (qinst->op - QOP_TEX_S)),
419 fixup_raddr_conflict(c, &src[0], &src[1]);
420 queue(c, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S), src[0], src[1]));
425 *last_inst(c) = qpu_set_sig(*last_inst(c),
430 case QOP_R4_UNPACK_A:
431 case QOP_R4_UNPACK_B:
432 case QOP_R4_UNPACK_C:
433 case QOP_R4_UNPACK_D:
434 assert(src[0].mux == QPU_MUX_R4);
435 queue(c, qpu_a_MOV(dst, src[0]));
436 *last_inst(c) |= QPU_PM;
437 *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A +
447 case QOP_UNPACK_8D: {
448 assert(src[0].mux == QPU_MUX_A);
450 /* And, since we're setting the pack bits, if the
451 * destination is in A it would get re-packed.
453 struct qpu_reg orig_dst = dst;
454 if (orig_dst.mux == QPU_MUX_A)
457 queue(c, qpu_a_FMAX(dst, src[0], src[0]));
458 *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A +
463 if (orig_dst.mux == QPU_MUX_A) {
464 queue(c, qpu_a_MOV(orig_dst, dst));
470 assert(qinst->op < ARRAY_SIZE(translate));
471 assert(translate[qinst->op].op != 0); /* NOPs */
473 /* If we have only one source, put it in the second
474 * argument slot as well so that we don't take up
475 * another raddr just to get unused data.
477 if (qir_get_op_nsrc(qinst->op) == 1)
480 fixup_raddr_conflict(c, &src[0], &src[1]);
482 if (translate[qinst->op].is_mul) {
483 queue(c, qpu_m_alu2(translate[qinst->op].op,
487 queue(c, qpu_a_alu2(translate[qinst->op].op,
495 qpu_schedule_instructions(c);
497 /* thread end can't have VPM write or read */
498 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
499 QPU_WADDR_ADD) == QPU_W_VPM ||
500 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
501 QPU_WADDR_MUL) == QPU_W_VPM ||
502 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
503 QPU_RADDR_A) == QPU_R_VPM ||
504 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
505 QPU_RADDR_B) == QPU_R_VPM) {
506 qpu_serialize_one_inst(c, qpu_NOP());
509 /* thread end can't have uniform read */
510 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
511 QPU_RADDR_A) == QPU_R_UNIF ||
512 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
513 QPU_RADDR_B) == QPU_R_UNIF) {
514 qpu_serialize_one_inst(c, qpu_NOP());
517 /* thread end can't have TLB operations */
518 if (qpu_inst_is_tlb(c->qpu_insts[c->qpu_inst_count - 1]))
519 qpu_serialize_one_inst(c, qpu_NOP());
521 c->qpu_insts[c->qpu_inst_count - 1] =
522 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
524 qpu_serialize_one_inst(c, qpu_NOP());
525 qpu_serialize_one_inst(c, qpu_NOP());
532 c->qpu_insts[c->qpu_inst_count - 1] =
533 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
534 QPU_SIG_SCOREBOARD_UNLOCK);
538 if (vc4_debug & VC4_DEBUG_QPU)
541 vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
543 free(temp_registers);